1dee1ad47SJeff Kirsher /******************************************************************************* 2dee1ad47SJeff Kirsher 3dee1ad47SJeff Kirsher Intel 10 Gigabit PCI Express Linux driver 4434c5e39SDon Skidmore Copyright(c) 1999 - 2013 Intel Corporation. 5dee1ad47SJeff Kirsher 6dee1ad47SJeff Kirsher This program is free software; you can redistribute it and/or modify it 7dee1ad47SJeff Kirsher under the terms and conditions of the GNU General Public License, 8dee1ad47SJeff Kirsher version 2, as published by the Free Software Foundation. 9dee1ad47SJeff Kirsher 10dee1ad47SJeff Kirsher This program is distributed in the hope it will be useful, but WITHOUT 11dee1ad47SJeff Kirsher ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12dee1ad47SJeff Kirsher FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13dee1ad47SJeff Kirsher more details. 14dee1ad47SJeff Kirsher 15dee1ad47SJeff Kirsher You should have received a copy of the GNU General Public License along with 16dee1ad47SJeff Kirsher this program; if not, write to the Free Software Foundation, Inc., 17dee1ad47SJeff Kirsher 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18dee1ad47SJeff Kirsher 19dee1ad47SJeff Kirsher The full GNU General Public License is included in this distribution in 20dee1ad47SJeff Kirsher the file called "COPYING". 21dee1ad47SJeff Kirsher 22dee1ad47SJeff Kirsher Contact Information: 23dee1ad47SJeff Kirsher Linux NICS <linux.nics@intel.com> 24dee1ad47SJeff Kirsher e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25dee1ad47SJeff Kirsher Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26dee1ad47SJeff Kirsher 27dee1ad47SJeff Kirsher *******************************************************************************/ 28dee1ad47SJeff Kirsher 29dee1ad47SJeff Kirsher #include "ixgbe.h" 30dee1ad47SJeff Kirsher #include "ixgbe_type.h" 31dee1ad47SJeff Kirsher #include "ixgbe_dcb.h" 32dee1ad47SJeff Kirsher #include "ixgbe_dcb_82598.h" 33dee1ad47SJeff Kirsher 34dee1ad47SJeff Kirsher /** 35dee1ad47SJeff Kirsher * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter 36dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 37dee1ad47SJeff Kirsher * @dcb_config: pointer to ixgbe_dcb_config structure 38dee1ad47SJeff Kirsher * 39dee1ad47SJeff Kirsher * Configure Rx Data Arbiter and credits for each traffic class. 40dee1ad47SJeff Kirsher */ 41dee1ad47SJeff Kirsher s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, 42dee1ad47SJeff Kirsher u16 *refill, 43dee1ad47SJeff Kirsher u16 *max, 44dee1ad47SJeff Kirsher u8 *prio_type) 45dee1ad47SJeff Kirsher { 46dee1ad47SJeff Kirsher u32 reg = 0; 47dee1ad47SJeff Kirsher u32 credit_refill = 0; 48dee1ad47SJeff Kirsher u32 credit_max = 0; 49dee1ad47SJeff Kirsher u8 i = 0; 50dee1ad47SJeff Kirsher 51dee1ad47SJeff Kirsher reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; 52dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); 53dee1ad47SJeff Kirsher 54dee1ad47SJeff Kirsher reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 55dee1ad47SJeff Kirsher /* Enable Arbiter */ 56dee1ad47SJeff Kirsher reg &= ~IXGBE_RMCS_ARBDIS; 57dee1ad47SJeff Kirsher /* Enable Receive Recycle within the BWG */ 58dee1ad47SJeff Kirsher reg |= IXGBE_RMCS_RRM; 59dee1ad47SJeff Kirsher /* Enable Deficit Fixed Priority arbitration*/ 60dee1ad47SJeff Kirsher reg |= IXGBE_RMCS_DFP; 61dee1ad47SJeff Kirsher 62dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); 63dee1ad47SJeff Kirsher 64dee1ad47SJeff Kirsher /* Configure traffic class credits and priority */ 65dee1ad47SJeff Kirsher for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 66dee1ad47SJeff Kirsher credit_refill = refill[i]; 67dee1ad47SJeff Kirsher credit_max = max[i]; 68dee1ad47SJeff Kirsher 69dee1ad47SJeff Kirsher reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); 70dee1ad47SJeff Kirsher 71dee1ad47SJeff Kirsher if (prio_type[i] == prio_link) 72dee1ad47SJeff Kirsher reg |= IXGBE_RT2CR_LSP; 73dee1ad47SJeff Kirsher 74dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg); 75dee1ad47SJeff Kirsher } 76dee1ad47SJeff Kirsher 77dee1ad47SJeff Kirsher reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 78dee1ad47SJeff Kirsher reg |= IXGBE_RDRXCTL_RDMTS_1_2; 79dee1ad47SJeff Kirsher reg |= IXGBE_RDRXCTL_MPBEN; 80dee1ad47SJeff Kirsher reg |= IXGBE_RDRXCTL_MCEN; 81dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 82dee1ad47SJeff Kirsher 83dee1ad47SJeff Kirsher reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 84dee1ad47SJeff Kirsher /* Make sure there is enough descriptors before arbitration */ 85dee1ad47SJeff Kirsher reg &= ~IXGBE_RXCTRL_DMBYPS; 86dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg); 87dee1ad47SJeff Kirsher 88dee1ad47SJeff Kirsher return 0; 89dee1ad47SJeff Kirsher } 90dee1ad47SJeff Kirsher 91dee1ad47SJeff Kirsher /** 92dee1ad47SJeff Kirsher * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter 93dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 94dee1ad47SJeff Kirsher * @dcb_config: pointer to ixgbe_dcb_config structure 95dee1ad47SJeff Kirsher * 96dee1ad47SJeff Kirsher * Configure Tx Descriptor Arbiter and credits for each traffic class. 97dee1ad47SJeff Kirsher */ 98dee1ad47SJeff Kirsher s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, 99dee1ad47SJeff Kirsher u16 *refill, 100dee1ad47SJeff Kirsher u16 *max, 101dee1ad47SJeff Kirsher u8 *bwg_id, 102dee1ad47SJeff Kirsher u8 *prio_type) 103dee1ad47SJeff Kirsher { 104dee1ad47SJeff Kirsher u32 reg, max_credits; 105dee1ad47SJeff Kirsher u8 i; 106dee1ad47SJeff Kirsher 107dee1ad47SJeff Kirsher reg = IXGBE_READ_REG(hw, IXGBE_DPMCS); 108dee1ad47SJeff Kirsher 109dee1ad47SJeff Kirsher /* Enable arbiter */ 110dee1ad47SJeff Kirsher reg &= ~IXGBE_DPMCS_ARBDIS; 111dee1ad47SJeff Kirsher reg |= IXGBE_DPMCS_TSOEF; 1121eb9ac14SJacob Keller 113dee1ad47SJeff Kirsher /* Configure Max TSO packet size 34KB including payload and headers */ 114dee1ad47SJeff Kirsher reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT); 115dee1ad47SJeff Kirsher 116dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg); 117dee1ad47SJeff Kirsher 118dee1ad47SJeff Kirsher /* Configure traffic class credits and priority */ 119dee1ad47SJeff Kirsher for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 120dee1ad47SJeff Kirsher max_credits = max[i]; 121dee1ad47SJeff Kirsher reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT; 122dee1ad47SJeff Kirsher reg |= refill[i]; 123dee1ad47SJeff Kirsher reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT; 124dee1ad47SJeff Kirsher 125dee1ad47SJeff Kirsher if (prio_type[i] == prio_group) 126dee1ad47SJeff Kirsher reg |= IXGBE_TDTQ2TCCR_GSP; 127dee1ad47SJeff Kirsher 128dee1ad47SJeff Kirsher if (prio_type[i] == prio_link) 129dee1ad47SJeff Kirsher reg |= IXGBE_TDTQ2TCCR_LSP; 130dee1ad47SJeff Kirsher 131dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg); 132dee1ad47SJeff Kirsher } 133dee1ad47SJeff Kirsher 134dee1ad47SJeff Kirsher return 0; 135dee1ad47SJeff Kirsher } 136dee1ad47SJeff Kirsher 137dee1ad47SJeff Kirsher /** 138dee1ad47SJeff Kirsher * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter 139dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 140dee1ad47SJeff Kirsher * @dcb_config: pointer to ixgbe_dcb_config structure 141dee1ad47SJeff Kirsher * 142dee1ad47SJeff Kirsher * Configure Tx Data Arbiter and credits for each traffic class. 143dee1ad47SJeff Kirsher */ 144dee1ad47SJeff Kirsher s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, 145dee1ad47SJeff Kirsher u16 *refill, 146dee1ad47SJeff Kirsher u16 *max, 147dee1ad47SJeff Kirsher u8 *bwg_id, 148dee1ad47SJeff Kirsher u8 *prio_type) 149dee1ad47SJeff Kirsher { 150dee1ad47SJeff Kirsher u32 reg; 151dee1ad47SJeff Kirsher u8 i; 152dee1ad47SJeff Kirsher 153dee1ad47SJeff Kirsher reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS); 154dee1ad47SJeff Kirsher /* Enable Data Plane Arbiter */ 155dee1ad47SJeff Kirsher reg &= ~IXGBE_PDPMCS_ARBDIS; 156dee1ad47SJeff Kirsher /* Enable DFP and Transmit Recycle Mode */ 157dee1ad47SJeff Kirsher reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM); 158dee1ad47SJeff Kirsher 159dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg); 160dee1ad47SJeff Kirsher 161dee1ad47SJeff Kirsher /* Configure traffic class credits and priority */ 162dee1ad47SJeff Kirsher for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 163dee1ad47SJeff Kirsher reg = refill[i]; 164dee1ad47SJeff Kirsher reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT; 165dee1ad47SJeff Kirsher reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT; 166dee1ad47SJeff Kirsher 167dee1ad47SJeff Kirsher if (prio_type[i] == prio_group) 168dee1ad47SJeff Kirsher reg |= IXGBE_TDPT2TCCR_GSP; 169dee1ad47SJeff Kirsher 170dee1ad47SJeff Kirsher if (prio_type[i] == prio_link) 171dee1ad47SJeff Kirsher reg |= IXGBE_TDPT2TCCR_LSP; 172dee1ad47SJeff Kirsher 173dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg); 174dee1ad47SJeff Kirsher } 175dee1ad47SJeff Kirsher 176dee1ad47SJeff Kirsher /* Enable Tx packet buffer division */ 177dee1ad47SJeff Kirsher reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL); 178dee1ad47SJeff Kirsher reg |= IXGBE_DTXCTL_ENDBUBD; 179dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg); 180dee1ad47SJeff Kirsher 181dee1ad47SJeff Kirsher return 0; 182dee1ad47SJeff Kirsher } 183dee1ad47SJeff Kirsher 184dee1ad47SJeff Kirsher /** 185dee1ad47SJeff Kirsher * ixgbe_dcb_config_pfc_82598 - Config priority flow control 186dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 187dee1ad47SJeff Kirsher * @dcb_config: pointer to ixgbe_dcb_config structure 188dee1ad47SJeff Kirsher * 189dee1ad47SJeff Kirsher * Configure Priority Flow Control for each traffic class. 190dee1ad47SJeff Kirsher */ 191dee1ad47SJeff Kirsher s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en) 192dee1ad47SJeff Kirsher { 193943561d3SAlexander Duyck u32 fcrtl, reg; 194dee1ad47SJeff Kirsher u8 i; 195dee1ad47SJeff Kirsher 196dee1ad47SJeff Kirsher /* Enable Transmit Priority Flow Control */ 197dee1ad47SJeff Kirsher reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 198dee1ad47SJeff Kirsher reg &= ~IXGBE_RMCS_TFCE_802_3X; 199dee1ad47SJeff Kirsher reg |= IXGBE_RMCS_TFCE_PRIORITY; 200dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); 201dee1ad47SJeff Kirsher 202dee1ad47SJeff Kirsher /* Enable Receive Priority Flow Control */ 203dee1ad47SJeff Kirsher reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 204943561d3SAlexander Duyck reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE); 205943561d3SAlexander Duyck 206943561d3SAlexander Duyck if (pfc_en) 207dee1ad47SJeff Kirsher reg |= IXGBE_FCTRL_RPFCE; 208943561d3SAlexander Duyck 209dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg); 210dee1ad47SJeff Kirsher 211943561d3SAlexander Duyck /* Configure PFC Tx thresholds per TC */ 212943561d3SAlexander Duyck for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 213943561d3SAlexander Duyck if (!(pfc_en & (1 << i))) { 214943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); 215943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); 216943561d3SAlexander Duyck continue; 217dee1ad47SJeff Kirsher } 218dee1ad47SJeff Kirsher 219e5776620SJacob Keller fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 220943561d3SAlexander Duyck reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 221943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl); 222dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg); 223dee1ad47SJeff Kirsher } 224dee1ad47SJeff Kirsher 225943561d3SAlexander Duyck /* Configure pause time */ 226943561d3SAlexander Duyck reg = hw->fc.pause_time * 0x00010001; 227943561d3SAlexander Duyck for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 228943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 229943561d3SAlexander Duyck 230943561d3SAlexander Duyck /* Configure flow control refresh threshold value */ 231943561d3SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 232943561d3SAlexander Duyck 233943561d3SAlexander Duyck 234dee1ad47SJeff Kirsher return 0; 235dee1ad47SJeff Kirsher } 236dee1ad47SJeff Kirsher 237dee1ad47SJeff Kirsher /** 238dee1ad47SJeff Kirsher * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics 239dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 240dee1ad47SJeff Kirsher * 241dee1ad47SJeff Kirsher * Configure queue statistics registers, all queues belonging to same traffic 242dee1ad47SJeff Kirsher * class uses a single set of queue statistics counters. 243dee1ad47SJeff Kirsher */ 244dee1ad47SJeff Kirsher static s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw) 245dee1ad47SJeff Kirsher { 246dee1ad47SJeff Kirsher u32 reg = 0; 247dee1ad47SJeff Kirsher u8 i = 0; 248dee1ad47SJeff Kirsher u8 j = 0; 249dee1ad47SJeff Kirsher 250dee1ad47SJeff Kirsher /* Receive Queues stats setting - 8 queues per statistics reg */ 251dee1ad47SJeff Kirsher for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) { 252dee1ad47SJeff Kirsher reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i)); 253dee1ad47SJeff Kirsher reg |= ((0x1010101) * j); 254dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); 255dee1ad47SJeff Kirsher reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1)); 256dee1ad47SJeff Kirsher reg |= ((0x1010101) * j); 257dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg); 258dee1ad47SJeff Kirsher } 259dee1ad47SJeff Kirsher /* Transmit Queues stats setting - 4 queues per statistics reg */ 260dee1ad47SJeff Kirsher for (i = 0; i < 8; i++) { 261dee1ad47SJeff Kirsher reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i)); 262dee1ad47SJeff Kirsher reg |= ((0x1010101) * i); 263dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg); 264dee1ad47SJeff Kirsher } 265dee1ad47SJeff Kirsher 266dee1ad47SJeff Kirsher return 0; 267dee1ad47SJeff Kirsher } 268dee1ad47SJeff Kirsher 269dee1ad47SJeff Kirsher /** 270dee1ad47SJeff Kirsher * ixgbe_dcb_hw_config_82598 - Config and enable DCB 271dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 272dee1ad47SJeff Kirsher * @dcb_config: pointer to ixgbe_dcb_config structure 273dee1ad47SJeff Kirsher * 274dee1ad47SJeff Kirsher * Configure dcb settings and enable dcb mode. 275dee1ad47SJeff Kirsher */ 276dee1ad47SJeff Kirsher s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill, 277dee1ad47SJeff Kirsher u16 *max, u8 *bwg_id, u8 *prio_type) 278dee1ad47SJeff Kirsher { 279dee1ad47SJeff Kirsher ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, prio_type); 280dee1ad47SJeff Kirsher ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, 281dee1ad47SJeff Kirsher bwg_id, prio_type); 282dee1ad47SJeff Kirsher ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, 283dee1ad47SJeff Kirsher bwg_id, prio_type); 284dee1ad47SJeff Kirsher ixgbe_dcb_config_pfc_82598(hw, pfc_en); 285dee1ad47SJeff Kirsher ixgbe_dcb_config_tc_stats_82598(hw); 286dee1ad47SJeff Kirsher 287dee1ad47SJeff Kirsher return 0; 288dee1ad47SJeff Kirsher } 289