1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2011 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 30 #include "ixgbe.h" 31 #include "ixgbe_type.h" 32 #include "ixgbe_dcb.h" 33 #include "ixgbe_dcb_82598.h" 34 #include "ixgbe_dcb_82599.h" 35 36 /** 37 * ixgbe_ieee_credits - This calculates the ieee traffic class 38 * credits from the configured bandwidth percentages. Credits 39 * are the smallest unit programmable into the underlying 40 * hardware. The IEEE 802.1Qaz specification do not use bandwidth 41 * groups so this is much simplified from the CEE case. 42 */ 43 static s32 ixgbe_ieee_credits(__u8 *bw, __u16 *refill, 44 __u16 *max, int max_frame) 45 { 46 int min_percent = 100; 47 int min_credit, multiplier; 48 int i; 49 50 min_credit = ((max_frame / 2) + DCB_CREDIT_QUANTUM - 1) / 51 DCB_CREDIT_QUANTUM; 52 53 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 54 if (bw[i] < min_percent && bw[i]) 55 min_percent = bw[i]; 56 } 57 58 multiplier = (min_credit / min_percent) + 1; 59 60 /* Find out the hw credits for each TC */ 61 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 62 int val = min(bw[i] * multiplier, MAX_CREDIT_REFILL); 63 64 if (val < min_credit) 65 val = min_credit; 66 refill[i] = val; 67 68 max[i] = bw[i] ? (bw[i] * MAX_CREDIT)/100 : min_credit; 69 } 70 return 0; 71 } 72 73 /** 74 * ixgbe_dcb_calculate_tc_credits - Calculates traffic class credits 75 * @ixgbe_dcb_config: Struct containing DCB settings. 76 * @direction: Configuring either Tx or Rx. 77 * 78 * This function calculates the credits allocated to each traffic class. 79 * It should be called only after the rules are checked by 80 * ixgbe_dcb_check_config(). 81 */ 82 s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_hw *hw, 83 struct ixgbe_dcb_config *dcb_config, 84 int max_frame, u8 direction) 85 { 86 struct tc_bw_alloc *p; 87 int min_credit; 88 int min_multiplier; 89 int min_percent = 100; 90 s32 ret_val = 0; 91 /* Initialization values default for Tx settings */ 92 u32 credit_refill = 0; 93 u32 credit_max = 0; 94 u16 link_percentage = 0; 95 u8 bw_percent = 0; 96 u8 i; 97 98 if (dcb_config == NULL) { 99 ret_val = DCB_ERR_CONFIG; 100 goto out; 101 } 102 103 min_credit = ((max_frame / 2) + DCB_CREDIT_QUANTUM - 1) / 104 DCB_CREDIT_QUANTUM; 105 106 /* Find smallest link percentage */ 107 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 108 p = &dcb_config->tc_config[i].path[direction]; 109 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id]; 110 link_percentage = p->bwg_percent; 111 112 link_percentage = (link_percentage * bw_percent) / 100; 113 114 if (link_percentage && link_percentage < min_percent) 115 min_percent = link_percentage; 116 } 117 118 /* 119 * The ratio between traffic classes will control the bandwidth 120 * percentages seen on the wire. To calculate this ratio we use 121 * a multiplier. It is required that the refill credits must be 122 * larger than the max frame size so here we find the smallest 123 * multiplier that will allow all bandwidth percentages to be 124 * greater than the max frame size. 125 */ 126 min_multiplier = (min_credit / min_percent) + 1; 127 128 /* Find out the link percentage for each TC first */ 129 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 130 p = &dcb_config->tc_config[i].path[direction]; 131 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id]; 132 133 link_percentage = p->bwg_percent; 134 /* Must be careful of integer division for very small nums */ 135 link_percentage = (link_percentage * bw_percent) / 100; 136 if (p->bwg_percent > 0 && link_percentage == 0) 137 link_percentage = 1; 138 139 /* Save link_percentage for reference */ 140 p->link_percent = (u8)link_percentage; 141 142 /* Calculate credit refill ratio using multiplier */ 143 credit_refill = min(link_percentage * min_multiplier, 144 MAX_CREDIT_REFILL); 145 p->data_credits_refill = (u16)credit_refill; 146 147 /* Calculate maximum credit for the TC */ 148 credit_max = (link_percentage * MAX_CREDIT) / 100; 149 150 /* 151 * Adjustment based on rule checking, if the percentage 152 * of a TC is too small, the maximum credit may not be 153 * enough to send out a jumbo frame in data plane arbitration. 154 */ 155 if (credit_max && (credit_max < min_credit)) 156 credit_max = min_credit; 157 158 if (direction == DCB_TX_CONFIG) { 159 /* 160 * Adjustment based on rule checking, if the 161 * percentage of a TC is too small, the maximum 162 * credit may not be enough to send out a TSO 163 * packet in descriptor plane arbitration. 164 */ 165 if ((hw->mac.type == ixgbe_mac_82598EB) && 166 credit_max && 167 (credit_max < MINIMUM_CREDIT_FOR_TSO)) 168 credit_max = MINIMUM_CREDIT_FOR_TSO; 169 170 dcb_config->tc_config[i].desc_credits_max = 171 (u16)credit_max; 172 } 173 174 p->data_credits_max = (u16)credit_max; 175 } 176 177 out: 178 return ret_val; 179 } 180 181 void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config *cfg, u8 *pfc_en) 182 { 183 int i; 184 185 *pfc_en = 0; 186 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) 187 *pfc_en |= !!(cfg->tc_config[i].dcb_pfc & 0xF) << i; 188 } 189 190 void ixgbe_dcb_unpack_refill(struct ixgbe_dcb_config *cfg, int direction, 191 u16 *refill) 192 { 193 struct tc_bw_alloc *p; 194 int i; 195 196 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 197 p = &cfg->tc_config[i].path[direction]; 198 refill[i] = p->data_credits_refill; 199 } 200 } 201 202 void ixgbe_dcb_unpack_max(struct ixgbe_dcb_config *cfg, u16 *max) 203 { 204 int i; 205 206 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) 207 max[i] = cfg->tc_config[i].desc_credits_max; 208 } 209 210 void ixgbe_dcb_unpack_bwgid(struct ixgbe_dcb_config *cfg, int direction, 211 u8 *bwgid) 212 { 213 struct tc_bw_alloc *p; 214 int i; 215 216 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 217 p = &cfg->tc_config[i].path[direction]; 218 bwgid[i] = p->bwg_id; 219 } 220 } 221 222 void ixgbe_dcb_unpack_prio(struct ixgbe_dcb_config *cfg, int direction, 223 u8 *ptype) 224 { 225 struct tc_bw_alloc *p; 226 int i; 227 228 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 229 p = &cfg->tc_config[i].path[direction]; 230 ptype[i] = p->prio_type; 231 } 232 } 233 234 void ixgbe_dcb_unpack_map(struct ixgbe_dcb_config *cfg, int direction, u8 *map) 235 { 236 int i, up; 237 unsigned long bitmap; 238 239 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 240 bitmap = cfg->tc_config[i].path[direction].up_to_tc_bitmap; 241 for_each_set_bit(up, &bitmap, MAX_USER_PRIORITY) 242 map[up] = i; 243 } 244 } 245 246 /** 247 * ixgbe_dcb_hw_config - Config and enable DCB 248 * @hw: pointer to hardware structure 249 * @dcb_config: pointer to ixgbe_dcb_config structure 250 * 251 * Configure dcb settings and enable dcb mode. 252 */ 253 s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, 254 struct ixgbe_dcb_config *dcb_config) 255 { 256 s32 ret = 0; 257 u8 pfc_en; 258 u8 ptype[MAX_TRAFFIC_CLASS]; 259 u8 bwgid[MAX_TRAFFIC_CLASS]; 260 u8 prio_tc[MAX_TRAFFIC_CLASS]; 261 u16 refill[MAX_TRAFFIC_CLASS]; 262 u16 max[MAX_TRAFFIC_CLASS]; 263 264 /* Unpack CEE standard containers */ 265 ixgbe_dcb_unpack_pfc(dcb_config, &pfc_en); 266 ixgbe_dcb_unpack_refill(dcb_config, DCB_TX_CONFIG, refill); 267 ixgbe_dcb_unpack_max(dcb_config, max); 268 ixgbe_dcb_unpack_bwgid(dcb_config, DCB_TX_CONFIG, bwgid); 269 ixgbe_dcb_unpack_prio(dcb_config, DCB_TX_CONFIG, ptype); 270 ixgbe_dcb_unpack_map(dcb_config, DCB_TX_CONFIG, prio_tc); 271 272 switch (hw->mac.type) { 273 case ixgbe_mac_82598EB: 274 ret = ixgbe_dcb_hw_config_82598(hw, pfc_en, refill, max, 275 bwgid, ptype); 276 break; 277 case ixgbe_mac_82599EB: 278 case ixgbe_mac_X540: 279 ret = ixgbe_dcb_hw_config_82599(hw, pfc_en, refill, max, 280 bwgid, ptype, prio_tc); 281 break; 282 default: 283 break; 284 } 285 return ret; 286 } 287 288 /* Helper routines to abstract HW specifics from DCB netlink ops */ 289 s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc) 290 { 291 int ret = -EINVAL; 292 293 switch (hw->mac.type) { 294 case ixgbe_mac_82598EB: 295 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en); 296 break; 297 case ixgbe_mac_82599EB: 298 case ixgbe_mac_X540: 299 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc); 300 break; 301 default: 302 break; 303 } 304 return ret; 305 } 306 307 s32 ixgbe_dcb_hw_ets(struct ixgbe_hw *hw, struct ieee_ets *ets, int max_frame) 308 { 309 __u16 refill[IEEE_8021QAZ_MAX_TCS], max[IEEE_8021QAZ_MAX_TCS]; 310 __u8 prio_type[IEEE_8021QAZ_MAX_TCS]; 311 int i; 312 313 /* naively give each TC a bwg to map onto CEE hardware */ 314 __u8 bwg_id[IEEE_8021QAZ_MAX_TCS] = {0, 1, 2, 3, 4, 5, 6, 7}; 315 316 /* Map TSA onto CEE prio type */ 317 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 318 switch (ets->tc_tsa[i]) { 319 case IEEE_8021QAZ_TSA_STRICT: 320 prio_type[i] = 2; 321 break; 322 case IEEE_8021QAZ_TSA_ETS: 323 prio_type[i] = 0; 324 break; 325 default: 326 /* Hardware only supports priority strict or 327 * ETS transmission selection algorithms if 328 * we receive some other value from dcbnl 329 * throw an error 330 */ 331 return -EINVAL; 332 } 333 } 334 335 ixgbe_ieee_credits(ets->tc_tx_bw, refill, max, max_frame); 336 return ixgbe_dcb_hw_ets_config(hw, refill, max, 337 bwg_id, prio_type, ets->prio_tc); 338 } 339 340 s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw, 341 u16 *refill, u16 *max, u8 *bwg_id, 342 u8 *prio_type, u8 *prio_tc) 343 { 344 switch (hw->mac.type) { 345 case ixgbe_mac_82598EB: 346 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, 347 prio_type); 348 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, 349 bwg_id, prio_type); 350 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, 351 bwg_id, prio_type); 352 break; 353 case ixgbe_mac_82599EB: 354 case ixgbe_mac_X540: 355 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, 356 bwg_id, prio_type, prio_tc); 357 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, 358 bwg_id, prio_type); 359 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, 360 prio_type, prio_tc); 361 break; 362 default: 363 break; 364 } 365 return 0; 366 } 367