1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/pci.h> 30 #include <linux/delay.h> 31 #include <linux/sched.h> 32 #include <linux/netdevice.h> 33 34 #include "ixgbe.h" 35 #include "ixgbe_common.h" 36 #include "ixgbe_phy.h" 37 38 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 39 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 40 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 41 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 42 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 43 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 44 u16 count); 45 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 46 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 47 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 48 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 49 50 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 51 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg); 52 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 53 u16 words, u16 *data); 54 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 55 u16 words, u16 *data); 56 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 57 u16 offset); 58 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw); 59 60 /* Base table for registers values that change by MAC */ 61 const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = { 62 IXGBE_MVALS_INIT(8259X) 63 }; 64 65 /** 66 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow 67 * control 68 * @hw: pointer to hardware structure 69 * 70 * There are several phys that do not support autoneg flow control. This 71 * function check the device id to see if the associated phy supports 72 * autoneg flow control. 73 **/ 74 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 75 { 76 bool supported = false; 77 ixgbe_link_speed speed; 78 bool link_up; 79 80 switch (hw->phy.media_type) { 81 case ixgbe_media_type_fiber: 82 hw->mac.ops.check_link(hw, &speed, &link_up, false); 83 /* if link is down, assume supported */ 84 if (link_up) 85 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? 86 true : false; 87 else 88 supported = true; 89 break; 90 case ixgbe_media_type_backplane: 91 supported = true; 92 break; 93 case ixgbe_media_type_copper: 94 /* only some copper devices support flow control autoneg */ 95 switch (hw->device_id) { 96 case IXGBE_DEV_ID_82599_T3_LOM: 97 case IXGBE_DEV_ID_X540T: 98 case IXGBE_DEV_ID_X540T1: 99 case IXGBE_DEV_ID_X550T: 100 case IXGBE_DEV_ID_X550T1: 101 case IXGBE_DEV_ID_X550EM_X_10G_T: 102 case IXGBE_DEV_ID_X550EM_A_10G_T: 103 case IXGBE_DEV_ID_X550EM_A_1G_T: 104 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 105 supported = true; 106 break; 107 default: 108 break; 109 } 110 default: 111 break; 112 } 113 114 return supported; 115 } 116 117 /** 118 * ixgbe_setup_fc_generic - Set up flow control 119 * @hw: pointer to hardware structure 120 * 121 * Called at init time to set up flow control. 122 **/ 123 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) 124 { 125 s32 ret_val = 0; 126 u32 reg = 0, reg_bp = 0; 127 u16 reg_cu = 0; 128 bool locked = false; 129 130 /* 131 * Validate the requested mode. Strict IEEE mode does not allow 132 * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 133 */ 134 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 135 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 136 return IXGBE_ERR_INVALID_LINK_SETTINGS; 137 } 138 139 /* 140 * 10gig parts do not have a word in the EEPROM to determine the 141 * default flow control setting, so we explicitly set it to full. 142 */ 143 if (hw->fc.requested_mode == ixgbe_fc_default) 144 hw->fc.requested_mode = ixgbe_fc_full; 145 146 /* 147 * Set up the 1G and 10G flow control advertisement registers so the 148 * HW will be able to do fc autoneg once the cable is plugged in. If 149 * we link at 10G, the 1G advertisement is harmless and vice versa. 150 */ 151 switch (hw->phy.media_type) { 152 case ixgbe_media_type_backplane: 153 /* some MAC's need RMW protection on AUTOC */ 154 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 155 if (ret_val) 156 return ret_val; 157 158 /* only backplane uses autoc so fall though */ 159 case ixgbe_media_type_fiber: 160 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 161 162 break; 163 case ixgbe_media_type_copper: 164 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 165 MDIO_MMD_AN, ®_cu); 166 break; 167 default: 168 break; 169 } 170 171 /* 172 * The possible values of fc.requested_mode are: 173 * 0: Flow control is completely disabled 174 * 1: Rx flow control is enabled (we can receive pause frames, 175 * but not send pause frames). 176 * 2: Tx flow control is enabled (we can send pause frames but 177 * we do not support receiving pause frames). 178 * 3: Both Rx and Tx flow control (symmetric) are enabled. 179 * other: Invalid. 180 */ 181 switch (hw->fc.requested_mode) { 182 case ixgbe_fc_none: 183 /* Flow control completely disabled by software override. */ 184 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 185 if (hw->phy.media_type == ixgbe_media_type_backplane) 186 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 187 IXGBE_AUTOC_ASM_PAUSE); 188 else if (hw->phy.media_type == ixgbe_media_type_copper) 189 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 190 break; 191 case ixgbe_fc_tx_pause: 192 /* 193 * Tx Flow control is enabled, and Rx Flow control is 194 * disabled by software override. 195 */ 196 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 197 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 198 if (hw->phy.media_type == ixgbe_media_type_backplane) { 199 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 200 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 201 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 202 reg_cu |= IXGBE_TAF_ASM_PAUSE; 203 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 204 } 205 break; 206 case ixgbe_fc_rx_pause: 207 /* 208 * Rx Flow control is enabled and Tx Flow control is 209 * disabled by software override. Since there really 210 * isn't a way to advertise that we are capable of RX 211 * Pause ONLY, we will advertise that we support both 212 * symmetric and asymmetric Rx PAUSE, as such we fall 213 * through to the fc_full statement. Later, we will 214 * disable the adapter's ability to send PAUSE frames. 215 */ 216 case ixgbe_fc_full: 217 /* Flow control (both Rx and Tx) is enabled by SW override. */ 218 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 219 if (hw->phy.media_type == ixgbe_media_type_backplane) 220 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 221 IXGBE_AUTOC_ASM_PAUSE; 222 else if (hw->phy.media_type == ixgbe_media_type_copper) 223 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 224 break; 225 default: 226 hw_dbg(hw, "Flow control param set incorrectly\n"); 227 return IXGBE_ERR_CONFIG; 228 } 229 230 if (hw->mac.type != ixgbe_mac_X540) { 231 /* 232 * Enable auto-negotiation between the MAC & PHY; 233 * the MAC will advertise clause 37 flow control. 234 */ 235 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 236 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 237 238 /* Disable AN timeout */ 239 if (hw->fc.strict_ieee) 240 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 241 242 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 243 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); 244 } 245 246 /* 247 * AUTOC restart handles negotiation of 1G and 10G on backplane 248 * and copper. There is no need to set the PCS1GCTL register. 249 * 250 */ 251 if (hw->phy.media_type == ixgbe_media_type_backplane) { 252 /* Need the SW/FW semaphore around AUTOC writes if 82599 and 253 * LESM is on, likewise reset_pipeline requries the lock as 254 * it also writes AUTOC. 255 */ 256 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 257 if (ret_val) 258 return ret_val; 259 260 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 261 ixgbe_device_supports_autoneg_fc(hw)) { 262 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 263 MDIO_MMD_AN, reg_cu); 264 } 265 266 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); 267 return ret_val; 268 } 269 270 /** 271 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 272 * @hw: pointer to hardware structure 273 * 274 * Starts the hardware by filling the bus info structure and media type, clears 275 * all on chip counters, initializes receive address registers, multicast 276 * table, VLAN filter table, calls routine to set up link and flow control 277 * settings, and leaves transmit and receive units disabled and uninitialized 278 **/ 279 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 280 { 281 s32 ret_val; 282 u32 ctrl_ext; 283 u16 device_caps; 284 285 /* Set the media type */ 286 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 287 288 /* Identify the PHY */ 289 hw->phy.ops.identify(hw); 290 291 /* Clear the VLAN filter table */ 292 hw->mac.ops.clear_vfta(hw); 293 294 /* Clear statistics registers */ 295 hw->mac.ops.clear_hw_cntrs(hw); 296 297 /* Set No Snoop Disable */ 298 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 299 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 300 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 301 IXGBE_WRITE_FLUSH(hw); 302 303 /* Setup flow control if method for doing so */ 304 if (hw->mac.ops.setup_fc) { 305 ret_val = hw->mac.ops.setup_fc(hw); 306 if (ret_val) 307 return ret_val; 308 } 309 310 /* Cashe bit indicating need for crosstalk fix */ 311 switch (hw->mac.type) { 312 case ixgbe_mac_82599EB: 313 case ixgbe_mac_X550EM_x: 314 case ixgbe_mac_x550em_a: 315 hw->mac.ops.get_device_caps(hw, &device_caps); 316 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) 317 hw->need_crosstalk_fix = false; 318 else 319 hw->need_crosstalk_fix = true; 320 break; 321 default: 322 hw->need_crosstalk_fix = false; 323 break; 324 } 325 326 /* Clear adapter stopped flag */ 327 hw->adapter_stopped = false; 328 329 return 0; 330 } 331 332 /** 333 * ixgbe_start_hw_gen2 - Init sequence for common device family 334 * @hw: pointer to hw structure 335 * 336 * Performs the init sequence common to the second generation 337 * of 10 GbE devices. 338 * Devices in the second generation: 339 * 82599 340 * X540 341 **/ 342 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 343 { 344 u32 i; 345 346 /* Clear the rate limiters */ 347 for (i = 0; i < hw->mac.max_tx_queues; i++) { 348 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 349 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 350 } 351 IXGBE_WRITE_FLUSH(hw); 352 353 #ifndef CONFIG_ARCH_WANT_RELAX_ORDER 354 /* Disable relaxed ordering */ 355 for (i = 0; i < hw->mac.max_tx_queues; i++) { 356 u32 regval; 357 358 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 359 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 360 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 361 } 362 363 for (i = 0; i < hw->mac.max_rx_queues; i++) { 364 u32 regval; 365 366 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 367 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 368 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 369 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 370 } 371 #endif 372 return 0; 373 } 374 375 /** 376 * ixgbe_init_hw_generic - Generic hardware initialization 377 * @hw: pointer to hardware structure 378 * 379 * Initialize the hardware by resetting the hardware, filling the bus info 380 * structure and media type, clears all on chip counters, initializes receive 381 * address registers, multicast table, VLAN filter table, calls routine to set 382 * up link and flow control settings, and leaves transmit and receive units 383 * disabled and uninitialized 384 **/ 385 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 386 { 387 s32 status; 388 389 /* Reset the hardware */ 390 status = hw->mac.ops.reset_hw(hw); 391 392 if (status == 0) { 393 /* Start the HW */ 394 status = hw->mac.ops.start_hw(hw); 395 } 396 397 /* Initialize the LED link active for LED blink support */ 398 hw->mac.ops.init_led_link_act(hw); 399 400 return status; 401 } 402 403 /** 404 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 405 * @hw: pointer to hardware structure 406 * 407 * Clears all hardware statistics counters by reading them from the hardware 408 * Statistics counters are clear on read. 409 **/ 410 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 411 { 412 u16 i = 0; 413 414 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 415 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 416 IXGBE_READ_REG(hw, IXGBE_ERRBC); 417 IXGBE_READ_REG(hw, IXGBE_MSPDC); 418 for (i = 0; i < 8; i++) 419 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 420 421 IXGBE_READ_REG(hw, IXGBE_MLFC); 422 IXGBE_READ_REG(hw, IXGBE_MRFC); 423 IXGBE_READ_REG(hw, IXGBE_RLEC); 424 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 425 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 426 if (hw->mac.type >= ixgbe_mac_82599EB) { 427 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 428 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 429 } else { 430 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 431 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 432 } 433 434 for (i = 0; i < 8; i++) { 435 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 436 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 437 if (hw->mac.type >= ixgbe_mac_82599EB) { 438 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 439 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 440 } else { 441 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 442 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 443 } 444 } 445 if (hw->mac.type >= ixgbe_mac_82599EB) 446 for (i = 0; i < 8; i++) 447 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 448 IXGBE_READ_REG(hw, IXGBE_PRC64); 449 IXGBE_READ_REG(hw, IXGBE_PRC127); 450 IXGBE_READ_REG(hw, IXGBE_PRC255); 451 IXGBE_READ_REG(hw, IXGBE_PRC511); 452 IXGBE_READ_REG(hw, IXGBE_PRC1023); 453 IXGBE_READ_REG(hw, IXGBE_PRC1522); 454 IXGBE_READ_REG(hw, IXGBE_GPRC); 455 IXGBE_READ_REG(hw, IXGBE_BPRC); 456 IXGBE_READ_REG(hw, IXGBE_MPRC); 457 IXGBE_READ_REG(hw, IXGBE_GPTC); 458 IXGBE_READ_REG(hw, IXGBE_GORCL); 459 IXGBE_READ_REG(hw, IXGBE_GORCH); 460 IXGBE_READ_REG(hw, IXGBE_GOTCL); 461 IXGBE_READ_REG(hw, IXGBE_GOTCH); 462 if (hw->mac.type == ixgbe_mac_82598EB) 463 for (i = 0; i < 8; i++) 464 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 465 IXGBE_READ_REG(hw, IXGBE_RUC); 466 IXGBE_READ_REG(hw, IXGBE_RFC); 467 IXGBE_READ_REG(hw, IXGBE_ROC); 468 IXGBE_READ_REG(hw, IXGBE_RJC); 469 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 470 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 471 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 472 IXGBE_READ_REG(hw, IXGBE_TORL); 473 IXGBE_READ_REG(hw, IXGBE_TORH); 474 IXGBE_READ_REG(hw, IXGBE_TPR); 475 IXGBE_READ_REG(hw, IXGBE_TPT); 476 IXGBE_READ_REG(hw, IXGBE_PTC64); 477 IXGBE_READ_REG(hw, IXGBE_PTC127); 478 IXGBE_READ_REG(hw, IXGBE_PTC255); 479 IXGBE_READ_REG(hw, IXGBE_PTC511); 480 IXGBE_READ_REG(hw, IXGBE_PTC1023); 481 IXGBE_READ_REG(hw, IXGBE_PTC1522); 482 IXGBE_READ_REG(hw, IXGBE_MPTC); 483 IXGBE_READ_REG(hw, IXGBE_BPTC); 484 for (i = 0; i < 16; i++) { 485 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 486 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 487 if (hw->mac.type >= ixgbe_mac_82599EB) { 488 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 489 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 490 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 491 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 492 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 493 } else { 494 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 495 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 496 } 497 } 498 499 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { 500 if (hw->phy.id == 0) 501 hw->phy.ops.identify(hw); 502 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i); 503 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i); 504 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i); 505 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i); 506 } 507 508 return 0; 509 } 510 511 /** 512 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 513 * @hw: pointer to hardware structure 514 * @pba_num: stores the part number string from the EEPROM 515 * @pba_num_size: part number string buffer length 516 * 517 * Reads the part number string from the EEPROM. 518 **/ 519 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 520 u32 pba_num_size) 521 { 522 s32 ret_val; 523 u16 data; 524 u16 pba_ptr; 525 u16 offset; 526 u16 length; 527 528 if (pba_num == NULL) { 529 hw_dbg(hw, "PBA string buffer was null\n"); 530 return IXGBE_ERR_INVALID_ARGUMENT; 531 } 532 533 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 534 if (ret_val) { 535 hw_dbg(hw, "NVM Read Error\n"); 536 return ret_val; 537 } 538 539 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 540 if (ret_val) { 541 hw_dbg(hw, "NVM Read Error\n"); 542 return ret_val; 543 } 544 545 /* 546 * if data is not ptr guard the PBA must be in legacy format which 547 * means pba_ptr is actually our second data word for the PBA number 548 * and we can decode it into an ascii string 549 */ 550 if (data != IXGBE_PBANUM_PTR_GUARD) { 551 hw_dbg(hw, "NVM PBA number is not stored as string\n"); 552 553 /* we will need 11 characters to store the PBA */ 554 if (pba_num_size < 11) { 555 hw_dbg(hw, "PBA string buffer too small\n"); 556 return IXGBE_ERR_NO_SPACE; 557 } 558 559 /* extract hex string from data and pba_ptr */ 560 pba_num[0] = (data >> 12) & 0xF; 561 pba_num[1] = (data >> 8) & 0xF; 562 pba_num[2] = (data >> 4) & 0xF; 563 pba_num[3] = data & 0xF; 564 pba_num[4] = (pba_ptr >> 12) & 0xF; 565 pba_num[5] = (pba_ptr >> 8) & 0xF; 566 pba_num[6] = '-'; 567 pba_num[7] = 0; 568 pba_num[8] = (pba_ptr >> 4) & 0xF; 569 pba_num[9] = pba_ptr & 0xF; 570 571 /* put a null character on the end of our string */ 572 pba_num[10] = '\0'; 573 574 /* switch all the data but the '-' to hex char */ 575 for (offset = 0; offset < 10; offset++) { 576 if (pba_num[offset] < 0xA) 577 pba_num[offset] += '0'; 578 else if (pba_num[offset] < 0x10) 579 pba_num[offset] += 'A' - 0xA; 580 } 581 582 return 0; 583 } 584 585 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 586 if (ret_val) { 587 hw_dbg(hw, "NVM Read Error\n"); 588 return ret_val; 589 } 590 591 if (length == 0xFFFF || length == 0) { 592 hw_dbg(hw, "NVM PBA number section invalid length\n"); 593 return IXGBE_ERR_PBA_SECTION; 594 } 595 596 /* check if pba_num buffer is big enough */ 597 if (pba_num_size < (((u32)length * 2) - 1)) { 598 hw_dbg(hw, "PBA string buffer too small\n"); 599 return IXGBE_ERR_NO_SPACE; 600 } 601 602 /* trim pba length from start of string */ 603 pba_ptr++; 604 length--; 605 606 for (offset = 0; offset < length; offset++) { 607 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 608 if (ret_val) { 609 hw_dbg(hw, "NVM Read Error\n"); 610 return ret_val; 611 } 612 pba_num[offset * 2] = (u8)(data >> 8); 613 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 614 } 615 pba_num[offset * 2] = '\0'; 616 617 return 0; 618 } 619 620 /** 621 * ixgbe_get_mac_addr_generic - Generic get MAC address 622 * @hw: pointer to hardware structure 623 * @mac_addr: Adapter MAC address 624 * 625 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 626 * A reset of the adapter must be performed prior to calling this function 627 * in order for the MAC address to have been loaded from the EEPROM into RAR0 628 **/ 629 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 630 { 631 u32 rar_high; 632 u32 rar_low; 633 u16 i; 634 635 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 636 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 637 638 for (i = 0; i < 4; i++) 639 mac_addr[i] = (u8)(rar_low >> (i*8)); 640 641 for (i = 0; i < 2; i++) 642 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 643 644 return 0; 645 } 646 647 enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status) 648 { 649 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 650 case IXGBE_PCI_LINK_WIDTH_1: 651 return ixgbe_bus_width_pcie_x1; 652 case IXGBE_PCI_LINK_WIDTH_2: 653 return ixgbe_bus_width_pcie_x2; 654 case IXGBE_PCI_LINK_WIDTH_4: 655 return ixgbe_bus_width_pcie_x4; 656 case IXGBE_PCI_LINK_WIDTH_8: 657 return ixgbe_bus_width_pcie_x8; 658 default: 659 return ixgbe_bus_width_unknown; 660 } 661 } 662 663 enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status) 664 { 665 switch (link_status & IXGBE_PCI_LINK_SPEED) { 666 case IXGBE_PCI_LINK_SPEED_2500: 667 return ixgbe_bus_speed_2500; 668 case IXGBE_PCI_LINK_SPEED_5000: 669 return ixgbe_bus_speed_5000; 670 case IXGBE_PCI_LINK_SPEED_8000: 671 return ixgbe_bus_speed_8000; 672 default: 673 return ixgbe_bus_speed_unknown; 674 } 675 } 676 677 /** 678 * ixgbe_get_bus_info_generic - Generic set PCI bus info 679 * @hw: pointer to hardware structure 680 * 681 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 682 **/ 683 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 684 { 685 u16 link_status; 686 687 hw->bus.type = ixgbe_bus_type_pci_express; 688 689 /* Get the negotiated link width and speed from PCI config space */ 690 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS); 691 692 hw->bus.width = ixgbe_convert_bus_width(link_status); 693 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 694 695 hw->mac.ops.set_lan_id(hw); 696 697 return 0; 698 } 699 700 /** 701 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 702 * @hw: pointer to the HW structure 703 * 704 * Determines the LAN function id by reading memory-mapped registers 705 * and swaps the port value if requested. 706 **/ 707 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 708 { 709 struct ixgbe_bus_info *bus = &hw->bus; 710 u16 ee_ctrl_4; 711 u32 reg; 712 713 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 714 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 715 bus->lan_id = bus->func; 716 717 /* check for a port swap */ 718 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); 719 if (reg & IXGBE_FACTPS_LFS) 720 bus->func ^= 0x1; 721 722 /* Get MAC instance from EEPROM for configuring CS4227 */ 723 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { 724 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); 725 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> 726 IXGBE_EE_CTRL_4_INST_ID_SHIFT; 727 } 728 } 729 730 /** 731 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 732 * @hw: pointer to hardware structure 733 * 734 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 735 * disables transmit and receive units. The adapter_stopped flag is used by 736 * the shared code and drivers to determine if the adapter is in a stopped 737 * state and should not touch the hardware. 738 **/ 739 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 740 { 741 u32 reg_val; 742 u16 i; 743 744 /* 745 * Set the adapter_stopped flag so other driver functions stop touching 746 * the hardware 747 */ 748 hw->adapter_stopped = true; 749 750 /* Disable the receive unit */ 751 hw->mac.ops.disable_rx(hw); 752 753 /* Clear interrupt mask to stop interrupts from being generated */ 754 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 755 756 /* Clear any pending interrupts, flush previous writes */ 757 IXGBE_READ_REG(hw, IXGBE_EICR); 758 759 /* Disable the transmit unit. Each queue must be disabled. */ 760 for (i = 0; i < hw->mac.max_tx_queues; i++) 761 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 762 763 /* Disable the receive unit by stopping each queue */ 764 for (i = 0; i < hw->mac.max_rx_queues; i++) { 765 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 766 reg_val &= ~IXGBE_RXDCTL_ENABLE; 767 reg_val |= IXGBE_RXDCTL_SWFLSH; 768 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 769 } 770 771 /* flush all queues disables */ 772 IXGBE_WRITE_FLUSH(hw); 773 usleep_range(1000, 2000); 774 775 /* 776 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 777 * access and verify no pending requests 778 */ 779 return ixgbe_disable_pcie_master(hw); 780 } 781 782 /** 783 * ixgbe_init_led_link_act_generic - Store the LED index link/activity. 784 * @hw: pointer to hardware structure 785 * 786 * Store the index for the link active LED. This will be used to support 787 * blinking the LED. 788 **/ 789 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) 790 { 791 struct ixgbe_mac_info *mac = &hw->mac; 792 u32 led_reg, led_mode; 793 u16 i; 794 795 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 796 797 /* Get LED link active from the LEDCTL register */ 798 for (i = 0; i < 4; i++) { 799 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i); 800 801 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) == 802 IXGBE_LED_LINK_ACTIVE) { 803 mac->led_link_act = i; 804 return 0; 805 } 806 } 807 808 /* If LEDCTL register does not have the LED link active set, then use 809 * known MAC defaults. 810 */ 811 switch (hw->mac.type) { 812 case ixgbe_mac_x550em_a: 813 mac->led_link_act = 0; 814 break; 815 case ixgbe_mac_X550EM_x: 816 mac->led_link_act = 1; 817 break; 818 default: 819 mac->led_link_act = 2; 820 } 821 822 return 0; 823 } 824 825 /** 826 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 827 * @hw: pointer to hardware structure 828 * @index: led number to turn on 829 **/ 830 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 831 { 832 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 833 834 if (index > 3) 835 return IXGBE_ERR_PARAM; 836 837 /* To turn on the LED, set mode to ON. */ 838 led_reg &= ~IXGBE_LED_MODE_MASK(index); 839 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 840 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 841 IXGBE_WRITE_FLUSH(hw); 842 843 return 0; 844 } 845 846 /** 847 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 848 * @hw: pointer to hardware structure 849 * @index: led number to turn off 850 **/ 851 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 852 { 853 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 854 855 if (index > 3) 856 return IXGBE_ERR_PARAM; 857 858 /* To turn off the LED, set mode to OFF. */ 859 led_reg &= ~IXGBE_LED_MODE_MASK(index); 860 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 861 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 862 IXGBE_WRITE_FLUSH(hw); 863 864 return 0; 865 } 866 867 /** 868 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 869 * @hw: pointer to hardware structure 870 * 871 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 872 * ixgbe_hw struct in order to set up EEPROM access. 873 **/ 874 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 875 { 876 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 877 u32 eec; 878 u16 eeprom_size; 879 880 if (eeprom->type == ixgbe_eeprom_uninitialized) { 881 eeprom->type = ixgbe_eeprom_none; 882 /* Set default semaphore delay to 10ms which is a well 883 * tested value */ 884 eeprom->semaphore_delay = 10; 885 /* Clear EEPROM page size, it will be initialized as needed */ 886 eeprom->word_page_size = 0; 887 888 /* 889 * Check for EEPROM present first. 890 * If not present leave as none 891 */ 892 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 893 if (eec & IXGBE_EEC_PRES) { 894 eeprom->type = ixgbe_eeprom_spi; 895 896 /* 897 * SPI EEPROM is assumed here. This code would need to 898 * change if a future EEPROM is not SPI. 899 */ 900 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 901 IXGBE_EEC_SIZE_SHIFT); 902 eeprom->word_size = BIT(eeprom_size + 903 IXGBE_EEPROM_WORD_SIZE_SHIFT); 904 } 905 906 if (eec & IXGBE_EEC_ADDR_SIZE) 907 eeprom->address_bits = 16; 908 else 909 eeprom->address_bits = 8; 910 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n", 911 eeprom->type, eeprom->word_size, eeprom->address_bits); 912 } 913 914 return 0; 915 } 916 917 /** 918 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 919 * @hw: pointer to hardware structure 920 * @offset: offset within the EEPROM to write 921 * @words: number of words 922 * @data: 16 bit word(s) to write to EEPROM 923 * 924 * Reads 16 bit word(s) from EEPROM through bit-bang method 925 **/ 926 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 927 u16 words, u16 *data) 928 { 929 s32 status; 930 u16 i, count; 931 932 hw->eeprom.ops.init_params(hw); 933 934 if (words == 0) 935 return IXGBE_ERR_INVALID_ARGUMENT; 936 937 if (offset + words > hw->eeprom.word_size) 938 return IXGBE_ERR_EEPROM; 939 940 /* 941 * The EEPROM page size cannot be queried from the chip. We do lazy 942 * initialization. It is worth to do that when we write large buffer. 943 */ 944 if ((hw->eeprom.word_page_size == 0) && 945 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 946 ixgbe_detect_eeprom_page_size_generic(hw, offset); 947 948 /* 949 * We cannot hold synchronization semaphores for too long 950 * to avoid other entity starvation. However it is more efficient 951 * to read in bursts than synchronizing access for each word. 952 */ 953 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 954 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 955 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 956 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 957 count, &data[i]); 958 959 if (status != 0) 960 break; 961 } 962 963 return status; 964 } 965 966 /** 967 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 968 * @hw: pointer to hardware structure 969 * @offset: offset within the EEPROM to be written to 970 * @words: number of word(s) 971 * @data: 16 bit word(s) to be written to the EEPROM 972 * 973 * If ixgbe_eeprom_update_checksum is not called after this function, the 974 * EEPROM will most likely contain an invalid checksum. 975 **/ 976 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 977 u16 words, u16 *data) 978 { 979 s32 status; 980 u16 word; 981 u16 page_size; 982 u16 i; 983 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 984 985 /* Prepare the EEPROM for writing */ 986 status = ixgbe_acquire_eeprom(hw); 987 if (status) 988 return status; 989 990 if (ixgbe_ready_eeprom(hw) != 0) { 991 ixgbe_release_eeprom(hw); 992 return IXGBE_ERR_EEPROM; 993 } 994 995 for (i = 0; i < words; i++) { 996 ixgbe_standby_eeprom(hw); 997 998 /* Send the WRITE ENABLE command (8 bit opcode) */ 999 ixgbe_shift_out_eeprom_bits(hw, 1000 IXGBE_EEPROM_WREN_OPCODE_SPI, 1001 IXGBE_EEPROM_OPCODE_BITS); 1002 1003 ixgbe_standby_eeprom(hw); 1004 1005 /* Some SPI eeproms use the 8th address bit embedded 1006 * in the opcode 1007 */ 1008 if ((hw->eeprom.address_bits == 8) && 1009 ((offset + i) >= 128)) 1010 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1011 1012 /* Send the Write command (8-bit opcode + addr) */ 1013 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 1014 IXGBE_EEPROM_OPCODE_BITS); 1015 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1016 hw->eeprom.address_bits); 1017 1018 page_size = hw->eeprom.word_page_size; 1019 1020 /* Send the data in burst via SPI */ 1021 do { 1022 word = data[i]; 1023 word = (word >> 8) | (word << 8); 1024 ixgbe_shift_out_eeprom_bits(hw, word, 16); 1025 1026 if (page_size == 0) 1027 break; 1028 1029 /* do not wrap around page */ 1030 if (((offset + i) & (page_size - 1)) == 1031 (page_size - 1)) 1032 break; 1033 } while (++i < words); 1034 1035 ixgbe_standby_eeprom(hw); 1036 usleep_range(10000, 20000); 1037 } 1038 /* Done with writing - release the EEPROM */ 1039 ixgbe_release_eeprom(hw); 1040 1041 return 0; 1042 } 1043 1044 /** 1045 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1046 * @hw: pointer to hardware structure 1047 * @offset: offset within the EEPROM to be written to 1048 * @data: 16 bit word to be written to the EEPROM 1049 * 1050 * If ixgbe_eeprom_update_checksum is not called after this function, the 1051 * EEPROM will most likely contain an invalid checksum. 1052 **/ 1053 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1054 { 1055 hw->eeprom.ops.init_params(hw); 1056 1057 if (offset >= hw->eeprom.word_size) 1058 return IXGBE_ERR_EEPROM; 1059 1060 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1061 } 1062 1063 /** 1064 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1065 * @hw: pointer to hardware structure 1066 * @offset: offset within the EEPROM to be read 1067 * @words: number of word(s) 1068 * @data: read 16 bit words(s) from EEPROM 1069 * 1070 * Reads 16 bit word(s) from EEPROM through bit-bang method 1071 **/ 1072 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1073 u16 words, u16 *data) 1074 { 1075 s32 status; 1076 u16 i, count; 1077 1078 hw->eeprom.ops.init_params(hw); 1079 1080 if (words == 0) 1081 return IXGBE_ERR_INVALID_ARGUMENT; 1082 1083 if (offset + words > hw->eeprom.word_size) 1084 return IXGBE_ERR_EEPROM; 1085 1086 /* 1087 * We cannot hold synchronization semaphores for too long 1088 * to avoid other entity starvation. However it is more efficient 1089 * to read in bursts than synchronizing access for each word. 1090 */ 1091 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1092 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1093 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1094 1095 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1096 count, &data[i]); 1097 1098 if (status) 1099 return status; 1100 } 1101 1102 return 0; 1103 } 1104 1105 /** 1106 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1107 * @hw: pointer to hardware structure 1108 * @offset: offset within the EEPROM to be read 1109 * @words: number of word(s) 1110 * @data: read 16 bit word(s) from EEPROM 1111 * 1112 * Reads 16 bit word(s) from EEPROM through bit-bang method 1113 **/ 1114 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1115 u16 words, u16 *data) 1116 { 1117 s32 status; 1118 u16 word_in; 1119 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1120 u16 i; 1121 1122 /* Prepare the EEPROM for reading */ 1123 status = ixgbe_acquire_eeprom(hw); 1124 if (status) 1125 return status; 1126 1127 if (ixgbe_ready_eeprom(hw) != 0) { 1128 ixgbe_release_eeprom(hw); 1129 return IXGBE_ERR_EEPROM; 1130 } 1131 1132 for (i = 0; i < words; i++) { 1133 ixgbe_standby_eeprom(hw); 1134 /* Some SPI eeproms use the 8th address bit embedded 1135 * in the opcode 1136 */ 1137 if ((hw->eeprom.address_bits == 8) && 1138 ((offset + i) >= 128)) 1139 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1140 1141 /* Send the READ command (opcode + addr) */ 1142 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1143 IXGBE_EEPROM_OPCODE_BITS); 1144 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1145 hw->eeprom.address_bits); 1146 1147 /* Read the data. */ 1148 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1149 data[i] = (word_in >> 8) | (word_in << 8); 1150 } 1151 1152 /* End this read operation */ 1153 ixgbe_release_eeprom(hw); 1154 1155 return 0; 1156 } 1157 1158 /** 1159 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1160 * @hw: pointer to hardware structure 1161 * @offset: offset within the EEPROM to be read 1162 * @data: read 16 bit value from EEPROM 1163 * 1164 * Reads 16 bit value from EEPROM through bit-bang method 1165 **/ 1166 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1167 u16 *data) 1168 { 1169 hw->eeprom.ops.init_params(hw); 1170 1171 if (offset >= hw->eeprom.word_size) 1172 return IXGBE_ERR_EEPROM; 1173 1174 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1175 } 1176 1177 /** 1178 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1179 * @hw: pointer to hardware structure 1180 * @offset: offset of word in the EEPROM to read 1181 * @words: number of word(s) 1182 * @data: 16 bit word(s) from the EEPROM 1183 * 1184 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1185 **/ 1186 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1187 u16 words, u16 *data) 1188 { 1189 u32 eerd; 1190 s32 status; 1191 u32 i; 1192 1193 hw->eeprom.ops.init_params(hw); 1194 1195 if (words == 0) 1196 return IXGBE_ERR_INVALID_ARGUMENT; 1197 1198 if (offset >= hw->eeprom.word_size) 1199 return IXGBE_ERR_EEPROM; 1200 1201 for (i = 0; i < words; i++) { 1202 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1203 IXGBE_EEPROM_RW_REG_START; 1204 1205 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1206 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1207 1208 if (status == 0) { 1209 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1210 IXGBE_EEPROM_RW_REG_DATA); 1211 } else { 1212 hw_dbg(hw, "Eeprom read timed out\n"); 1213 return status; 1214 } 1215 } 1216 1217 return 0; 1218 } 1219 1220 /** 1221 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1222 * @hw: pointer to hardware structure 1223 * @offset: offset within the EEPROM to be used as a scratch pad 1224 * 1225 * Discover EEPROM page size by writing marching data at given offset. 1226 * This function is called only when we are writing a new large buffer 1227 * at given offset so the data would be overwritten anyway. 1228 **/ 1229 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1230 u16 offset) 1231 { 1232 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1233 s32 status; 1234 u16 i; 1235 1236 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1237 data[i] = i; 1238 1239 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1240 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1241 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1242 hw->eeprom.word_page_size = 0; 1243 if (status) 1244 return status; 1245 1246 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1247 if (status) 1248 return status; 1249 1250 /* 1251 * When writing in burst more than the actual page size 1252 * EEPROM address wraps around current page. 1253 */ 1254 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1255 1256 hw_dbg(hw, "Detected EEPROM page size = %d words.\n", 1257 hw->eeprom.word_page_size); 1258 return 0; 1259 } 1260 1261 /** 1262 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1263 * @hw: pointer to hardware structure 1264 * @offset: offset of word in the EEPROM to read 1265 * @data: word read from the EEPROM 1266 * 1267 * Reads a 16 bit word from the EEPROM using the EERD register. 1268 **/ 1269 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1270 { 1271 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1272 } 1273 1274 /** 1275 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1276 * @hw: pointer to hardware structure 1277 * @offset: offset of word in the EEPROM to write 1278 * @words: number of words 1279 * @data: word(s) write to the EEPROM 1280 * 1281 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1282 **/ 1283 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1284 u16 words, u16 *data) 1285 { 1286 u32 eewr; 1287 s32 status; 1288 u16 i; 1289 1290 hw->eeprom.ops.init_params(hw); 1291 1292 if (words == 0) 1293 return IXGBE_ERR_INVALID_ARGUMENT; 1294 1295 if (offset >= hw->eeprom.word_size) 1296 return IXGBE_ERR_EEPROM; 1297 1298 for (i = 0; i < words; i++) { 1299 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1300 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1301 IXGBE_EEPROM_RW_REG_START; 1302 1303 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1304 if (status) { 1305 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1306 return status; 1307 } 1308 1309 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1310 1311 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1312 if (status) { 1313 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1314 return status; 1315 } 1316 } 1317 1318 return 0; 1319 } 1320 1321 /** 1322 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1323 * @hw: pointer to hardware structure 1324 * @offset: offset of word in the EEPROM to write 1325 * @data: word write to the EEPROM 1326 * 1327 * Write a 16 bit word to the EEPROM using the EEWR register. 1328 **/ 1329 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1330 { 1331 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1332 } 1333 1334 /** 1335 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1336 * @hw: pointer to hardware structure 1337 * @ee_reg: EEPROM flag for polling 1338 * 1339 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1340 * read or write is done respectively. 1341 **/ 1342 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1343 { 1344 u32 i; 1345 u32 reg; 1346 1347 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1348 if (ee_reg == IXGBE_NVM_POLL_READ) 1349 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1350 else 1351 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1352 1353 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1354 return 0; 1355 } 1356 udelay(5); 1357 } 1358 return IXGBE_ERR_EEPROM; 1359 } 1360 1361 /** 1362 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1363 * @hw: pointer to hardware structure 1364 * 1365 * Prepares EEPROM for access using bit-bang method. This function should 1366 * be called before issuing a command to the EEPROM. 1367 **/ 1368 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1369 { 1370 u32 eec; 1371 u32 i; 1372 1373 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) 1374 return IXGBE_ERR_SWFW_SYNC; 1375 1376 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1377 1378 /* Request EEPROM Access */ 1379 eec |= IXGBE_EEC_REQ; 1380 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1381 1382 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1383 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1384 if (eec & IXGBE_EEC_GNT) 1385 break; 1386 udelay(5); 1387 } 1388 1389 /* Release if grant not acquired */ 1390 if (!(eec & IXGBE_EEC_GNT)) { 1391 eec &= ~IXGBE_EEC_REQ; 1392 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1393 hw_dbg(hw, "Could not acquire EEPROM grant\n"); 1394 1395 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1396 return IXGBE_ERR_EEPROM; 1397 } 1398 1399 /* Setup EEPROM for Read/Write */ 1400 /* Clear CS and SK */ 1401 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1402 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1403 IXGBE_WRITE_FLUSH(hw); 1404 udelay(1); 1405 return 0; 1406 } 1407 1408 /** 1409 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1410 * @hw: pointer to hardware structure 1411 * 1412 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1413 **/ 1414 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1415 { 1416 u32 timeout = 2000; 1417 u32 i; 1418 u32 swsm; 1419 1420 /* Get SMBI software semaphore between device drivers first */ 1421 for (i = 0; i < timeout; i++) { 1422 /* 1423 * If the SMBI bit is 0 when we read it, then the bit will be 1424 * set and we have the semaphore 1425 */ 1426 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1427 if (!(swsm & IXGBE_SWSM_SMBI)) 1428 break; 1429 usleep_range(50, 100); 1430 } 1431 1432 if (i == timeout) { 1433 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n"); 1434 /* this release is particularly important because our attempts 1435 * above to get the semaphore may have succeeded, and if there 1436 * was a timeout, we should unconditionally clear the semaphore 1437 * bits to free the driver to make progress 1438 */ 1439 ixgbe_release_eeprom_semaphore(hw); 1440 1441 usleep_range(50, 100); 1442 /* one last try 1443 * If the SMBI bit is 0 when we read it, then the bit will be 1444 * set and we have the semaphore 1445 */ 1446 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1447 if (swsm & IXGBE_SWSM_SMBI) { 1448 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n"); 1449 return IXGBE_ERR_EEPROM; 1450 } 1451 } 1452 1453 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1454 for (i = 0; i < timeout; i++) { 1455 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1456 1457 /* Set the SW EEPROM semaphore bit to request access */ 1458 swsm |= IXGBE_SWSM_SWESMBI; 1459 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); 1460 1461 /* If we set the bit successfully then we got the 1462 * semaphore. 1463 */ 1464 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1465 if (swsm & IXGBE_SWSM_SWESMBI) 1466 break; 1467 1468 usleep_range(50, 100); 1469 } 1470 1471 /* Release semaphores and return error if SW EEPROM semaphore 1472 * was not granted because we don't have access to the EEPROM 1473 */ 1474 if (i >= timeout) { 1475 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n"); 1476 ixgbe_release_eeprom_semaphore(hw); 1477 return IXGBE_ERR_EEPROM; 1478 } 1479 1480 return 0; 1481 } 1482 1483 /** 1484 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1485 * @hw: pointer to hardware structure 1486 * 1487 * This function clears hardware semaphore bits. 1488 **/ 1489 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1490 { 1491 u32 swsm; 1492 1493 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1494 1495 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1496 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1497 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); 1498 IXGBE_WRITE_FLUSH(hw); 1499 } 1500 1501 /** 1502 * ixgbe_ready_eeprom - Polls for EEPROM ready 1503 * @hw: pointer to hardware structure 1504 **/ 1505 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1506 { 1507 u16 i; 1508 u8 spi_stat_reg; 1509 1510 /* 1511 * Read "Status Register" repeatedly until the LSB is cleared. The 1512 * EEPROM will signal that the command has been completed by clearing 1513 * bit 0 of the internal status register. If it's not cleared within 1514 * 5 milliseconds, then error out. 1515 */ 1516 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 1517 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1518 IXGBE_EEPROM_OPCODE_BITS); 1519 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 1520 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 1521 break; 1522 1523 udelay(5); 1524 ixgbe_standby_eeprom(hw); 1525 } 1526 1527 /* 1528 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 1529 * devices (and only 0-5mSec on 5V devices) 1530 */ 1531 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 1532 hw_dbg(hw, "SPI EEPROM Status error\n"); 1533 return IXGBE_ERR_EEPROM; 1534 } 1535 1536 return 0; 1537 } 1538 1539 /** 1540 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 1541 * @hw: pointer to hardware structure 1542 **/ 1543 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 1544 { 1545 u32 eec; 1546 1547 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1548 1549 /* Toggle CS to flush commands */ 1550 eec |= IXGBE_EEC_CS; 1551 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1552 IXGBE_WRITE_FLUSH(hw); 1553 udelay(1); 1554 eec &= ~IXGBE_EEC_CS; 1555 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1556 IXGBE_WRITE_FLUSH(hw); 1557 udelay(1); 1558 } 1559 1560 /** 1561 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 1562 * @hw: pointer to hardware structure 1563 * @data: data to send to the EEPROM 1564 * @count: number of bits to shift out 1565 **/ 1566 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 1567 u16 count) 1568 { 1569 u32 eec; 1570 u32 mask; 1571 u32 i; 1572 1573 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1574 1575 /* 1576 * Mask is used to shift "count" bits of "data" out to the EEPROM 1577 * one bit at a time. Determine the starting bit based on count 1578 */ 1579 mask = BIT(count - 1); 1580 1581 for (i = 0; i < count; i++) { 1582 /* 1583 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 1584 * "1", and then raising and then lowering the clock (the SK 1585 * bit controls the clock input to the EEPROM). A "0" is 1586 * shifted out to the EEPROM by setting "DI" to "0" and then 1587 * raising and then lowering the clock. 1588 */ 1589 if (data & mask) 1590 eec |= IXGBE_EEC_DI; 1591 else 1592 eec &= ~IXGBE_EEC_DI; 1593 1594 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1595 IXGBE_WRITE_FLUSH(hw); 1596 1597 udelay(1); 1598 1599 ixgbe_raise_eeprom_clk(hw, &eec); 1600 ixgbe_lower_eeprom_clk(hw, &eec); 1601 1602 /* 1603 * Shift mask to signify next bit of data to shift in to the 1604 * EEPROM 1605 */ 1606 mask = mask >> 1; 1607 } 1608 1609 /* We leave the "DI" bit set to "0" when we leave this routine. */ 1610 eec &= ~IXGBE_EEC_DI; 1611 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1612 IXGBE_WRITE_FLUSH(hw); 1613 } 1614 1615 /** 1616 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 1617 * @hw: pointer to hardware structure 1618 **/ 1619 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 1620 { 1621 u32 eec; 1622 u32 i; 1623 u16 data = 0; 1624 1625 /* 1626 * In order to read a register from the EEPROM, we need to shift 1627 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 1628 * the clock input to the EEPROM (setting the SK bit), and then reading 1629 * the value of the "DO" bit. During this "shifting in" process the 1630 * "DI" bit should always be clear. 1631 */ 1632 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1633 1634 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 1635 1636 for (i = 0; i < count; i++) { 1637 data = data << 1; 1638 ixgbe_raise_eeprom_clk(hw, &eec); 1639 1640 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1641 1642 eec &= ~(IXGBE_EEC_DI); 1643 if (eec & IXGBE_EEC_DO) 1644 data |= 1; 1645 1646 ixgbe_lower_eeprom_clk(hw, &eec); 1647 } 1648 1649 return data; 1650 } 1651 1652 /** 1653 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1654 * @hw: pointer to hardware structure 1655 * @eec: EEC register's current value 1656 **/ 1657 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1658 { 1659 /* 1660 * Raise the clock input to the EEPROM 1661 * (setting the SK bit), then delay 1662 */ 1663 *eec = *eec | IXGBE_EEC_SK; 1664 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); 1665 IXGBE_WRITE_FLUSH(hw); 1666 udelay(1); 1667 } 1668 1669 /** 1670 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1671 * @hw: pointer to hardware structure 1672 * @eecd: EECD's current value 1673 **/ 1674 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1675 { 1676 /* 1677 * Lower the clock input to the EEPROM (clearing the SK bit), then 1678 * delay 1679 */ 1680 *eec = *eec & ~IXGBE_EEC_SK; 1681 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); 1682 IXGBE_WRITE_FLUSH(hw); 1683 udelay(1); 1684 } 1685 1686 /** 1687 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1688 * @hw: pointer to hardware structure 1689 **/ 1690 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 1691 { 1692 u32 eec; 1693 1694 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1695 1696 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1697 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1698 1699 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1700 IXGBE_WRITE_FLUSH(hw); 1701 1702 udelay(1); 1703 1704 /* Stop requesting EEPROM access */ 1705 eec &= ~IXGBE_EEC_REQ; 1706 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1707 1708 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1709 1710 /* 1711 * Delay before attempt to obtain semaphore again to allow FW 1712 * access. semaphore_delay is in ms we need us for usleep_range 1713 */ 1714 usleep_range(hw->eeprom.semaphore_delay * 1000, 1715 hw->eeprom.semaphore_delay * 2000); 1716 } 1717 1718 /** 1719 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 1720 * @hw: pointer to hardware structure 1721 **/ 1722 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 1723 { 1724 u16 i; 1725 u16 j; 1726 u16 checksum = 0; 1727 u16 length = 0; 1728 u16 pointer = 0; 1729 u16 word = 0; 1730 1731 /* Include 0x0-0x3F in the checksum */ 1732 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1733 if (hw->eeprom.ops.read(hw, i, &word)) { 1734 hw_dbg(hw, "EEPROM read failed\n"); 1735 break; 1736 } 1737 checksum += word; 1738 } 1739 1740 /* Include all data from pointers except for the fw pointer */ 1741 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1742 if (hw->eeprom.ops.read(hw, i, &pointer)) { 1743 hw_dbg(hw, "EEPROM read failed\n"); 1744 return IXGBE_ERR_EEPROM; 1745 } 1746 1747 /* If the pointer seems invalid */ 1748 if (pointer == 0xFFFF || pointer == 0) 1749 continue; 1750 1751 if (hw->eeprom.ops.read(hw, pointer, &length)) { 1752 hw_dbg(hw, "EEPROM read failed\n"); 1753 return IXGBE_ERR_EEPROM; 1754 } 1755 1756 if (length == 0xFFFF || length == 0) 1757 continue; 1758 1759 for (j = pointer + 1; j <= pointer + length; j++) { 1760 if (hw->eeprom.ops.read(hw, j, &word)) { 1761 hw_dbg(hw, "EEPROM read failed\n"); 1762 return IXGBE_ERR_EEPROM; 1763 } 1764 checksum += word; 1765 } 1766 } 1767 1768 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1769 1770 return (s32)checksum; 1771 } 1772 1773 /** 1774 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1775 * @hw: pointer to hardware structure 1776 * @checksum_val: calculated checksum 1777 * 1778 * Performs checksum calculation and validates the EEPROM checksum. If the 1779 * caller does not need checksum_val, the value can be NULL. 1780 **/ 1781 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1782 u16 *checksum_val) 1783 { 1784 s32 status; 1785 u16 checksum; 1786 u16 read_checksum = 0; 1787 1788 /* 1789 * Read the first word from the EEPROM. If this times out or fails, do 1790 * not continue or we could be in for a very long wait while every 1791 * EEPROM read fails 1792 */ 1793 status = hw->eeprom.ops.read(hw, 0, &checksum); 1794 if (status) { 1795 hw_dbg(hw, "EEPROM read failed\n"); 1796 return status; 1797 } 1798 1799 status = hw->eeprom.ops.calc_checksum(hw); 1800 if (status < 0) 1801 return status; 1802 1803 checksum = (u16)(status & 0xffff); 1804 1805 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1806 if (status) { 1807 hw_dbg(hw, "EEPROM read failed\n"); 1808 return status; 1809 } 1810 1811 /* Verify read checksum from EEPROM is the same as 1812 * calculated checksum 1813 */ 1814 if (read_checksum != checksum) 1815 status = IXGBE_ERR_EEPROM_CHECKSUM; 1816 1817 /* If the user cares, return the calculated checksum */ 1818 if (checksum_val) 1819 *checksum_val = checksum; 1820 1821 return status; 1822 } 1823 1824 /** 1825 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1826 * @hw: pointer to hardware structure 1827 **/ 1828 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1829 { 1830 s32 status; 1831 u16 checksum; 1832 1833 /* 1834 * Read the first word from the EEPROM. If this times out or fails, do 1835 * not continue or we could be in for a very long wait while every 1836 * EEPROM read fails 1837 */ 1838 status = hw->eeprom.ops.read(hw, 0, &checksum); 1839 if (status) { 1840 hw_dbg(hw, "EEPROM read failed\n"); 1841 return status; 1842 } 1843 1844 status = hw->eeprom.ops.calc_checksum(hw); 1845 if (status < 0) 1846 return status; 1847 1848 checksum = (u16)(status & 0xffff); 1849 1850 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 1851 1852 return status; 1853 } 1854 1855 /** 1856 * ixgbe_set_rar_generic - Set Rx address register 1857 * @hw: pointer to hardware structure 1858 * @index: Receive address register to write 1859 * @addr: Address to put into receive address register 1860 * @vmdq: VMDq "set" or "pool" index 1861 * @enable_addr: set flag that address is active 1862 * 1863 * Puts an ethernet address into a receive address register. 1864 **/ 1865 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1866 u32 enable_addr) 1867 { 1868 u32 rar_low, rar_high; 1869 u32 rar_entries = hw->mac.num_rar_entries; 1870 1871 /* Make sure we are using a valid rar index range */ 1872 if (index >= rar_entries) { 1873 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1874 return IXGBE_ERR_INVALID_ARGUMENT; 1875 } 1876 1877 /* setup VMDq pool selection before this RAR gets enabled */ 1878 hw->mac.ops.set_vmdq(hw, index, vmdq); 1879 1880 /* 1881 * HW expects these in little endian so we reverse the byte 1882 * order from network order (big endian) to little endian 1883 */ 1884 rar_low = ((u32)addr[0] | 1885 ((u32)addr[1] << 8) | 1886 ((u32)addr[2] << 16) | 1887 ((u32)addr[3] << 24)); 1888 /* 1889 * Some parts put the VMDq setting in the extra RAH bits, 1890 * so save everything except the lower 16 bits that hold part 1891 * of the address and the address valid bit. 1892 */ 1893 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1894 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1895 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1896 1897 if (enable_addr != 0) 1898 rar_high |= IXGBE_RAH_AV; 1899 1900 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1901 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1902 1903 return 0; 1904 } 1905 1906 /** 1907 * ixgbe_clear_rar_generic - Remove Rx address register 1908 * @hw: pointer to hardware structure 1909 * @index: Receive address register to write 1910 * 1911 * Clears an ethernet address from a receive address register. 1912 **/ 1913 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1914 { 1915 u32 rar_high; 1916 u32 rar_entries = hw->mac.num_rar_entries; 1917 1918 /* Make sure we are using a valid rar index range */ 1919 if (index >= rar_entries) { 1920 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1921 return IXGBE_ERR_INVALID_ARGUMENT; 1922 } 1923 1924 /* 1925 * Some parts put the VMDq setting in the extra RAH bits, 1926 * so save everything except the lower 16 bits that hold part 1927 * of the address and the address valid bit. 1928 */ 1929 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1930 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1931 1932 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1933 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1934 1935 /* clear VMDq pool/queue selection for this RAR */ 1936 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1937 1938 return 0; 1939 } 1940 1941 /** 1942 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1943 * @hw: pointer to hardware structure 1944 * 1945 * Places the MAC address in receive address register 0 and clears the rest 1946 * of the receive address registers. Clears the multicast table. Assumes 1947 * the receiver is in reset when the routine is called. 1948 **/ 1949 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1950 { 1951 u32 i; 1952 u32 rar_entries = hw->mac.num_rar_entries; 1953 1954 /* 1955 * If the current mac address is valid, assume it is a software override 1956 * to the permanent address. 1957 * Otherwise, use the permanent address from the eeprom. 1958 */ 1959 if (!is_valid_ether_addr(hw->mac.addr)) { 1960 /* Get the MAC address from the RAR0 for later reference */ 1961 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1962 1963 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr); 1964 } else { 1965 /* Setup the receive address. */ 1966 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); 1967 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr); 1968 1969 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1970 } 1971 1972 /* clear VMDq pool/queue selection for RAR 0 */ 1973 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 1974 1975 hw->addr_ctrl.overflow_promisc = 0; 1976 1977 hw->addr_ctrl.rar_used_count = 1; 1978 1979 /* Zero out the other receive addresses. */ 1980 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); 1981 for (i = 1; i < rar_entries; i++) { 1982 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1983 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1984 } 1985 1986 /* Clear the MTA */ 1987 hw->addr_ctrl.mta_in_use = 0; 1988 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1989 1990 hw_dbg(hw, " Clearing MTA\n"); 1991 for (i = 0; i < hw->mac.mcft_size; i++) 1992 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1993 1994 if (hw->mac.ops.init_uta_tables) 1995 hw->mac.ops.init_uta_tables(hw); 1996 1997 return 0; 1998 } 1999 2000 /** 2001 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 2002 * @hw: pointer to hardware structure 2003 * @mc_addr: the multicast address 2004 * 2005 * Extracts the 12 bits, from a multicast address, to determine which 2006 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 2007 * incoming rx multicast addresses, to determine the bit-vector to check in 2008 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 2009 * by the MO field of the MCSTCTRL. The MO field is set during initialization 2010 * to mc_filter_type. 2011 **/ 2012 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 2013 { 2014 u32 vector = 0; 2015 2016 switch (hw->mac.mc_filter_type) { 2017 case 0: /* use bits [47:36] of the address */ 2018 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 2019 break; 2020 case 1: /* use bits [46:35] of the address */ 2021 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 2022 break; 2023 case 2: /* use bits [45:34] of the address */ 2024 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 2025 break; 2026 case 3: /* use bits [43:32] of the address */ 2027 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 2028 break; 2029 default: /* Invalid mc_filter_type */ 2030 hw_dbg(hw, "MC filter type param set incorrectly\n"); 2031 break; 2032 } 2033 2034 /* vector can only be 12-bits or boundary will be exceeded */ 2035 vector &= 0xFFF; 2036 return vector; 2037 } 2038 2039 /** 2040 * ixgbe_set_mta - Set bit-vector in multicast table 2041 * @hw: pointer to hardware structure 2042 * @hash_value: Multicast address hash value 2043 * 2044 * Sets the bit-vector in the multicast table. 2045 **/ 2046 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2047 { 2048 u32 vector; 2049 u32 vector_bit; 2050 u32 vector_reg; 2051 2052 hw->addr_ctrl.mta_in_use++; 2053 2054 vector = ixgbe_mta_vector(hw, mc_addr); 2055 hw_dbg(hw, " bit-vector = 0x%03X\n", vector); 2056 2057 /* 2058 * The MTA is a register array of 128 32-bit registers. It is treated 2059 * like an array of 4096 bits. We want to set bit 2060 * BitArray[vector_value]. So we figure out what register the bit is 2061 * in, read it, OR in the new bit, then write back the new value. The 2062 * register is determined by the upper 7 bits of the vector value and 2063 * the bit within that register are determined by the lower 5 bits of 2064 * the value. 2065 */ 2066 vector_reg = (vector >> 5) & 0x7F; 2067 vector_bit = vector & 0x1F; 2068 hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit); 2069 } 2070 2071 /** 2072 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2073 * @hw: pointer to hardware structure 2074 * @netdev: pointer to net device structure 2075 * 2076 * The given list replaces any existing list. Clears the MC addrs from receive 2077 * address registers and the multicast table. Uses unused receive address 2078 * registers for the first multicast addresses, and hashes the rest into the 2079 * multicast table. 2080 **/ 2081 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, 2082 struct net_device *netdev) 2083 { 2084 struct netdev_hw_addr *ha; 2085 u32 i; 2086 2087 /* 2088 * Set the new number of MC addresses that we are being requested to 2089 * use. 2090 */ 2091 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); 2092 hw->addr_ctrl.mta_in_use = 0; 2093 2094 /* Clear mta_shadow */ 2095 hw_dbg(hw, " Clearing MTA\n"); 2096 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2097 2098 /* Update mta shadow */ 2099 netdev_for_each_mc_addr(ha, netdev) { 2100 hw_dbg(hw, " Adding the multicast addresses:\n"); 2101 ixgbe_set_mta(hw, ha->addr); 2102 } 2103 2104 /* Enable mta */ 2105 for (i = 0; i < hw->mac.mcft_size; i++) 2106 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2107 hw->mac.mta_shadow[i]); 2108 2109 if (hw->addr_ctrl.mta_in_use > 0) 2110 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2111 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2112 2113 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); 2114 return 0; 2115 } 2116 2117 /** 2118 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2119 * @hw: pointer to hardware structure 2120 * 2121 * Enables multicast address in RAR and the use of the multicast hash table. 2122 **/ 2123 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2124 { 2125 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2126 2127 if (a->mta_in_use > 0) 2128 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2129 hw->mac.mc_filter_type); 2130 2131 return 0; 2132 } 2133 2134 /** 2135 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2136 * @hw: pointer to hardware structure 2137 * 2138 * Disables multicast address in RAR and the use of the multicast hash table. 2139 **/ 2140 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2141 { 2142 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2143 2144 if (a->mta_in_use > 0) 2145 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2146 2147 return 0; 2148 } 2149 2150 /** 2151 * ixgbe_fc_enable_generic - Enable flow control 2152 * @hw: pointer to hardware structure 2153 * 2154 * Enable flow control according to the current settings. 2155 **/ 2156 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2157 { 2158 u32 mflcn_reg, fccfg_reg; 2159 u32 reg; 2160 u32 fcrtl, fcrth; 2161 int i; 2162 2163 /* Validate the water mark configuration. */ 2164 if (!hw->fc.pause_time) 2165 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2166 2167 /* Low water mark of zero causes XOFF floods */ 2168 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 2169 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2170 hw->fc.high_water[i]) { 2171 if (!hw->fc.low_water[i] || 2172 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2173 hw_dbg(hw, "Invalid water mark configuration\n"); 2174 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2175 } 2176 } 2177 } 2178 2179 /* Negotiate the fc mode to use */ 2180 hw->mac.ops.fc_autoneg(hw); 2181 2182 /* Disable any previous flow control settings */ 2183 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2184 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2185 2186 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2187 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2188 2189 /* 2190 * The possible values of fc.current_mode are: 2191 * 0: Flow control is completely disabled 2192 * 1: Rx flow control is enabled (we can receive pause frames, 2193 * but not send pause frames). 2194 * 2: Tx flow control is enabled (we can send pause frames but 2195 * we do not support receiving pause frames). 2196 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2197 * other: Invalid. 2198 */ 2199 switch (hw->fc.current_mode) { 2200 case ixgbe_fc_none: 2201 /* 2202 * Flow control is disabled by software override or autoneg. 2203 * The code below will actually disable it in the HW. 2204 */ 2205 break; 2206 case ixgbe_fc_rx_pause: 2207 /* 2208 * Rx Flow control is enabled and Tx Flow control is 2209 * disabled by software override. Since there really 2210 * isn't a way to advertise that we are capable of RX 2211 * Pause ONLY, we will advertise that we support both 2212 * symmetric and asymmetric Rx PAUSE. Later, we will 2213 * disable the adapter's ability to send PAUSE frames. 2214 */ 2215 mflcn_reg |= IXGBE_MFLCN_RFCE; 2216 break; 2217 case ixgbe_fc_tx_pause: 2218 /* 2219 * Tx Flow control is enabled, and Rx Flow control is 2220 * disabled by software override. 2221 */ 2222 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2223 break; 2224 case ixgbe_fc_full: 2225 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2226 mflcn_reg |= IXGBE_MFLCN_RFCE; 2227 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2228 break; 2229 default: 2230 hw_dbg(hw, "Flow control param set incorrectly\n"); 2231 return IXGBE_ERR_CONFIG; 2232 } 2233 2234 /* Set 802.3x based flow control settings. */ 2235 mflcn_reg |= IXGBE_MFLCN_DPF; 2236 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2237 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2238 2239 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2240 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 2241 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2242 hw->fc.high_water[i]) { 2243 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2244 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2245 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2246 } else { 2247 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2248 /* 2249 * In order to prevent Tx hangs when the internal Tx 2250 * switch is enabled we must set the high water mark 2251 * to the Rx packet buffer size - 24KB. This allows 2252 * the Tx switch to function even under heavy Rx 2253 * workloads. 2254 */ 2255 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2256 } 2257 2258 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2259 } 2260 2261 /* Configure pause time (2 TCs per register) */ 2262 reg = hw->fc.pause_time * 0x00010001; 2263 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 2264 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2265 2266 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2267 2268 return 0; 2269 } 2270 2271 /** 2272 * ixgbe_negotiate_fc - Negotiate flow control 2273 * @hw: pointer to hardware structure 2274 * @adv_reg: flow control advertised settings 2275 * @lp_reg: link partner's flow control settings 2276 * @adv_sym: symmetric pause bit in advertisement 2277 * @adv_asm: asymmetric pause bit in advertisement 2278 * @lp_sym: symmetric pause bit in link partner advertisement 2279 * @lp_asm: asymmetric pause bit in link partner advertisement 2280 * 2281 * Find the intersection between advertised settings and link partner's 2282 * advertised settings 2283 **/ 2284 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2285 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2286 { 2287 if ((!(adv_reg)) || (!(lp_reg))) 2288 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2289 2290 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2291 /* 2292 * Now we need to check if the user selected Rx ONLY 2293 * of pause frames. In this case, we had to advertise 2294 * FULL flow control because we could not advertise RX 2295 * ONLY. Hence, we must now check to see if we need to 2296 * turn OFF the TRANSMISSION of PAUSE frames. 2297 */ 2298 if (hw->fc.requested_mode == ixgbe_fc_full) { 2299 hw->fc.current_mode = ixgbe_fc_full; 2300 hw_dbg(hw, "Flow Control = FULL.\n"); 2301 } else { 2302 hw->fc.current_mode = ixgbe_fc_rx_pause; 2303 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n"); 2304 } 2305 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2306 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2307 hw->fc.current_mode = ixgbe_fc_tx_pause; 2308 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); 2309 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2310 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2311 hw->fc.current_mode = ixgbe_fc_rx_pause; 2312 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); 2313 } else { 2314 hw->fc.current_mode = ixgbe_fc_none; 2315 hw_dbg(hw, "Flow Control = NONE.\n"); 2316 } 2317 return 0; 2318 } 2319 2320 /** 2321 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 2322 * @hw: pointer to hardware structure 2323 * 2324 * Enable flow control according on 1 gig fiber. 2325 **/ 2326 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 2327 { 2328 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 2329 s32 ret_val; 2330 2331 /* 2332 * On multispeed fiber at 1g, bail out if 2333 * - link is up but AN did not complete, or if 2334 * - link is up and AN completed but timed out 2335 */ 2336 2337 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 2338 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 2339 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) 2340 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2341 2342 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2343 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 2344 2345 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 2346 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 2347 IXGBE_PCS1GANA_ASM_PAUSE, 2348 IXGBE_PCS1GANA_SYM_PAUSE, 2349 IXGBE_PCS1GANA_ASM_PAUSE); 2350 2351 return ret_val; 2352 } 2353 2354 /** 2355 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 2356 * @hw: pointer to hardware structure 2357 * 2358 * Enable flow control according to IEEE clause 37. 2359 **/ 2360 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 2361 { 2362 u32 links2, anlp1_reg, autoc_reg, links; 2363 s32 ret_val; 2364 2365 /* 2366 * On backplane, bail out if 2367 * - backplane autoneg was not completed, or if 2368 * - we are 82599 and link partner is not AN enabled 2369 */ 2370 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 2371 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) 2372 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2373 2374 if (hw->mac.type == ixgbe_mac_82599EB) { 2375 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 2376 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) 2377 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2378 } 2379 /* 2380 * Read the 10g AN autoc and LP ability registers and resolve 2381 * local flow control settings accordingly 2382 */ 2383 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2384 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2385 2386 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 2387 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 2388 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 2389 2390 return ret_val; 2391 } 2392 2393 /** 2394 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 2395 * @hw: pointer to hardware structure 2396 * 2397 * Enable flow control according to IEEE clause 37. 2398 **/ 2399 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 2400 { 2401 u16 technology_ability_reg = 0; 2402 u16 lp_technology_ability_reg = 0; 2403 2404 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 2405 MDIO_MMD_AN, 2406 &technology_ability_reg); 2407 hw->phy.ops.read_reg(hw, MDIO_AN_LPA, 2408 MDIO_MMD_AN, 2409 &lp_technology_ability_reg); 2410 2411 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 2412 (u32)lp_technology_ability_reg, 2413 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 2414 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 2415 } 2416 2417 /** 2418 * ixgbe_fc_autoneg - Configure flow control 2419 * @hw: pointer to hardware structure 2420 * 2421 * Compares our advertised flow control capabilities to those advertised by 2422 * our link partner, and determines the proper flow control mode to use. 2423 **/ 2424 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 2425 { 2426 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2427 ixgbe_link_speed speed; 2428 bool link_up; 2429 2430 /* 2431 * AN should have completed when the cable was plugged in. 2432 * Look for reasons to bail out. Bail out if: 2433 * - FC autoneg is disabled, or if 2434 * - link is not up. 2435 * 2436 * Since we're being called from an LSC, link is already known to be up. 2437 * So use link_up_wait_to_complete=false. 2438 */ 2439 if (hw->fc.disable_fc_autoneg) 2440 goto out; 2441 2442 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2443 if (!link_up) 2444 goto out; 2445 2446 switch (hw->phy.media_type) { 2447 /* Autoneg flow control on fiber adapters */ 2448 case ixgbe_media_type_fiber: 2449 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 2450 ret_val = ixgbe_fc_autoneg_fiber(hw); 2451 break; 2452 2453 /* Autoneg flow control on backplane adapters */ 2454 case ixgbe_media_type_backplane: 2455 ret_val = ixgbe_fc_autoneg_backplane(hw); 2456 break; 2457 2458 /* Autoneg flow control on copper adapters */ 2459 case ixgbe_media_type_copper: 2460 if (ixgbe_device_supports_autoneg_fc(hw)) 2461 ret_val = ixgbe_fc_autoneg_copper(hw); 2462 break; 2463 2464 default: 2465 break; 2466 } 2467 2468 out: 2469 if (ret_val == 0) { 2470 hw->fc.fc_was_autonegged = true; 2471 } else { 2472 hw->fc.fc_was_autonegged = false; 2473 hw->fc.current_mode = hw->fc.requested_mode; 2474 } 2475 } 2476 2477 /** 2478 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 2479 * @hw: pointer to hardware structure 2480 * 2481 * System-wide timeout range is encoded in PCIe Device Control2 register. 2482 * 2483 * Add 10% to specified maximum and return the number of times to poll for 2484 * completion timeout, in units of 100 microsec. Never return less than 2485 * 800 = 80 millisec. 2486 **/ 2487 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 2488 { 2489 s16 devctl2; 2490 u32 pollcnt; 2491 2492 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); 2493 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 2494 2495 switch (devctl2) { 2496 case IXGBE_PCIDEVCTRL2_65_130ms: 2497 pollcnt = 1300; /* 130 millisec */ 2498 break; 2499 case IXGBE_PCIDEVCTRL2_260_520ms: 2500 pollcnt = 5200; /* 520 millisec */ 2501 break; 2502 case IXGBE_PCIDEVCTRL2_1_2s: 2503 pollcnt = 20000; /* 2 sec */ 2504 break; 2505 case IXGBE_PCIDEVCTRL2_4_8s: 2506 pollcnt = 80000; /* 8 sec */ 2507 break; 2508 case IXGBE_PCIDEVCTRL2_17_34s: 2509 pollcnt = 34000; /* 34 sec */ 2510 break; 2511 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 2512 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 2513 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 2514 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 2515 default: 2516 pollcnt = 800; /* 80 millisec minimum */ 2517 break; 2518 } 2519 2520 /* add 10% to spec maximum */ 2521 return (pollcnt * 11) / 10; 2522 } 2523 2524 /** 2525 * ixgbe_disable_pcie_master - Disable PCI-express master access 2526 * @hw: pointer to hardware structure 2527 * 2528 * Disables PCI-Express master access and verifies there are no pending 2529 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 2530 * bit hasn't caused the master requests to be disabled, else 0 2531 * is returned signifying master requests disabled. 2532 **/ 2533 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 2534 { 2535 u32 i, poll; 2536 u16 value; 2537 2538 /* Always set this bit to ensure any future transactions are blocked */ 2539 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 2540 2541 /* Poll for bit to read as set */ 2542 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2543 if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS) 2544 break; 2545 usleep_range(100, 120); 2546 } 2547 if (i >= IXGBE_PCI_MASTER_DISABLE_TIMEOUT) { 2548 hw_dbg(hw, "GIO disable did not set - requesting resets\n"); 2549 goto gio_disable_fail; 2550 } 2551 2552 /* Exit if master requests are blocked */ 2553 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 2554 ixgbe_removed(hw->hw_addr)) 2555 return 0; 2556 2557 /* Poll for master request bit to clear */ 2558 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2559 udelay(100); 2560 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2561 return 0; 2562 } 2563 2564 /* 2565 * Two consecutive resets are required via CTRL.RST per datasheet 2566 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 2567 * of this need. The first reset prevents new master requests from 2568 * being issued by our device. We then must wait 1usec or more for any 2569 * remaining completions from the PCIe bus to trickle in, and then reset 2570 * again to clear out any effects they may have had on our device. 2571 */ 2572 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n"); 2573 gio_disable_fail: 2574 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2575 2576 if (hw->mac.type >= ixgbe_mac_X550) 2577 return 0; 2578 2579 /* 2580 * Before proceeding, make sure that the PCIe block does not have 2581 * transactions pending. 2582 */ 2583 poll = ixgbe_pcie_timeout_poll(hw); 2584 for (i = 0; i < poll; i++) { 2585 udelay(100); 2586 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); 2587 if (ixgbe_removed(hw->hw_addr)) 2588 return 0; 2589 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 2590 return 0; 2591 } 2592 2593 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n"); 2594 return IXGBE_ERR_MASTER_REQUESTS_PENDING; 2595 } 2596 2597 /** 2598 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 2599 * @hw: pointer to hardware structure 2600 * @mask: Mask to specify which semaphore to acquire 2601 * 2602 * Acquires the SWFW semaphore through the GSSR register for the specified 2603 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2604 **/ 2605 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 2606 { 2607 u32 gssr = 0; 2608 u32 swmask = mask; 2609 u32 fwmask = mask << 5; 2610 u32 timeout = 200; 2611 u32 i; 2612 2613 for (i = 0; i < timeout; i++) { 2614 /* 2615 * SW NVM semaphore bit is used for access to all 2616 * SW_FW_SYNC bits (not just NVM) 2617 */ 2618 if (ixgbe_get_eeprom_semaphore(hw)) 2619 return IXGBE_ERR_SWFW_SYNC; 2620 2621 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2622 if (!(gssr & (fwmask | swmask))) { 2623 gssr |= swmask; 2624 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2625 ixgbe_release_eeprom_semaphore(hw); 2626 return 0; 2627 } else { 2628 /* Resource is currently in use by FW or SW */ 2629 ixgbe_release_eeprom_semaphore(hw); 2630 usleep_range(5000, 10000); 2631 } 2632 } 2633 2634 /* If time expired clear the bits holding the lock and retry */ 2635 if (gssr & (fwmask | swmask)) 2636 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 2637 2638 usleep_range(5000, 10000); 2639 return IXGBE_ERR_SWFW_SYNC; 2640 } 2641 2642 /** 2643 * ixgbe_release_swfw_sync - Release SWFW semaphore 2644 * @hw: pointer to hardware structure 2645 * @mask: Mask to specify which semaphore to release 2646 * 2647 * Releases the SWFW semaphore through the GSSR register for the specified 2648 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2649 **/ 2650 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 2651 { 2652 u32 gssr; 2653 u32 swmask = mask; 2654 2655 ixgbe_get_eeprom_semaphore(hw); 2656 2657 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2658 gssr &= ~swmask; 2659 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2660 2661 ixgbe_release_eeprom_semaphore(hw); 2662 } 2663 2664 /** 2665 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 2666 * @hw: pointer to hardware structure 2667 * @reg_val: Value we read from AUTOC 2668 * @locked: bool to indicate whether the SW/FW lock should be taken. Never 2669 * true in this the generic case. 2670 * 2671 * The default case requires no protection so just to the register read. 2672 **/ 2673 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 2674 { 2675 *locked = false; 2676 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2677 return 0; 2678 } 2679 2680 /** 2681 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 2682 * @hw: pointer to hardware structure 2683 * @reg_val: value to write to AUTOC 2684 * @locked: bool to indicate whether the SW/FW lock was already taken by 2685 * previous read. 2686 **/ 2687 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 2688 { 2689 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 2690 return 0; 2691 } 2692 2693 /** 2694 * ixgbe_disable_rx_buff_generic - Stops the receive data path 2695 * @hw: pointer to hardware structure 2696 * 2697 * Stops the receive data path and waits for the HW to internally 2698 * empty the Rx security block. 2699 **/ 2700 s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw) 2701 { 2702 #define IXGBE_MAX_SECRX_POLL 40 2703 int i; 2704 int secrxreg; 2705 2706 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2707 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 2708 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2709 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 2710 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 2711 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 2712 break; 2713 else 2714 /* Use interrupt-safe sleep just in case */ 2715 udelay(1000); 2716 } 2717 2718 /* For informational purposes only */ 2719 if (i >= IXGBE_MAX_SECRX_POLL) 2720 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n"); 2721 2722 return 0; 2723 2724 } 2725 2726 /** 2727 * ixgbe_enable_rx_buff - Enables the receive data path 2728 * @hw: pointer to hardware structure 2729 * 2730 * Enables the receive data path 2731 **/ 2732 s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw) 2733 { 2734 u32 secrxreg; 2735 2736 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2737 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 2738 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2739 IXGBE_WRITE_FLUSH(hw); 2740 2741 return 0; 2742 } 2743 2744 /** 2745 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 2746 * @hw: pointer to hardware structure 2747 * @regval: register value to write to RXCTRL 2748 * 2749 * Enables the Rx DMA unit 2750 **/ 2751 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 2752 { 2753 if (regval & IXGBE_RXCTRL_RXEN) 2754 hw->mac.ops.enable_rx(hw); 2755 else 2756 hw->mac.ops.disable_rx(hw); 2757 2758 return 0; 2759 } 2760 2761 /** 2762 * ixgbe_blink_led_start_generic - Blink LED based on index. 2763 * @hw: pointer to hardware structure 2764 * @index: led number to blink 2765 **/ 2766 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 2767 { 2768 ixgbe_link_speed speed = 0; 2769 bool link_up = false; 2770 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2771 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2772 bool locked = false; 2773 s32 ret_val; 2774 2775 if (index > 3) 2776 return IXGBE_ERR_PARAM; 2777 2778 /* 2779 * Link must be up to auto-blink the LEDs; 2780 * Force it if link is down. 2781 */ 2782 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2783 2784 if (!link_up) { 2785 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 2786 if (ret_val) 2787 return ret_val; 2788 2789 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2790 autoc_reg |= IXGBE_AUTOC_FLU; 2791 2792 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 2793 if (ret_val) 2794 return ret_val; 2795 2796 IXGBE_WRITE_FLUSH(hw); 2797 2798 usleep_range(10000, 20000); 2799 } 2800 2801 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2802 led_reg |= IXGBE_LED_BLINK(index); 2803 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2804 IXGBE_WRITE_FLUSH(hw); 2805 2806 return 0; 2807 } 2808 2809 /** 2810 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 2811 * @hw: pointer to hardware structure 2812 * @index: led number to stop blinking 2813 **/ 2814 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 2815 { 2816 u32 autoc_reg = 0; 2817 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2818 bool locked = false; 2819 s32 ret_val; 2820 2821 if (index > 3) 2822 return IXGBE_ERR_PARAM; 2823 2824 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 2825 if (ret_val) 2826 return ret_val; 2827 2828 autoc_reg &= ~IXGBE_AUTOC_FLU; 2829 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2830 2831 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 2832 if (ret_val) 2833 return ret_val; 2834 2835 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2836 led_reg &= ~IXGBE_LED_BLINK(index); 2837 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 2838 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2839 IXGBE_WRITE_FLUSH(hw); 2840 2841 return 0; 2842 } 2843 2844 /** 2845 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 2846 * @hw: pointer to hardware structure 2847 * @san_mac_offset: SAN MAC address offset 2848 * 2849 * This function will read the EEPROM location for the SAN MAC address 2850 * pointer, and returns the value at that location. This is used in both 2851 * get and set mac_addr routines. 2852 **/ 2853 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 2854 u16 *san_mac_offset) 2855 { 2856 s32 ret_val; 2857 2858 /* 2859 * First read the EEPROM pointer to see if the MAC addresses are 2860 * available. 2861 */ 2862 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 2863 san_mac_offset); 2864 if (ret_val) 2865 hw_err(hw, "eeprom read at offset %d failed\n", 2866 IXGBE_SAN_MAC_ADDR_PTR); 2867 2868 return ret_val; 2869 } 2870 2871 /** 2872 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 2873 * @hw: pointer to hardware structure 2874 * @san_mac_addr: SAN MAC address 2875 * 2876 * Reads the SAN MAC address from the EEPROM, if it's available. This is 2877 * per-port, so set_lan_id() must be called before reading the addresses. 2878 * set_lan_id() is called by identify_sfp(), but this cannot be relied 2879 * upon for non-SFP connections, so we must call it here. 2880 **/ 2881 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2882 { 2883 u16 san_mac_data, san_mac_offset; 2884 u8 i; 2885 s32 ret_val; 2886 2887 /* 2888 * First read the EEPROM pointer to see if the MAC addresses are 2889 * available. If they're not, no point in calling set_lan_id() here. 2890 */ 2891 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2892 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 2893 2894 goto san_mac_addr_clr; 2895 2896 /* make sure we know which port we need to program */ 2897 hw->mac.ops.set_lan_id(hw); 2898 /* apply the port offset to the address offset */ 2899 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2900 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2901 for (i = 0; i < 3; i++) { 2902 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 2903 &san_mac_data); 2904 if (ret_val) { 2905 hw_err(hw, "eeprom read at offset %d failed\n", 2906 san_mac_offset); 2907 goto san_mac_addr_clr; 2908 } 2909 san_mac_addr[i * 2] = (u8)(san_mac_data); 2910 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 2911 san_mac_offset++; 2912 } 2913 return 0; 2914 2915 san_mac_addr_clr: 2916 /* No addresses available in this EEPROM. It's not necessarily an 2917 * error though, so just wipe the local address and return. 2918 */ 2919 for (i = 0; i < 6; i++) 2920 san_mac_addr[i] = 0xFF; 2921 return ret_val; 2922 } 2923 2924 /** 2925 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 2926 * @hw: pointer to hardware structure 2927 * 2928 * Read PCIe configuration space, and get the MSI-X vector count from 2929 * the capabilities table. 2930 **/ 2931 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 2932 { 2933 u16 msix_count; 2934 u16 max_msix_count; 2935 u16 pcie_offset; 2936 2937 switch (hw->mac.type) { 2938 case ixgbe_mac_82598EB: 2939 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 2940 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 2941 break; 2942 case ixgbe_mac_82599EB: 2943 case ixgbe_mac_X540: 2944 case ixgbe_mac_X550: 2945 case ixgbe_mac_X550EM_x: 2946 case ixgbe_mac_x550em_a: 2947 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 2948 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 2949 break; 2950 default: 2951 return 1; 2952 } 2953 2954 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset); 2955 if (ixgbe_removed(hw->hw_addr)) 2956 msix_count = 0; 2957 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 2958 2959 /* MSI-X count is zero-based in HW */ 2960 msix_count++; 2961 2962 if (msix_count > max_msix_count) 2963 msix_count = max_msix_count; 2964 2965 return msix_count; 2966 } 2967 2968 /** 2969 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 2970 * @hw: pointer to hardware struct 2971 * @rar: receive address register index to disassociate 2972 * @vmdq: VMDq pool index to remove from the rar 2973 **/ 2974 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2975 { 2976 u32 mpsar_lo, mpsar_hi; 2977 u32 rar_entries = hw->mac.num_rar_entries; 2978 2979 /* Make sure we are using a valid rar index range */ 2980 if (rar >= rar_entries) { 2981 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 2982 return IXGBE_ERR_INVALID_ARGUMENT; 2983 } 2984 2985 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2986 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2987 2988 if (ixgbe_removed(hw->hw_addr)) 2989 return 0; 2990 2991 if (!mpsar_lo && !mpsar_hi) 2992 return 0; 2993 2994 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 2995 if (mpsar_lo) { 2996 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 2997 mpsar_lo = 0; 2998 } 2999 if (mpsar_hi) { 3000 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3001 mpsar_hi = 0; 3002 } 3003 } else if (vmdq < 32) { 3004 mpsar_lo &= ~BIT(vmdq); 3005 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 3006 } else { 3007 mpsar_hi &= ~BIT(vmdq - 32); 3008 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 3009 } 3010 3011 /* was that the last pool using this rar? */ 3012 if (mpsar_lo == 0 && mpsar_hi == 0 && 3013 rar != 0 && rar != hw->mac.san_mac_rar_index) 3014 hw->mac.ops.clear_rar(hw, rar); 3015 3016 return 0; 3017 } 3018 3019 /** 3020 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 3021 * @hw: pointer to hardware struct 3022 * @rar: receive address register index to associate with a VMDq index 3023 * @vmdq: VMDq pool index 3024 **/ 3025 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3026 { 3027 u32 mpsar; 3028 u32 rar_entries = hw->mac.num_rar_entries; 3029 3030 /* Make sure we are using a valid rar index range */ 3031 if (rar >= rar_entries) { 3032 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 3033 return IXGBE_ERR_INVALID_ARGUMENT; 3034 } 3035 3036 if (vmdq < 32) { 3037 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3038 mpsar |= BIT(vmdq); 3039 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3040 } else { 3041 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3042 mpsar |= BIT(vmdq - 32); 3043 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3044 } 3045 return 0; 3046 } 3047 3048 /** 3049 * This function should only be involved in the IOV mode. 3050 * In IOV mode, Default pool is next pool after the number of 3051 * VFs advertized and not 0. 3052 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3053 * 3054 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address 3055 * @hw: pointer to hardware struct 3056 * @vmdq: VMDq pool index 3057 **/ 3058 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3059 { 3060 u32 rar = hw->mac.san_mac_rar_index; 3061 3062 if (vmdq < 32) { 3063 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq)); 3064 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3065 } else { 3066 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3067 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32)); 3068 } 3069 3070 return 0; 3071 } 3072 3073 /** 3074 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3075 * @hw: pointer to hardware structure 3076 **/ 3077 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3078 { 3079 int i; 3080 3081 for (i = 0; i < 128; i++) 3082 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3083 3084 return 0; 3085 } 3086 3087 /** 3088 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3089 * @hw: pointer to hardware structure 3090 * @vlan: VLAN id to write to VLAN filter 3091 * 3092 * return the VLVF index where this VLAN id should be placed 3093 * 3094 **/ 3095 static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) 3096 { 3097 s32 regindex, first_empty_slot; 3098 u32 bits; 3099 3100 /* short cut the special case */ 3101 if (vlan == 0) 3102 return 0; 3103 3104 /* if vlvf_bypass is set we don't want to use an empty slot, we 3105 * will simply bypass the VLVF if there are no entries present in the 3106 * VLVF that contain our VLAN 3107 */ 3108 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0; 3109 3110 /* add VLAN enable bit for comparison */ 3111 vlan |= IXGBE_VLVF_VIEN; 3112 3113 /* Search for the vlan id in the VLVF entries. Save off the first empty 3114 * slot found along the way. 3115 * 3116 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 3117 */ 3118 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { 3119 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3120 if (bits == vlan) 3121 return regindex; 3122 if (!first_empty_slot && !bits) 3123 first_empty_slot = regindex; 3124 } 3125 3126 /* If we are here then we didn't find the VLAN. Return first empty 3127 * slot we found during our search, else error. 3128 */ 3129 if (!first_empty_slot) 3130 hw_dbg(hw, "No space in VLVF.\n"); 3131 3132 return first_empty_slot ? : IXGBE_ERR_NO_SPACE; 3133 } 3134 3135 /** 3136 * ixgbe_set_vfta_generic - Set VLAN filter table 3137 * @hw: pointer to hardware structure 3138 * @vlan: VLAN id to write to VLAN filter 3139 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 3140 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 3141 * @vlvf_bypass: boolean flag indicating updating default pool is okay 3142 * 3143 * Turn on/off specified VLAN in the VLAN filter table. 3144 **/ 3145 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3146 bool vlan_on, bool vlvf_bypass) 3147 { 3148 u32 regidx, vfta_delta, vfta, bits; 3149 s32 vlvf_index; 3150 3151 if ((vlan > 4095) || (vind > 63)) 3152 return IXGBE_ERR_PARAM; 3153 3154 /* 3155 * this is a 2 part operation - first the VFTA, then the 3156 * VLVF and VLVFB if VT Mode is set 3157 * We don't write the VFTA until we know the VLVF part succeeded. 3158 */ 3159 3160 /* Part 1 3161 * The VFTA is a bitstring made up of 128 32-bit registers 3162 * that enable the particular VLAN id, much like the MTA: 3163 * bits[11-5]: which register 3164 * bits[4-0]: which bit in the register 3165 */ 3166 regidx = vlan / 32; 3167 vfta_delta = BIT(vlan % 32); 3168 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); 3169 3170 /* vfta_delta represents the difference between the current value 3171 * of vfta and the value we want in the register. Since the diff 3172 * is an XOR mask we can just update vfta using an XOR. 3173 */ 3174 vfta_delta &= vlan_on ? ~vfta : vfta; 3175 vfta ^= vfta_delta; 3176 3177 /* Part 2 3178 * If VT Mode is set 3179 * Either vlan_on 3180 * make sure the vlan is in VLVF 3181 * set the vind bit in the matching VLVFB 3182 * Or !vlan_on 3183 * clear the pool bit and possibly the vind 3184 */ 3185 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) 3186 goto vfta_update; 3187 3188 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 3189 if (vlvf_index < 0) { 3190 if (vlvf_bypass) 3191 goto vfta_update; 3192 return vlvf_index; 3193 } 3194 3195 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); 3196 3197 /* set the pool bit */ 3198 bits |= BIT(vind % 32); 3199 if (vlan_on) 3200 goto vlvf_update; 3201 3202 /* clear the pool bit */ 3203 bits ^= BIT(vind % 32); 3204 3205 if (!bits && 3206 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 3207 /* Clear VFTA first, then disable VLVF. Otherwise 3208 * we run the risk of stray packets leaking into 3209 * the PF via the default pool 3210 */ 3211 if (vfta_delta) 3212 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 3213 3214 /* disable VLVF and clear remaining bit from pool */ 3215 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 3216 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); 3217 3218 return 0; 3219 } 3220 3221 /* If there are still bits set in the VLVFB registers 3222 * for the VLAN ID indicated we need to see if the 3223 * caller is requesting that we clear the VFTA entry bit. 3224 * If the caller has requested that we clear the VFTA 3225 * entry bit but there are still pools/VFs using this VLAN 3226 * ID entry then ignore the request. We're not worried 3227 * about the case where we're turning the VFTA VLAN ID 3228 * entry bit on, only when requested to turn it off as 3229 * there may be multiple pools and/or VFs using the 3230 * VLAN ID entry. In that case we cannot clear the 3231 * VFTA bit until all pools/VFs using that VLAN ID have also 3232 * been cleared. This will be indicated by "bits" being 3233 * zero. 3234 */ 3235 vfta_delta = 0; 3236 3237 vlvf_update: 3238 /* record pool change and enable VLAN ID if not already enabled */ 3239 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); 3240 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); 3241 3242 vfta_update: 3243 /* Update VFTA now that we are ready for traffic */ 3244 if (vfta_delta) 3245 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 3246 3247 return 0; 3248 } 3249 3250 /** 3251 * ixgbe_clear_vfta_generic - Clear VLAN filter table 3252 * @hw: pointer to hardware structure 3253 * 3254 * Clears the VLAN filer table, and the VMDq index associated with the filter 3255 **/ 3256 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 3257 { 3258 u32 offset; 3259 3260 for (offset = 0; offset < hw->mac.vft_size; offset++) 3261 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 3262 3263 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 3264 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 3265 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 3266 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); 3267 } 3268 3269 return 0; 3270 } 3271 3272 /** 3273 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix 3274 * @hw: pointer to hardware structure 3275 * 3276 * Contains the logic to identify if we need to verify link for the 3277 * crosstalk fix 3278 **/ 3279 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) 3280 { 3281 /* Does FW say we need the fix */ 3282 if (!hw->need_crosstalk_fix) 3283 return false; 3284 3285 /* Only consider SFP+ PHYs i.e. media type fiber */ 3286 switch (hw->mac.ops.get_media_type(hw)) { 3287 case ixgbe_media_type_fiber: 3288 case ixgbe_media_type_fiber_qsfp: 3289 break; 3290 default: 3291 return false; 3292 } 3293 3294 return true; 3295 } 3296 3297 /** 3298 * ixgbe_check_mac_link_generic - Determine link and speed status 3299 * @hw: pointer to hardware structure 3300 * @speed: pointer to link speed 3301 * @link_up: true when link is up 3302 * @link_up_wait_to_complete: bool used to wait for link up or not 3303 * 3304 * Reads the links register to determine if link is up and the current speed 3305 **/ 3306 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3307 bool *link_up, bool link_up_wait_to_complete) 3308 { 3309 u32 links_reg, links_orig; 3310 u32 i; 3311 3312 /* If Crosstalk fix enabled do the sanity check of making sure 3313 * the SFP+ cage is full. 3314 */ 3315 if (ixgbe_need_crosstalk_fix(hw)) { 3316 u32 sfp_cage_full; 3317 3318 switch (hw->mac.type) { 3319 case ixgbe_mac_82599EB: 3320 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3321 IXGBE_ESDP_SDP2; 3322 break; 3323 case ixgbe_mac_X550EM_x: 3324 case ixgbe_mac_x550em_a: 3325 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3326 IXGBE_ESDP_SDP0; 3327 break; 3328 default: 3329 /* sanity check - No SFP+ devices here */ 3330 sfp_cage_full = false; 3331 break; 3332 } 3333 3334 if (!sfp_cage_full) { 3335 *link_up = false; 3336 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3337 return 0; 3338 } 3339 } 3340 3341 /* clear the old state */ 3342 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 3343 3344 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3345 3346 if (links_orig != links_reg) { 3347 hw_dbg(hw, "LINKS changed from %08X to %08X\n", 3348 links_orig, links_reg); 3349 } 3350 3351 if (link_up_wait_to_complete) { 3352 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 3353 if (links_reg & IXGBE_LINKS_UP) { 3354 *link_up = true; 3355 break; 3356 } else { 3357 *link_up = false; 3358 } 3359 msleep(100); 3360 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3361 } 3362 } else { 3363 if (links_reg & IXGBE_LINKS_UP) 3364 *link_up = true; 3365 else 3366 *link_up = false; 3367 } 3368 3369 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 3370 case IXGBE_LINKS_SPEED_10G_82599: 3371 if ((hw->mac.type >= ixgbe_mac_X550) && 3372 (links_reg & IXGBE_LINKS_SPEED_NON_STD)) 3373 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 3374 else 3375 *speed = IXGBE_LINK_SPEED_10GB_FULL; 3376 break; 3377 case IXGBE_LINKS_SPEED_1G_82599: 3378 *speed = IXGBE_LINK_SPEED_1GB_FULL; 3379 break; 3380 case IXGBE_LINKS_SPEED_100_82599: 3381 if ((hw->mac.type >= ixgbe_mac_X550) && 3382 (links_reg & IXGBE_LINKS_SPEED_NON_STD)) 3383 *speed = IXGBE_LINK_SPEED_5GB_FULL; 3384 else 3385 *speed = IXGBE_LINK_SPEED_100_FULL; 3386 break; 3387 case IXGBE_LINKS_SPEED_10_X550EM_A: 3388 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3389 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 3390 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) { 3391 *speed = IXGBE_LINK_SPEED_10_FULL; 3392 } 3393 break; 3394 default: 3395 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3396 } 3397 3398 return 0; 3399 } 3400 3401 /** 3402 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 3403 * the EEPROM 3404 * @hw: pointer to hardware structure 3405 * @wwnn_prefix: the alternative WWNN prefix 3406 * @wwpn_prefix: the alternative WWPN prefix 3407 * 3408 * This function will read the EEPROM from the alternative SAN MAC address 3409 * block to check the support for the alternative WWNN/WWPN prefix support. 3410 **/ 3411 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 3412 u16 *wwpn_prefix) 3413 { 3414 u16 offset, caps; 3415 u16 alt_san_mac_blk_offset; 3416 3417 /* clear output first */ 3418 *wwnn_prefix = 0xFFFF; 3419 *wwpn_prefix = 0xFFFF; 3420 3421 /* check if alternative SAN MAC is supported */ 3422 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 3423 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 3424 goto wwn_prefix_err; 3425 3426 if ((alt_san_mac_blk_offset == 0) || 3427 (alt_san_mac_blk_offset == 0xFFFF)) 3428 return 0; 3429 3430 /* check capability in alternative san mac address block */ 3431 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 3432 if (hw->eeprom.ops.read(hw, offset, &caps)) 3433 goto wwn_prefix_err; 3434 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 3435 return 0; 3436 3437 /* get the corresponding prefix for WWNN/WWPN */ 3438 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 3439 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) 3440 hw_err(hw, "eeprom read at offset %d failed\n", offset); 3441 3442 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 3443 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 3444 goto wwn_prefix_err; 3445 3446 return 0; 3447 3448 wwn_prefix_err: 3449 hw_err(hw, "eeprom read at offset %d failed\n", offset); 3450 return 0; 3451 } 3452 3453 /** 3454 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 3455 * @hw: pointer to hardware structure 3456 * @enable: enable or disable switch for MAC anti-spoofing 3457 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing 3458 * 3459 **/ 3460 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 3461 { 3462 int vf_target_reg = vf >> 3; 3463 int vf_target_shift = vf % 8; 3464 u32 pfvfspoof; 3465 3466 if (hw->mac.type == ixgbe_mac_82598EB) 3467 return; 3468 3469 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3470 if (enable) 3471 pfvfspoof |= BIT(vf_target_shift); 3472 else 3473 pfvfspoof &= ~BIT(vf_target_shift); 3474 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3475 } 3476 3477 /** 3478 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 3479 * @hw: pointer to hardware structure 3480 * @enable: enable or disable switch for VLAN anti-spoofing 3481 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 3482 * 3483 **/ 3484 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 3485 { 3486 int vf_target_reg = vf >> 3; 3487 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 3488 u32 pfvfspoof; 3489 3490 if (hw->mac.type == ixgbe_mac_82598EB) 3491 return; 3492 3493 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3494 if (enable) 3495 pfvfspoof |= BIT(vf_target_shift); 3496 else 3497 pfvfspoof &= ~BIT(vf_target_shift); 3498 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3499 } 3500 3501 /** 3502 * ixgbe_get_device_caps_generic - Get additional device capabilities 3503 * @hw: pointer to hardware structure 3504 * @device_caps: the EEPROM word with the extra device capabilities 3505 * 3506 * This function will read the EEPROM location for the device capabilities, 3507 * and return the word through device_caps. 3508 **/ 3509 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 3510 { 3511 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 3512 3513 return 0; 3514 } 3515 3516 /** 3517 * ixgbe_set_rxpba_generic - Initialize RX packet buffer 3518 * @hw: pointer to hardware structure 3519 * @num_pb: number of packet buffers to allocate 3520 * @headroom: reserve n KB of headroom 3521 * @strategy: packet buffer allocation strategy 3522 **/ 3523 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, 3524 int num_pb, 3525 u32 headroom, 3526 int strategy) 3527 { 3528 u32 pbsize = hw->mac.rx_pb_size; 3529 int i = 0; 3530 u32 rxpktsize, txpktsize, txpbthresh; 3531 3532 /* Reserve headroom */ 3533 pbsize -= headroom; 3534 3535 if (!num_pb) 3536 num_pb = 1; 3537 3538 /* Divide remaining packet buffer space amongst the number 3539 * of packet buffers requested using supplied strategy. 3540 */ 3541 switch (strategy) { 3542 case (PBA_STRATEGY_WEIGHTED): 3543 /* pba_80_48 strategy weight first half of packet buffer with 3544 * 5/8 of the packet buffer space. 3545 */ 3546 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8)); 3547 pbsize -= rxpktsize * (num_pb / 2); 3548 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 3549 for (; i < (num_pb / 2); i++) 3550 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3551 /* Fall through to configure remaining packet buffers */ 3552 case (PBA_STRATEGY_EQUAL): 3553 /* Divide the remaining Rx packet buffer evenly among the TCs */ 3554 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 3555 for (; i < num_pb; i++) 3556 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3557 break; 3558 default: 3559 break; 3560 } 3561 3562 /* 3563 * Setup Tx packet buffer and threshold equally for all TCs 3564 * TXPBTHRESH register is set in K so divide by 1024 and subtract 3565 * 10 since the largest packet we support is just over 9K. 3566 */ 3567 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 3568 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 3569 for (i = 0; i < num_pb; i++) { 3570 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 3571 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 3572 } 3573 3574 /* Clear unused TCs, if any, to zero buffer size*/ 3575 for (; i < IXGBE_MAX_PB; i++) { 3576 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 3577 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 3578 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 3579 } 3580 } 3581 3582 /** 3583 * ixgbe_calculate_checksum - Calculate checksum for buffer 3584 * @buffer: pointer to EEPROM 3585 * @length: size of EEPROM to calculate a checksum for 3586 * 3587 * Calculates the checksum for some buffer on a specified length. The 3588 * checksum calculated is returned. 3589 **/ 3590 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 3591 { 3592 u32 i; 3593 u8 sum = 0; 3594 3595 if (!buffer) 3596 return 0; 3597 3598 for (i = 0; i < length; i++) 3599 sum += buffer[i]; 3600 3601 return (u8) (0 - sum); 3602 } 3603 3604 /** 3605 * ixgbe_hic_unlocked - Issue command to manageability block unlocked 3606 * @hw: pointer to the HW structure 3607 * @buffer: command to write and where the return status will be placed 3608 * @length: length of buffer, must be multiple of 4 bytes 3609 * @timeout: time in ms to wait for command completion 3610 * 3611 * Communicates with the manageability block. On success return 0 3612 * else returns semaphore error when encountering an error acquiring 3613 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 3614 * 3615 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held 3616 * by the caller. 3617 **/ 3618 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, 3619 u32 timeout) 3620 { 3621 u32 hicr, i, fwsts; 3622 u16 dword_len; 3623 3624 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 3625 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); 3626 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3627 } 3628 3629 /* Set bit 9 of FWSTS clearing FW reset indication */ 3630 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 3631 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 3632 3633 /* Check that the host interface is enabled. */ 3634 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3635 if (!(hicr & IXGBE_HICR_EN)) { 3636 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n"); 3637 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3638 } 3639 3640 /* Calculate length in DWORDs. We must be DWORD aligned */ 3641 if (length % sizeof(u32)) { 3642 hw_dbg(hw, "Buffer length failure, not aligned to dword"); 3643 return IXGBE_ERR_INVALID_ARGUMENT; 3644 } 3645 3646 dword_len = length >> 2; 3647 3648 /* The device driver writes the relevant command block 3649 * into the ram area. 3650 */ 3651 for (i = 0; i < dword_len; i++) 3652 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 3653 i, cpu_to_le32(buffer[i])); 3654 3655 /* Setting this bit tells the ARC that a new command is pending. */ 3656 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 3657 3658 for (i = 0; i < timeout; i++) { 3659 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3660 if (!(hicr & IXGBE_HICR_C)) 3661 break; 3662 usleep_range(1000, 2000); 3663 } 3664 3665 /* Check command successful completion. */ 3666 if ((timeout && i == timeout) || 3667 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) 3668 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3669 3670 return 0; 3671 } 3672 3673 /** 3674 * ixgbe_host_interface_command - Issue command to manageability block 3675 * @hw: pointer to the HW structure 3676 * @buffer: contains the command to write and where the return status will 3677 * be placed 3678 * @length: length of buffer, must be multiple of 4 bytes 3679 * @timeout: time in ms to wait for command completion 3680 * @return_data: read and return data from the buffer (true) or not (false) 3681 * Needed because FW structures are big endian and decoding of 3682 * these fields can be 8 bit or 16 bit based on command. Decoding 3683 * is not easily understood without making a table of commands. 3684 * So we will leave this up to the caller to read back the data 3685 * in these cases. 3686 * 3687 * Communicates with the manageability block. On success return 0 3688 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND. 3689 **/ 3690 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer, 3691 u32 length, u32 timeout, 3692 bool return_data) 3693 { 3694 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 3695 union { 3696 struct ixgbe_hic_hdr hdr; 3697 u32 u32arr[1]; 3698 } *bp = buffer; 3699 u16 buf_len, dword_len; 3700 s32 status; 3701 u32 bi; 3702 3703 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 3704 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); 3705 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3706 } 3707 /* Take management host interface semaphore */ 3708 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 3709 if (status) 3710 return status; 3711 3712 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); 3713 if (status) 3714 goto rel_out; 3715 3716 if (!return_data) 3717 goto rel_out; 3718 3719 /* Calculate length in DWORDs */ 3720 dword_len = hdr_size >> 2; 3721 3722 /* first pull in the header so we know the buffer length */ 3723 for (bi = 0; bi < dword_len; bi++) { 3724 bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3725 le32_to_cpus(&bp->u32arr[bi]); 3726 } 3727 3728 /* If there is any thing in data position pull it in */ 3729 buf_len = bp->hdr.buf_len; 3730 if (!buf_len) 3731 goto rel_out; 3732 3733 if (length < round_up(buf_len, 4) + hdr_size) { 3734 hw_dbg(hw, "Buffer not large enough for reply message.\n"); 3735 status = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3736 goto rel_out; 3737 } 3738 3739 /* Calculate length in DWORDs, add 3 for odd lengths */ 3740 dword_len = (buf_len + 3) >> 2; 3741 3742 /* Pull in the rest of the buffer (bi is where we left off) */ 3743 for (; bi <= dword_len; bi++) { 3744 bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3745 le32_to_cpus(&bp->u32arr[bi]); 3746 } 3747 3748 rel_out: 3749 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 3750 3751 return status; 3752 } 3753 3754 /** 3755 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 3756 * @hw: pointer to the HW structure 3757 * @maj: driver version major number 3758 * @min: driver version minor number 3759 * @build: driver version build number 3760 * @sub: driver version sub build number 3761 * @len: length of driver_ver string 3762 * @driver_ver: driver string 3763 * 3764 * Sends driver version number to firmware through the manageability 3765 * block. On success return 0 3766 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 3767 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 3768 **/ 3769 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 3770 u8 build, u8 sub, __always_unused u16 len, 3771 __always_unused const char *driver_ver) 3772 { 3773 struct ixgbe_hic_drv_info fw_cmd; 3774 int i; 3775 s32 ret_val; 3776 3777 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 3778 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 3779 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 3780 fw_cmd.port_num = hw->bus.func; 3781 fw_cmd.ver_maj = maj; 3782 fw_cmd.ver_min = min; 3783 fw_cmd.ver_build = build; 3784 fw_cmd.ver_sub = sub; 3785 fw_cmd.hdr.checksum = 0; 3786 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 3787 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 3788 fw_cmd.pad = 0; 3789 fw_cmd.pad2 = 0; 3790 3791 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 3792 ret_val = ixgbe_host_interface_command(hw, &fw_cmd, 3793 sizeof(fw_cmd), 3794 IXGBE_HI_COMMAND_TIMEOUT, 3795 true); 3796 if (ret_val != 0) 3797 continue; 3798 3799 if (fw_cmd.hdr.cmd_or_resp.ret_status == 3800 FW_CEM_RESP_STATUS_SUCCESS) 3801 ret_val = 0; 3802 else 3803 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3804 3805 break; 3806 } 3807 3808 return ret_val; 3809 } 3810 3811 /** 3812 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 3813 * @hw: pointer to the hardware structure 3814 * 3815 * The 82599 and x540 MACs can experience issues if TX work is still pending 3816 * when a reset occurs. This function prevents this by flushing the PCIe 3817 * buffers on the system. 3818 **/ 3819 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 3820 { 3821 u32 gcr_ext, hlreg0, i, poll; 3822 u16 value; 3823 3824 /* 3825 * If double reset is not requested then all transactions should 3826 * already be clear and as such there is no work to do 3827 */ 3828 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 3829 return; 3830 3831 /* 3832 * Set loopback enable to prevent any transmits from being sent 3833 * should the link come up. This assumes that the RXCTRL.RXEN bit 3834 * has already been cleared. 3835 */ 3836 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3837 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 3838 3839 /* wait for a last completion before clearing buffers */ 3840 IXGBE_WRITE_FLUSH(hw); 3841 usleep_range(3000, 6000); 3842 3843 /* Before proceeding, make sure that the PCIe block does not have 3844 * transactions pending. 3845 */ 3846 poll = ixgbe_pcie_timeout_poll(hw); 3847 for (i = 0; i < poll; i++) { 3848 usleep_range(100, 200); 3849 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); 3850 if (ixgbe_removed(hw->hw_addr)) 3851 break; 3852 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3853 break; 3854 } 3855 3856 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 3857 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 3858 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 3859 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 3860 3861 /* Flush all writes and allow 20usec for all transactions to clear */ 3862 IXGBE_WRITE_FLUSH(hw); 3863 udelay(20); 3864 3865 /* restore previous register values */ 3866 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 3867 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3868 } 3869 3870 static const u8 ixgbe_emc_temp_data[4] = { 3871 IXGBE_EMC_INTERNAL_DATA, 3872 IXGBE_EMC_DIODE1_DATA, 3873 IXGBE_EMC_DIODE2_DATA, 3874 IXGBE_EMC_DIODE3_DATA 3875 }; 3876 static const u8 ixgbe_emc_therm_limit[4] = { 3877 IXGBE_EMC_INTERNAL_THERM_LIMIT, 3878 IXGBE_EMC_DIODE1_THERM_LIMIT, 3879 IXGBE_EMC_DIODE2_THERM_LIMIT, 3880 IXGBE_EMC_DIODE3_THERM_LIMIT 3881 }; 3882 3883 /** 3884 * ixgbe_get_ets_data - Extracts the ETS bit data 3885 * @hw: pointer to hardware structure 3886 * @ets_cfg: extected ETS data 3887 * @ets_offset: offset of ETS data 3888 * 3889 * Returns error code. 3890 **/ 3891 static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg, 3892 u16 *ets_offset) 3893 { 3894 s32 status; 3895 3896 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset); 3897 if (status) 3898 return status; 3899 3900 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF)) 3901 return IXGBE_NOT_IMPLEMENTED; 3902 3903 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg); 3904 if (status) 3905 return status; 3906 3907 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED) 3908 return IXGBE_NOT_IMPLEMENTED; 3909 3910 return 0; 3911 } 3912 3913 /** 3914 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data 3915 * @hw: pointer to hardware structure 3916 * 3917 * Returns the thermal sensor data structure 3918 **/ 3919 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) 3920 { 3921 s32 status; 3922 u16 ets_offset; 3923 u16 ets_cfg; 3924 u16 ets_sensor; 3925 u8 num_sensors; 3926 u8 i; 3927 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 3928 3929 /* Only support thermal sensors attached to physical port 0 */ 3930 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 3931 return IXGBE_NOT_IMPLEMENTED; 3932 3933 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); 3934 if (status) 3935 return status; 3936 3937 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 3938 if (num_sensors > IXGBE_MAX_SENSORS) 3939 num_sensors = IXGBE_MAX_SENSORS; 3940 3941 for (i = 0; i < num_sensors; i++) { 3942 u8 sensor_index; 3943 u8 sensor_location; 3944 3945 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), 3946 &ets_sensor); 3947 if (status) 3948 return status; 3949 3950 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 3951 IXGBE_ETS_DATA_INDEX_SHIFT); 3952 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 3953 IXGBE_ETS_DATA_LOC_SHIFT); 3954 3955 if (sensor_location != 0) { 3956 status = hw->phy.ops.read_i2c_byte(hw, 3957 ixgbe_emc_temp_data[sensor_index], 3958 IXGBE_I2C_THERMAL_SENSOR_ADDR, 3959 &data->sensor[i].temp); 3960 if (status) 3961 return status; 3962 } 3963 } 3964 3965 return 0; 3966 } 3967 3968 /** 3969 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds 3970 * @hw: pointer to hardware structure 3971 * 3972 * Inits the thermal sensor thresholds according to the NVM map 3973 * and save off the threshold and location values into mac.thermal_sensor_data 3974 **/ 3975 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) 3976 { 3977 s32 status; 3978 u16 ets_offset; 3979 u16 ets_cfg; 3980 u16 ets_sensor; 3981 u8 low_thresh_delta; 3982 u8 num_sensors; 3983 u8 therm_limit; 3984 u8 i; 3985 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 3986 3987 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data)); 3988 3989 /* Only support thermal sensors attached to physical port 0 */ 3990 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 3991 return IXGBE_NOT_IMPLEMENTED; 3992 3993 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); 3994 if (status) 3995 return status; 3996 3997 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >> 3998 IXGBE_ETS_LTHRES_DELTA_SHIFT); 3999 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 4000 if (num_sensors > IXGBE_MAX_SENSORS) 4001 num_sensors = IXGBE_MAX_SENSORS; 4002 4003 for (i = 0; i < num_sensors; i++) { 4004 u8 sensor_index; 4005 u8 sensor_location; 4006 4007 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) { 4008 hw_err(hw, "eeprom read at offset %d failed\n", 4009 ets_offset + 1 + i); 4010 continue; 4011 } 4012 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 4013 IXGBE_ETS_DATA_INDEX_SHIFT); 4014 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 4015 IXGBE_ETS_DATA_LOC_SHIFT); 4016 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK; 4017 4018 hw->phy.ops.write_i2c_byte(hw, 4019 ixgbe_emc_therm_limit[sensor_index], 4020 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit); 4021 4022 if (sensor_location == 0) 4023 continue; 4024 4025 data->sensor[i].location = sensor_location; 4026 data->sensor[i].caution_thresh = therm_limit; 4027 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta; 4028 } 4029 4030 return 0; 4031 } 4032 4033 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 4034 { 4035 u32 rxctrl; 4036 4037 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4038 if (rxctrl & IXGBE_RXCTRL_RXEN) { 4039 if (hw->mac.type != ixgbe_mac_82598EB) { 4040 u32 pfdtxgswc; 4041 4042 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 4043 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 4044 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 4045 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 4046 hw->mac.set_lben = true; 4047 } else { 4048 hw->mac.set_lben = false; 4049 } 4050 } 4051 rxctrl &= ~IXGBE_RXCTRL_RXEN; 4052 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 4053 } 4054 } 4055 4056 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 4057 { 4058 u32 rxctrl; 4059 4060 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4061 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 4062 4063 if (hw->mac.type != ixgbe_mac_82598EB) { 4064 if (hw->mac.set_lben) { 4065 u32 pfdtxgswc; 4066 4067 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 4068 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 4069 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 4070 hw->mac.set_lben = false; 4071 } 4072 } 4073 } 4074 4075 /** ixgbe_mng_present - returns true when management capability is present 4076 * @hw: pointer to hardware structure 4077 **/ 4078 bool ixgbe_mng_present(struct ixgbe_hw *hw) 4079 { 4080 u32 fwsm; 4081 4082 if (hw->mac.type < ixgbe_mac_82599EB) 4083 return false; 4084 4085 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 4086 fwsm &= IXGBE_FWSM_MODE_MASK; 4087 return fwsm == IXGBE_FWSM_FW_MODE_PT; 4088 } 4089 4090 /** 4091 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 4092 * @hw: pointer to hardware structure 4093 * @speed: new link speed 4094 * @autoneg_wait_to_complete: true when waiting for completion is needed 4095 * 4096 * Set the link speed in the MAC and/or PHY register and restarts link. 4097 */ 4098 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 4099 ixgbe_link_speed speed, 4100 bool autoneg_wait_to_complete) 4101 { 4102 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4103 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4104 s32 status = 0; 4105 u32 speedcnt = 0; 4106 u32 i = 0; 4107 bool autoneg, link_up = false; 4108 4109 /* Mask off requested but non-supported speeds */ 4110 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg); 4111 if (status) 4112 return status; 4113 4114 speed &= link_speed; 4115 4116 /* Try each speed one by one, highest priority first. We do this in 4117 * software because 10Gb fiber doesn't support speed autonegotiation. 4118 */ 4119 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 4120 speedcnt++; 4121 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 4122 4123 /* If we already have link at this speed, just jump out */ 4124 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 4125 false); 4126 if (status) 4127 return status; 4128 4129 if (link_speed == IXGBE_LINK_SPEED_10GB_FULL && link_up) 4130 goto out; 4131 4132 /* Set the module link speed */ 4133 switch (hw->phy.media_type) { 4134 case ixgbe_media_type_fiber: 4135 hw->mac.ops.set_rate_select_speed(hw, 4136 IXGBE_LINK_SPEED_10GB_FULL); 4137 break; 4138 case ixgbe_media_type_fiber_qsfp: 4139 /* QSFP module automatically detects MAC link speed */ 4140 break; 4141 default: 4142 hw_dbg(hw, "Unexpected media type\n"); 4143 break; 4144 } 4145 4146 /* Allow module to change analog characteristics (1G->10G) */ 4147 msleep(40); 4148 4149 status = hw->mac.ops.setup_mac_link(hw, 4150 IXGBE_LINK_SPEED_10GB_FULL, 4151 autoneg_wait_to_complete); 4152 if (status) 4153 return status; 4154 4155 /* Flap the Tx laser if it has not already been done */ 4156 if (hw->mac.ops.flap_tx_laser) 4157 hw->mac.ops.flap_tx_laser(hw); 4158 4159 /* Wait for the controller to acquire link. Per IEEE 802.3ap, 4160 * Section 73.10.2, we may have to wait up to 500ms if KR is 4161 * attempted. 82599 uses the same timing for 10g SFI. 4162 */ 4163 for (i = 0; i < 5; i++) { 4164 /* Wait for the link partner to also set speed */ 4165 msleep(100); 4166 4167 /* If we have link, just jump out */ 4168 status = hw->mac.ops.check_link(hw, &link_speed, 4169 &link_up, false); 4170 if (status) 4171 return status; 4172 4173 if (link_up) 4174 goto out; 4175 } 4176 } 4177 4178 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 4179 speedcnt++; 4180 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 4181 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 4182 4183 /* If we already have link at this speed, just jump out */ 4184 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 4185 false); 4186 if (status) 4187 return status; 4188 4189 if (link_speed == IXGBE_LINK_SPEED_1GB_FULL && link_up) 4190 goto out; 4191 4192 /* Set the module link speed */ 4193 switch (hw->phy.media_type) { 4194 case ixgbe_media_type_fiber: 4195 hw->mac.ops.set_rate_select_speed(hw, 4196 IXGBE_LINK_SPEED_1GB_FULL); 4197 break; 4198 case ixgbe_media_type_fiber_qsfp: 4199 /* QSFP module automatically detects link speed */ 4200 break; 4201 default: 4202 hw_dbg(hw, "Unexpected media type\n"); 4203 break; 4204 } 4205 4206 /* Allow module to change analog characteristics (10G->1G) */ 4207 msleep(40); 4208 4209 status = hw->mac.ops.setup_mac_link(hw, 4210 IXGBE_LINK_SPEED_1GB_FULL, 4211 autoneg_wait_to_complete); 4212 if (status) 4213 return status; 4214 4215 /* Flap the Tx laser if it has not already been done */ 4216 if (hw->mac.ops.flap_tx_laser) 4217 hw->mac.ops.flap_tx_laser(hw); 4218 4219 /* Wait for the link partner to also set speed */ 4220 msleep(100); 4221 4222 /* If we have link, just jump out */ 4223 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 4224 false); 4225 if (status) 4226 return status; 4227 4228 if (link_up) 4229 goto out; 4230 } 4231 4232 /* We didn't get link. Configure back to the highest speed we tried, 4233 * (if there was more than one). We call ourselves back with just the 4234 * single highest speed that the user requested. 4235 */ 4236 if (speedcnt > 1) 4237 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 4238 highest_link_speed, 4239 autoneg_wait_to_complete); 4240 4241 out: 4242 /* Set autoneg_advertised value based on input link speed */ 4243 hw->phy.autoneg_advertised = 0; 4244 4245 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 4246 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 4247 4248 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 4249 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 4250 4251 return status; 4252 } 4253 4254 /** 4255 * ixgbe_set_soft_rate_select_speed - Set module link speed 4256 * @hw: pointer to hardware structure 4257 * @speed: link speed to set 4258 * 4259 * Set module link speed via the soft rate select. 4260 */ 4261 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 4262 ixgbe_link_speed speed) 4263 { 4264 s32 status; 4265 u8 rs, eeprom_data; 4266 4267 switch (speed) { 4268 case IXGBE_LINK_SPEED_10GB_FULL: 4269 /* one bit mask same as setting on */ 4270 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 4271 break; 4272 case IXGBE_LINK_SPEED_1GB_FULL: 4273 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 4274 break; 4275 default: 4276 hw_dbg(hw, "Invalid fixed module speed\n"); 4277 return; 4278 } 4279 4280 /* Set RS0 */ 4281 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4282 IXGBE_I2C_EEPROM_DEV_ADDR2, 4283 &eeprom_data); 4284 if (status) { 4285 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n"); 4286 return; 4287 } 4288 4289 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 4290 4291 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4292 IXGBE_I2C_EEPROM_DEV_ADDR2, 4293 eeprom_data); 4294 if (status) { 4295 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n"); 4296 return; 4297 } 4298 } 4299