1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/pci.h> 30 #include <linux/delay.h> 31 #include <linux/sched.h> 32 #include <linux/netdevice.h> 33 34 #include "ixgbe.h" 35 #include "ixgbe_common.h" 36 #include "ixgbe_phy.h" 37 38 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 39 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 40 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 41 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 42 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 43 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 44 u16 count); 45 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 46 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 47 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 48 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 49 50 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 51 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg); 52 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 53 u16 words, u16 *data); 54 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 55 u16 words, u16 *data); 56 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 57 u16 offset); 58 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw); 59 60 /* Base table for registers values that change by MAC */ 61 const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = { 62 IXGBE_MVALS_INIT(8259X) 63 }; 64 65 /** 66 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow 67 * control 68 * @hw: pointer to hardware structure 69 * 70 * There are several phys that do not support autoneg flow control. This 71 * function check the device id to see if the associated phy supports 72 * autoneg flow control. 73 **/ 74 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 75 { 76 bool supported = false; 77 ixgbe_link_speed speed; 78 bool link_up; 79 80 switch (hw->phy.media_type) { 81 case ixgbe_media_type_fiber: 82 hw->mac.ops.check_link(hw, &speed, &link_up, false); 83 /* if link is down, assume supported */ 84 if (link_up) 85 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? 86 true : false; 87 else 88 supported = true; 89 break; 90 case ixgbe_media_type_backplane: 91 supported = true; 92 break; 93 case ixgbe_media_type_copper: 94 /* only some copper devices support flow control autoneg */ 95 switch (hw->device_id) { 96 case IXGBE_DEV_ID_82599_T3_LOM: 97 case IXGBE_DEV_ID_X540T: 98 case IXGBE_DEV_ID_X540T1: 99 case IXGBE_DEV_ID_X550T: 100 case IXGBE_DEV_ID_X550T1: 101 case IXGBE_DEV_ID_X550EM_X_10G_T: 102 supported = true; 103 break; 104 default: 105 break; 106 } 107 default: 108 break; 109 } 110 111 return supported; 112 } 113 114 /** 115 * ixgbe_setup_fc_generic - Set up flow control 116 * @hw: pointer to hardware structure 117 * 118 * Called at init time to set up flow control. 119 **/ 120 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) 121 { 122 s32 ret_val = 0; 123 u32 reg = 0, reg_bp = 0; 124 u16 reg_cu = 0; 125 bool locked = false; 126 127 /* 128 * Validate the requested mode. Strict IEEE mode does not allow 129 * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 130 */ 131 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 132 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 133 return IXGBE_ERR_INVALID_LINK_SETTINGS; 134 } 135 136 /* 137 * 10gig parts do not have a word in the EEPROM to determine the 138 * default flow control setting, so we explicitly set it to full. 139 */ 140 if (hw->fc.requested_mode == ixgbe_fc_default) 141 hw->fc.requested_mode = ixgbe_fc_full; 142 143 /* 144 * Set up the 1G and 10G flow control advertisement registers so the 145 * HW will be able to do fc autoneg once the cable is plugged in. If 146 * we link at 10G, the 1G advertisement is harmless and vice versa. 147 */ 148 switch (hw->phy.media_type) { 149 case ixgbe_media_type_backplane: 150 /* some MAC's need RMW protection on AUTOC */ 151 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 152 if (ret_val) 153 return ret_val; 154 155 /* only backplane uses autoc so fall though */ 156 case ixgbe_media_type_fiber: 157 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 158 159 break; 160 case ixgbe_media_type_copper: 161 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 162 MDIO_MMD_AN, ®_cu); 163 break; 164 default: 165 break; 166 } 167 168 /* 169 * The possible values of fc.requested_mode are: 170 * 0: Flow control is completely disabled 171 * 1: Rx flow control is enabled (we can receive pause frames, 172 * but not send pause frames). 173 * 2: Tx flow control is enabled (we can send pause frames but 174 * we do not support receiving pause frames). 175 * 3: Both Rx and Tx flow control (symmetric) are enabled. 176 * other: Invalid. 177 */ 178 switch (hw->fc.requested_mode) { 179 case ixgbe_fc_none: 180 /* Flow control completely disabled by software override. */ 181 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 182 if (hw->phy.media_type == ixgbe_media_type_backplane) 183 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 184 IXGBE_AUTOC_ASM_PAUSE); 185 else if (hw->phy.media_type == ixgbe_media_type_copper) 186 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 187 break; 188 case ixgbe_fc_tx_pause: 189 /* 190 * Tx Flow control is enabled, and Rx Flow control is 191 * disabled by software override. 192 */ 193 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 194 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 195 if (hw->phy.media_type == ixgbe_media_type_backplane) { 196 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 197 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 198 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 199 reg_cu |= IXGBE_TAF_ASM_PAUSE; 200 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 201 } 202 break; 203 case ixgbe_fc_rx_pause: 204 /* 205 * Rx Flow control is enabled and Tx Flow control is 206 * disabled by software override. Since there really 207 * isn't a way to advertise that we are capable of RX 208 * Pause ONLY, we will advertise that we support both 209 * symmetric and asymmetric Rx PAUSE, as such we fall 210 * through to the fc_full statement. Later, we will 211 * disable the adapter's ability to send PAUSE frames. 212 */ 213 case ixgbe_fc_full: 214 /* Flow control (both Rx and Tx) is enabled by SW override. */ 215 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 216 if (hw->phy.media_type == ixgbe_media_type_backplane) 217 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 218 IXGBE_AUTOC_ASM_PAUSE; 219 else if (hw->phy.media_type == ixgbe_media_type_copper) 220 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 221 break; 222 default: 223 hw_dbg(hw, "Flow control param set incorrectly\n"); 224 return IXGBE_ERR_CONFIG; 225 } 226 227 if (hw->mac.type != ixgbe_mac_X540) { 228 /* 229 * Enable auto-negotiation between the MAC & PHY; 230 * the MAC will advertise clause 37 flow control. 231 */ 232 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 233 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 234 235 /* Disable AN timeout */ 236 if (hw->fc.strict_ieee) 237 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 238 239 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 240 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); 241 } 242 243 /* 244 * AUTOC restart handles negotiation of 1G and 10G on backplane 245 * and copper. There is no need to set the PCS1GCTL register. 246 * 247 */ 248 if (hw->phy.media_type == ixgbe_media_type_backplane) { 249 /* Need the SW/FW semaphore around AUTOC writes if 82599 and 250 * LESM is on, likewise reset_pipeline requries the lock as 251 * it also writes AUTOC. 252 */ 253 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 254 if (ret_val) 255 return ret_val; 256 257 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 258 ixgbe_device_supports_autoneg_fc(hw)) { 259 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 260 MDIO_MMD_AN, reg_cu); 261 } 262 263 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); 264 return ret_val; 265 } 266 267 /** 268 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 269 * @hw: pointer to hardware structure 270 * 271 * Starts the hardware by filling the bus info structure and media type, clears 272 * all on chip counters, initializes receive address registers, multicast 273 * table, VLAN filter table, calls routine to set up link and flow control 274 * settings, and leaves transmit and receive units disabled and uninitialized 275 **/ 276 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 277 { 278 s32 ret_val; 279 u32 ctrl_ext; 280 u16 device_caps; 281 282 /* Set the media type */ 283 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 284 285 /* Identify the PHY */ 286 hw->phy.ops.identify(hw); 287 288 /* Clear the VLAN filter table */ 289 hw->mac.ops.clear_vfta(hw); 290 291 /* Clear statistics registers */ 292 hw->mac.ops.clear_hw_cntrs(hw); 293 294 /* Set No Snoop Disable */ 295 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 296 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 297 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 298 IXGBE_WRITE_FLUSH(hw); 299 300 /* Setup flow control */ 301 ret_val = hw->mac.ops.setup_fc(hw); 302 if (ret_val) 303 return ret_val; 304 305 /* Cashe bit indicating need for crosstalk fix */ 306 switch (hw->mac.type) { 307 case ixgbe_mac_82599EB: 308 case ixgbe_mac_X550EM_x: 309 case ixgbe_mac_x550em_a: 310 hw->mac.ops.get_device_caps(hw, &device_caps); 311 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) 312 hw->need_crosstalk_fix = false; 313 else 314 hw->need_crosstalk_fix = true; 315 break; 316 default: 317 hw->need_crosstalk_fix = false; 318 break; 319 } 320 321 /* Clear adapter stopped flag */ 322 hw->adapter_stopped = false; 323 324 return 0; 325 } 326 327 /** 328 * ixgbe_start_hw_gen2 - Init sequence for common device family 329 * @hw: pointer to hw structure 330 * 331 * Performs the init sequence common to the second generation 332 * of 10 GbE devices. 333 * Devices in the second generation: 334 * 82599 335 * X540 336 **/ 337 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 338 { 339 u32 i; 340 341 /* Clear the rate limiters */ 342 for (i = 0; i < hw->mac.max_tx_queues; i++) { 343 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 344 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 345 } 346 IXGBE_WRITE_FLUSH(hw); 347 348 #ifndef CONFIG_SPARC 349 /* Disable relaxed ordering */ 350 for (i = 0; i < hw->mac.max_tx_queues; i++) { 351 u32 regval; 352 353 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 354 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 355 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 356 } 357 358 for (i = 0; i < hw->mac.max_rx_queues; i++) { 359 u32 regval; 360 361 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 362 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 363 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 364 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 365 } 366 #endif 367 return 0; 368 } 369 370 /** 371 * ixgbe_init_hw_generic - Generic hardware initialization 372 * @hw: pointer to hardware structure 373 * 374 * Initialize the hardware by resetting the hardware, filling the bus info 375 * structure and media type, clears all on chip counters, initializes receive 376 * address registers, multicast table, VLAN filter table, calls routine to set 377 * up link and flow control settings, and leaves transmit and receive units 378 * disabled and uninitialized 379 **/ 380 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 381 { 382 s32 status; 383 384 /* Reset the hardware */ 385 status = hw->mac.ops.reset_hw(hw); 386 387 if (status == 0) { 388 /* Start the HW */ 389 status = hw->mac.ops.start_hw(hw); 390 } 391 392 return status; 393 } 394 395 /** 396 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 397 * @hw: pointer to hardware structure 398 * 399 * Clears all hardware statistics counters by reading them from the hardware 400 * Statistics counters are clear on read. 401 **/ 402 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 403 { 404 u16 i = 0; 405 406 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 407 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 408 IXGBE_READ_REG(hw, IXGBE_ERRBC); 409 IXGBE_READ_REG(hw, IXGBE_MSPDC); 410 for (i = 0; i < 8; i++) 411 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 412 413 IXGBE_READ_REG(hw, IXGBE_MLFC); 414 IXGBE_READ_REG(hw, IXGBE_MRFC); 415 IXGBE_READ_REG(hw, IXGBE_RLEC); 416 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 417 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 418 if (hw->mac.type >= ixgbe_mac_82599EB) { 419 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 420 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 421 } else { 422 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 423 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 424 } 425 426 for (i = 0; i < 8; i++) { 427 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 428 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 429 if (hw->mac.type >= ixgbe_mac_82599EB) { 430 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 431 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 432 } else { 433 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 434 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 435 } 436 } 437 if (hw->mac.type >= ixgbe_mac_82599EB) 438 for (i = 0; i < 8; i++) 439 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 440 IXGBE_READ_REG(hw, IXGBE_PRC64); 441 IXGBE_READ_REG(hw, IXGBE_PRC127); 442 IXGBE_READ_REG(hw, IXGBE_PRC255); 443 IXGBE_READ_REG(hw, IXGBE_PRC511); 444 IXGBE_READ_REG(hw, IXGBE_PRC1023); 445 IXGBE_READ_REG(hw, IXGBE_PRC1522); 446 IXGBE_READ_REG(hw, IXGBE_GPRC); 447 IXGBE_READ_REG(hw, IXGBE_BPRC); 448 IXGBE_READ_REG(hw, IXGBE_MPRC); 449 IXGBE_READ_REG(hw, IXGBE_GPTC); 450 IXGBE_READ_REG(hw, IXGBE_GORCL); 451 IXGBE_READ_REG(hw, IXGBE_GORCH); 452 IXGBE_READ_REG(hw, IXGBE_GOTCL); 453 IXGBE_READ_REG(hw, IXGBE_GOTCH); 454 if (hw->mac.type == ixgbe_mac_82598EB) 455 for (i = 0; i < 8; i++) 456 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 457 IXGBE_READ_REG(hw, IXGBE_RUC); 458 IXGBE_READ_REG(hw, IXGBE_RFC); 459 IXGBE_READ_REG(hw, IXGBE_ROC); 460 IXGBE_READ_REG(hw, IXGBE_RJC); 461 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 462 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 463 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 464 IXGBE_READ_REG(hw, IXGBE_TORL); 465 IXGBE_READ_REG(hw, IXGBE_TORH); 466 IXGBE_READ_REG(hw, IXGBE_TPR); 467 IXGBE_READ_REG(hw, IXGBE_TPT); 468 IXGBE_READ_REG(hw, IXGBE_PTC64); 469 IXGBE_READ_REG(hw, IXGBE_PTC127); 470 IXGBE_READ_REG(hw, IXGBE_PTC255); 471 IXGBE_READ_REG(hw, IXGBE_PTC511); 472 IXGBE_READ_REG(hw, IXGBE_PTC1023); 473 IXGBE_READ_REG(hw, IXGBE_PTC1522); 474 IXGBE_READ_REG(hw, IXGBE_MPTC); 475 IXGBE_READ_REG(hw, IXGBE_BPTC); 476 for (i = 0; i < 16; i++) { 477 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 478 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 479 if (hw->mac.type >= ixgbe_mac_82599EB) { 480 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 481 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 482 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 483 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 484 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 485 } else { 486 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 487 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 488 } 489 } 490 491 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { 492 if (hw->phy.id == 0) 493 hw->phy.ops.identify(hw); 494 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i); 495 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i); 496 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i); 497 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i); 498 } 499 500 return 0; 501 } 502 503 /** 504 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 505 * @hw: pointer to hardware structure 506 * @pba_num: stores the part number string from the EEPROM 507 * @pba_num_size: part number string buffer length 508 * 509 * Reads the part number string from the EEPROM. 510 **/ 511 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 512 u32 pba_num_size) 513 { 514 s32 ret_val; 515 u16 data; 516 u16 pba_ptr; 517 u16 offset; 518 u16 length; 519 520 if (pba_num == NULL) { 521 hw_dbg(hw, "PBA string buffer was null\n"); 522 return IXGBE_ERR_INVALID_ARGUMENT; 523 } 524 525 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 526 if (ret_val) { 527 hw_dbg(hw, "NVM Read Error\n"); 528 return ret_val; 529 } 530 531 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 532 if (ret_val) { 533 hw_dbg(hw, "NVM Read Error\n"); 534 return ret_val; 535 } 536 537 /* 538 * if data is not ptr guard the PBA must be in legacy format which 539 * means pba_ptr is actually our second data word for the PBA number 540 * and we can decode it into an ascii string 541 */ 542 if (data != IXGBE_PBANUM_PTR_GUARD) { 543 hw_dbg(hw, "NVM PBA number is not stored as string\n"); 544 545 /* we will need 11 characters to store the PBA */ 546 if (pba_num_size < 11) { 547 hw_dbg(hw, "PBA string buffer too small\n"); 548 return IXGBE_ERR_NO_SPACE; 549 } 550 551 /* extract hex string from data and pba_ptr */ 552 pba_num[0] = (data >> 12) & 0xF; 553 pba_num[1] = (data >> 8) & 0xF; 554 pba_num[2] = (data >> 4) & 0xF; 555 pba_num[3] = data & 0xF; 556 pba_num[4] = (pba_ptr >> 12) & 0xF; 557 pba_num[5] = (pba_ptr >> 8) & 0xF; 558 pba_num[6] = '-'; 559 pba_num[7] = 0; 560 pba_num[8] = (pba_ptr >> 4) & 0xF; 561 pba_num[9] = pba_ptr & 0xF; 562 563 /* put a null character on the end of our string */ 564 pba_num[10] = '\0'; 565 566 /* switch all the data but the '-' to hex char */ 567 for (offset = 0; offset < 10; offset++) { 568 if (pba_num[offset] < 0xA) 569 pba_num[offset] += '0'; 570 else if (pba_num[offset] < 0x10) 571 pba_num[offset] += 'A' - 0xA; 572 } 573 574 return 0; 575 } 576 577 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 578 if (ret_val) { 579 hw_dbg(hw, "NVM Read Error\n"); 580 return ret_val; 581 } 582 583 if (length == 0xFFFF || length == 0) { 584 hw_dbg(hw, "NVM PBA number section invalid length\n"); 585 return IXGBE_ERR_PBA_SECTION; 586 } 587 588 /* check if pba_num buffer is big enough */ 589 if (pba_num_size < (((u32)length * 2) - 1)) { 590 hw_dbg(hw, "PBA string buffer too small\n"); 591 return IXGBE_ERR_NO_SPACE; 592 } 593 594 /* trim pba length from start of string */ 595 pba_ptr++; 596 length--; 597 598 for (offset = 0; offset < length; offset++) { 599 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 600 if (ret_val) { 601 hw_dbg(hw, "NVM Read Error\n"); 602 return ret_val; 603 } 604 pba_num[offset * 2] = (u8)(data >> 8); 605 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 606 } 607 pba_num[offset * 2] = '\0'; 608 609 return 0; 610 } 611 612 /** 613 * ixgbe_get_mac_addr_generic - Generic get MAC address 614 * @hw: pointer to hardware structure 615 * @mac_addr: Adapter MAC address 616 * 617 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 618 * A reset of the adapter must be performed prior to calling this function 619 * in order for the MAC address to have been loaded from the EEPROM into RAR0 620 **/ 621 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 622 { 623 u32 rar_high; 624 u32 rar_low; 625 u16 i; 626 627 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 628 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 629 630 for (i = 0; i < 4; i++) 631 mac_addr[i] = (u8)(rar_low >> (i*8)); 632 633 for (i = 0; i < 2; i++) 634 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 635 636 return 0; 637 } 638 639 enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status) 640 { 641 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 642 case IXGBE_PCI_LINK_WIDTH_1: 643 return ixgbe_bus_width_pcie_x1; 644 case IXGBE_PCI_LINK_WIDTH_2: 645 return ixgbe_bus_width_pcie_x2; 646 case IXGBE_PCI_LINK_WIDTH_4: 647 return ixgbe_bus_width_pcie_x4; 648 case IXGBE_PCI_LINK_WIDTH_8: 649 return ixgbe_bus_width_pcie_x8; 650 default: 651 return ixgbe_bus_width_unknown; 652 } 653 } 654 655 enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status) 656 { 657 switch (link_status & IXGBE_PCI_LINK_SPEED) { 658 case IXGBE_PCI_LINK_SPEED_2500: 659 return ixgbe_bus_speed_2500; 660 case IXGBE_PCI_LINK_SPEED_5000: 661 return ixgbe_bus_speed_5000; 662 case IXGBE_PCI_LINK_SPEED_8000: 663 return ixgbe_bus_speed_8000; 664 default: 665 return ixgbe_bus_speed_unknown; 666 } 667 } 668 669 /** 670 * ixgbe_get_bus_info_generic - Generic set PCI bus info 671 * @hw: pointer to hardware structure 672 * 673 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 674 **/ 675 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 676 { 677 u16 link_status; 678 679 hw->bus.type = ixgbe_bus_type_pci_express; 680 681 /* Get the negotiated link width and speed from PCI config space */ 682 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS); 683 684 hw->bus.width = ixgbe_convert_bus_width(link_status); 685 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 686 687 hw->mac.ops.set_lan_id(hw); 688 689 return 0; 690 } 691 692 /** 693 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 694 * @hw: pointer to the HW structure 695 * 696 * Determines the LAN function id by reading memory-mapped registers 697 * and swaps the port value if requested. 698 **/ 699 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 700 { 701 struct ixgbe_bus_info *bus = &hw->bus; 702 u16 ee_ctrl_4; 703 u32 reg; 704 705 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 706 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 707 bus->lan_id = bus->func; 708 709 /* check for a port swap */ 710 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); 711 if (reg & IXGBE_FACTPS_LFS) 712 bus->func ^= 0x1; 713 714 /* Get MAC instance from EEPROM for configuring CS4227 */ 715 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { 716 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); 717 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> 718 IXGBE_EE_CTRL_4_INST_ID_SHIFT; 719 } 720 } 721 722 /** 723 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 724 * @hw: pointer to hardware structure 725 * 726 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 727 * disables transmit and receive units. The adapter_stopped flag is used by 728 * the shared code and drivers to determine if the adapter is in a stopped 729 * state and should not touch the hardware. 730 **/ 731 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 732 { 733 u32 reg_val; 734 u16 i; 735 736 /* 737 * Set the adapter_stopped flag so other driver functions stop touching 738 * the hardware 739 */ 740 hw->adapter_stopped = true; 741 742 /* Disable the receive unit */ 743 hw->mac.ops.disable_rx(hw); 744 745 /* Clear interrupt mask to stop interrupts from being generated */ 746 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 747 748 /* Clear any pending interrupts, flush previous writes */ 749 IXGBE_READ_REG(hw, IXGBE_EICR); 750 751 /* Disable the transmit unit. Each queue must be disabled. */ 752 for (i = 0; i < hw->mac.max_tx_queues; i++) 753 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 754 755 /* Disable the receive unit by stopping each queue */ 756 for (i = 0; i < hw->mac.max_rx_queues; i++) { 757 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 758 reg_val &= ~IXGBE_RXDCTL_ENABLE; 759 reg_val |= IXGBE_RXDCTL_SWFLSH; 760 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 761 } 762 763 /* flush all queues disables */ 764 IXGBE_WRITE_FLUSH(hw); 765 usleep_range(1000, 2000); 766 767 /* 768 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 769 * access and verify no pending requests 770 */ 771 return ixgbe_disable_pcie_master(hw); 772 } 773 774 /** 775 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 776 * @hw: pointer to hardware structure 777 * @index: led number to turn on 778 **/ 779 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 780 { 781 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 782 783 if (index > 3) 784 return IXGBE_ERR_PARAM; 785 786 /* To turn on the LED, set mode to ON. */ 787 led_reg &= ~IXGBE_LED_MODE_MASK(index); 788 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 789 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 790 IXGBE_WRITE_FLUSH(hw); 791 792 return 0; 793 } 794 795 /** 796 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 797 * @hw: pointer to hardware structure 798 * @index: led number to turn off 799 **/ 800 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 801 { 802 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 803 804 if (index > 3) 805 return IXGBE_ERR_PARAM; 806 807 /* To turn off the LED, set mode to OFF. */ 808 led_reg &= ~IXGBE_LED_MODE_MASK(index); 809 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 810 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 811 IXGBE_WRITE_FLUSH(hw); 812 813 return 0; 814 } 815 816 /** 817 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 818 * @hw: pointer to hardware structure 819 * 820 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 821 * ixgbe_hw struct in order to set up EEPROM access. 822 **/ 823 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 824 { 825 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 826 u32 eec; 827 u16 eeprom_size; 828 829 if (eeprom->type == ixgbe_eeprom_uninitialized) { 830 eeprom->type = ixgbe_eeprom_none; 831 /* Set default semaphore delay to 10ms which is a well 832 * tested value */ 833 eeprom->semaphore_delay = 10; 834 /* Clear EEPROM page size, it will be initialized as needed */ 835 eeprom->word_page_size = 0; 836 837 /* 838 * Check for EEPROM present first. 839 * If not present leave as none 840 */ 841 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 842 if (eec & IXGBE_EEC_PRES) { 843 eeprom->type = ixgbe_eeprom_spi; 844 845 /* 846 * SPI EEPROM is assumed here. This code would need to 847 * change if a future EEPROM is not SPI. 848 */ 849 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 850 IXGBE_EEC_SIZE_SHIFT); 851 eeprom->word_size = BIT(eeprom_size + 852 IXGBE_EEPROM_WORD_SIZE_SHIFT); 853 } 854 855 if (eec & IXGBE_EEC_ADDR_SIZE) 856 eeprom->address_bits = 16; 857 else 858 eeprom->address_bits = 8; 859 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n", 860 eeprom->type, eeprom->word_size, eeprom->address_bits); 861 } 862 863 return 0; 864 } 865 866 /** 867 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 868 * @hw: pointer to hardware structure 869 * @offset: offset within the EEPROM to write 870 * @words: number of words 871 * @data: 16 bit word(s) to write to EEPROM 872 * 873 * Reads 16 bit word(s) from EEPROM through bit-bang method 874 **/ 875 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 876 u16 words, u16 *data) 877 { 878 s32 status; 879 u16 i, count; 880 881 hw->eeprom.ops.init_params(hw); 882 883 if (words == 0) 884 return IXGBE_ERR_INVALID_ARGUMENT; 885 886 if (offset + words > hw->eeprom.word_size) 887 return IXGBE_ERR_EEPROM; 888 889 /* 890 * The EEPROM page size cannot be queried from the chip. We do lazy 891 * initialization. It is worth to do that when we write large buffer. 892 */ 893 if ((hw->eeprom.word_page_size == 0) && 894 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 895 ixgbe_detect_eeprom_page_size_generic(hw, offset); 896 897 /* 898 * We cannot hold synchronization semaphores for too long 899 * to avoid other entity starvation. However it is more efficient 900 * to read in bursts than synchronizing access for each word. 901 */ 902 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 903 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 904 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 905 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 906 count, &data[i]); 907 908 if (status != 0) 909 break; 910 } 911 912 return status; 913 } 914 915 /** 916 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 917 * @hw: pointer to hardware structure 918 * @offset: offset within the EEPROM to be written to 919 * @words: number of word(s) 920 * @data: 16 bit word(s) to be written to the EEPROM 921 * 922 * If ixgbe_eeprom_update_checksum is not called after this function, the 923 * EEPROM will most likely contain an invalid checksum. 924 **/ 925 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 926 u16 words, u16 *data) 927 { 928 s32 status; 929 u16 word; 930 u16 page_size; 931 u16 i; 932 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 933 934 /* Prepare the EEPROM for writing */ 935 status = ixgbe_acquire_eeprom(hw); 936 if (status) 937 return status; 938 939 if (ixgbe_ready_eeprom(hw) != 0) { 940 ixgbe_release_eeprom(hw); 941 return IXGBE_ERR_EEPROM; 942 } 943 944 for (i = 0; i < words; i++) { 945 ixgbe_standby_eeprom(hw); 946 947 /* Send the WRITE ENABLE command (8 bit opcode) */ 948 ixgbe_shift_out_eeprom_bits(hw, 949 IXGBE_EEPROM_WREN_OPCODE_SPI, 950 IXGBE_EEPROM_OPCODE_BITS); 951 952 ixgbe_standby_eeprom(hw); 953 954 /* Some SPI eeproms use the 8th address bit embedded 955 * in the opcode 956 */ 957 if ((hw->eeprom.address_bits == 8) && 958 ((offset + i) >= 128)) 959 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 960 961 /* Send the Write command (8-bit opcode + addr) */ 962 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 963 IXGBE_EEPROM_OPCODE_BITS); 964 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 965 hw->eeprom.address_bits); 966 967 page_size = hw->eeprom.word_page_size; 968 969 /* Send the data in burst via SPI */ 970 do { 971 word = data[i]; 972 word = (word >> 8) | (word << 8); 973 ixgbe_shift_out_eeprom_bits(hw, word, 16); 974 975 if (page_size == 0) 976 break; 977 978 /* do not wrap around page */ 979 if (((offset + i) & (page_size - 1)) == 980 (page_size - 1)) 981 break; 982 } while (++i < words); 983 984 ixgbe_standby_eeprom(hw); 985 usleep_range(10000, 20000); 986 } 987 /* Done with writing - release the EEPROM */ 988 ixgbe_release_eeprom(hw); 989 990 return 0; 991 } 992 993 /** 994 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 995 * @hw: pointer to hardware structure 996 * @offset: offset within the EEPROM to be written to 997 * @data: 16 bit word to be written to the EEPROM 998 * 999 * If ixgbe_eeprom_update_checksum is not called after this function, the 1000 * EEPROM will most likely contain an invalid checksum. 1001 **/ 1002 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1003 { 1004 hw->eeprom.ops.init_params(hw); 1005 1006 if (offset >= hw->eeprom.word_size) 1007 return IXGBE_ERR_EEPROM; 1008 1009 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1010 } 1011 1012 /** 1013 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1014 * @hw: pointer to hardware structure 1015 * @offset: offset within the EEPROM to be read 1016 * @words: number of word(s) 1017 * @data: read 16 bit words(s) from EEPROM 1018 * 1019 * Reads 16 bit word(s) from EEPROM through bit-bang method 1020 **/ 1021 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1022 u16 words, u16 *data) 1023 { 1024 s32 status; 1025 u16 i, count; 1026 1027 hw->eeprom.ops.init_params(hw); 1028 1029 if (words == 0) 1030 return IXGBE_ERR_INVALID_ARGUMENT; 1031 1032 if (offset + words > hw->eeprom.word_size) 1033 return IXGBE_ERR_EEPROM; 1034 1035 /* 1036 * We cannot hold synchronization semaphores for too long 1037 * to avoid other entity starvation. However it is more efficient 1038 * to read in bursts than synchronizing access for each word. 1039 */ 1040 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1041 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1042 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1043 1044 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1045 count, &data[i]); 1046 1047 if (status) 1048 return status; 1049 } 1050 1051 return 0; 1052 } 1053 1054 /** 1055 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1056 * @hw: pointer to hardware structure 1057 * @offset: offset within the EEPROM to be read 1058 * @words: number of word(s) 1059 * @data: read 16 bit word(s) from EEPROM 1060 * 1061 * Reads 16 bit word(s) from EEPROM through bit-bang method 1062 **/ 1063 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1064 u16 words, u16 *data) 1065 { 1066 s32 status; 1067 u16 word_in; 1068 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1069 u16 i; 1070 1071 /* Prepare the EEPROM for reading */ 1072 status = ixgbe_acquire_eeprom(hw); 1073 if (status) 1074 return status; 1075 1076 if (ixgbe_ready_eeprom(hw) != 0) { 1077 ixgbe_release_eeprom(hw); 1078 return IXGBE_ERR_EEPROM; 1079 } 1080 1081 for (i = 0; i < words; i++) { 1082 ixgbe_standby_eeprom(hw); 1083 /* Some SPI eeproms use the 8th address bit embedded 1084 * in the opcode 1085 */ 1086 if ((hw->eeprom.address_bits == 8) && 1087 ((offset + i) >= 128)) 1088 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1089 1090 /* Send the READ command (opcode + addr) */ 1091 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1092 IXGBE_EEPROM_OPCODE_BITS); 1093 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1094 hw->eeprom.address_bits); 1095 1096 /* Read the data. */ 1097 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1098 data[i] = (word_in >> 8) | (word_in << 8); 1099 } 1100 1101 /* End this read operation */ 1102 ixgbe_release_eeprom(hw); 1103 1104 return 0; 1105 } 1106 1107 /** 1108 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1109 * @hw: pointer to hardware structure 1110 * @offset: offset within the EEPROM to be read 1111 * @data: read 16 bit value from EEPROM 1112 * 1113 * Reads 16 bit value from EEPROM through bit-bang method 1114 **/ 1115 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1116 u16 *data) 1117 { 1118 hw->eeprom.ops.init_params(hw); 1119 1120 if (offset >= hw->eeprom.word_size) 1121 return IXGBE_ERR_EEPROM; 1122 1123 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1124 } 1125 1126 /** 1127 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1128 * @hw: pointer to hardware structure 1129 * @offset: offset of word in the EEPROM to read 1130 * @words: number of word(s) 1131 * @data: 16 bit word(s) from the EEPROM 1132 * 1133 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1134 **/ 1135 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1136 u16 words, u16 *data) 1137 { 1138 u32 eerd; 1139 s32 status; 1140 u32 i; 1141 1142 hw->eeprom.ops.init_params(hw); 1143 1144 if (words == 0) 1145 return IXGBE_ERR_INVALID_ARGUMENT; 1146 1147 if (offset >= hw->eeprom.word_size) 1148 return IXGBE_ERR_EEPROM; 1149 1150 for (i = 0; i < words; i++) { 1151 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1152 IXGBE_EEPROM_RW_REG_START; 1153 1154 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1155 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1156 1157 if (status == 0) { 1158 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1159 IXGBE_EEPROM_RW_REG_DATA); 1160 } else { 1161 hw_dbg(hw, "Eeprom read timed out\n"); 1162 return status; 1163 } 1164 } 1165 1166 return 0; 1167 } 1168 1169 /** 1170 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1171 * @hw: pointer to hardware structure 1172 * @offset: offset within the EEPROM to be used as a scratch pad 1173 * 1174 * Discover EEPROM page size by writing marching data at given offset. 1175 * This function is called only when we are writing a new large buffer 1176 * at given offset so the data would be overwritten anyway. 1177 **/ 1178 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1179 u16 offset) 1180 { 1181 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1182 s32 status; 1183 u16 i; 1184 1185 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1186 data[i] = i; 1187 1188 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1189 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1190 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1191 hw->eeprom.word_page_size = 0; 1192 if (status) 1193 return status; 1194 1195 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1196 if (status) 1197 return status; 1198 1199 /* 1200 * When writing in burst more than the actual page size 1201 * EEPROM address wraps around current page. 1202 */ 1203 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1204 1205 hw_dbg(hw, "Detected EEPROM page size = %d words.\n", 1206 hw->eeprom.word_page_size); 1207 return 0; 1208 } 1209 1210 /** 1211 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1212 * @hw: pointer to hardware structure 1213 * @offset: offset of word in the EEPROM to read 1214 * @data: word read from the EEPROM 1215 * 1216 * Reads a 16 bit word from the EEPROM using the EERD register. 1217 **/ 1218 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1219 { 1220 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1221 } 1222 1223 /** 1224 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1225 * @hw: pointer to hardware structure 1226 * @offset: offset of word in the EEPROM to write 1227 * @words: number of words 1228 * @data: word(s) write to the EEPROM 1229 * 1230 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1231 **/ 1232 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1233 u16 words, u16 *data) 1234 { 1235 u32 eewr; 1236 s32 status; 1237 u16 i; 1238 1239 hw->eeprom.ops.init_params(hw); 1240 1241 if (words == 0) 1242 return IXGBE_ERR_INVALID_ARGUMENT; 1243 1244 if (offset >= hw->eeprom.word_size) 1245 return IXGBE_ERR_EEPROM; 1246 1247 for (i = 0; i < words; i++) { 1248 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1249 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1250 IXGBE_EEPROM_RW_REG_START; 1251 1252 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1253 if (status) { 1254 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1255 return status; 1256 } 1257 1258 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1259 1260 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1261 if (status) { 1262 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1263 return status; 1264 } 1265 } 1266 1267 return 0; 1268 } 1269 1270 /** 1271 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1272 * @hw: pointer to hardware structure 1273 * @offset: offset of word in the EEPROM to write 1274 * @data: word write to the EEPROM 1275 * 1276 * Write a 16 bit word to the EEPROM using the EEWR register. 1277 **/ 1278 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1279 { 1280 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1281 } 1282 1283 /** 1284 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1285 * @hw: pointer to hardware structure 1286 * @ee_reg: EEPROM flag for polling 1287 * 1288 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1289 * read or write is done respectively. 1290 **/ 1291 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1292 { 1293 u32 i; 1294 u32 reg; 1295 1296 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1297 if (ee_reg == IXGBE_NVM_POLL_READ) 1298 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1299 else 1300 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1301 1302 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1303 return 0; 1304 } 1305 udelay(5); 1306 } 1307 return IXGBE_ERR_EEPROM; 1308 } 1309 1310 /** 1311 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1312 * @hw: pointer to hardware structure 1313 * 1314 * Prepares EEPROM for access using bit-bang method. This function should 1315 * be called before issuing a command to the EEPROM. 1316 **/ 1317 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1318 { 1319 u32 eec; 1320 u32 i; 1321 1322 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) 1323 return IXGBE_ERR_SWFW_SYNC; 1324 1325 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1326 1327 /* Request EEPROM Access */ 1328 eec |= IXGBE_EEC_REQ; 1329 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1330 1331 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1332 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1333 if (eec & IXGBE_EEC_GNT) 1334 break; 1335 udelay(5); 1336 } 1337 1338 /* Release if grant not acquired */ 1339 if (!(eec & IXGBE_EEC_GNT)) { 1340 eec &= ~IXGBE_EEC_REQ; 1341 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1342 hw_dbg(hw, "Could not acquire EEPROM grant\n"); 1343 1344 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1345 return IXGBE_ERR_EEPROM; 1346 } 1347 1348 /* Setup EEPROM for Read/Write */ 1349 /* Clear CS and SK */ 1350 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1351 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1352 IXGBE_WRITE_FLUSH(hw); 1353 udelay(1); 1354 return 0; 1355 } 1356 1357 /** 1358 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1359 * @hw: pointer to hardware structure 1360 * 1361 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1362 **/ 1363 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1364 { 1365 u32 timeout = 2000; 1366 u32 i; 1367 u32 swsm; 1368 1369 /* Get SMBI software semaphore between device drivers first */ 1370 for (i = 0; i < timeout; i++) { 1371 /* 1372 * If the SMBI bit is 0 when we read it, then the bit will be 1373 * set and we have the semaphore 1374 */ 1375 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1376 if (!(swsm & IXGBE_SWSM_SMBI)) 1377 break; 1378 usleep_range(50, 100); 1379 } 1380 1381 if (i == timeout) { 1382 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n"); 1383 /* this release is particularly important because our attempts 1384 * above to get the semaphore may have succeeded, and if there 1385 * was a timeout, we should unconditionally clear the semaphore 1386 * bits to free the driver to make progress 1387 */ 1388 ixgbe_release_eeprom_semaphore(hw); 1389 1390 usleep_range(50, 100); 1391 /* one last try 1392 * If the SMBI bit is 0 when we read it, then the bit will be 1393 * set and we have the semaphore 1394 */ 1395 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1396 if (swsm & IXGBE_SWSM_SMBI) { 1397 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n"); 1398 return IXGBE_ERR_EEPROM; 1399 } 1400 } 1401 1402 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1403 for (i = 0; i < timeout; i++) { 1404 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1405 1406 /* Set the SW EEPROM semaphore bit to request access */ 1407 swsm |= IXGBE_SWSM_SWESMBI; 1408 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); 1409 1410 /* If we set the bit successfully then we got the 1411 * semaphore. 1412 */ 1413 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1414 if (swsm & IXGBE_SWSM_SWESMBI) 1415 break; 1416 1417 usleep_range(50, 100); 1418 } 1419 1420 /* Release semaphores and return error if SW EEPROM semaphore 1421 * was not granted because we don't have access to the EEPROM 1422 */ 1423 if (i >= timeout) { 1424 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n"); 1425 ixgbe_release_eeprom_semaphore(hw); 1426 return IXGBE_ERR_EEPROM; 1427 } 1428 1429 return 0; 1430 } 1431 1432 /** 1433 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1434 * @hw: pointer to hardware structure 1435 * 1436 * This function clears hardware semaphore bits. 1437 **/ 1438 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1439 { 1440 u32 swsm; 1441 1442 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1443 1444 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1445 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1446 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); 1447 IXGBE_WRITE_FLUSH(hw); 1448 } 1449 1450 /** 1451 * ixgbe_ready_eeprom - Polls for EEPROM ready 1452 * @hw: pointer to hardware structure 1453 **/ 1454 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1455 { 1456 u16 i; 1457 u8 spi_stat_reg; 1458 1459 /* 1460 * Read "Status Register" repeatedly until the LSB is cleared. The 1461 * EEPROM will signal that the command has been completed by clearing 1462 * bit 0 of the internal status register. If it's not cleared within 1463 * 5 milliseconds, then error out. 1464 */ 1465 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 1466 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1467 IXGBE_EEPROM_OPCODE_BITS); 1468 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 1469 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 1470 break; 1471 1472 udelay(5); 1473 ixgbe_standby_eeprom(hw); 1474 } 1475 1476 /* 1477 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 1478 * devices (and only 0-5mSec on 5V devices) 1479 */ 1480 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 1481 hw_dbg(hw, "SPI EEPROM Status error\n"); 1482 return IXGBE_ERR_EEPROM; 1483 } 1484 1485 return 0; 1486 } 1487 1488 /** 1489 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 1490 * @hw: pointer to hardware structure 1491 **/ 1492 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 1493 { 1494 u32 eec; 1495 1496 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1497 1498 /* Toggle CS to flush commands */ 1499 eec |= IXGBE_EEC_CS; 1500 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1501 IXGBE_WRITE_FLUSH(hw); 1502 udelay(1); 1503 eec &= ~IXGBE_EEC_CS; 1504 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1505 IXGBE_WRITE_FLUSH(hw); 1506 udelay(1); 1507 } 1508 1509 /** 1510 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 1511 * @hw: pointer to hardware structure 1512 * @data: data to send to the EEPROM 1513 * @count: number of bits to shift out 1514 **/ 1515 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 1516 u16 count) 1517 { 1518 u32 eec; 1519 u32 mask; 1520 u32 i; 1521 1522 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1523 1524 /* 1525 * Mask is used to shift "count" bits of "data" out to the EEPROM 1526 * one bit at a time. Determine the starting bit based on count 1527 */ 1528 mask = BIT(count - 1); 1529 1530 for (i = 0; i < count; i++) { 1531 /* 1532 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 1533 * "1", and then raising and then lowering the clock (the SK 1534 * bit controls the clock input to the EEPROM). A "0" is 1535 * shifted out to the EEPROM by setting "DI" to "0" and then 1536 * raising and then lowering the clock. 1537 */ 1538 if (data & mask) 1539 eec |= IXGBE_EEC_DI; 1540 else 1541 eec &= ~IXGBE_EEC_DI; 1542 1543 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1544 IXGBE_WRITE_FLUSH(hw); 1545 1546 udelay(1); 1547 1548 ixgbe_raise_eeprom_clk(hw, &eec); 1549 ixgbe_lower_eeprom_clk(hw, &eec); 1550 1551 /* 1552 * Shift mask to signify next bit of data to shift in to the 1553 * EEPROM 1554 */ 1555 mask = mask >> 1; 1556 } 1557 1558 /* We leave the "DI" bit set to "0" when we leave this routine. */ 1559 eec &= ~IXGBE_EEC_DI; 1560 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1561 IXGBE_WRITE_FLUSH(hw); 1562 } 1563 1564 /** 1565 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 1566 * @hw: pointer to hardware structure 1567 **/ 1568 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 1569 { 1570 u32 eec; 1571 u32 i; 1572 u16 data = 0; 1573 1574 /* 1575 * In order to read a register from the EEPROM, we need to shift 1576 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 1577 * the clock input to the EEPROM (setting the SK bit), and then reading 1578 * the value of the "DO" bit. During this "shifting in" process the 1579 * "DI" bit should always be clear. 1580 */ 1581 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1582 1583 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 1584 1585 for (i = 0; i < count; i++) { 1586 data = data << 1; 1587 ixgbe_raise_eeprom_clk(hw, &eec); 1588 1589 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1590 1591 eec &= ~(IXGBE_EEC_DI); 1592 if (eec & IXGBE_EEC_DO) 1593 data |= 1; 1594 1595 ixgbe_lower_eeprom_clk(hw, &eec); 1596 } 1597 1598 return data; 1599 } 1600 1601 /** 1602 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1603 * @hw: pointer to hardware structure 1604 * @eec: EEC register's current value 1605 **/ 1606 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1607 { 1608 /* 1609 * Raise the clock input to the EEPROM 1610 * (setting the SK bit), then delay 1611 */ 1612 *eec = *eec | IXGBE_EEC_SK; 1613 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); 1614 IXGBE_WRITE_FLUSH(hw); 1615 udelay(1); 1616 } 1617 1618 /** 1619 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1620 * @hw: pointer to hardware structure 1621 * @eecd: EECD's current value 1622 **/ 1623 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1624 { 1625 /* 1626 * Lower the clock input to the EEPROM (clearing the SK bit), then 1627 * delay 1628 */ 1629 *eec = *eec & ~IXGBE_EEC_SK; 1630 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); 1631 IXGBE_WRITE_FLUSH(hw); 1632 udelay(1); 1633 } 1634 1635 /** 1636 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1637 * @hw: pointer to hardware structure 1638 **/ 1639 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 1640 { 1641 u32 eec; 1642 1643 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1644 1645 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1646 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1647 1648 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1649 IXGBE_WRITE_FLUSH(hw); 1650 1651 udelay(1); 1652 1653 /* Stop requesting EEPROM access */ 1654 eec &= ~IXGBE_EEC_REQ; 1655 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1656 1657 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1658 1659 /* 1660 * Delay before attempt to obtain semaphore again to allow FW 1661 * access. semaphore_delay is in ms we need us for usleep_range 1662 */ 1663 usleep_range(hw->eeprom.semaphore_delay * 1000, 1664 hw->eeprom.semaphore_delay * 2000); 1665 } 1666 1667 /** 1668 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 1669 * @hw: pointer to hardware structure 1670 **/ 1671 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 1672 { 1673 u16 i; 1674 u16 j; 1675 u16 checksum = 0; 1676 u16 length = 0; 1677 u16 pointer = 0; 1678 u16 word = 0; 1679 1680 /* Include 0x0-0x3F in the checksum */ 1681 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1682 if (hw->eeprom.ops.read(hw, i, &word)) { 1683 hw_dbg(hw, "EEPROM read failed\n"); 1684 break; 1685 } 1686 checksum += word; 1687 } 1688 1689 /* Include all data from pointers except for the fw pointer */ 1690 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1691 if (hw->eeprom.ops.read(hw, i, &pointer)) { 1692 hw_dbg(hw, "EEPROM read failed\n"); 1693 return IXGBE_ERR_EEPROM; 1694 } 1695 1696 /* If the pointer seems invalid */ 1697 if (pointer == 0xFFFF || pointer == 0) 1698 continue; 1699 1700 if (hw->eeprom.ops.read(hw, pointer, &length)) { 1701 hw_dbg(hw, "EEPROM read failed\n"); 1702 return IXGBE_ERR_EEPROM; 1703 } 1704 1705 if (length == 0xFFFF || length == 0) 1706 continue; 1707 1708 for (j = pointer + 1; j <= pointer + length; j++) { 1709 if (hw->eeprom.ops.read(hw, j, &word)) { 1710 hw_dbg(hw, "EEPROM read failed\n"); 1711 return IXGBE_ERR_EEPROM; 1712 } 1713 checksum += word; 1714 } 1715 } 1716 1717 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1718 1719 return (s32)checksum; 1720 } 1721 1722 /** 1723 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1724 * @hw: pointer to hardware structure 1725 * @checksum_val: calculated checksum 1726 * 1727 * Performs checksum calculation and validates the EEPROM checksum. If the 1728 * caller does not need checksum_val, the value can be NULL. 1729 **/ 1730 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1731 u16 *checksum_val) 1732 { 1733 s32 status; 1734 u16 checksum; 1735 u16 read_checksum = 0; 1736 1737 /* 1738 * Read the first word from the EEPROM. If this times out or fails, do 1739 * not continue or we could be in for a very long wait while every 1740 * EEPROM read fails 1741 */ 1742 status = hw->eeprom.ops.read(hw, 0, &checksum); 1743 if (status) { 1744 hw_dbg(hw, "EEPROM read failed\n"); 1745 return status; 1746 } 1747 1748 status = hw->eeprom.ops.calc_checksum(hw); 1749 if (status < 0) 1750 return status; 1751 1752 checksum = (u16)(status & 0xffff); 1753 1754 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1755 if (status) { 1756 hw_dbg(hw, "EEPROM read failed\n"); 1757 return status; 1758 } 1759 1760 /* Verify read checksum from EEPROM is the same as 1761 * calculated checksum 1762 */ 1763 if (read_checksum != checksum) 1764 status = IXGBE_ERR_EEPROM_CHECKSUM; 1765 1766 /* If the user cares, return the calculated checksum */ 1767 if (checksum_val) 1768 *checksum_val = checksum; 1769 1770 return status; 1771 } 1772 1773 /** 1774 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1775 * @hw: pointer to hardware structure 1776 **/ 1777 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1778 { 1779 s32 status; 1780 u16 checksum; 1781 1782 /* 1783 * Read the first word from the EEPROM. If this times out or fails, do 1784 * not continue or we could be in for a very long wait while every 1785 * EEPROM read fails 1786 */ 1787 status = hw->eeprom.ops.read(hw, 0, &checksum); 1788 if (status) { 1789 hw_dbg(hw, "EEPROM read failed\n"); 1790 return status; 1791 } 1792 1793 status = hw->eeprom.ops.calc_checksum(hw); 1794 if (status < 0) 1795 return status; 1796 1797 checksum = (u16)(status & 0xffff); 1798 1799 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 1800 1801 return status; 1802 } 1803 1804 /** 1805 * ixgbe_set_rar_generic - Set Rx address register 1806 * @hw: pointer to hardware structure 1807 * @index: Receive address register to write 1808 * @addr: Address to put into receive address register 1809 * @vmdq: VMDq "set" or "pool" index 1810 * @enable_addr: set flag that address is active 1811 * 1812 * Puts an ethernet address into a receive address register. 1813 **/ 1814 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1815 u32 enable_addr) 1816 { 1817 u32 rar_low, rar_high; 1818 u32 rar_entries = hw->mac.num_rar_entries; 1819 1820 /* Make sure we are using a valid rar index range */ 1821 if (index >= rar_entries) { 1822 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1823 return IXGBE_ERR_INVALID_ARGUMENT; 1824 } 1825 1826 /* setup VMDq pool selection before this RAR gets enabled */ 1827 hw->mac.ops.set_vmdq(hw, index, vmdq); 1828 1829 /* 1830 * HW expects these in little endian so we reverse the byte 1831 * order from network order (big endian) to little endian 1832 */ 1833 rar_low = ((u32)addr[0] | 1834 ((u32)addr[1] << 8) | 1835 ((u32)addr[2] << 16) | 1836 ((u32)addr[3] << 24)); 1837 /* 1838 * Some parts put the VMDq setting in the extra RAH bits, 1839 * so save everything except the lower 16 bits that hold part 1840 * of the address and the address valid bit. 1841 */ 1842 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1843 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1844 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1845 1846 if (enable_addr != 0) 1847 rar_high |= IXGBE_RAH_AV; 1848 1849 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1850 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1851 1852 return 0; 1853 } 1854 1855 /** 1856 * ixgbe_clear_rar_generic - Remove Rx address register 1857 * @hw: pointer to hardware structure 1858 * @index: Receive address register to write 1859 * 1860 * Clears an ethernet address from a receive address register. 1861 **/ 1862 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1863 { 1864 u32 rar_high; 1865 u32 rar_entries = hw->mac.num_rar_entries; 1866 1867 /* Make sure we are using a valid rar index range */ 1868 if (index >= rar_entries) { 1869 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1870 return IXGBE_ERR_INVALID_ARGUMENT; 1871 } 1872 1873 /* 1874 * Some parts put the VMDq setting in the extra RAH bits, 1875 * so save everything except the lower 16 bits that hold part 1876 * of the address and the address valid bit. 1877 */ 1878 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1879 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1880 1881 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1882 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1883 1884 /* clear VMDq pool/queue selection for this RAR */ 1885 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1886 1887 return 0; 1888 } 1889 1890 /** 1891 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1892 * @hw: pointer to hardware structure 1893 * 1894 * Places the MAC address in receive address register 0 and clears the rest 1895 * of the receive address registers. Clears the multicast table. Assumes 1896 * the receiver is in reset when the routine is called. 1897 **/ 1898 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1899 { 1900 u32 i; 1901 u32 rar_entries = hw->mac.num_rar_entries; 1902 1903 /* 1904 * If the current mac address is valid, assume it is a software override 1905 * to the permanent address. 1906 * Otherwise, use the permanent address from the eeprom. 1907 */ 1908 if (!is_valid_ether_addr(hw->mac.addr)) { 1909 /* Get the MAC address from the RAR0 for later reference */ 1910 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1911 1912 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr); 1913 } else { 1914 /* Setup the receive address. */ 1915 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); 1916 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr); 1917 1918 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1919 } 1920 1921 /* clear VMDq pool/queue selection for RAR 0 */ 1922 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 1923 1924 hw->addr_ctrl.overflow_promisc = 0; 1925 1926 hw->addr_ctrl.rar_used_count = 1; 1927 1928 /* Zero out the other receive addresses. */ 1929 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); 1930 for (i = 1; i < rar_entries; i++) { 1931 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1932 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1933 } 1934 1935 /* Clear the MTA */ 1936 hw->addr_ctrl.mta_in_use = 0; 1937 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1938 1939 hw_dbg(hw, " Clearing MTA\n"); 1940 for (i = 0; i < hw->mac.mcft_size; i++) 1941 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1942 1943 if (hw->mac.ops.init_uta_tables) 1944 hw->mac.ops.init_uta_tables(hw); 1945 1946 return 0; 1947 } 1948 1949 /** 1950 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1951 * @hw: pointer to hardware structure 1952 * @mc_addr: the multicast address 1953 * 1954 * Extracts the 12 bits, from a multicast address, to determine which 1955 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1956 * incoming rx multicast addresses, to determine the bit-vector to check in 1957 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1958 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1959 * to mc_filter_type. 1960 **/ 1961 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 1962 { 1963 u32 vector = 0; 1964 1965 switch (hw->mac.mc_filter_type) { 1966 case 0: /* use bits [47:36] of the address */ 1967 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1968 break; 1969 case 1: /* use bits [46:35] of the address */ 1970 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1971 break; 1972 case 2: /* use bits [45:34] of the address */ 1973 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1974 break; 1975 case 3: /* use bits [43:32] of the address */ 1976 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1977 break; 1978 default: /* Invalid mc_filter_type */ 1979 hw_dbg(hw, "MC filter type param set incorrectly\n"); 1980 break; 1981 } 1982 1983 /* vector can only be 12-bits or boundary will be exceeded */ 1984 vector &= 0xFFF; 1985 return vector; 1986 } 1987 1988 /** 1989 * ixgbe_set_mta - Set bit-vector in multicast table 1990 * @hw: pointer to hardware structure 1991 * @hash_value: Multicast address hash value 1992 * 1993 * Sets the bit-vector in the multicast table. 1994 **/ 1995 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 1996 { 1997 u32 vector; 1998 u32 vector_bit; 1999 u32 vector_reg; 2000 2001 hw->addr_ctrl.mta_in_use++; 2002 2003 vector = ixgbe_mta_vector(hw, mc_addr); 2004 hw_dbg(hw, " bit-vector = 0x%03X\n", vector); 2005 2006 /* 2007 * The MTA is a register array of 128 32-bit registers. It is treated 2008 * like an array of 4096 bits. We want to set bit 2009 * BitArray[vector_value]. So we figure out what register the bit is 2010 * in, read it, OR in the new bit, then write back the new value. The 2011 * register is determined by the upper 7 bits of the vector value and 2012 * the bit within that register are determined by the lower 5 bits of 2013 * the value. 2014 */ 2015 vector_reg = (vector >> 5) & 0x7F; 2016 vector_bit = vector & 0x1F; 2017 hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit); 2018 } 2019 2020 /** 2021 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2022 * @hw: pointer to hardware structure 2023 * @netdev: pointer to net device structure 2024 * 2025 * The given list replaces any existing list. Clears the MC addrs from receive 2026 * address registers and the multicast table. Uses unused receive address 2027 * registers for the first multicast addresses, and hashes the rest into the 2028 * multicast table. 2029 **/ 2030 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, 2031 struct net_device *netdev) 2032 { 2033 struct netdev_hw_addr *ha; 2034 u32 i; 2035 2036 /* 2037 * Set the new number of MC addresses that we are being requested to 2038 * use. 2039 */ 2040 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); 2041 hw->addr_ctrl.mta_in_use = 0; 2042 2043 /* Clear mta_shadow */ 2044 hw_dbg(hw, " Clearing MTA\n"); 2045 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2046 2047 /* Update mta shadow */ 2048 netdev_for_each_mc_addr(ha, netdev) { 2049 hw_dbg(hw, " Adding the multicast addresses:\n"); 2050 ixgbe_set_mta(hw, ha->addr); 2051 } 2052 2053 /* Enable mta */ 2054 for (i = 0; i < hw->mac.mcft_size; i++) 2055 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2056 hw->mac.mta_shadow[i]); 2057 2058 if (hw->addr_ctrl.mta_in_use > 0) 2059 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2060 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2061 2062 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); 2063 return 0; 2064 } 2065 2066 /** 2067 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2068 * @hw: pointer to hardware structure 2069 * 2070 * Enables multicast address in RAR and the use of the multicast hash table. 2071 **/ 2072 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2073 { 2074 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2075 2076 if (a->mta_in_use > 0) 2077 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2078 hw->mac.mc_filter_type); 2079 2080 return 0; 2081 } 2082 2083 /** 2084 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2085 * @hw: pointer to hardware structure 2086 * 2087 * Disables multicast address in RAR and the use of the multicast hash table. 2088 **/ 2089 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2090 { 2091 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2092 2093 if (a->mta_in_use > 0) 2094 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2095 2096 return 0; 2097 } 2098 2099 /** 2100 * ixgbe_fc_enable_generic - Enable flow control 2101 * @hw: pointer to hardware structure 2102 * 2103 * Enable flow control according to the current settings. 2104 **/ 2105 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2106 { 2107 u32 mflcn_reg, fccfg_reg; 2108 u32 reg; 2109 u32 fcrtl, fcrth; 2110 int i; 2111 2112 /* Validate the water mark configuration. */ 2113 if (!hw->fc.pause_time) 2114 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2115 2116 /* Low water mark of zero causes XOFF floods */ 2117 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 2118 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2119 hw->fc.high_water[i]) { 2120 if (!hw->fc.low_water[i] || 2121 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2122 hw_dbg(hw, "Invalid water mark configuration\n"); 2123 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2124 } 2125 } 2126 } 2127 2128 /* Negotiate the fc mode to use */ 2129 ixgbe_fc_autoneg(hw); 2130 2131 /* Disable any previous flow control settings */ 2132 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2133 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2134 2135 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2136 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2137 2138 /* 2139 * The possible values of fc.current_mode are: 2140 * 0: Flow control is completely disabled 2141 * 1: Rx flow control is enabled (we can receive pause frames, 2142 * but not send pause frames). 2143 * 2: Tx flow control is enabled (we can send pause frames but 2144 * we do not support receiving pause frames). 2145 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2146 * other: Invalid. 2147 */ 2148 switch (hw->fc.current_mode) { 2149 case ixgbe_fc_none: 2150 /* 2151 * Flow control is disabled by software override or autoneg. 2152 * The code below will actually disable it in the HW. 2153 */ 2154 break; 2155 case ixgbe_fc_rx_pause: 2156 /* 2157 * Rx Flow control is enabled and Tx Flow control is 2158 * disabled by software override. Since there really 2159 * isn't a way to advertise that we are capable of RX 2160 * Pause ONLY, we will advertise that we support both 2161 * symmetric and asymmetric Rx PAUSE. Later, we will 2162 * disable the adapter's ability to send PAUSE frames. 2163 */ 2164 mflcn_reg |= IXGBE_MFLCN_RFCE; 2165 break; 2166 case ixgbe_fc_tx_pause: 2167 /* 2168 * Tx Flow control is enabled, and Rx Flow control is 2169 * disabled by software override. 2170 */ 2171 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2172 break; 2173 case ixgbe_fc_full: 2174 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2175 mflcn_reg |= IXGBE_MFLCN_RFCE; 2176 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2177 break; 2178 default: 2179 hw_dbg(hw, "Flow control param set incorrectly\n"); 2180 return IXGBE_ERR_CONFIG; 2181 } 2182 2183 /* Set 802.3x based flow control settings. */ 2184 mflcn_reg |= IXGBE_MFLCN_DPF; 2185 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2186 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2187 2188 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2189 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 2190 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2191 hw->fc.high_water[i]) { 2192 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2193 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2194 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2195 } else { 2196 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2197 /* 2198 * In order to prevent Tx hangs when the internal Tx 2199 * switch is enabled we must set the high water mark 2200 * to the Rx packet buffer size - 24KB. This allows 2201 * the Tx switch to function even under heavy Rx 2202 * workloads. 2203 */ 2204 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2205 } 2206 2207 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2208 } 2209 2210 /* Configure pause time (2 TCs per register) */ 2211 reg = hw->fc.pause_time * 0x00010001; 2212 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 2213 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2214 2215 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2216 2217 return 0; 2218 } 2219 2220 /** 2221 * ixgbe_negotiate_fc - Negotiate flow control 2222 * @hw: pointer to hardware structure 2223 * @adv_reg: flow control advertised settings 2224 * @lp_reg: link partner's flow control settings 2225 * @adv_sym: symmetric pause bit in advertisement 2226 * @adv_asm: asymmetric pause bit in advertisement 2227 * @lp_sym: symmetric pause bit in link partner advertisement 2228 * @lp_asm: asymmetric pause bit in link partner advertisement 2229 * 2230 * Find the intersection between advertised settings and link partner's 2231 * advertised settings 2232 **/ 2233 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2234 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2235 { 2236 if ((!(adv_reg)) || (!(lp_reg))) 2237 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2238 2239 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2240 /* 2241 * Now we need to check if the user selected Rx ONLY 2242 * of pause frames. In this case, we had to advertise 2243 * FULL flow control because we could not advertise RX 2244 * ONLY. Hence, we must now check to see if we need to 2245 * turn OFF the TRANSMISSION of PAUSE frames. 2246 */ 2247 if (hw->fc.requested_mode == ixgbe_fc_full) { 2248 hw->fc.current_mode = ixgbe_fc_full; 2249 hw_dbg(hw, "Flow Control = FULL.\n"); 2250 } else { 2251 hw->fc.current_mode = ixgbe_fc_rx_pause; 2252 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n"); 2253 } 2254 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2255 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2256 hw->fc.current_mode = ixgbe_fc_tx_pause; 2257 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); 2258 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2259 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2260 hw->fc.current_mode = ixgbe_fc_rx_pause; 2261 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); 2262 } else { 2263 hw->fc.current_mode = ixgbe_fc_none; 2264 hw_dbg(hw, "Flow Control = NONE.\n"); 2265 } 2266 return 0; 2267 } 2268 2269 /** 2270 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 2271 * @hw: pointer to hardware structure 2272 * 2273 * Enable flow control according on 1 gig fiber. 2274 **/ 2275 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 2276 { 2277 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 2278 s32 ret_val; 2279 2280 /* 2281 * On multispeed fiber at 1g, bail out if 2282 * - link is up but AN did not complete, or if 2283 * - link is up and AN completed but timed out 2284 */ 2285 2286 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 2287 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 2288 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) 2289 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2290 2291 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2292 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 2293 2294 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 2295 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 2296 IXGBE_PCS1GANA_ASM_PAUSE, 2297 IXGBE_PCS1GANA_SYM_PAUSE, 2298 IXGBE_PCS1GANA_ASM_PAUSE); 2299 2300 return ret_val; 2301 } 2302 2303 /** 2304 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 2305 * @hw: pointer to hardware structure 2306 * 2307 * Enable flow control according to IEEE clause 37. 2308 **/ 2309 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 2310 { 2311 u32 links2, anlp1_reg, autoc_reg, links; 2312 s32 ret_val; 2313 2314 /* 2315 * On backplane, bail out if 2316 * - backplane autoneg was not completed, or if 2317 * - we are 82599 and link partner is not AN enabled 2318 */ 2319 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 2320 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) 2321 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2322 2323 if (hw->mac.type == ixgbe_mac_82599EB) { 2324 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 2325 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) 2326 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2327 } 2328 /* 2329 * Read the 10g AN autoc and LP ability registers and resolve 2330 * local flow control settings accordingly 2331 */ 2332 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2333 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2334 2335 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 2336 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 2337 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 2338 2339 return ret_val; 2340 } 2341 2342 /** 2343 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 2344 * @hw: pointer to hardware structure 2345 * 2346 * Enable flow control according to IEEE clause 37. 2347 **/ 2348 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 2349 { 2350 u16 technology_ability_reg = 0; 2351 u16 lp_technology_ability_reg = 0; 2352 2353 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 2354 MDIO_MMD_AN, 2355 &technology_ability_reg); 2356 hw->phy.ops.read_reg(hw, MDIO_AN_LPA, 2357 MDIO_MMD_AN, 2358 &lp_technology_ability_reg); 2359 2360 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 2361 (u32)lp_technology_ability_reg, 2362 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 2363 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 2364 } 2365 2366 /** 2367 * ixgbe_fc_autoneg - Configure flow control 2368 * @hw: pointer to hardware structure 2369 * 2370 * Compares our advertised flow control capabilities to those advertised by 2371 * our link partner, and determines the proper flow control mode to use. 2372 **/ 2373 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 2374 { 2375 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2376 ixgbe_link_speed speed; 2377 bool link_up; 2378 2379 /* 2380 * AN should have completed when the cable was plugged in. 2381 * Look for reasons to bail out. Bail out if: 2382 * - FC autoneg is disabled, or if 2383 * - link is not up. 2384 * 2385 * Since we're being called from an LSC, link is already known to be up. 2386 * So use link_up_wait_to_complete=false. 2387 */ 2388 if (hw->fc.disable_fc_autoneg) 2389 goto out; 2390 2391 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2392 if (!link_up) 2393 goto out; 2394 2395 switch (hw->phy.media_type) { 2396 /* Autoneg flow control on fiber adapters */ 2397 case ixgbe_media_type_fiber: 2398 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 2399 ret_val = ixgbe_fc_autoneg_fiber(hw); 2400 break; 2401 2402 /* Autoneg flow control on backplane adapters */ 2403 case ixgbe_media_type_backplane: 2404 ret_val = ixgbe_fc_autoneg_backplane(hw); 2405 break; 2406 2407 /* Autoneg flow control on copper adapters */ 2408 case ixgbe_media_type_copper: 2409 if (ixgbe_device_supports_autoneg_fc(hw)) 2410 ret_val = ixgbe_fc_autoneg_copper(hw); 2411 break; 2412 2413 default: 2414 break; 2415 } 2416 2417 out: 2418 if (ret_val == 0) { 2419 hw->fc.fc_was_autonegged = true; 2420 } else { 2421 hw->fc.fc_was_autonegged = false; 2422 hw->fc.current_mode = hw->fc.requested_mode; 2423 } 2424 } 2425 2426 /** 2427 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 2428 * @hw: pointer to hardware structure 2429 * 2430 * System-wide timeout range is encoded in PCIe Device Control2 register. 2431 * 2432 * Add 10% to specified maximum and return the number of times to poll for 2433 * completion timeout, in units of 100 microsec. Never return less than 2434 * 800 = 80 millisec. 2435 **/ 2436 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 2437 { 2438 s16 devctl2; 2439 u32 pollcnt; 2440 2441 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); 2442 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 2443 2444 switch (devctl2) { 2445 case IXGBE_PCIDEVCTRL2_65_130ms: 2446 pollcnt = 1300; /* 130 millisec */ 2447 break; 2448 case IXGBE_PCIDEVCTRL2_260_520ms: 2449 pollcnt = 5200; /* 520 millisec */ 2450 break; 2451 case IXGBE_PCIDEVCTRL2_1_2s: 2452 pollcnt = 20000; /* 2 sec */ 2453 break; 2454 case IXGBE_PCIDEVCTRL2_4_8s: 2455 pollcnt = 80000; /* 8 sec */ 2456 break; 2457 case IXGBE_PCIDEVCTRL2_17_34s: 2458 pollcnt = 34000; /* 34 sec */ 2459 break; 2460 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 2461 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 2462 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 2463 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 2464 default: 2465 pollcnt = 800; /* 80 millisec minimum */ 2466 break; 2467 } 2468 2469 /* add 10% to spec maximum */ 2470 return (pollcnt * 11) / 10; 2471 } 2472 2473 /** 2474 * ixgbe_disable_pcie_master - Disable PCI-express master access 2475 * @hw: pointer to hardware structure 2476 * 2477 * Disables PCI-Express master access and verifies there are no pending 2478 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 2479 * bit hasn't caused the master requests to be disabled, else 0 2480 * is returned signifying master requests disabled. 2481 **/ 2482 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 2483 { 2484 u32 i, poll; 2485 u16 value; 2486 2487 /* Always set this bit to ensure any future transactions are blocked */ 2488 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 2489 2490 /* Poll for bit to read as set */ 2491 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2492 if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS) 2493 break; 2494 usleep_range(100, 120); 2495 } 2496 if (i >= IXGBE_PCI_MASTER_DISABLE_TIMEOUT) { 2497 hw_dbg(hw, "GIO disable did not set - requesting resets\n"); 2498 goto gio_disable_fail; 2499 } 2500 2501 /* Exit if master requests are blocked */ 2502 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 2503 ixgbe_removed(hw->hw_addr)) 2504 return 0; 2505 2506 /* Poll for master request bit to clear */ 2507 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2508 udelay(100); 2509 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2510 return 0; 2511 } 2512 2513 /* 2514 * Two consecutive resets are required via CTRL.RST per datasheet 2515 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 2516 * of this need. The first reset prevents new master requests from 2517 * being issued by our device. We then must wait 1usec or more for any 2518 * remaining completions from the PCIe bus to trickle in, and then reset 2519 * again to clear out any effects they may have had on our device. 2520 */ 2521 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n"); 2522 gio_disable_fail: 2523 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2524 2525 if (hw->mac.type >= ixgbe_mac_X550) 2526 return 0; 2527 2528 /* 2529 * Before proceeding, make sure that the PCIe block does not have 2530 * transactions pending. 2531 */ 2532 poll = ixgbe_pcie_timeout_poll(hw); 2533 for (i = 0; i < poll; i++) { 2534 udelay(100); 2535 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); 2536 if (ixgbe_removed(hw->hw_addr)) 2537 return 0; 2538 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 2539 return 0; 2540 } 2541 2542 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n"); 2543 return IXGBE_ERR_MASTER_REQUESTS_PENDING; 2544 } 2545 2546 /** 2547 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 2548 * @hw: pointer to hardware structure 2549 * @mask: Mask to specify which semaphore to acquire 2550 * 2551 * Acquires the SWFW semaphore through the GSSR register for the specified 2552 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2553 **/ 2554 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 2555 { 2556 u32 gssr = 0; 2557 u32 swmask = mask; 2558 u32 fwmask = mask << 5; 2559 u32 timeout = 200; 2560 u32 i; 2561 2562 for (i = 0; i < timeout; i++) { 2563 /* 2564 * SW NVM semaphore bit is used for access to all 2565 * SW_FW_SYNC bits (not just NVM) 2566 */ 2567 if (ixgbe_get_eeprom_semaphore(hw)) 2568 return IXGBE_ERR_SWFW_SYNC; 2569 2570 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2571 if (!(gssr & (fwmask | swmask))) { 2572 gssr |= swmask; 2573 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2574 ixgbe_release_eeprom_semaphore(hw); 2575 return 0; 2576 } else { 2577 /* Resource is currently in use by FW or SW */ 2578 ixgbe_release_eeprom_semaphore(hw); 2579 usleep_range(5000, 10000); 2580 } 2581 } 2582 2583 /* If time expired clear the bits holding the lock and retry */ 2584 if (gssr & (fwmask | swmask)) 2585 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 2586 2587 usleep_range(5000, 10000); 2588 return IXGBE_ERR_SWFW_SYNC; 2589 } 2590 2591 /** 2592 * ixgbe_release_swfw_sync - Release SWFW semaphore 2593 * @hw: pointer to hardware structure 2594 * @mask: Mask to specify which semaphore to release 2595 * 2596 * Releases the SWFW semaphore through the GSSR register for the specified 2597 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2598 **/ 2599 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 2600 { 2601 u32 gssr; 2602 u32 swmask = mask; 2603 2604 ixgbe_get_eeprom_semaphore(hw); 2605 2606 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2607 gssr &= ~swmask; 2608 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2609 2610 ixgbe_release_eeprom_semaphore(hw); 2611 } 2612 2613 /** 2614 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 2615 * @hw: pointer to hardware structure 2616 * @reg_val: Value we read from AUTOC 2617 * @locked: bool to indicate whether the SW/FW lock should be taken. Never 2618 * true in this the generic case. 2619 * 2620 * The default case requires no protection so just to the register read. 2621 **/ 2622 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 2623 { 2624 *locked = false; 2625 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2626 return 0; 2627 } 2628 2629 /** 2630 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 2631 * @hw: pointer to hardware structure 2632 * @reg_val: value to write to AUTOC 2633 * @locked: bool to indicate whether the SW/FW lock was already taken by 2634 * previous read. 2635 **/ 2636 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 2637 { 2638 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 2639 return 0; 2640 } 2641 2642 /** 2643 * ixgbe_disable_rx_buff_generic - Stops the receive data path 2644 * @hw: pointer to hardware structure 2645 * 2646 * Stops the receive data path and waits for the HW to internally 2647 * empty the Rx security block. 2648 **/ 2649 s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw) 2650 { 2651 #define IXGBE_MAX_SECRX_POLL 40 2652 int i; 2653 int secrxreg; 2654 2655 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2656 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 2657 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2658 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 2659 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 2660 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 2661 break; 2662 else 2663 /* Use interrupt-safe sleep just in case */ 2664 udelay(1000); 2665 } 2666 2667 /* For informational purposes only */ 2668 if (i >= IXGBE_MAX_SECRX_POLL) 2669 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n"); 2670 2671 return 0; 2672 2673 } 2674 2675 /** 2676 * ixgbe_enable_rx_buff - Enables the receive data path 2677 * @hw: pointer to hardware structure 2678 * 2679 * Enables the receive data path 2680 **/ 2681 s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw) 2682 { 2683 u32 secrxreg; 2684 2685 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2686 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 2687 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2688 IXGBE_WRITE_FLUSH(hw); 2689 2690 return 0; 2691 } 2692 2693 /** 2694 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 2695 * @hw: pointer to hardware structure 2696 * @regval: register value to write to RXCTRL 2697 * 2698 * Enables the Rx DMA unit 2699 **/ 2700 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 2701 { 2702 if (regval & IXGBE_RXCTRL_RXEN) 2703 hw->mac.ops.enable_rx(hw); 2704 else 2705 hw->mac.ops.disable_rx(hw); 2706 2707 return 0; 2708 } 2709 2710 /** 2711 * ixgbe_blink_led_start_generic - Blink LED based on index. 2712 * @hw: pointer to hardware structure 2713 * @index: led number to blink 2714 **/ 2715 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 2716 { 2717 ixgbe_link_speed speed = 0; 2718 bool link_up = false; 2719 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2720 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2721 bool locked = false; 2722 s32 ret_val; 2723 2724 if (index > 3) 2725 return IXGBE_ERR_PARAM; 2726 2727 /* 2728 * Link must be up to auto-blink the LEDs; 2729 * Force it if link is down. 2730 */ 2731 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2732 2733 if (!link_up) { 2734 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 2735 if (ret_val) 2736 return ret_val; 2737 2738 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2739 autoc_reg |= IXGBE_AUTOC_FLU; 2740 2741 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 2742 if (ret_val) 2743 return ret_val; 2744 2745 IXGBE_WRITE_FLUSH(hw); 2746 2747 usleep_range(10000, 20000); 2748 } 2749 2750 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2751 led_reg |= IXGBE_LED_BLINK(index); 2752 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2753 IXGBE_WRITE_FLUSH(hw); 2754 2755 return 0; 2756 } 2757 2758 /** 2759 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 2760 * @hw: pointer to hardware structure 2761 * @index: led number to stop blinking 2762 **/ 2763 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 2764 { 2765 u32 autoc_reg = 0; 2766 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2767 bool locked = false; 2768 s32 ret_val; 2769 2770 if (index > 3) 2771 return IXGBE_ERR_PARAM; 2772 2773 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 2774 if (ret_val) 2775 return ret_val; 2776 2777 autoc_reg &= ~IXGBE_AUTOC_FLU; 2778 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2779 2780 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 2781 if (ret_val) 2782 return ret_val; 2783 2784 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2785 led_reg &= ~IXGBE_LED_BLINK(index); 2786 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 2787 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2788 IXGBE_WRITE_FLUSH(hw); 2789 2790 return 0; 2791 } 2792 2793 /** 2794 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 2795 * @hw: pointer to hardware structure 2796 * @san_mac_offset: SAN MAC address offset 2797 * 2798 * This function will read the EEPROM location for the SAN MAC address 2799 * pointer, and returns the value at that location. This is used in both 2800 * get and set mac_addr routines. 2801 **/ 2802 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 2803 u16 *san_mac_offset) 2804 { 2805 s32 ret_val; 2806 2807 /* 2808 * First read the EEPROM pointer to see if the MAC addresses are 2809 * available. 2810 */ 2811 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 2812 san_mac_offset); 2813 if (ret_val) 2814 hw_err(hw, "eeprom read at offset %d failed\n", 2815 IXGBE_SAN_MAC_ADDR_PTR); 2816 2817 return ret_val; 2818 } 2819 2820 /** 2821 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 2822 * @hw: pointer to hardware structure 2823 * @san_mac_addr: SAN MAC address 2824 * 2825 * Reads the SAN MAC address from the EEPROM, if it's available. This is 2826 * per-port, so set_lan_id() must be called before reading the addresses. 2827 * set_lan_id() is called by identify_sfp(), but this cannot be relied 2828 * upon for non-SFP connections, so we must call it here. 2829 **/ 2830 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2831 { 2832 u16 san_mac_data, san_mac_offset; 2833 u8 i; 2834 s32 ret_val; 2835 2836 /* 2837 * First read the EEPROM pointer to see if the MAC addresses are 2838 * available. If they're not, no point in calling set_lan_id() here. 2839 */ 2840 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2841 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 2842 2843 goto san_mac_addr_clr; 2844 2845 /* make sure we know which port we need to program */ 2846 hw->mac.ops.set_lan_id(hw); 2847 /* apply the port offset to the address offset */ 2848 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2849 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2850 for (i = 0; i < 3; i++) { 2851 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 2852 &san_mac_data); 2853 if (ret_val) { 2854 hw_err(hw, "eeprom read at offset %d failed\n", 2855 san_mac_offset); 2856 goto san_mac_addr_clr; 2857 } 2858 san_mac_addr[i * 2] = (u8)(san_mac_data); 2859 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 2860 san_mac_offset++; 2861 } 2862 return 0; 2863 2864 san_mac_addr_clr: 2865 /* No addresses available in this EEPROM. It's not necessarily an 2866 * error though, so just wipe the local address and return. 2867 */ 2868 for (i = 0; i < 6; i++) 2869 san_mac_addr[i] = 0xFF; 2870 return ret_val; 2871 } 2872 2873 /** 2874 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 2875 * @hw: pointer to hardware structure 2876 * 2877 * Read PCIe configuration space, and get the MSI-X vector count from 2878 * the capabilities table. 2879 **/ 2880 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 2881 { 2882 u16 msix_count; 2883 u16 max_msix_count; 2884 u16 pcie_offset; 2885 2886 switch (hw->mac.type) { 2887 case ixgbe_mac_82598EB: 2888 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 2889 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 2890 break; 2891 case ixgbe_mac_82599EB: 2892 case ixgbe_mac_X540: 2893 case ixgbe_mac_X550: 2894 case ixgbe_mac_X550EM_x: 2895 case ixgbe_mac_x550em_a: 2896 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 2897 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 2898 break; 2899 default: 2900 return 1; 2901 } 2902 2903 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset); 2904 if (ixgbe_removed(hw->hw_addr)) 2905 msix_count = 0; 2906 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 2907 2908 /* MSI-X count is zero-based in HW */ 2909 msix_count++; 2910 2911 if (msix_count > max_msix_count) 2912 msix_count = max_msix_count; 2913 2914 return msix_count; 2915 } 2916 2917 /** 2918 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 2919 * @hw: pointer to hardware struct 2920 * @rar: receive address register index to disassociate 2921 * @vmdq: VMDq pool index to remove from the rar 2922 **/ 2923 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2924 { 2925 u32 mpsar_lo, mpsar_hi; 2926 u32 rar_entries = hw->mac.num_rar_entries; 2927 2928 /* Make sure we are using a valid rar index range */ 2929 if (rar >= rar_entries) { 2930 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 2931 return IXGBE_ERR_INVALID_ARGUMENT; 2932 } 2933 2934 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2935 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2936 2937 if (ixgbe_removed(hw->hw_addr)) 2938 return 0; 2939 2940 if (!mpsar_lo && !mpsar_hi) 2941 return 0; 2942 2943 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 2944 if (mpsar_lo) { 2945 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 2946 mpsar_lo = 0; 2947 } 2948 if (mpsar_hi) { 2949 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 2950 mpsar_hi = 0; 2951 } 2952 } else if (vmdq < 32) { 2953 mpsar_lo &= ~BIT(vmdq); 2954 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 2955 } else { 2956 mpsar_hi &= ~BIT(vmdq - 32); 2957 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 2958 } 2959 2960 /* was that the last pool using this rar? */ 2961 if (mpsar_lo == 0 && mpsar_hi == 0 && 2962 rar != 0 && rar != hw->mac.san_mac_rar_index) 2963 hw->mac.ops.clear_rar(hw, rar); 2964 2965 return 0; 2966 } 2967 2968 /** 2969 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 2970 * @hw: pointer to hardware struct 2971 * @rar: receive address register index to associate with a VMDq index 2972 * @vmdq: VMDq pool index 2973 **/ 2974 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2975 { 2976 u32 mpsar; 2977 u32 rar_entries = hw->mac.num_rar_entries; 2978 2979 /* Make sure we are using a valid rar index range */ 2980 if (rar >= rar_entries) { 2981 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 2982 return IXGBE_ERR_INVALID_ARGUMENT; 2983 } 2984 2985 if (vmdq < 32) { 2986 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2987 mpsar |= BIT(vmdq); 2988 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 2989 } else { 2990 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2991 mpsar |= BIT(vmdq - 32); 2992 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 2993 } 2994 return 0; 2995 } 2996 2997 /** 2998 * This function should only be involved in the IOV mode. 2999 * In IOV mode, Default pool is next pool after the number of 3000 * VFs advertized and not 0. 3001 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3002 * 3003 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address 3004 * @hw: pointer to hardware struct 3005 * @vmdq: VMDq pool index 3006 **/ 3007 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3008 { 3009 u32 rar = hw->mac.san_mac_rar_index; 3010 3011 if (vmdq < 32) { 3012 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq)); 3013 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3014 } else { 3015 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3016 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32)); 3017 } 3018 3019 return 0; 3020 } 3021 3022 /** 3023 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3024 * @hw: pointer to hardware structure 3025 **/ 3026 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3027 { 3028 int i; 3029 3030 for (i = 0; i < 128; i++) 3031 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3032 3033 return 0; 3034 } 3035 3036 /** 3037 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3038 * @hw: pointer to hardware structure 3039 * @vlan: VLAN id to write to VLAN filter 3040 * 3041 * return the VLVF index where this VLAN id should be placed 3042 * 3043 **/ 3044 static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) 3045 { 3046 s32 regindex, first_empty_slot; 3047 u32 bits; 3048 3049 /* short cut the special case */ 3050 if (vlan == 0) 3051 return 0; 3052 3053 /* if vlvf_bypass is set we don't want to use an empty slot, we 3054 * will simply bypass the VLVF if there are no entries present in the 3055 * VLVF that contain our VLAN 3056 */ 3057 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0; 3058 3059 /* add VLAN enable bit for comparison */ 3060 vlan |= IXGBE_VLVF_VIEN; 3061 3062 /* Search for the vlan id in the VLVF entries. Save off the first empty 3063 * slot found along the way. 3064 * 3065 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 3066 */ 3067 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { 3068 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3069 if (bits == vlan) 3070 return regindex; 3071 if (!first_empty_slot && !bits) 3072 first_empty_slot = regindex; 3073 } 3074 3075 /* If we are here then we didn't find the VLAN. Return first empty 3076 * slot we found during our search, else error. 3077 */ 3078 if (!first_empty_slot) 3079 hw_dbg(hw, "No space in VLVF.\n"); 3080 3081 return first_empty_slot ? : IXGBE_ERR_NO_SPACE; 3082 } 3083 3084 /** 3085 * ixgbe_set_vfta_generic - Set VLAN filter table 3086 * @hw: pointer to hardware structure 3087 * @vlan: VLAN id to write to VLAN filter 3088 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 3089 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 3090 * @vlvf_bypass: boolean flag indicating updating default pool is okay 3091 * 3092 * Turn on/off specified VLAN in the VLAN filter table. 3093 **/ 3094 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3095 bool vlan_on, bool vlvf_bypass) 3096 { 3097 u32 regidx, vfta_delta, vfta, bits; 3098 s32 vlvf_index; 3099 3100 if ((vlan > 4095) || (vind > 63)) 3101 return IXGBE_ERR_PARAM; 3102 3103 /* 3104 * this is a 2 part operation - first the VFTA, then the 3105 * VLVF and VLVFB if VT Mode is set 3106 * We don't write the VFTA until we know the VLVF part succeeded. 3107 */ 3108 3109 /* Part 1 3110 * The VFTA is a bitstring made up of 128 32-bit registers 3111 * that enable the particular VLAN id, much like the MTA: 3112 * bits[11-5]: which register 3113 * bits[4-0]: which bit in the register 3114 */ 3115 regidx = vlan / 32; 3116 vfta_delta = BIT(vlan % 32); 3117 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); 3118 3119 /* vfta_delta represents the difference between the current value 3120 * of vfta and the value we want in the register. Since the diff 3121 * is an XOR mask we can just update vfta using an XOR. 3122 */ 3123 vfta_delta &= vlan_on ? ~vfta : vfta; 3124 vfta ^= vfta_delta; 3125 3126 /* Part 2 3127 * If VT Mode is set 3128 * Either vlan_on 3129 * make sure the vlan is in VLVF 3130 * set the vind bit in the matching VLVFB 3131 * Or !vlan_on 3132 * clear the pool bit and possibly the vind 3133 */ 3134 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) 3135 goto vfta_update; 3136 3137 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 3138 if (vlvf_index < 0) { 3139 if (vlvf_bypass) 3140 goto vfta_update; 3141 return vlvf_index; 3142 } 3143 3144 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); 3145 3146 /* set the pool bit */ 3147 bits |= BIT(vind % 32); 3148 if (vlan_on) 3149 goto vlvf_update; 3150 3151 /* clear the pool bit */ 3152 bits ^= BIT(vind % 32); 3153 3154 if (!bits && 3155 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 3156 /* Clear VFTA first, then disable VLVF. Otherwise 3157 * we run the risk of stray packets leaking into 3158 * the PF via the default pool 3159 */ 3160 if (vfta_delta) 3161 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 3162 3163 /* disable VLVF and clear remaining bit from pool */ 3164 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 3165 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); 3166 3167 return 0; 3168 } 3169 3170 /* If there are still bits set in the VLVFB registers 3171 * for the VLAN ID indicated we need to see if the 3172 * caller is requesting that we clear the VFTA entry bit. 3173 * If the caller has requested that we clear the VFTA 3174 * entry bit but there are still pools/VFs using this VLAN 3175 * ID entry then ignore the request. We're not worried 3176 * about the case where we're turning the VFTA VLAN ID 3177 * entry bit on, only when requested to turn it off as 3178 * there may be multiple pools and/or VFs using the 3179 * VLAN ID entry. In that case we cannot clear the 3180 * VFTA bit until all pools/VFs using that VLAN ID have also 3181 * been cleared. This will be indicated by "bits" being 3182 * zero. 3183 */ 3184 vfta_delta = 0; 3185 3186 vlvf_update: 3187 /* record pool change and enable VLAN ID if not already enabled */ 3188 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); 3189 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); 3190 3191 vfta_update: 3192 /* Update VFTA now that we are ready for traffic */ 3193 if (vfta_delta) 3194 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 3195 3196 return 0; 3197 } 3198 3199 /** 3200 * ixgbe_clear_vfta_generic - Clear VLAN filter table 3201 * @hw: pointer to hardware structure 3202 * 3203 * Clears the VLAN filer table, and the VMDq index associated with the filter 3204 **/ 3205 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 3206 { 3207 u32 offset; 3208 3209 for (offset = 0; offset < hw->mac.vft_size; offset++) 3210 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 3211 3212 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 3213 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 3214 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 3215 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); 3216 } 3217 3218 return 0; 3219 } 3220 3221 /** 3222 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix 3223 * @hw: pointer to hardware structure 3224 * 3225 * Contains the logic to identify if we need to verify link for the 3226 * crosstalk fix 3227 **/ 3228 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) 3229 { 3230 /* Does FW say we need the fix */ 3231 if (!hw->need_crosstalk_fix) 3232 return false; 3233 3234 /* Only consider SFP+ PHYs i.e. media type fiber */ 3235 switch (hw->mac.ops.get_media_type(hw)) { 3236 case ixgbe_media_type_fiber: 3237 case ixgbe_media_type_fiber_qsfp: 3238 break; 3239 default: 3240 return false; 3241 } 3242 3243 return true; 3244 } 3245 3246 /** 3247 * ixgbe_check_mac_link_generic - Determine link and speed status 3248 * @hw: pointer to hardware structure 3249 * @speed: pointer to link speed 3250 * @link_up: true when link is up 3251 * @link_up_wait_to_complete: bool used to wait for link up or not 3252 * 3253 * Reads the links register to determine if link is up and the current speed 3254 **/ 3255 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3256 bool *link_up, bool link_up_wait_to_complete) 3257 { 3258 u32 links_reg, links_orig; 3259 u32 i; 3260 3261 /* If Crosstalk fix enabled do the sanity check of making sure 3262 * the SFP+ cage is full. 3263 */ 3264 if (ixgbe_need_crosstalk_fix(hw)) { 3265 u32 sfp_cage_full; 3266 3267 switch (hw->mac.type) { 3268 case ixgbe_mac_82599EB: 3269 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3270 IXGBE_ESDP_SDP2; 3271 break; 3272 case ixgbe_mac_X550EM_x: 3273 case ixgbe_mac_x550em_a: 3274 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3275 IXGBE_ESDP_SDP0; 3276 break; 3277 default: 3278 /* sanity check - No SFP+ devices here */ 3279 sfp_cage_full = false; 3280 break; 3281 } 3282 3283 if (!sfp_cage_full) { 3284 *link_up = false; 3285 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3286 return 0; 3287 } 3288 } 3289 3290 /* clear the old state */ 3291 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 3292 3293 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3294 3295 if (links_orig != links_reg) { 3296 hw_dbg(hw, "LINKS changed from %08X to %08X\n", 3297 links_orig, links_reg); 3298 } 3299 3300 if (link_up_wait_to_complete) { 3301 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 3302 if (links_reg & IXGBE_LINKS_UP) { 3303 *link_up = true; 3304 break; 3305 } else { 3306 *link_up = false; 3307 } 3308 msleep(100); 3309 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3310 } 3311 } else { 3312 if (links_reg & IXGBE_LINKS_UP) 3313 *link_up = true; 3314 else 3315 *link_up = false; 3316 } 3317 3318 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 3319 case IXGBE_LINKS_SPEED_10G_82599: 3320 if ((hw->mac.type >= ixgbe_mac_X550) && 3321 (links_reg & IXGBE_LINKS_SPEED_NON_STD)) 3322 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 3323 else 3324 *speed = IXGBE_LINK_SPEED_10GB_FULL; 3325 break; 3326 case IXGBE_LINKS_SPEED_1G_82599: 3327 *speed = IXGBE_LINK_SPEED_1GB_FULL; 3328 break; 3329 case IXGBE_LINKS_SPEED_100_82599: 3330 if ((hw->mac.type >= ixgbe_mac_X550) && 3331 (links_reg & IXGBE_LINKS_SPEED_NON_STD)) 3332 *speed = IXGBE_LINK_SPEED_5GB_FULL; 3333 else 3334 *speed = IXGBE_LINK_SPEED_100_FULL; 3335 break; 3336 default: 3337 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3338 } 3339 3340 return 0; 3341 } 3342 3343 /** 3344 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 3345 * the EEPROM 3346 * @hw: pointer to hardware structure 3347 * @wwnn_prefix: the alternative WWNN prefix 3348 * @wwpn_prefix: the alternative WWPN prefix 3349 * 3350 * This function will read the EEPROM from the alternative SAN MAC address 3351 * block to check the support for the alternative WWNN/WWPN prefix support. 3352 **/ 3353 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 3354 u16 *wwpn_prefix) 3355 { 3356 u16 offset, caps; 3357 u16 alt_san_mac_blk_offset; 3358 3359 /* clear output first */ 3360 *wwnn_prefix = 0xFFFF; 3361 *wwpn_prefix = 0xFFFF; 3362 3363 /* check if alternative SAN MAC is supported */ 3364 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 3365 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 3366 goto wwn_prefix_err; 3367 3368 if ((alt_san_mac_blk_offset == 0) || 3369 (alt_san_mac_blk_offset == 0xFFFF)) 3370 return 0; 3371 3372 /* check capability in alternative san mac address block */ 3373 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 3374 if (hw->eeprom.ops.read(hw, offset, &caps)) 3375 goto wwn_prefix_err; 3376 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 3377 return 0; 3378 3379 /* get the corresponding prefix for WWNN/WWPN */ 3380 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 3381 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) 3382 hw_err(hw, "eeprom read at offset %d failed\n", offset); 3383 3384 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 3385 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 3386 goto wwn_prefix_err; 3387 3388 return 0; 3389 3390 wwn_prefix_err: 3391 hw_err(hw, "eeprom read at offset %d failed\n", offset); 3392 return 0; 3393 } 3394 3395 /** 3396 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 3397 * @hw: pointer to hardware structure 3398 * @enable: enable or disable switch for MAC anti-spoofing 3399 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing 3400 * 3401 **/ 3402 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 3403 { 3404 int vf_target_reg = vf >> 3; 3405 int vf_target_shift = vf % 8; 3406 u32 pfvfspoof; 3407 3408 if (hw->mac.type == ixgbe_mac_82598EB) 3409 return; 3410 3411 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3412 if (enable) 3413 pfvfspoof |= BIT(vf_target_shift); 3414 else 3415 pfvfspoof &= ~BIT(vf_target_shift); 3416 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3417 } 3418 3419 /** 3420 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 3421 * @hw: pointer to hardware structure 3422 * @enable: enable or disable switch for VLAN anti-spoofing 3423 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 3424 * 3425 **/ 3426 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 3427 { 3428 int vf_target_reg = vf >> 3; 3429 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 3430 u32 pfvfspoof; 3431 3432 if (hw->mac.type == ixgbe_mac_82598EB) 3433 return; 3434 3435 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3436 if (enable) 3437 pfvfspoof |= BIT(vf_target_shift); 3438 else 3439 pfvfspoof &= ~BIT(vf_target_shift); 3440 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3441 } 3442 3443 /** 3444 * ixgbe_get_device_caps_generic - Get additional device capabilities 3445 * @hw: pointer to hardware structure 3446 * @device_caps: the EEPROM word with the extra device capabilities 3447 * 3448 * This function will read the EEPROM location for the device capabilities, 3449 * and return the word through device_caps. 3450 **/ 3451 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 3452 { 3453 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 3454 3455 return 0; 3456 } 3457 3458 /** 3459 * ixgbe_set_rxpba_generic - Initialize RX packet buffer 3460 * @hw: pointer to hardware structure 3461 * @num_pb: number of packet buffers to allocate 3462 * @headroom: reserve n KB of headroom 3463 * @strategy: packet buffer allocation strategy 3464 **/ 3465 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, 3466 int num_pb, 3467 u32 headroom, 3468 int strategy) 3469 { 3470 u32 pbsize = hw->mac.rx_pb_size; 3471 int i = 0; 3472 u32 rxpktsize, txpktsize, txpbthresh; 3473 3474 /* Reserve headroom */ 3475 pbsize -= headroom; 3476 3477 if (!num_pb) 3478 num_pb = 1; 3479 3480 /* Divide remaining packet buffer space amongst the number 3481 * of packet buffers requested using supplied strategy. 3482 */ 3483 switch (strategy) { 3484 case (PBA_STRATEGY_WEIGHTED): 3485 /* pba_80_48 strategy weight first half of packet buffer with 3486 * 5/8 of the packet buffer space. 3487 */ 3488 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8)); 3489 pbsize -= rxpktsize * (num_pb / 2); 3490 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 3491 for (; i < (num_pb / 2); i++) 3492 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3493 /* Fall through to configure remaining packet buffers */ 3494 case (PBA_STRATEGY_EQUAL): 3495 /* Divide the remaining Rx packet buffer evenly among the TCs */ 3496 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 3497 for (; i < num_pb; i++) 3498 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3499 break; 3500 default: 3501 break; 3502 } 3503 3504 /* 3505 * Setup Tx packet buffer and threshold equally for all TCs 3506 * TXPBTHRESH register is set in K so divide by 1024 and subtract 3507 * 10 since the largest packet we support is just over 9K. 3508 */ 3509 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 3510 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 3511 for (i = 0; i < num_pb; i++) { 3512 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 3513 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 3514 } 3515 3516 /* Clear unused TCs, if any, to zero buffer size*/ 3517 for (; i < IXGBE_MAX_PB; i++) { 3518 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 3519 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 3520 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 3521 } 3522 } 3523 3524 /** 3525 * ixgbe_calculate_checksum - Calculate checksum for buffer 3526 * @buffer: pointer to EEPROM 3527 * @length: size of EEPROM to calculate a checksum for 3528 * 3529 * Calculates the checksum for some buffer on a specified length. The 3530 * checksum calculated is returned. 3531 **/ 3532 static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 3533 { 3534 u32 i; 3535 u8 sum = 0; 3536 3537 if (!buffer) 3538 return 0; 3539 3540 for (i = 0; i < length; i++) 3541 sum += buffer[i]; 3542 3543 return (u8) (0 - sum); 3544 } 3545 3546 /** 3547 * ixgbe_host_interface_command - Issue command to manageability block 3548 * @hw: pointer to the HW structure 3549 * @buffer: contains the command to write and where the return status will 3550 * be placed 3551 * @length: length of buffer, must be multiple of 4 bytes 3552 * @timeout: time in ms to wait for command completion 3553 * @return_data: read and return data from the buffer (true) or not (false) 3554 * Needed because FW structures are big endian and decoding of 3555 * these fields can be 8 bit or 16 bit based on command. Decoding 3556 * is not easily understood without making a table of commands. 3557 * So we will leave this up to the caller to read back the data 3558 * in these cases. 3559 * 3560 * Communicates with the manageability block. On success return 0 3561 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND. 3562 **/ 3563 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer, 3564 u32 length, u32 timeout, 3565 bool return_data) 3566 { 3567 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 3568 u32 hicr, i, bi, fwsts; 3569 u16 buf_len, dword_len; 3570 union { 3571 struct ixgbe_hic_hdr hdr; 3572 u32 u32arr[1]; 3573 } *bp = buffer; 3574 s32 status; 3575 3576 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 3577 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); 3578 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3579 } 3580 /* Take management host interface semaphore */ 3581 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 3582 if (status) 3583 return status; 3584 3585 /* Set bit 9 of FWSTS clearing FW reset indication */ 3586 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 3587 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 3588 3589 /* Check that the host interface is enabled. */ 3590 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3591 if (!(hicr & IXGBE_HICR_EN)) { 3592 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n"); 3593 status = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3594 goto rel_out; 3595 } 3596 3597 /* Calculate length in DWORDs. We must be DWORD aligned */ 3598 if (length % sizeof(u32)) { 3599 hw_dbg(hw, "Buffer length failure, not aligned to dword"); 3600 status = IXGBE_ERR_INVALID_ARGUMENT; 3601 goto rel_out; 3602 } 3603 3604 dword_len = length >> 2; 3605 3606 /* The device driver writes the relevant command block 3607 * into the ram area. 3608 */ 3609 for (i = 0; i < dword_len; i++) 3610 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 3611 i, cpu_to_le32(bp->u32arr[i])); 3612 3613 /* Setting this bit tells the ARC that a new command is pending. */ 3614 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 3615 3616 for (i = 0; i < timeout; i++) { 3617 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3618 if (!(hicr & IXGBE_HICR_C)) 3619 break; 3620 usleep_range(1000, 2000); 3621 } 3622 3623 /* Check command successful completion. */ 3624 if ((timeout && i == timeout) || 3625 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) { 3626 hw_dbg(hw, "Command has failed with no status valid.\n"); 3627 status = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3628 goto rel_out; 3629 } 3630 3631 if (!return_data) 3632 goto rel_out; 3633 3634 /* Calculate length in DWORDs */ 3635 dword_len = hdr_size >> 2; 3636 3637 /* first pull in the header so we know the buffer length */ 3638 for (bi = 0; bi < dword_len; bi++) { 3639 bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3640 le32_to_cpus(&bp->u32arr[bi]); 3641 } 3642 3643 /* If there is any thing in data position pull it in */ 3644 buf_len = bp->hdr.buf_len; 3645 if (!buf_len) 3646 goto rel_out; 3647 3648 if (length < round_up(buf_len, 4) + hdr_size) { 3649 hw_dbg(hw, "Buffer not large enough for reply message.\n"); 3650 status = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3651 goto rel_out; 3652 } 3653 3654 /* Calculate length in DWORDs, add 3 for odd lengths */ 3655 dword_len = (buf_len + 3) >> 2; 3656 3657 /* Pull in the rest of the buffer (bi is where we left off) */ 3658 for (; bi <= dword_len; bi++) { 3659 bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3660 le32_to_cpus(&bp->u32arr[bi]); 3661 } 3662 3663 rel_out: 3664 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 3665 3666 return status; 3667 } 3668 3669 /** 3670 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 3671 * @hw: pointer to the HW structure 3672 * @maj: driver version major number 3673 * @min: driver version minor number 3674 * @build: driver version build number 3675 * @sub: driver version sub build number 3676 * 3677 * Sends driver version number to firmware through the manageability 3678 * block. On success return 0 3679 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 3680 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 3681 **/ 3682 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 3683 u8 build, u8 sub) 3684 { 3685 struct ixgbe_hic_drv_info fw_cmd; 3686 int i; 3687 s32 ret_val; 3688 3689 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 3690 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 3691 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 3692 fw_cmd.port_num = hw->bus.func; 3693 fw_cmd.ver_maj = maj; 3694 fw_cmd.ver_min = min; 3695 fw_cmd.ver_build = build; 3696 fw_cmd.ver_sub = sub; 3697 fw_cmd.hdr.checksum = 0; 3698 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 3699 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 3700 fw_cmd.pad = 0; 3701 fw_cmd.pad2 = 0; 3702 3703 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 3704 ret_val = ixgbe_host_interface_command(hw, &fw_cmd, 3705 sizeof(fw_cmd), 3706 IXGBE_HI_COMMAND_TIMEOUT, 3707 true); 3708 if (ret_val != 0) 3709 continue; 3710 3711 if (fw_cmd.hdr.cmd_or_resp.ret_status == 3712 FW_CEM_RESP_STATUS_SUCCESS) 3713 ret_val = 0; 3714 else 3715 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3716 3717 break; 3718 } 3719 3720 return ret_val; 3721 } 3722 3723 /** 3724 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 3725 * @hw: pointer to the hardware structure 3726 * 3727 * The 82599 and x540 MACs can experience issues if TX work is still pending 3728 * when a reset occurs. This function prevents this by flushing the PCIe 3729 * buffers on the system. 3730 **/ 3731 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 3732 { 3733 u32 gcr_ext, hlreg0, i, poll; 3734 u16 value; 3735 3736 /* 3737 * If double reset is not requested then all transactions should 3738 * already be clear and as such there is no work to do 3739 */ 3740 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 3741 return; 3742 3743 /* 3744 * Set loopback enable to prevent any transmits from being sent 3745 * should the link come up. This assumes that the RXCTRL.RXEN bit 3746 * has already been cleared. 3747 */ 3748 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3749 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 3750 3751 /* wait for a last completion before clearing buffers */ 3752 IXGBE_WRITE_FLUSH(hw); 3753 usleep_range(3000, 6000); 3754 3755 /* Before proceeding, make sure that the PCIe block does not have 3756 * transactions pending. 3757 */ 3758 poll = ixgbe_pcie_timeout_poll(hw); 3759 for (i = 0; i < poll; i++) { 3760 usleep_range(100, 200); 3761 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); 3762 if (ixgbe_removed(hw->hw_addr)) 3763 break; 3764 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3765 break; 3766 } 3767 3768 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 3769 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 3770 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 3771 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 3772 3773 /* Flush all writes and allow 20usec for all transactions to clear */ 3774 IXGBE_WRITE_FLUSH(hw); 3775 udelay(20); 3776 3777 /* restore previous register values */ 3778 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 3779 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3780 } 3781 3782 static const u8 ixgbe_emc_temp_data[4] = { 3783 IXGBE_EMC_INTERNAL_DATA, 3784 IXGBE_EMC_DIODE1_DATA, 3785 IXGBE_EMC_DIODE2_DATA, 3786 IXGBE_EMC_DIODE3_DATA 3787 }; 3788 static const u8 ixgbe_emc_therm_limit[4] = { 3789 IXGBE_EMC_INTERNAL_THERM_LIMIT, 3790 IXGBE_EMC_DIODE1_THERM_LIMIT, 3791 IXGBE_EMC_DIODE2_THERM_LIMIT, 3792 IXGBE_EMC_DIODE3_THERM_LIMIT 3793 }; 3794 3795 /** 3796 * ixgbe_get_ets_data - Extracts the ETS bit data 3797 * @hw: pointer to hardware structure 3798 * @ets_cfg: extected ETS data 3799 * @ets_offset: offset of ETS data 3800 * 3801 * Returns error code. 3802 **/ 3803 static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg, 3804 u16 *ets_offset) 3805 { 3806 s32 status; 3807 3808 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset); 3809 if (status) 3810 return status; 3811 3812 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF)) 3813 return IXGBE_NOT_IMPLEMENTED; 3814 3815 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg); 3816 if (status) 3817 return status; 3818 3819 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED) 3820 return IXGBE_NOT_IMPLEMENTED; 3821 3822 return 0; 3823 } 3824 3825 /** 3826 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data 3827 * @hw: pointer to hardware structure 3828 * 3829 * Returns the thermal sensor data structure 3830 **/ 3831 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) 3832 { 3833 s32 status; 3834 u16 ets_offset; 3835 u16 ets_cfg; 3836 u16 ets_sensor; 3837 u8 num_sensors; 3838 u8 i; 3839 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 3840 3841 /* Only support thermal sensors attached to physical port 0 */ 3842 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 3843 return IXGBE_NOT_IMPLEMENTED; 3844 3845 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); 3846 if (status) 3847 return status; 3848 3849 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 3850 if (num_sensors > IXGBE_MAX_SENSORS) 3851 num_sensors = IXGBE_MAX_SENSORS; 3852 3853 for (i = 0; i < num_sensors; i++) { 3854 u8 sensor_index; 3855 u8 sensor_location; 3856 3857 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), 3858 &ets_sensor); 3859 if (status) 3860 return status; 3861 3862 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 3863 IXGBE_ETS_DATA_INDEX_SHIFT); 3864 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 3865 IXGBE_ETS_DATA_LOC_SHIFT); 3866 3867 if (sensor_location != 0) { 3868 status = hw->phy.ops.read_i2c_byte(hw, 3869 ixgbe_emc_temp_data[sensor_index], 3870 IXGBE_I2C_THERMAL_SENSOR_ADDR, 3871 &data->sensor[i].temp); 3872 if (status) 3873 return status; 3874 } 3875 } 3876 3877 return 0; 3878 } 3879 3880 /** 3881 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds 3882 * @hw: pointer to hardware structure 3883 * 3884 * Inits the thermal sensor thresholds according to the NVM map 3885 * and save off the threshold and location values into mac.thermal_sensor_data 3886 **/ 3887 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) 3888 { 3889 s32 status; 3890 u16 ets_offset; 3891 u16 ets_cfg; 3892 u16 ets_sensor; 3893 u8 low_thresh_delta; 3894 u8 num_sensors; 3895 u8 therm_limit; 3896 u8 i; 3897 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 3898 3899 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data)); 3900 3901 /* Only support thermal sensors attached to physical port 0 */ 3902 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 3903 return IXGBE_NOT_IMPLEMENTED; 3904 3905 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); 3906 if (status) 3907 return status; 3908 3909 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >> 3910 IXGBE_ETS_LTHRES_DELTA_SHIFT); 3911 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 3912 if (num_sensors > IXGBE_MAX_SENSORS) 3913 num_sensors = IXGBE_MAX_SENSORS; 3914 3915 for (i = 0; i < num_sensors; i++) { 3916 u8 sensor_index; 3917 u8 sensor_location; 3918 3919 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) { 3920 hw_err(hw, "eeprom read at offset %d failed\n", 3921 ets_offset + 1 + i); 3922 continue; 3923 } 3924 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 3925 IXGBE_ETS_DATA_INDEX_SHIFT); 3926 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 3927 IXGBE_ETS_DATA_LOC_SHIFT); 3928 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK; 3929 3930 hw->phy.ops.write_i2c_byte(hw, 3931 ixgbe_emc_therm_limit[sensor_index], 3932 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit); 3933 3934 if (sensor_location == 0) 3935 continue; 3936 3937 data->sensor[i].location = sensor_location; 3938 data->sensor[i].caution_thresh = therm_limit; 3939 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta; 3940 } 3941 3942 return 0; 3943 } 3944 3945 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 3946 { 3947 u32 rxctrl; 3948 3949 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3950 if (rxctrl & IXGBE_RXCTRL_RXEN) { 3951 if (hw->mac.type != ixgbe_mac_82598EB) { 3952 u32 pfdtxgswc; 3953 3954 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 3955 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 3956 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 3957 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 3958 hw->mac.set_lben = true; 3959 } else { 3960 hw->mac.set_lben = false; 3961 } 3962 } 3963 rxctrl &= ~IXGBE_RXCTRL_RXEN; 3964 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 3965 } 3966 } 3967 3968 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 3969 { 3970 u32 rxctrl; 3971 3972 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3973 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 3974 3975 if (hw->mac.type != ixgbe_mac_82598EB) { 3976 if (hw->mac.set_lben) { 3977 u32 pfdtxgswc; 3978 3979 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 3980 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 3981 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 3982 hw->mac.set_lben = false; 3983 } 3984 } 3985 } 3986 3987 /** ixgbe_mng_present - returns true when management capability is present 3988 * @hw: pointer to hardware structure 3989 **/ 3990 bool ixgbe_mng_present(struct ixgbe_hw *hw) 3991 { 3992 u32 fwsm; 3993 3994 if (hw->mac.type < ixgbe_mac_82599EB) 3995 return false; 3996 3997 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 3998 fwsm &= IXGBE_FWSM_MODE_MASK; 3999 return fwsm == IXGBE_FWSM_FW_MODE_PT; 4000 } 4001 4002 /** 4003 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 4004 * @hw: pointer to hardware structure 4005 * @speed: new link speed 4006 * @autoneg_wait_to_complete: true when waiting for completion is needed 4007 * 4008 * Set the link speed in the MAC and/or PHY register and restarts link. 4009 */ 4010 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 4011 ixgbe_link_speed speed, 4012 bool autoneg_wait_to_complete) 4013 { 4014 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4015 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4016 s32 status = 0; 4017 u32 speedcnt = 0; 4018 u32 i = 0; 4019 bool autoneg, link_up = false; 4020 4021 /* Mask off requested but non-supported speeds */ 4022 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg); 4023 if (status) 4024 return status; 4025 4026 speed &= link_speed; 4027 4028 /* Try each speed one by one, highest priority first. We do this in 4029 * software because 10Gb fiber doesn't support speed autonegotiation. 4030 */ 4031 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 4032 speedcnt++; 4033 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 4034 4035 /* If we already have link at this speed, just jump out */ 4036 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 4037 false); 4038 if (status) 4039 return status; 4040 4041 if (link_speed == IXGBE_LINK_SPEED_10GB_FULL && link_up) 4042 goto out; 4043 4044 /* Set the module link speed */ 4045 switch (hw->phy.media_type) { 4046 case ixgbe_media_type_fiber: 4047 hw->mac.ops.set_rate_select_speed(hw, 4048 IXGBE_LINK_SPEED_10GB_FULL); 4049 break; 4050 case ixgbe_media_type_fiber_qsfp: 4051 /* QSFP module automatically detects MAC link speed */ 4052 break; 4053 default: 4054 hw_dbg(hw, "Unexpected media type\n"); 4055 break; 4056 } 4057 4058 /* Allow module to change analog characteristics (1G->10G) */ 4059 msleep(40); 4060 4061 status = hw->mac.ops.setup_mac_link(hw, 4062 IXGBE_LINK_SPEED_10GB_FULL, 4063 autoneg_wait_to_complete); 4064 if (status) 4065 return status; 4066 4067 /* Flap the Tx laser if it has not already been done */ 4068 if (hw->mac.ops.flap_tx_laser) 4069 hw->mac.ops.flap_tx_laser(hw); 4070 4071 /* Wait for the controller to acquire link. Per IEEE 802.3ap, 4072 * Section 73.10.2, we may have to wait up to 500ms if KR is 4073 * attempted. 82599 uses the same timing for 10g SFI. 4074 */ 4075 for (i = 0; i < 5; i++) { 4076 /* Wait for the link partner to also set speed */ 4077 msleep(100); 4078 4079 /* If we have link, just jump out */ 4080 status = hw->mac.ops.check_link(hw, &link_speed, 4081 &link_up, false); 4082 if (status) 4083 return status; 4084 4085 if (link_up) 4086 goto out; 4087 } 4088 } 4089 4090 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 4091 speedcnt++; 4092 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 4093 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 4094 4095 /* If we already have link at this speed, just jump out */ 4096 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 4097 false); 4098 if (status) 4099 return status; 4100 4101 if (link_speed == IXGBE_LINK_SPEED_1GB_FULL && link_up) 4102 goto out; 4103 4104 /* Set the module link speed */ 4105 switch (hw->phy.media_type) { 4106 case ixgbe_media_type_fiber: 4107 hw->mac.ops.set_rate_select_speed(hw, 4108 IXGBE_LINK_SPEED_1GB_FULL); 4109 break; 4110 case ixgbe_media_type_fiber_qsfp: 4111 /* QSFP module automatically detects link speed */ 4112 break; 4113 default: 4114 hw_dbg(hw, "Unexpected media type\n"); 4115 break; 4116 } 4117 4118 /* Allow module to change analog characteristics (10G->1G) */ 4119 msleep(40); 4120 4121 status = hw->mac.ops.setup_mac_link(hw, 4122 IXGBE_LINK_SPEED_1GB_FULL, 4123 autoneg_wait_to_complete); 4124 if (status) 4125 return status; 4126 4127 /* Flap the Tx laser if it has not already been done */ 4128 if (hw->mac.ops.flap_tx_laser) 4129 hw->mac.ops.flap_tx_laser(hw); 4130 4131 /* Wait for the link partner to also set speed */ 4132 msleep(100); 4133 4134 /* If we have link, just jump out */ 4135 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 4136 false); 4137 if (status) 4138 return status; 4139 4140 if (link_up) 4141 goto out; 4142 } 4143 4144 /* We didn't get link. Configure back to the highest speed we tried, 4145 * (if there was more than one). We call ourselves back with just the 4146 * single highest speed that the user requested. 4147 */ 4148 if (speedcnt > 1) 4149 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 4150 highest_link_speed, 4151 autoneg_wait_to_complete); 4152 4153 out: 4154 /* Set autoneg_advertised value based on input link speed */ 4155 hw->phy.autoneg_advertised = 0; 4156 4157 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 4158 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 4159 4160 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 4161 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 4162 4163 return status; 4164 } 4165 4166 /** 4167 * ixgbe_set_soft_rate_select_speed - Set module link speed 4168 * @hw: pointer to hardware structure 4169 * @speed: link speed to set 4170 * 4171 * Set module link speed via the soft rate select. 4172 */ 4173 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 4174 ixgbe_link_speed speed) 4175 { 4176 s32 status; 4177 u8 rs, eeprom_data; 4178 4179 switch (speed) { 4180 case IXGBE_LINK_SPEED_10GB_FULL: 4181 /* one bit mask same as setting on */ 4182 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 4183 break; 4184 case IXGBE_LINK_SPEED_1GB_FULL: 4185 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 4186 break; 4187 default: 4188 hw_dbg(hw, "Invalid fixed module speed\n"); 4189 return; 4190 } 4191 4192 /* Set RS0 */ 4193 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4194 IXGBE_I2C_EEPROM_DEV_ADDR2, 4195 &eeprom_data); 4196 if (status) { 4197 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n"); 4198 return; 4199 } 4200 4201 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 4202 4203 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4204 IXGBE_I2C_EEPROM_DEV_ADDR2, 4205 eeprom_data); 4206 if (status) { 4207 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n"); 4208 return; 4209 } 4210 } 4211