1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2015 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/pci.h> 30 #include <linux/delay.h> 31 #include <linux/sched.h> 32 #include <linux/netdevice.h> 33 34 #include "ixgbe.h" 35 #include "ixgbe_common.h" 36 #include "ixgbe_phy.h" 37 38 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 39 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 40 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 41 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 42 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 43 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 44 u16 count); 45 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 46 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 47 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 48 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 49 50 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 51 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg); 52 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 53 u16 words, u16 *data); 54 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 55 u16 words, u16 *data); 56 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 57 u16 offset); 58 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw); 59 60 /* Base table for registers values that change by MAC */ 61 const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = { 62 IXGBE_MVALS_INIT(8259X) 63 }; 64 65 /** 66 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow 67 * control 68 * @hw: pointer to hardware structure 69 * 70 * There are several phys that do not support autoneg flow control. This 71 * function check the device id to see if the associated phy supports 72 * autoneg flow control. 73 **/ 74 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 75 { 76 bool supported = false; 77 ixgbe_link_speed speed; 78 bool link_up; 79 80 switch (hw->phy.media_type) { 81 case ixgbe_media_type_fiber: 82 hw->mac.ops.check_link(hw, &speed, &link_up, false); 83 /* if link is down, assume supported */ 84 if (link_up) 85 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? 86 true : false; 87 else 88 supported = true; 89 break; 90 case ixgbe_media_type_backplane: 91 supported = true; 92 break; 93 case ixgbe_media_type_copper: 94 /* only some copper devices support flow control autoneg */ 95 switch (hw->device_id) { 96 case IXGBE_DEV_ID_82599_T3_LOM: 97 case IXGBE_DEV_ID_X540T: 98 case IXGBE_DEV_ID_X540T1: 99 case IXGBE_DEV_ID_X550T: 100 case IXGBE_DEV_ID_X550EM_X_10G_T: 101 supported = true; 102 break; 103 default: 104 break; 105 } 106 default: 107 break; 108 } 109 110 return supported; 111 } 112 113 /** 114 * ixgbe_setup_fc - Set up flow control 115 * @hw: pointer to hardware structure 116 * 117 * Called at init time to set up flow control. 118 **/ 119 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 120 { 121 s32 ret_val = 0; 122 u32 reg = 0, reg_bp = 0; 123 u16 reg_cu = 0; 124 bool locked = false; 125 126 /* 127 * Validate the requested mode. Strict IEEE mode does not allow 128 * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 129 */ 130 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 131 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 132 return IXGBE_ERR_INVALID_LINK_SETTINGS; 133 } 134 135 /* 136 * 10gig parts do not have a word in the EEPROM to determine the 137 * default flow control setting, so we explicitly set it to full. 138 */ 139 if (hw->fc.requested_mode == ixgbe_fc_default) 140 hw->fc.requested_mode = ixgbe_fc_full; 141 142 /* 143 * Set up the 1G and 10G flow control advertisement registers so the 144 * HW will be able to do fc autoneg once the cable is plugged in. If 145 * we link at 10G, the 1G advertisement is harmless and vice versa. 146 */ 147 switch (hw->phy.media_type) { 148 case ixgbe_media_type_backplane: 149 /* some MAC's need RMW protection on AUTOC */ 150 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 151 if (ret_val) 152 return ret_val; 153 154 /* only backplane uses autoc so fall though */ 155 case ixgbe_media_type_fiber: 156 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 157 158 break; 159 case ixgbe_media_type_copper: 160 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 161 MDIO_MMD_AN, ®_cu); 162 break; 163 default: 164 break; 165 } 166 167 /* 168 * The possible values of fc.requested_mode are: 169 * 0: Flow control is completely disabled 170 * 1: Rx flow control is enabled (we can receive pause frames, 171 * but not send pause frames). 172 * 2: Tx flow control is enabled (we can send pause frames but 173 * we do not support receiving pause frames). 174 * 3: Both Rx and Tx flow control (symmetric) are enabled. 175 * other: Invalid. 176 */ 177 switch (hw->fc.requested_mode) { 178 case ixgbe_fc_none: 179 /* Flow control completely disabled by software override. */ 180 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 181 if (hw->phy.media_type == ixgbe_media_type_backplane) 182 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 183 IXGBE_AUTOC_ASM_PAUSE); 184 else if (hw->phy.media_type == ixgbe_media_type_copper) 185 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 186 break; 187 case ixgbe_fc_tx_pause: 188 /* 189 * Tx Flow control is enabled, and Rx Flow control is 190 * disabled by software override. 191 */ 192 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 193 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 194 if (hw->phy.media_type == ixgbe_media_type_backplane) { 195 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 196 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 197 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 198 reg_cu |= IXGBE_TAF_ASM_PAUSE; 199 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 200 } 201 break; 202 case ixgbe_fc_rx_pause: 203 /* 204 * Rx Flow control is enabled and Tx Flow control is 205 * disabled by software override. Since there really 206 * isn't a way to advertise that we are capable of RX 207 * Pause ONLY, we will advertise that we support both 208 * symmetric and asymmetric Rx PAUSE, as such we fall 209 * through to the fc_full statement. Later, we will 210 * disable the adapter's ability to send PAUSE frames. 211 */ 212 case ixgbe_fc_full: 213 /* Flow control (both Rx and Tx) is enabled by SW override. */ 214 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 215 if (hw->phy.media_type == ixgbe_media_type_backplane) 216 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 217 IXGBE_AUTOC_ASM_PAUSE; 218 else if (hw->phy.media_type == ixgbe_media_type_copper) 219 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 220 break; 221 default: 222 hw_dbg(hw, "Flow control param set incorrectly\n"); 223 return IXGBE_ERR_CONFIG; 224 } 225 226 if (hw->mac.type != ixgbe_mac_X540) { 227 /* 228 * Enable auto-negotiation between the MAC & PHY; 229 * the MAC will advertise clause 37 flow control. 230 */ 231 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 232 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 233 234 /* Disable AN timeout */ 235 if (hw->fc.strict_ieee) 236 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 237 238 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 239 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); 240 } 241 242 /* 243 * AUTOC restart handles negotiation of 1G and 10G on backplane 244 * and copper. There is no need to set the PCS1GCTL register. 245 * 246 */ 247 if (hw->phy.media_type == ixgbe_media_type_backplane) { 248 /* Need the SW/FW semaphore around AUTOC writes if 82599 and 249 * LESM is on, likewise reset_pipeline requries the lock as 250 * it also writes AUTOC. 251 */ 252 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 253 if (ret_val) 254 return ret_val; 255 256 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 257 ixgbe_device_supports_autoneg_fc(hw)) { 258 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 259 MDIO_MMD_AN, reg_cu); 260 } 261 262 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); 263 return ret_val; 264 } 265 266 /** 267 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 268 * @hw: pointer to hardware structure 269 * 270 * Starts the hardware by filling the bus info structure and media type, clears 271 * all on chip counters, initializes receive address registers, multicast 272 * table, VLAN filter table, calls routine to set up link and flow control 273 * settings, and leaves transmit and receive units disabled and uninitialized 274 **/ 275 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 276 { 277 s32 ret_val; 278 u32 ctrl_ext; 279 280 /* Set the media type */ 281 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 282 283 /* Identify the PHY */ 284 hw->phy.ops.identify(hw); 285 286 /* Clear the VLAN filter table */ 287 hw->mac.ops.clear_vfta(hw); 288 289 /* Clear statistics registers */ 290 hw->mac.ops.clear_hw_cntrs(hw); 291 292 /* Set No Snoop Disable */ 293 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 294 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 295 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 296 IXGBE_WRITE_FLUSH(hw); 297 298 /* Setup flow control */ 299 ret_val = ixgbe_setup_fc(hw); 300 if (ret_val) 301 return ret_val; 302 303 /* Clear adapter stopped flag */ 304 hw->adapter_stopped = false; 305 306 return 0; 307 } 308 309 /** 310 * ixgbe_start_hw_gen2 - Init sequence for common device family 311 * @hw: pointer to hw structure 312 * 313 * Performs the init sequence common to the second generation 314 * of 10 GbE devices. 315 * Devices in the second generation: 316 * 82599 317 * X540 318 **/ 319 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 320 { 321 u32 i; 322 323 /* Clear the rate limiters */ 324 for (i = 0; i < hw->mac.max_tx_queues; i++) { 325 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 326 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 327 } 328 IXGBE_WRITE_FLUSH(hw); 329 330 #ifndef CONFIG_SPARC 331 /* Disable relaxed ordering */ 332 for (i = 0; i < hw->mac.max_tx_queues; i++) { 333 u32 regval; 334 335 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 336 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 337 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 338 } 339 340 for (i = 0; i < hw->mac.max_rx_queues; i++) { 341 u32 regval; 342 343 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 344 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 345 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 346 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 347 } 348 #endif 349 return 0; 350 } 351 352 /** 353 * ixgbe_init_hw_generic - Generic hardware initialization 354 * @hw: pointer to hardware structure 355 * 356 * Initialize the hardware by resetting the hardware, filling the bus info 357 * structure and media type, clears all on chip counters, initializes receive 358 * address registers, multicast table, VLAN filter table, calls routine to set 359 * up link and flow control settings, and leaves transmit and receive units 360 * disabled and uninitialized 361 **/ 362 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 363 { 364 s32 status; 365 366 /* Reset the hardware */ 367 status = hw->mac.ops.reset_hw(hw); 368 369 if (status == 0) { 370 /* Start the HW */ 371 status = hw->mac.ops.start_hw(hw); 372 } 373 374 return status; 375 } 376 377 /** 378 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 379 * @hw: pointer to hardware structure 380 * 381 * Clears all hardware statistics counters by reading them from the hardware 382 * Statistics counters are clear on read. 383 **/ 384 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 385 { 386 u16 i = 0; 387 388 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 389 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 390 IXGBE_READ_REG(hw, IXGBE_ERRBC); 391 IXGBE_READ_REG(hw, IXGBE_MSPDC); 392 for (i = 0; i < 8; i++) 393 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 394 395 IXGBE_READ_REG(hw, IXGBE_MLFC); 396 IXGBE_READ_REG(hw, IXGBE_MRFC); 397 IXGBE_READ_REG(hw, IXGBE_RLEC); 398 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 399 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 400 if (hw->mac.type >= ixgbe_mac_82599EB) { 401 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 402 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 403 } else { 404 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 405 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 406 } 407 408 for (i = 0; i < 8; i++) { 409 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 410 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 411 if (hw->mac.type >= ixgbe_mac_82599EB) { 412 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 413 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 414 } else { 415 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 416 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 417 } 418 } 419 if (hw->mac.type >= ixgbe_mac_82599EB) 420 for (i = 0; i < 8; i++) 421 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 422 IXGBE_READ_REG(hw, IXGBE_PRC64); 423 IXGBE_READ_REG(hw, IXGBE_PRC127); 424 IXGBE_READ_REG(hw, IXGBE_PRC255); 425 IXGBE_READ_REG(hw, IXGBE_PRC511); 426 IXGBE_READ_REG(hw, IXGBE_PRC1023); 427 IXGBE_READ_REG(hw, IXGBE_PRC1522); 428 IXGBE_READ_REG(hw, IXGBE_GPRC); 429 IXGBE_READ_REG(hw, IXGBE_BPRC); 430 IXGBE_READ_REG(hw, IXGBE_MPRC); 431 IXGBE_READ_REG(hw, IXGBE_GPTC); 432 IXGBE_READ_REG(hw, IXGBE_GORCL); 433 IXGBE_READ_REG(hw, IXGBE_GORCH); 434 IXGBE_READ_REG(hw, IXGBE_GOTCL); 435 IXGBE_READ_REG(hw, IXGBE_GOTCH); 436 if (hw->mac.type == ixgbe_mac_82598EB) 437 for (i = 0; i < 8; i++) 438 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 439 IXGBE_READ_REG(hw, IXGBE_RUC); 440 IXGBE_READ_REG(hw, IXGBE_RFC); 441 IXGBE_READ_REG(hw, IXGBE_ROC); 442 IXGBE_READ_REG(hw, IXGBE_RJC); 443 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 444 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 445 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 446 IXGBE_READ_REG(hw, IXGBE_TORL); 447 IXGBE_READ_REG(hw, IXGBE_TORH); 448 IXGBE_READ_REG(hw, IXGBE_TPR); 449 IXGBE_READ_REG(hw, IXGBE_TPT); 450 IXGBE_READ_REG(hw, IXGBE_PTC64); 451 IXGBE_READ_REG(hw, IXGBE_PTC127); 452 IXGBE_READ_REG(hw, IXGBE_PTC255); 453 IXGBE_READ_REG(hw, IXGBE_PTC511); 454 IXGBE_READ_REG(hw, IXGBE_PTC1023); 455 IXGBE_READ_REG(hw, IXGBE_PTC1522); 456 IXGBE_READ_REG(hw, IXGBE_MPTC); 457 IXGBE_READ_REG(hw, IXGBE_BPTC); 458 for (i = 0; i < 16; i++) { 459 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 460 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 461 if (hw->mac.type >= ixgbe_mac_82599EB) { 462 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 463 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 464 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 465 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 466 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 467 } else { 468 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 469 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 470 } 471 } 472 473 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { 474 if (hw->phy.id == 0) 475 hw->phy.ops.identify(hw); 476 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i); 477 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i); 478 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i); 479 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i); 480 } 481 482 return 0; 483 } 484 485 /** 486 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 487 * @hw: pointer to hardware structure 488 * @pba_num: stores the part number string from the EEPROM 489 * @pba_num_size: part number string buffer length 490 * 491 * Reads the part number string from the EEPROM. 492 **/ 493 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 494 u32 pba_num_size) 495 { 496 s32 ret_val; 497 u16 data; 498 u16 pba_ptr; 499 u16 offset; 500 u16 length; 501 502 if (pba_num == NULL) { 503 hw_dbg(hw, "PBA string buffer was null\n"); 504 return IXGBE_ERR_INVALID_ARGUMENT; 505 } 506 507 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 508 if (ret_val) { 509 hw_dbg(hw, "NVM Read Error\n"); 510 return ret_val; 511 } 512 513 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 514 if (ret_val) { 515 hw_dbg(hw, "NVM Read Error\n"); 516 return ret_val; 517 } 518 519 /* 520 * if data is not ptr guard the PBA must be in legacy format which 521 * means pba_ptr is actually our second data word for the PBA number 522 * and we can decode it into an ascii string 523 */ 524 if (data != IXGBE_PBANUM_PTR_GUARD) { 525 hw_dbg(hw, "NVM PBA number is not stored as string\n"); 526 527 /* we will need 11 characters to store the PBA */ 528 if (pba_num_size < 11) { 529 hw_dbg(hw, "PBA string buffer too small\n"); 530 return IXGBE_ERR_NO_SPACE; 531 } 532 533 /* extract hex string from data and pba_ptr */ 534 pba_num[0] = (data >> 12) & 0xF; 535 pba_num[1] = (data >> 8) & 0xF; 536 pba_num[2] = (data >> 4) & 0xF; 537 pba_num[3] = data & 0xF; 538 pba_num[4] = (pba_ptr >> 12) & 0xF; 539 pba_num[5] = (pba_ptr >> 8) & 0xF; 540 pba_num[6] = '-'; 541 pba_num[7] = 0; 542 pba_num[8] = (pba_ptr >> 4) & 0xF; 543 pba_num[9] = pba_ptr & 0xF; 544 545 /* put a null character on the end of our string */ 546 pba_num[10] = '\0'; 547 548 /* switch all the data but the '-' to hex char */ 549 for (offset = 0; offset < 10; offset++) { 550 if (pba_num[offset] < 0xA) 551 pba_num[offset] += '0'; 552 else if (pba_num[offset] < 0x10) 553 pba_num[offset] += 'A' - 0xA; 554 } 555 556 return 0; 557 } 558 559 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 560 if (ret_val) { 561 hw_dbg(hw, "NVM Read Error\n"); 562 return ret_val; 563 } 564 565 if (length == 0xFFFF || length == 0) { 566 hw_dbg(hw, "NVM PBA number section invalid length\n"); 567 return IXGBE_ERR_PBA_SECTION; 568 } 569 570 /* check if pba_num buffer is big enough */ 571 if (pba_num_size < (((u32)length * 2) - 1)) { 572 hw_dbg(hw, "PBA string buffer too small\n"); 573 return IXGBE_ERR_NO_SPACE; 574 } 575 576 /* trim pba length from start of string */ 577 pba_ptr++; 578 length--; 579 580 for (offset = 0; offset < length; offset++) { 581 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 582 if (ret_val) { 583 hw_dbg(hw, "NVM Read Error\n"); 584 return ret_val; 585 } 586 pba_num[offset * 2] = (u8)(data >> 8); 587 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 588 } 589 pba_num[offset * 2] = '\0'; 590 591 return 0; 592 } 593 594 /** 595 * ixgbe_get_mac_addr_generic - Generic get MAC address 596 * @hw: pointer to hardware structure 597 * @mac_addr: Adapter MAC address 598 * 599 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 600 * A reset of the adapter must be performed prior to calling this function 601 * in order for the MAC address to have been loaded from the EEPROM into RAR0 602 **/ 603 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 604 { 605 u32 rar_high; 606 u32 rar_low; 607 u16 i; 608 609 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 610 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 611 612 for (i = 0; i < 4; i++) 613 mac_addr[i] = (u8)(rar_low >> (i*8)); 614 615 for (i = 0; i < 2; i++) 616 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 617 618 return 0; 619 } 620 621 enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status) 622 { 623 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 624 case IXGBE_PCI_LINK_WIDTH_1: 625 return ixgbe_bus_width_pcie_x1; 626 case IXGBE_PCI_LINK_WIDTH_2: 627 return ixgbe_bus_width_pcie_x2; 628 case IXGBE_PCI_LINK_WIDTH_4: 629 return ixgbe_bus_width_pcie_x4; 630 case IXGBE_PCI_LINK_WIDTH_8: 631 return ixgbe_bus_width_pcie_x8; 632 default: 633 return ixgbe_bus_width_unknown; 634 } 635 } 636 637 enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status) 638 { 639 switch (link_status & IXGBE_PCI_LINK_SPEED) { 640 case IXGBE_PCI_LINK_SPEED_2500: 641 return ixgbe_bus_speed_2500; 642 case IXGBE_PCI_LINK_SPEED_5000: 643 return ixgbe_bus_speed_5000; 644 case IXGBE_PCI_LINK_SPEED_8000: 645 return ixgbe_bus_speed_8000; 646 default: 647 return ixgbe_bus_speed_unknown; 648 } 649 } 650 651 /** 652 * ixgbe_get_bus_info_generic - Generic set PCI bus info 653 * @hw: pointer to hardware structure 654 * 655 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 656 **/ 657 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 658 { 659 u16 link_status; 660 661 hw->bus.type = ixgbe_bus_type_pci_express; 662 663 /* Get the negotiated link width and speed from PCI config space */ 664 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS); 665 666 hw->bus.width = ixgbe_convert_bus_width(link_status); 667 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 668 669 hw->mac.ops.set_lan_id(hw); 670 671 return 0; 672 } 673 674 /** 675 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 676 * @hw: pointer to the HW structure 677 * 678 * Determines the LAN function id by reading memory-mapped registers 679 * and swaps the port value if requested. 680 **/ 681 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 682 { 683 struct ixgbe_bus_info *bus = &hw->bus; 684 u32 reg; 685 686 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 687 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 688 bus->lan_id = bus->func; 689 690 /* check for a port swap */ 691 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); 692 if (reg & IXGBE_FACTPS_LFS) 693 bus->func ^= 0x1; 694 } 695 696 /** 697 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 698 * @hw: pointer to hardware structure 699 * 700 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 701 * disables transmit and receive units. The adapter_stopped flag is used by 702 * the shared code and drivers to determine if the adapter is in a stopped 703 * state and should not touch the hardware. 704 **/ 705 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 706 { 707 u32 reg_val; 708 u16 i; 709 710 /* 711 * Set the adapter_stopped flag so other driver functions stop touching 712 * the hardware 713 */ 714 hw->adapter_stopped = true; 715 716 /* Disable the receive unit */ 717 hw->mac.ops.disable_rx(hw); 718 719 /* Clear interrupt mask to stop interrupts from being generated */ 720 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 721 722 /* Clear any pending interrupts, flush previous writes */ 723 IXGBE_READ_REG(hw, IXGBE_EICR); 724 725 /* Disable the transmit unit. Each queue must be disabled. */ 726 for (i = 0; i < hw->mac.max_tx_queues; i++) 727 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 728 729 /* Disable the receive unit by stopping each queue */ 730 for (i = 0; i < hw->mac.max_rx_queues; i++) { 731 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 732 reg_val &= ~IXGBE_RXDCTL_ENABLE; 733 reg_val |= IXGBE_RXDCTL_SWFLSH; 734 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 735 } 736 737 /* flush all queues disables */ 738 IXGBE_WRITE_FLUSH(hw); 739 usleep_range(1000, 2000); 740 741 /* 742 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 743 * access and verify no pending requests 744 */ 745 return ixgbe_disable_pcie_master(hw); 746 } 747 748 /** 749 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 750 * @hw: pointer to hardware structure 751 * @index: led number to turn on 752 **/ 753 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 754 { 755 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 756 757 /* To turn on the LED, set mode to ON. */ 758 led_reg &= ~IXGBE_LED_MODE_MASK(index); 759 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 760 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 761 IXGBE_WRITE_FLUSH(hw); 762 763 return 0; 764 } 765 766 /** 767 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 768 * @hw: pointer to hardware structure 769 * @index: led number to turn off 770 **/ 771 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 772 { 773 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 774 775 /* To turn off the LED, set mode to OFF. */ 776 led_reg &= ~IXGBE_LED_MODE_MASK(index); 777 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 778 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 779 IXGBE_WRITE_FLUSH(hw); 780 781 return 0; 782 } 783 784 /** 785 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 786 * @hw: pointer to hardware structure 787 * 788 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 789 * ixgbe_hw struct in order to set up EEPROM access. 790 **/ 791 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 792 { 793 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 794 u32 eec; 795 u16 eeprom_size; 796 797 if (eeprom->type == ixgbe_eeprom_uninitialized) { 798 eeprom->type = ixgbe_eeprom_none; 799 /* Set default semaphore delay to 10ms which is a well 800 * tested value */ 801 eeprom->semaphore_delay = 10; 802 /* Clear EEPROM page size, it will be initialized as needed */ 803 eeprom->word_page_size = 0; 804 805 /* 806 * Check for EEPROM present first. 807 * If not present leave as none 808 */ 809 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 810 if (eec & IXGBE_EEC_PRES) { 811 eeprom->type = ixgbe_eeprom_spi; 812 813 /* 814 * SPI EEPROM is assumed here. This code would need to 815 * change if a future EEPROM is not SPI. 816 */ 817 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 818 IXGBE_EEC_SIZE_SHIFT); 819 eeprom->word_size = 1 << (eeprom_size + 820 IXGBE_EEPROM_WORD_SIZE_SHIFT); 821 } 822 823 if (eec & IXGBE_EEC_ADDR_SIZE) 824 eeprom->address_bits = 16; 825 else 826 eeprom->address_bits = 8; 827 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n", 828 eeprom->type, eeprom->word_size, eeprom->address_bits); 829 } 830 831 return 0; 832 } 833 834 /** 835 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 836 * @hw: pointer to hardware structure 837 * @offset: offset within the EEPROM to write 838 * @words: number of words 839 * @data: 16 bit word(s) to write to EEPROM 840 * 841 * Reads 16 bit word(s) from EEPROM through bit-bang method 842 **/ 843 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 844 u16 words, u16 *data) 845 { 846 s32 status; 847 u16 i, count; 848 849 hw->eeprom.ops.init_params(hw); 850 851 if (words == 0) 852 return IXGBE_ERR_INVALID_ARGUMENT; 853 854 if (offset + words > hw->eeprom.word_size) 855 return IXGBE_ERR_EEPROM; 856 857 /* 858 * The EEPROM page size cannot be queried from the chip. We do lazy 859 * initialization. It is worth to do that when we write large buffer. 860 */ 861 if ((hw->eeprom.word_page_size == 0) && 862 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 863 ixgbe_detect_eeprom_page_size_generic(hw, offset); 864 865 /* 866 * We cannot hold synchronization semaphores for too long 867 * to avoid other entity starvation. However it is more efficient 868 * to read in bursts than synchronizing access for each word. 869 */ 870 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 871 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 872 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 873 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 874 count, &data[i]); 875 876 if (status != 0) 877 break; 878 } 879 880 return status; 881 } 882 883 /** 884 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 885 * @hw: pointer to hardware structure 886 * @offset: offset within the EEPROM to be written to 887 * @words: number of word(s) 888 * @data: 16 bit word(s) to be written to the EEPROM 889 * 890 * If ixgbe_eeprom_update_checksum is not called after this function, the 891 * EEPROM will most likely contain an invalid checksum. 892 **/ 893 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 894 u16 words, u16 *data) 895 { 896 s32 status; 897 u16 word; 898 u16 page_size; 899 u16 i; 900 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 901 902 /* Prepare the EEPROM for writing */ 903 status = ixgbe_acquire_eeprom(hw); 904 if (status) 905 return status; 906 907 if (ixgbe_ready_eeprom(hw) != 0) { 908 ixgbe_release_eeprom(hw); 909 return IXGBE_ERR_EEPROM; 910 } 911 912 for (i = 0; i < words; i++) { 913 ixgbe_standby_eeprom(hw); 914 915 /* Send the WRITE ENABLE command (8 bit opcode) */ 916 ixgbe_shift_out_eeprom_bits(hw, 917 IXGBE_EEPROM_WREN_OPCODE_SPI, 918 IXGBE_EEPROM_OPCODE_BITS); 919 920 ixgbe_standby_eeprom(hw); 921 922 /* Some SPI eeproms use the 8th address bit embedded 923 * in the opcode 924 */ 925 if ((hw->eeprom.address_bits == 8) && 926 ((offset + i) >= 128)) 927 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 928 929 /* Send the Write command (8-bit opcode + addr) */ 930 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 931 IXGBE_EEPROM_OPCODE_BITS); 932 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 933 hw->eeprom.address_bits); 934 935 page_size = hw->eeprom.word_page_size; 936 937 /* Send the data in burst via SPI */ 938 do { 939 word = data[i]; 940 word = (word >> 8) | (word << 8); 941 ixgbe_shift_out_eeprom_bits(hw, word, 16); 942 943 if (page_size == 0) 944 break; 945 946 /* do not wrap around page */ 947 if (((offset + i) & (page_size - 1)) == 948 (page_size - 1)) 949 break; 950 } while (++i < words); 951 952 ixgbe_standby_eeprom(hw); 953 usleep_range(10000, 20000); 954 } 955 /* Done with writing - release the EEPROM */ 956 ixgbe_release_eeprom(hw); 957 958 return 0; 959 } 960 961 /** 962 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 963 * @hw: pointer to hardware structure 964 * @offset: offset within the EEPROM to be written to 965 * @data: 16 bit word to be written to the EEPROM 966 * 967 * If ixgbe_eeprom_update_checksum is not called after this function, the 968 * EEPROM will most likely contain an invalid checksum. 969 **/ 970 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 971 { 972 hw->eeprom.ops.init_params(hw); 973 974 if (offset >= hw->eeprom.word_size) 975 return IXGBE_ERR_EEPROM; 976 977 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 978 } 979 980 /** 981 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 982 * @hw: pointer to hardware structure 983 * @offset: offset within the EEPROM to be read 984 * @words: number of word(s) 985 * @data: read 16 bit words(s) from EEPROM 986 * 987 * Reads 16 bit word(s) from EEPROM through bit-bang method 988 **/ 989 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 990 u16 words, u16 *data) 991 { 992 s32 status; 993 u16 i, count; 994 995 hw->eeprom.ops.init_params(hw); 996 997 if (words == 0) 998 return IXGBE_ERR_INVALID_ARGUMENT; 999 1000 if (offset + words > hw->eeprom.word_size) 1001 return IXGBE_ERR_EEPROM; 1002 1003 /* 1004 * We cannot hold synchronization semaphores for too long 1005 * to avoid other entity starvation. However it is more efficient 1006 * to read in bursts than synchronizing access for each word. 1007 */ 1008 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1009 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1010 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1011 1012 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1013 count, &data[i]); 1014 1015 if (status) 1016 return status; 1017 } 1018 1019 return 0; 1020 } 1021 1022 /** 1023 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1024 * @hw: pointer to hardware structure 1025 * @offset: offset within the EEPROM to be read 1026 * @words: number of word(s) 1027 * @data: read 16 bit word(s) from EEPROM 1028 * 1029 * Reads 16 bit word(s) from EEPROM through bit-bang method 1030 **/ 1031 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1032 u16 words, u16 *data) 1033 { 1034 s32 status; 1035 u16 word_in; 1036 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1037 u16 i; 1038 1039 /* Prepare the EEPROM for reading */ 1040 status = ixgbe_acquire_eeprom(hw); 1041 if (status) 1042 return status; 1043 1044 if (ixgbe_ready_eeprom(hw) != 0) { 1045 ixgbe_release_eeprom(hw); 1046 return IXGBE_ERR_EEPROM; 1047 } 1048 1049 for (i = 0; i < words; i++) { 1050 ixgbe_standby_eeprom(hw); 1051 /* Some SPI eeproms use the 8th address bit embedded 1052 * in the opcode 1053 */ 1054 if ((hw->eeprom.address_bits == 8) && 1055 ((offset + i) >= 128)) 1056 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1057 1058 /* Send the READ command (opcode + addr) */ 1059 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1060 IXGBE_EEPROM_OPCODE_BITS); 1061 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1062 hw->eeprom.address_bits); 1063 1064 /* Read the data. */ 1065 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1066 data[i] = (word_in >> 8) | (word_in << 8); 1067 } 1068 1069 /* End this read operation */ 1070 ixgbe_release_eeprom(hw); 1071 1072 return 0; 1073 } 1074 1075 /** 1076 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1077 * @hw: pointer to hardware structure 1078 * @offset: offset within the EEPROM to be read 1079 * @data: read 16 bit value from EEPROM 1080 * 1081 * Reads 16 bit value from EEPROM through bit-bang method 1082 **/ 1083 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1084 u16 *data) 1085 { 1086 hw->eeprom.ops.init_params(hw); 1087 1088 if (offset >= hw->eeprom.word_size) 1089 return IXGBE_ERR_EEPROM; 1090 1091 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1092 } 1093 1094 /** 1095 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1096 * @hw: pointer to hardware structure 1097 * @offset: offset of word in the EEPROM to read 1098 * @words: number of word(s) 1099 * @data: 16 bit word(s) from the EEPROM 1100 * 1101 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1102 **/ 1103 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1104 u16 words, u16 *data) 1105 { 1106 u32 eerd; 1107 s32 status; 1108 u32 i; 1109 1110 hw->eeprom.ops.init_params(hw); 1111 1112 if (words == 0) 1113 return IXGBE_ERR_INVALID_ARGUMENT; 1114 1115 if (offset >= hw->eeprom.word_size) 1116 return IXGBE_ERR_EEPROM; 1117 1118 for (i = 0; i < words; i++) { 1119 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1120 IXGBE_EEPROM_RW_REG_START; 1121 1122 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1123 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1124 1125 if (status == 0) { 1126 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1127 IXGBE_EEPROM_RW_REG_DATA); 1128 } else { 1129 hw_dbg(hw, "Eeprom read timed out\n"); 1130 return status; 1131 } 1132 } 1133 1134 return 0; 1135 } 1136 1137 /** 1138 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1139 * @hw: pointer to hardware structure 1140 * @offset: offset within the EEPROM to be used as a scratch pad 1141 * 1142 * Discover EEPROM page size by writing marching data at given offset. 1143 * This function is called only when we are writing a new large buffer 1144 * at given offset so the data would be overwritten anyway. 1145 **/ 1146 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1147 u16 offset) 1148 { 1149 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1150 s32 status; 1151 u16 i; 1152 1153 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1154 data[i] = i; 1155 1156 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1157 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1158 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1159 hw->eeprom.word_page_size = 0; 1160 if (status) 1161 return status; 1162 1163 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1164 if (status) 1165 return status; 1166 1167 /* 1168 * When writing in burst more than the actual page size 1169 * EEPROM address wraps around current page. 1170 */ 1171 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1172 1173 hw_dbg(hw, "Detected EEPROM page size = %d words.\n", 1174 hw->eeprom.word_page_size); 1175 return 0; 1176 } 1177 1178 /** 1179 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1180 * @hw: pointer to hardware structure 1181 * @offset: offset of word in the EEPROM to read 1182 * @data: word read from the EEPROM 1183 * 1184 * Reads a 16 bit word from the EEPROM using the EERD register. 1185 **/ 1186 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1187 { 1188 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1189 } 1190 1191 /** 1192 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1193 * @hw: pointer to hardware structure 1194 * @offset: offset of word in the EEPROM to write 1195 * @words: number of words 1196 * @data: word(s) write to the EEPROM 1197 * 1198 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1199 **/ 1200 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1201 u16 words, u16 *data) 1202 { 1203 u32 eewr; 1204 s32 status; 1205 u16 i; 1206 1207 hw->eeprom.ops.init_params(hw); 1208 1209 if (words == 0) 1210 return IXGBE_ERR_INVALID_ARGUMENT; 1211 1212 if (offset >= hw->eeprom.word_size) 1213 return IXGBE_ERR_EEPROM; 1214 1215 for (i = 0; i < words; i++) { 1216 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1217 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1218 IXGBE_EEPROM_RW_REG_START; 1219 1220 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1221 if (status) { 1222 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1223 return status; 1224 } 1225 1226 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1227 1228 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1229 if (status) { 1230 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1231 return status; 1232 } 1233 } 1234 1235 return 0; 1236 } 1237 1238 /** 1239 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1240 * @hw: pointer to hardware structure 1241 * @offset: offset of word in the EEPROM to write 1242 * @data: word write to the EEPROM 1243 * 1244 * Write a 16 bit word to the EEPROM using the EEWR register. 1245 **/ 1246 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1247 { 1248 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1249 } 1250 1251 /** 1252 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1253 * @hw: pointer to hardware structure 1254 * @ee_reg: EEPROM flag for polling 1255 * 1256 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1257 * read or write is done respectively. 1258 **/ 1259 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1260 { 1261 u32 i; 1262 u32 reg; 1263 1264 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1265 if (ee_reg == IXGBE_NVM_POLL_READ) 1266 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1267 else 1268 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1269 1270 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1271 return 0; 1272 } 1273 udelay(5); 1274 } 1275 return IXGBE_ERR_EEPROM; 1276 } 1277 1278 /** 1279 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1280 * @hw: pointer to hardware structure 1281 * 1282 * Prepares EEPROM for access using bit-bang method. This function should 1283 * be called before issuing a command to the EEPROM. 1284 **/ 1285 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1286 { 1287 u32 eec; 1288 u32 i; 1289 1290 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) 1291 return IXGBE_ERR_SWFW_SYNC; 1292 1293 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1294 1295 /* Request EEPROM Access */ 1296 eec |= IXGBE_EEC_REQ; 1297 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1298 1299 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1300 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1301 if (eec & IXGBE_EEC_GNT) 1302 break; 1303 udelay(5); 1304 } 1305 1306 /* Release if grant not acquired */ 1307 if (!(eec & IXGBE_EEC_GNT)) { 1308 eec &= ~IXGBE_EEC_REQ; 1309 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1310 hw_dbg(hw, "Could not acquire EEPROM grant\n"); 1311 1312 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1313 return IXGBE_ERR_EEPROM; 1314 } 1315 1316 /* Setup EEPROM for Read/Write */ 1317 /* Clear CS and SK */ 1318 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1319 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1320 IXGBE_WRITE_FLUSH(hw); 1321 udelay(1); 1322 return 0; 1323 } 1324 1325 /** 1326 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1327 * @hw: pointer to hardware structure 1328 * 1329 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1330 **/ 1331 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1332 { 1333 u32 timeout = 2000; 1334 u32 i; 1335 u32 swsm; 1336 1337 /* Get SMBI software semaphore between device drivers first */ 1338 for (i = 0; i < timeout; i++) { 1339 /* 1340 * If the SMBI bit is 0 when we read it, then the bit will be 1341 * set and we have the semaphore 1342 */ 1343 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1344 if (!(swsm & IXGBE_SWSM_SMBI)) 1345 break; 1346 usleep_range(50, 100); 1347 } 1348 1349 if (i == timeout) { 1350 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n"); 1351 /* this release is particularly important because our attempts 1352 * above to get the semaphore may have succeeded, and if there 1353 * was a timeout, we should unconditionally clear the semaphore 1354 * bits to free the driver to make progress 1355 */ 1356 ixgbe_release_eeprom_semaphore(hw); 1357 1358 usleep_range(50, 100); 1359 /* one last try 1360 * If the SMBI bit is 0 when we read it, then the bit will be 1361 * set and we have the semaphore 1362 */ 1363 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1364 if (swsm & IXGBE_SWSM_SMBI) { 1365 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n"); 1366 return IXGBE_ERR_EEPROM; 1367 } 1368 } 1369 1370 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1371 for (i = 0; i < timeout; i++) { 1372 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1373 1374 /* Set the SW EEPROM semaphore bit to request access */ 1375 swsm |= IXGBE_SWSM_SWESMBI; 1376 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); 1377 1378 /* If we set the bit successfully then we got the 1379 * semaphore. 1380 */ 1381 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1382 if (swsm & IXGBE_SWSM_SWESMBI) 1383 break; 1384 1385 usleep_range(50, 100); 1386 } 1387 1388 /* Release semaphores and return error if SW EEPROM semaphore 1389 * was not granted because we don't have access to the EEPROM 1390 */ 1391 if (i >= timeout) { 1392 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n"); 1393 ixgbe_release_eeprom_semaphore(hw); 1394 return IXGBE_ERR_EEPROM; 1395 } 1396 1397 return 0; 1398 } 1399 1400 /** 1401 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1402 * @hw: pointer to hardware structure 1403 * 1404 * This function clears hardware semaphore bits. 1405 **/ 1406 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1407 { 1408 u32 swsm; 1409 1410 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1411 1412 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1413 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1414 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); 1415 IXGBE_WRITE_FLUSH(hw); 1416 } 1417 1418 /** 1419 * ixgbe_ready_eeprom - Polls for EEPROM ready 1420 * @hw: pointer to hardware structure 1421 **/ 1422 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1423 { 1424 u16 i; 1425 u8 spi_stat_reg; 1426 1427 /* 1428 * Read "Status Register" repeatedly until the LSB is cleared. The 1429 * EEPROM will signal that the command has been completed by clearing 1430 * bit 0 of the internal status register. If it's not cleared within 1431 * 5 milliseconds, then error out. 1432 */ 1433 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 1434 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1435 IXGBE_EEPROM_OPCODE_BITS); 1436 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 1437 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 1438 break; 1439 1440 udelay(5); 1441 ixgbe_standby_eeprom(hw); 1442 } 1443 1444 /* 1445 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 1446 * devices (and only 0-5mSec on 5V devices) 1447 */ 1448 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 1449 hw_dbg(hw, "SPI EEPROM Status error\n"); 1450 return IXGBE_ERR_EEPROM; 1451 } 1452 1453 return 0; 1454 } 1455 1456 /** 1457 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 1458 * @hw: pointer to hardware structure 1459 **/ 1460 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 1461 { 1462 u32 eec; 1463 1464 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1465 1466 /* Toggle CS to flush commands */ 1467 eec |= IXGBE_EEC_CS; 1468 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1469 IXGBE_WRITE_FLUSH(hw); 1470 udelay(1); 1471 eec &= ~IXGBE_EEC_CS; 1472 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1473 IXGBE_WRITE_FLUSH(hw); 1474 udelay(1); 1475 } 1476 1477 /** 1478 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 1479 * @hw: pointer to hardware structure 1480 * @data: data to send to the EEPROM 1481 * @count: number of bits to shift out 1482 **/ 1483 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 1484 u16 count) 1485 { 1486 u32 eec; 1487 u32 mask; 1488 u32 i; 1489 1490 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1491 1492 /* 1493 * Mask is used to shift "count" bits of "data" out to the EEPROM 1494 * one bit at a time. Determine the starting bit based on count 1495 */ 1496 mask = 0x01 << (count - 1); 1497 1498 for (i = 0; i < count; i++) { 1499 /* 1500 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 1501 * "1", and then raising and then lowering the clock (the SK 1502 * bit controls the clock input to the EEPROM). A "0" is 1503 * shifted out to the EEPROM by setting "DI" to "0" and then 1504 * raising and then lowering the clock. 1505 */ 1506 if (data & mask) 1507 eec |= IXGBE_EEC_DI; 1508 else 1509 eec &= ~IXGBE_EEC_DI; 1510 1511 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1512 IXGBE_WRITE_FLUSH(hw); 1513 1514 udelay(1); 1515 1516 ixgbe_raise_eeprom_clk(hw, &eec); 1517 ixgbe_lower_eeprom_clk(hw, &eec); 1518 1519 /* 1520 * Shift mask to signify next bit of data to shift in to the 1521 * EEPROM 1522 */ 1523 mask = mask >> 1; 1524 } 1525 1526 /* We leave the "DI" bit set to "0" when we leave this routine. */ 1527 eec &= ~IXGBE_EEC_DI; 1528 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1529 IXGBE_WRITE_FLUSH(hw); 1530 } 1531 1532 /** 1533 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 1534 * @hw: pointer to hardware structure 1535 **/ 1536 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 1537 { 1538 u32 eec; 1539 u32 i; 1540 u16 data = 0; 1541 1542 /* 1543 * In order to read a register from the EEPROM, we need to shift 1544 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 1545 * the clock input to the EEPROM (setting the SK bit), and then reading 1546 * the value of the "DO" bit. During this "shifting in" process the 1547 * "DI" bit should always be clear. 1548 */ 1549 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1550 1551 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 1552 1553 for (i = 0; i < count; i++) { 1554 data = data << 1; 1555 ixgbe_raise_eeprom_clk(hw, &eec); 1556 1557 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1558 1559 eec &= ~(IXGBE_EEC_DI); 1560 if (eec & IXGBE_EEC_DO) 1561 data |= 1; 1562 1563 ixgbe_lower_eeprom_clk(hw, &eec); 1564 } 1565 1566 return data; 1567 } 1568 1569 /** 1570 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1571 * @hw: pointer to hardware structure 1572 * @eec: EEC register's current value 1573 **/ 1574 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1575 { 1576 /* 1577 * Raise the clock input to the EEPROM 1578 * (setting the SK bit), then delay 1579 */ 1580 *eec = *eec | IXGBE_EEC_SK; 1581 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); 1582 IXGBE_WRITE_FLUSH(hw); 1583 udelay(1); 1584 } 1585 1586 /** 1587 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1588 * @hw: pointer to hardware structure 1589 * @eecd: EECD's current value 1590 **/ 1591 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1592 { 1593 /* 1594 * Lower the clock input to the EEPROM (clearing the SK bit), then 1595 * delay 1596 */ 1597 *eec = *eec & ~IXGBE_EEC_SK; 1598 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); 1599 IXGBE_WRITE_FLUSH(hw); 1600 udelay(1); 1601 } 1602 1603 /** 1604 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1605 * @hw: pointer to hardware structure 1606 **/ 1607 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 1608 { 1609 u32 eec; 1610 1611 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1612 1613 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1614 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1615 1616 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1617 IXGBE_WRITE_FLUSH(hw); 1618 1619 udelay(1); 1620 1621 /* Stop requesting EEPROM access */ 1622 eec &= ~IXGBE_EEC_REQ; 1623 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1624 1625 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1626 1627 /* 1628 * Delay before attempt to obtain semaphore again to allow FW 1629 * access. semaphore_delay is in ms we need us for usleep_range 1630 */ 1631 usleep_range(hw->eeprom.semaphore_delay * 1000, 1632 hw->eeprom.semaphore_delay * 2000); 1633 } 1634 1635 /** 1636 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 1637 * @hw: pointer to hardware structure 1638 **/ 1639 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 1640 { 1641 u16 i; 1642 u16 j; 1643 u16 checksum = 0; 1644 u16 length = 0; 1645 u16 pointer = 0; 1646 u16 word = 0; 1647 1648 /* Include 0x0-0x3F in the checksum */ 1649 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1650 if (hw->eeprom.ops.read(hw, i, &word)) { 1651 hw_dbg(hw, "EEPROM read failed\n"); 1652 break; 1653 } 1654 checksum += word; 1655 } 1656 1657 /* Include all data from pointers except for the fw pointer */ 1658 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1659 if (hw->eeprom.ops.read(hw, i, &pointer)) { 1660 hw_dbg(hw, "EEPROM read failed\n"); 1661 return IXGBE_ERR_EEPROM; 1662 } 1663 1664 /* If the pointer seems invalid */ 1665 if (pointer == 0xFFFF || pointer == 0) 1666 continue; 1667 1668 if (hw->eeprom.ops.read(hw, pointer, &length)) { 1669 hw_dbg(hw, "EEPROM read failed\n"); 1670 return IXGBE_ERR_EEPROM; 1671 } 1672 1673 if (length == 0xFFFF || length == 0) 1674 continue; 1675 1676 for (j = pointer + 1; j <= pointer + length; j++) { 1677 if (hw->eeprom.ops.read(hw, j, &word)) { 1678 hw_dbg(hw, "EEPROM read failed\n"); 1679 return IXGBE_ERR_EEPROM; 1680 } 1681 checksum += word; 1682 } 1683 } 1684 1685 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1686 1687 return (s32)checksum; 1688 } 1689 1690 /** 1691 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1692 * @hw: pointer to hardware structure 1693 * @checksum_val: calculated checksum 1694 * 1695 * Performs checksum calculation and validates the EEPROM checksum. If the 1696 * caller does not need checksum_val, the value can be NULL. 1697 **/ 1698 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1699 u16 *checksum_val) 1700 { 1701 s32 status; 1702 u16 checksum; 1703 u16 read_checksum = 0; 1704 1705 /* 1706 * Read the first word from the EEPROM. If this times out or fails, do 1707 * not continue or we could be in for a very long wait while every 1708 * EEPROM read fails 1709 */ 1710 status = hw->eeprom.ops.read(hw, 0, &checksum); 1711 if (status) { 1712 hw_dbg(hw, "EEPROM read failed\n"); 1713 return status; 1714 } 1715 1716 status = hw->eeprom.ops.calc_checksum(hw); 1717 if (status < 0) 1718 return status; 1719 1720 checksum = (u16)(status & 0xffff); 1721 1722 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1723 if (status) { 1724 hw_dbg(hw, "EEPROM read failed\n"); 1725 return status; 1726 } 1727 1728 /* Verify read checksum from EEPROM is the same as 1729 * calculated checksum 1730 */ 1731 if (read_checksum != checksum) 1732 status = IXGBE_ERR_EEPROM_CHECKSUM; 1733 1734 /* If the user cares, return the calculated checksum */ 1735 if (checksum_val) 1736 *checksum_val = checksum; 1737 1738 return status; 1739 } 1740 1741 /** 1742 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1743 * @hw: pointer to hardware structure 1744 **/ 1745 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1746 { 1747 s32 status; 1748 u16 checksum; 1749 1750 /* 1751 * Read the first word from the EEPROM. If this times out or fails, do 1752 * not continue or we could be in for a very long wait while every 1753 * EEPROM read fails 1754 */ 1755 status = hw->eeprom.ops.read(hw, 0, &checksum); 1756 if (status) { 1757 hw_dbg(hw, "EEPROM read failed\n"); 1758 return status; 1759 } 1760 1761 status = hw->eeprom.ops.calc_checksum(hw); 1762 if (status < 0) 1763 return status; 1764 1765 checksum = (u16)(status & 0xffff); 1766 1767 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 1768 1769 return status; 1770 } 1771 1772 /** 1773 * ixgbe_set_rar_generic - Set Rx address register 1774 * @hw: pointer to hardware structure 1775 * @index: Receive address register to write 1776 * @addr: Address to put into receive address register 1777 * @vmdq: VMDq "set" or "pool" index 1778 * @enable_addr: set flag that address is active 1779 * 1780 * Puts an ethernet address into a receive address register. 1781 **/ 1782 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1783 u32 enable_addr) 1784 { 1785 u32 rar_low, rar_high; 1786 u32 rar_entries = hw->mac.num_rar_entries; 1787 1788 /* Make sure we are using a valid rar index range */ 1789 if (index >= rar_entries) { 1790 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1791 return IXGBE_ERR_INVALID_ARGUMENT; 1792 } 1793 1794 /* setup VMDq pool selection before this RAR gets enabled */ 1795 hw->mac.ops.set_vmdq(hw, index, vmdq); 1796 1797 /* 1798 * HW expects these in little endian so we reverse the byte 1799 * order from network order (big endian) to little endian 1800 */ 1801 rar_low = ((u32)addr[0] | 1802 ((u32)addr[1] << 8) | 1803 ((u32)addr[2] << 16) | 1804 ((u32)addr[3] << 24)); 1805 /* 1806 * Some parts put the VMDq setting in the extra RAH bits, 1807 * so save everything except the lower 16 bits that hold part 1808 * of the address and the address valid bit. 1809 */ 1810 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1811 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1812 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1813 1814 if (enable_addr != 0) 1815 rar_high |= IXGBE_RAH_AV; 1816 1817 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1818 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1819 1820 return 0; 1821 } 1822 1823 /** 1824 * ixgbe_clear_rar_generic - Remove Rx address register 1825 * @hw: pointer to hardware structure 1826 * @index: Receive address register to write 1827 * 1828 * Clears an ethernet address from a receive address register. 1829 **/ 1830 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1831 { 1832 u32 rar_high; 1833 u32 rar_entries = hw->mac.num_rar_entries; 1834 1835 /* Make sure we are using a valid rar index range */ 1836 if (index >= rar_entries) { 1837 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1838 return IXGBE_ERR_INVALID_ARGUMENT; 1839 } 1840 1841 /* 1842 * Some parts put the VMDq setting in the extra RAH bits, 1843 * so save everything except the lower 16 bits that hold part 1844 * of the address and the address valid bit. 1845 */ 1846 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1847 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1848 1849 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1850 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1851 1852 /* clear VMDq pool/queue selection for this RAR */ 1853 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1854 1855 return 0; 1856 } 1857 1858 /** 1859 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1860 * @hw: pointer to hardware structure 1861 * 1862 * Places the MAC address in receive address register 0 and clears the rest 1863 * of the receive address registers. Clears the multicast table. Assumes 1864 * the receiver is in reset when the routine is called. 1865 **/ 1866 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1867 { 1868 u32 i; 1869 u32 rar_entries = hw->mac.num_rar_entries; 1870 1871 /* 1872 * If the current mac address is valid, assume it is a software override 1873 * to the permanent address. 1874 * Otherwise, use the permanent address from the eeprom. 1875 */ 1876 if (!is_valid_ether_addr(hw->mac.addr)) { 1877 /* Get the MAC address from the RAR0 for later reference */ 1878 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1879 1880 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr); 1881 } else { 1882 /* Setup the receive address. */ 1883 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); 1884 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr); 1885 1886 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1887 } 1888 1889 /* clear VMDq pool/queue selection for RAR 0 */ 1890 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 1891 1892 hw->addr_ctrl.overflow_promisc = 0; 1893 1894 hw->addr_ctrl.rar_used_count = 1; 1895 1896 /* Zero out the other receive addresses. */ 1897 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); 1898 for (i = 1; i < rar_entries; i++) { 1899 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1900 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1901 } 1902 1903 /* Clear the MTA */ 1904 hw->addr_ctrl.mta_in_use = 0; 1905 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1906 1907 hw_dbg(hw, " Clearing MTA\n"); 1908 for (i = 0; i < hw->mac.mcft_size; i++) 1909 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1910 1911 if (hw->mac.ops.init_uta_tables) 1912 hw->mac.ops.init_uta_tables(hw); 1913 1914 return 0; 1915 } 1916 1917 /** 1918 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1919 * @hw: pointer to hardware structure 1920 * @mc_addr: the multicast address 1921 * 1922 * Extracts the 12 bits, from a multicast address, to determine which 1923 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1924 * incoming rx multicast addresses, to determine the bit-vector to check in 1925 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1926 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1927 * to mc_filter_type. 1928 **/ 1929 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 1930 { 1931 u32 vector = 0; 1932 1933 switch (hw->mac.mc_filter_type) { 1934 case 0: /* use bits [47:36] of the address */ 1935 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1936 break; 1937 case 1: /* use bits [46:35] of the address */ 1938 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1939 break; 1940 case 2: /* use bits [45:34] of the address */ 1941 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1942 break; 1943 case 3: /* use bits [43:32] of the address */ 1944 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1945 break; 1946 default: /* Invalid mc_filter_type */ 1947 hw_dbg(hw, "MC filter type param set incorrectly\n"); 1948 break; 1949 } 1950 1951 /* vector can only be 12-bits or boundary will be exceeded */ 1952 vector &= 0xFFF; 1953 return vector; 1954 } 1955 1956 /** 1957 * ixgbe_set_mta - Set bit-vector in multicast table 1958 * @hw: pointer to hardware structure 1959 * @hash_value: Multicast address hash value 1960 * 1961 * Sets the bit-vector in the multicast table. 1962 **/ 1963 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 1964 { 1965 u32 vector; 1966 u32 vector_bit; 1967 u32 vector_reg; 1968 1969 hw->addr_ctrl.mta_in_use++; 1970 1971 vector = ixgbe_mta_vector(hw, mc_addr); 1972 hw_dbg(hw, " bit-vector = 0x%03X\n", vector); 1973 1974 /* 1975 * The MTA is a register array of 128 32-bit registers. It is treated 1976 * like an array of 4096 bits. We want to set bit 1977 * BitArray[vector_value]. So we figure out what register the bit is 1978 * in, read it, OR in the new bit, then write back the new value. The 1979 * register is determined by the upper 7 bits of the vector value and 1980 * the bit within that register are determined by the lower 5 bits of 1981 * the value. 1982 */ 1983 vector_reg = (vector >> 5) & 0x7F; 1984 vector_bit = vector & 0x1F; 1985 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 1986 } 1987 1988 /** 1989 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 1990 * @hw: pointer to hardware structure 1991 * @netdev: pointer to net device structure 1992 * 1993 * The given list replaces any existing list. Clears the MC addrs from receive 1994 * address registers and the multicast table. Uses unused receive address 1995 * registers for the first multicast addresses, and hashes the rest into the 1996 * multicast table. 1997 **/ 1998 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, 1999 struct net_device *netdev) 2000 { 2001 struct netdev_hw_addr *ha; 2002 u32 i; 2003 2004 /* 2005 * Set the new number of MC addresses that we are being requested to 2006 * use. 2007 */ 2008 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); 2009 hw->addr_ctrl.mta_in_use = 0; 2010 2011 /* Clear mta_shadow */ 2012 hw_dbg(hw, " Clearing MTA\n"); 2013 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2014 2015 /* Update mta shadow */ 2016 netdev_for_each_mc_addr(ha, netdev) { 2017 hw_dbg(hw, " Adding the multicast addresses:\n"); 2018 ixgbe_set_mta(hw, ha->addr); 2019 } 2020 2021 /* Enable mta */ 2022 for (i = 0; i < hw->mac.mcft_size; i++) 2023 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2024 hw->mac.mta_shadow[i]); 2025 2026 if (hw->addr_ctrl.mta_in_use > 0) 2027 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2028 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2029 2030 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); 2031 return 0; 2032 } 2033 2034 /** 2035 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2036 * @hw: pointer to hardware structure 2037 * 2038 * Enables multicast address in RAR and the use of the multicast hash table. 2039 **/ 2040 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2041 { 2042 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2043 2044 if (a->mta_in_use > 0) 2045 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2046 hw->mac.mc_filter_type); 2047 2048 return 0; 2049 } 2050 2051 /** 2052 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2053 * @hw: pointer to hardware structure 2054 * 2055 * Disables multicast address in RAR and the use of the multicast hash table. 2056 **/ 2057 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2058 { 2059 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2060 2061 if (a->mta_in_use > 0) 2062 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2063 2064 return 0; 2065 } 2066 2067 /** 2068 * ixgbe_fc_enable_generic - Enable flow control 2069 * @hw: pointer to hardware structure 2070 * 2071 * Enable flow control according to the current settings. 2072 **/ 2073 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2074 { 2075 u32 mflcn_reg, fccfg_reg; 2076 u32 reg; 2077 u32 fcrtl, fcrth; 2078 int i; 2079 2080 /* Validate the water mark configuration. */ 2081 if (!hw->fc.pause_time) 2082 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2083 2084 /* Low water mark of zero causes XOFF floods */ 2085 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 2086 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2087 hw->fc.high_water[i]) { 2088 if (!hw->fc.low_water[i] || 2089 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2090 hw_dbg(hw, "Invalid water mark configuration\n"); 2091 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2092 } 2093 } 2094 } 2095 2096 /* Negotiate the fc mode to use */ 2097 ixgbe_fc_autoneg(hw); 2098 2099 /* Disable any previous flow control settings */ 2100 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2101 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2102 2103 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2104 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2105 2106 /* 2107 * The possible values of fc.current_mode are: 2108 * 0: Flow control is completely disabled 2109 * 1: Rx flow control is enabled (we can receive pause frames, 2110 * but not send pause frames). 2111 * 2: Tx flow control is enabled (we can send pause frames but 2112 * we do not support receiving pause frames). 2113 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2114 * other: Invalid. 2115 */ 2116 switch (hw->fc.current_mode) { 2117 case ixgbe_fc_none: 2118 /* 2119 * Flow control is disabled by software override or autoneg. 2120 * The code below will actually disable it in the HW. 2121 */ 2122 break; 2123 case ixgbe_fc_rx_pause: 2124 /* 2125 * Rx Flow control is enabled and Tx Flow control is 2126 * disabled by software override. Since there really 2127 * isn't a way to advertise that we are capable of RX 2128 * Pause ONLY, we will advertise that we support both 2129 * symmetric and asymmetric Rx PAUSE. Later, we will 2130 * disable the adapter's ability to send PAUSE frames. 2131 */ 2132 mflcn_reg |= IXGBE_MFLCN_RFCE; 2133 break; 2134 case ixgbe_fc_tx_pause: 2135 /* 2136 * Tx Flow control is enabled, and Rx Flow control is 2137 * disabled by software override. 2138 */ 2139 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2140 break; 2141 case ixgbe_fc_full: 2142 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2143 mflcn_reg |= IXGBE_MFLCN_RFCE; 2144 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2145 break; 2146 default: 2147 hw_dbg(hw, "Flow control param set incorrectly\n"); 2148 return IXGBE_ERR_CONFIG; 2149 } 2150 2151 /* Set 802.3x based flow control settings. */ 2152 mflcn_reg |= IXGBE_MFLCN_DPF; 2153 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2154 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2155 2156 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2157 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 2158 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2159 hw->fc.high_water[i]) { 2160 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2161 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2162 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2163 } else { 2164 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2165 /* 2166 * In order to prevent Tx hangs when the internal Tx 2167 * switch is enabled we must set the high water mark 2168 * to the Rx packet buffer size - 24KB. This allows 2169 * the Tx switch to function even under heavy Rx 2170 * workloads. 2171 */ 2172 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2173 } 2174 2175 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2176 } 2177 2178 /* Configure pause time (2 TCs per register) */ 2179 reg = hw->fc.pause_time * 0x00010001; 2180 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 2181 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2182 2183 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2184 2185 return 0; 2186 } 2187 2188 /** 2189 * ixgbe_negotiate_fc - Negotiate flow control 2190 * @hw: pointer to hardware structure 2191 * @adv_reg: flow control advertised settings 2192 * @lp_reg: link partner's flow control settings 2193 * @adv_sym: symmetric pause bit in advertisement 2194 * @adv_asm: asymmetric pause bit in advertisement 2195 * @lp_sym: symmetric pause bit in link partner advertisement 2196 * @lp_asm: asymmetric pause bit in link partner advertisement 2197 * 2198 * Find the intersection between advertised settings and link partner's 2199 * advertised settings 2200 **/ 2201 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2202 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2203 { 2204 if ((!(adv_reg)) || (!(lp_reg))) 2205 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2206 2207 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2208 /* 2209 * Now we need to check if the user selected Rx ONLY 2210 * of pause frames. In this case, we had to advertise 2211 * FULL flow control because we could not advertise RX 2212 * ONLY. Hence, we must now check to see if we need to 2213 * turn OFF the TRANSMISSION of PAUSE frames. 2214 */ 2215 if (hw->fc.requested_mode == ixgbe_fc_full) { 2216 hw->fc.current_mode = ixgbe_fc_full; 2217 hw_dbg(hw, "Flow Control = FULL.\n"); 2218 } else { 2219 hw->fc.current_mode = ixgbe_fc_rx_pause; 2220 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n"); 2221 } 2222 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2223 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2224 hw->fc.current_mode = ixgbe_fc_tx_pause; 2225 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); 2226 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2227 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2228 hw->fc.current_mode = ixgbe_fc_rx_pause; 2229 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); 2230 } else { 2231 hw->fc.current_mode = ixgbe_fc_none; 2232 hw_dbg(hw, "Flow Control = NONE.\n"); 2233 } 2234 return 0; 2235 } 2236 2237 /** 2238 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 2239 * @hw: pointer to hardware structure 2240 * 2241 * Enable flow control according on 1 gig fiber. 2242 **/ 2243 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 2244 { 2245 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 2246 s32 ret_val; 2247 2248 /* 2249 * On multispeed fiber at 1g, bail out if 2250 * - link is up but AN did not complete, or if 2251 * - link is up and AN completed but timed out 2252 */ 2253 2254 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 2255 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 2256 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) 2257 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2258 2259 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2260 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 2261 2262 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 2263 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 2264 IXGBE_PCS1GANA_ASM_PAUSE, 2265 IXGBE_PCS1GANA_SYM_PAUSE, 2266 IXGBE_PCS1GANA_ASM_PAUSE); 2267 2268 return ret_val; 2269 } 2270 2271 /** 2272 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 2273 * @hw: pointer to hardware structure 2274 * 2275 * Enable flow control according to IEEE clause 37. 2276 **/ 2277 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 2278 { 2279 u32 links2, anlp1_reg, autoc_reg, links; 2280 s32 ret_val; 2281 2282 /* 2283 * On backplane, bail out if 2284 * - backplane autoneg was not completed, or if 2285 * - we are 82599 and link partner is not AN enabled 2286 */ 2287 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 2288 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) 2289 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2290 2291 if (hw->mac.type == ixgbe_mac_82599EB) { 2292 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 2293 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) 2294 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2295 } 2296 /* 2297 * Read the 10g AN autoc and LP ability registers and resolve 2298 * local flow control settings accordingly 2299 */ 2300 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2301 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2302 2303 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 2304 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 2305 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 2306 2307 return ret_val; 2308 } 2309 2310 /** 2311 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 2312 * @hw: pointer to hardware structure 2313 * 2314 * Enable flow control according to IEEE clause 37. 2315 **/ 2316 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 2317 { 2318 u16 technology_ability_reg = 0; 2319 u16 lp_technology_ability_reg = 0; 2320 2321 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 2322 MDIO_MMD_AN, 2323 &technology_ability_reg); 2324 hw->phy.ops.read_reg(hw, MDIO_AN_LPA, 2325 MDIO_MMD_AN, 2326 &lp_technology_ability_reg); 2327 2328 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 2329 (u32)lp_technology_ability_reg, 2330 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 2331 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 2332 } 2333 2334 /** 2335 * ixgbe_fc_autoneg - Configure flow control 2336 * @hw: pointer to hardware structure 2337 * 2338 * Compares our advertised flow control capabilities to those advertised by 2339 * our link partner, and determines the proper flow control mode to use. 2340 **/ 2341 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 2342 { 2343 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2344 ixgbe_link_speed speed; 2345 bool link_up; 2346 2347 /* 2348 * AN should have completed when the cable was plugged in. 2349 * Look for reasons to bail out. Bail out if: 2350 * - FC autoneg is disabled, or if 2351 * - link is not up. 2352 * 2353 * Since we're being called from an LSC, link is already known to be up. 2354 * So use link_up_wait_to_complete=false. 2355 */ 2356 if (hw->fc.disable_fc_autoneg) 2357 goto out; 2358 2359 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2360 if (!link_up) 2361 goto out; 2362 2363 switch (hw->phy.media_type) { 2364 /* Autoneg flow control on fiber adapters */ 2365 case ixgbe_media_type_fiber: 2366 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 2367 ret_val = ixgbe_fc_autoneg_fiber(hw); 2368 break; 2369 2370 /* Autoneg flow control on backplane adapters */ 2371 case ixgbe_media_type_backplane: 2372 ret_val = ixgbe_fc_autoneg_backplane(hw); 2373 break; 2374 2375 /* Autoneg flow control on copper adapters */ 2376 case ixgbe_media_type_copper: 2377 if (ixgbe_device_supports_autoneg_fc(hw)) 2378 ret_val = ixgbe_fc_autoneg_copper(hw); 2379 break; 2380 2381 default: 2382 break; 2383 } 2384 2385 out: 2386 if (ret_val == 0) { 2387 hw->fc.fc_was_autonegged = true; 2388 } else { 2389 hw->fc.fc_was_autonegged = false; 2390 hw->fc.current_mode = hw->fc.requested_mode; 2391 } 2392 } 2393 2394 /** 2395 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 2396 * @hw: pointer to hardware structure 2397 * 2398 * System-wide timeout range is encoded in PCIe Device Control2 register. 2399 * 2400 * Add 10% to specified maximum and return the number of times to poll for 2401 * completion timeout, in units of 100 microsec. Never return less than 2402 * 800 = 80 millisec. 2403 **/ 2404 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 2405 { 2406 s16 devctl2; 2407 u32 pollcnt; 2408 2409 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); 2410 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 2411 2412 switch (devctl2) { 2413 case IXGBE_PCIDEVCTRL2_65_130ms: 2414 pollcnt = 1300; /* 130 millisec */ 2415 break; 2416 case IXGBE_PCIDEVCTRL2_260_520ms: 2417 pollcnt = 5200; /* 520 millisec */ 2418 break; 2419 case IXGBE_PCIDEVCTRL2_1_2s: 2420 pollcnt = 20000; /* 2 sec */ 2421 break; 2422 case IXGBE_PCIDEVCTRL2_4_8s: 2423 pollcnt = 80000; /* 8 sec */ 2424 break; 2425 case IXGBE_PCIDEVCTRL2_17_34s: 2426 pollcnt = 34000; /* 34 sec */ 2427 break; 2428 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 2429 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 2430 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 2431 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 2432 default: 2433 pollcnt = 800; /* 80 millisec minimum */ 2434 break; 2435 } 2436 2437 /* add 10% to spec maximum */ 2438 return (pollcnt * 11) / 10; 2439 } 2440 2441 /** 2442 * ixgbe_disable_pcie_master - Disable PCI-express master access 2443 * @hw: pointer to hardware structure 2444 * 2445 * Disables PCI-Express master access and verifies there are no pending 2446 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 2447 * bit hasn't caused the master requests to be disabled, else 0 2448 * is returned signifying master requests disabled. 2449 **/ 2450 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 2451 { 2452 u32 i, poll; 2453 u16 value; 2454 2455 /* Always set this bit to ensure any future transactions are blocked */ 2456 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 2457 2458 /* Poll for bit to read as set */ 2459 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2460 if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS) 2461 break; 2462 usleep_range(100, 120); 2463 } 2464 if (i >= IXGBE_PCI_MASTER_DISABLE_TIMEOUT) { 2465 hw_dbg(hw, "GIO disable did not set - requesting resets\n"); 2466 goto gio_disable_fail; 2467 } 2468 2469 /* Exit if master requests are blocked */ 2470 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 2471 ixgbe_removed(hw->hw_addr)) 2472 return 0; 2473 2474 /* Poll for master request bit to clear */ 2475 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2476 udelay(100); 2477 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2478 return 0; 2479 } 2480 2481 /* 2482 * Two consecutive resets are required via CTRL.RST per datasheet 2483 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 2484 * of this need. The first reset prevents new master requests from 2485 * being issued by our device. We then must wait 1usec or more for any 2486 * remaining completions from the PCIe bus to trickle in, and then reset 2487 * again to clear out any effects they may have had on our device. 2488 */ 2489 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n"); 2490 gio_disable_fail: 2491 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2492 2493 if (hw->mac.type >= ixgbe_mac_X550) 2494 return 0; 2495 2496 /* 2497 * Before proceeding, make sure that the PCIe block does not have 2498 * transactions pending. 2499 */ 2500 poll = ixgbe_pcie_timeout_poll(hw); 2501 for (i = 0; i < poll; i++) { 2502 udelay(100); 2503 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); 2504 if (ixgbe_removed(hw->hw_addr)) 2505 return 0; 2506 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 2507 return 0; 2508 } 2509 2510 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n"); 2511 return IXGBE_ERR_MASTER_REQUESTS_PENDING; 2512 } 2513 2514 /** 2515 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 2516 * @hw: pointer to hardware structure 2517 * @mask: Mask to specify which semaphore to acquire 2518 * 2519 * Acquires the SWFW semaphore through the GSSR register for the specified 2520 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2521 **/ 2522 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 2523 { 2524 u32 gssr = 0; 2525 u32 swmask = mask; 2526 u32 fwmask = mask << 5; 2527 u32 timeout = 200; 2528 u32 i; 2529 2530 for (i = 0; i < timeout; i++) { 2531 /* 2532 * SW NVM semaphore bit is used for access to all 2533 * SW_FW_SYNC bits (not just NVM) 2534 */ 2535 if (ixgbe_get_eeprom_semaphore(hw)) 2536 return IXGBE_ERR_SWFW_SYNC; 2537 2538 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2539 if (!(gssr & (fwmask | swmask))) { 2540 gssr |= swmask; 2541 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2542 ixgbe_release_eeprom_semaphore(hw); 2543 return 0; 2544 } else { 2545 /* Resource is currently in use by FW or SW */ 2546 ixgbe_release_eeprom_semaphore(hw); 2547 usleep_range(5000, 10000); 2548 } 2549 } 2550 2551 /* If time expired clear the bits holding the lock and retry */ 2552 if (gssr & (fwmask | swmask)) 2553 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 2554 2555 usleep_range(5000, 10000); 2556 return IXGBE_ERR_SWFW_SYNC; 2557 } 2558 2559 /** 2560 * ixgbe_release_swfw_sync - Release SWFW semaphore 2561 * @hw: pointer to hardware structure 2562 * @mask: Mask to specify which semaphore to release 2563 * 2564 * Releases the SWFW semaphore through the GSSR register for the specified 2565 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2566 **/ 2567 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 2568 { 2569 u32 gssr; 2570 u32 swmask = mask; 2571 2572 ixgbe_get_eeprom_semaphore(hw); 2573 2574 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2575 gssr &= ~swmask; 2576 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2577 2578 ixgbe_release_eeprom_semaphore(hw); 2579 } 2580 2581 /** 2582 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 2583 * @hw: pointer to hardware structure 2584 * @reg_val: Value we read from AUTOC 2585 * @locked: bool to indicate whether the SW/FW lock should be taken. Never 2586 * true in this the generic case. 2587 * 2588 * The default case requires no protection so just to the register read. 2589 **/ 2590 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 2591 { 2592 *locked = false; 2593 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2594 return 0; 2595 } 2596 2597 /** 2598 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 2599 * @hw: pointer to hardware structure 2600 * @reg_val: value to write to AUTOC 2601 * @locked: bool to indicate whether the SW/FW lock was already taken by 2602 * previous read. 2603 **/ 2604 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 2605 { 2606 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 2607 return 0; 2608 } 2609 2610 /** 2611 * ixgbe_disable_rx_buff_generic - Stops the receive data path 2612 * @hw: pointer to hardware structure 2613 * 2614 * Stops the receive data path and waits for the HW to internally 2615 * empty the Rx security block. 2616 **/ 2617 s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw) 2618 { 2619 #define IXGBE_MAX_SECRX_POLL 40 2620 int i; 2621 int secrxreg; 2622 2623 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2624 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 2625 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2626 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 2627 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 2628 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 2629 break; 2630 else 2631 /* Use interrupt-safe sleep just in case */ 2632 udelay(1000); 2633 } 2634 2635 /* For informational purposes only */ 2636 if (i >= IXGBE_MAX_SECRX_POLL) 2637 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n"); 2638 2639 return 0; 2640 2641 } 2642 2643 /** 2644 * ixgbe_enable_rx_buff - Enables the receive data path 2645 * @hw: pointer to hardware structure 2646 * 2647 * Enables the receive data path 2648 **/ 2649 s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw) 2650 { 2651 int secrxreg; 2652 2653 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2654 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 2655 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2656 IXGBE_WRITE_FLUSH(hw); 2657 2658 return 0; 2659 } 2660 2661 /** 2662 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 2663 * @hw: pointer to hardware structure 2664 * @regval: register value to write to RXCTRL 2665 * 2666 * Enables the Rx DMA unit 2667 **/ 2668 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 2669 { 2670 if (regval & IXGBE_RXCTRL_RXEN) 2671 hw->mac.ops.enable_rx(hw); 2672 else 2673 hw->mac.ops.disable_rx(hw); 2674 2675 return 0; 2676 } 2677 2678 /** 2679 * ixgbe_blink_led_start_generic - Blink LED based on index. 2680 * @hw: pointer to hardware structure 2681 * @index: led number to blink 2682 **/ 2683 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 2684 { 2685 ixgbe_link_speed speed = 0; 2686 bool link_up = false; 2687 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2688 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2689 bool locked = false; 2690 s32 ret_val; 2691 2692 /* 2693 * Link must be up to auto-blink the LEDs; 2694 * Force it if link is down. 2695 */ 2696 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2697 2698 if (!link_up) { 2699 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 2700 if (ret_val) 2701 return ret_val; 2702 2703 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2704 autoc_reg |= IXGBE_AUTOC_FLU; 2705 2706 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 2707 if (ret_val) 2708 return ret_val; 2709 2710 IXGBE_WRITE_FLUSH(hw); 2711 2712 usleep_range(10000, 20000); 2713 } 2714 2715 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2716 led_reg |= IXGBE_LED_BLINK(index); 2717 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2718 IXGBE_WRITE_FLUSH(hw); 2719 2720 return 0; 2721 } 2722 2723 /** 2724 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 2725 * @hw: pointer to hardware structure 2726 * @index: led number to stop blinking 2727 **/ 2728 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 2729 { 2730 u32 autoc_reg = 0; 2731 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2732 bool locked = false; 2733 s32 ret_val; 2734 2735 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 2736 if (ret_val) 2737 return ret_val; 2738 2739 autoc_reg &= ~IXGBE_AUTOC_FLU; 2740 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2741 2742 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 2743 if (ret_val) 2744 return ret_val; 2745 2746 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2747 led_reg &= ~IXGBE_LED_BLINK(index); 2748 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 2749 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2750 IXGBE_WRITE_FLUSH(hw); 2751 2752 return 0; 2753 } 2754 2755 /** 2756 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 2757 * @hw: pointer to hardware structure 2758 * @san_mac_offset: SAN MAC address offset 2759 * 2760 * This function will read the EEPROM location for the SAN MAC address 2761 * pointer, and returns the value at that location. This is used in both 2762 * get and set mac_addr routines. 2763 **/ 2764 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 2765 u16 *san_mac_offset) 2766 { 2767 s32 ret_val; 2768 2769 /* 2770 * First read the EEPROM pointer to see if the MAC addresses are 2771 * available. 2772 */ 2773 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 2774 san_mac_offset); 2775 if (ret_val) 2776 hw_err(hw, "eeprom read at offset %d failed\n", 2777 IXGBE_SAN_MAC_ADDR_PTR); 2778 2779 return ret_val; 2780 } 2781 2782 /** 2783 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 2784 * @hw: pointer to hardware structure 2785 * @san_mac_addr: SAN MAC address 2786 * 2787 * Reads the SAN MAC address from the EEPROM, if it's available. This is 2788 * per-port, so set_lan_id() must be called before reading the addresses. 2789 * set_lan_id() is called by identify_sfp(), but this cannot be relied 2790 * upon for non-SFP connections, so we must call it here. 2791 **/ 2792 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2793 { 2794 u16 san_mac_data, san_mac_offset; 2795 u8 i; 2796 s32 ret_val; 2797 2798 /* 2799 * First read the EEPROM pointer to see if the MAC addresses are 2800 * available. If they're not, no point in calling set_lan_id() here. 2801 */ 2802 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2803 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 2804 2805 goto san_mac_addr_clr; 2806 2807 /* make sure we know which port we need to program */ 2808 hw->mac.ops.set_lan_id(hw); 2809 /* apply the port offset to the address offset */ 2810 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2811 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2812 for (i = 0; i < 3; i++) { 2813 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 2814 &san_mac_data); 2815 if (ret_val) { 2816 hw_err(hw, "eeprom read at offset %d failed\n", 2817 san_mac_offset); 2818 goto san_mac_addr_clr; 2819 } 2820 san_mac_addr[i * 2] = (u8)(san_mac_data); 2821 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 2822 san_mac_offset++; 2823 } 2824 return 0; 2825 2826 san_mac_addr_clr: 2827 /* No addresses available in this EEPROM. It's not necessarily an 2828 * error though, so just wipe the local address and return. 2829 */ 2830 for (i = 0; i < 6; i++) 2831 san_mac_addr[i] = 0xFF; 2832 return ret_val; 2833 } 2834 2835 /** 2836 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 2837 * @hw: pointer to hardware structure 2838 * 2839 * Read PCIe configuration space, and get the MSI-X vector count from 2840 * the capabilities table. 2841 **/ 2842 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 2843 { 2844 u16 msix_count; 2845 u16 max_msix_count; 2846 u16 pcie_offset; 2847 2848 switch (hw->mac.type) { 2849 case ixgbe_mac_82598EB: 2850 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 2851 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 2852 break; 2853 case ixgbe_mac_82599EB: 2854 case ixgbe_mac_X540: 2855 case ixgbe_mac_X550: 2856 case ixgbe_mac_X550EM_x: 2857 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 2858 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 2859 break; 2860 default: 2861 return 1; 2862 } 2863 2864 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset); 2865 if (ixgbe_removed(hw->hw_addr)) 2866 msix_count = 0; 2867 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 2868 2869 /* MSI-X count is zero-based in HW */ 2870 msix_count++; 2871 2872 if (msix_count > max_msix_count) 2873 msix_count = max_msix_count; 2874 2875 return msix_count; 2876 } 2877 2878 /** 2879 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 2880 * @hw: pointer to hardware struct 2881 * @rar: receive address register index to disassociate 2882 * @vmdq: VMDq pool index to remove from the rar 2883 **/ 2884 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2885 { 2886 u32 mpsar_lo, mpsar_hi; 2887 u32 rar_entries = hw->mac.num_rar_entries; 2888 2889 /* Make sure we are using a valid rar index range */ 2890 if (rar >= rar_entries) { 2891 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 2892 return IXGBE_ERR_INVALID_ARGUMENT; 2893 } 2894 2895 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2896 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2897 2898 if (ixgbe_removed(hw->hw_addr)) 2899 return 0; 2900 2901 if (!mpsar_lo && !mpsar_hi) 2902 return 0; 2903 2904 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 2905 if (mpsar_lo) { 2906 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 2907 mpsar_lo = 0; 2908 } 2909 if (mpsar_hi) { 2910 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 2911 mpsar_hi = 0; 2912 } 2913 } else if (vmdq < 32) { 2914 mpsar_lo &= ~(1 << vmdq); 2915 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 2916 } else { 2917 mpsar_hi &= ~(1 << (vmdq - 32)); 2918 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 2919 } 2920 2921 /* was that the last pool using this rar? */ 2922 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 2923 hw->mac.ops.clear_rar(hw, rar); 2924 return 0; 2925 } 2926 2927 /** 2928 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 2929 * @hw: pointer to hardware struct 2930 * @rar: receive address register index to associate with a VMDq index 2931 * @vmdq: VMDq pool index 2932 **/ 2933 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2934 { 2935 u32 mpsar; 2936 u32 rar_entries = hw->mac.num_rar_entries; 2937 2938 /* Make sure we are using a valid rar index range */ 2939 if (rar >= rar_entries) { 2940 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 2941 return IXGBE_ERR_INVALID_ARGUMENT; 2942 } 2943 2944 if (vmdq < 32) { 2945 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2946 mpsar |= 1 << vmdq; 2947 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 2948 } else { 2949 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2950 mpsar |= 1 << (vmdq - 32); 2951 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 2952 } 2953 return 0; 2954 } 2955 2956 /** 2957 * This function should only be involved in the IOV mode. 2958 * In IOV mode, Default pool is next pool after the number of 2959 * VFs advertized and not 0. 2960 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 2961 * 2962 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address 2963 * @hw: pointer to hardware struct 2964 * @vmdq: VMDq pool index 2965 **/ 2966 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 2967 { 2968 u32 rar = hw->mac.san_mac_rar_index; 2969 2970 if (vmdq < 32) { 2971 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); 2972 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 2973 } else { 2974 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 2975 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); 2976 } 2977 2978 return 0; 2979 } 2980 2981 /** 2982 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 2983 * @hw: pointer to hardware structure 2984 **/ 2985 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 2986 { 2987 int i; 2988 2989 for (i = 0; i < 128; i++) 2990 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 2991 2992 return 0; 2993 } 2994 2995 /** 2996 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 2997 * @hw: pointer to hardware structure 2998 * @vlan: VLAN id to write to VLAN filter 2999 * 3000 * return the VLVF index where this VLAN id should be placed 3001 * 3002 **/ 3003 static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) 3004 { 3005 s32 regindex, first_empty_slot; 3006 u32 bits; 3007 3008 /* short cut the special case */ 3009 if (vlan == 0) 3010 return 0; 3011 3012 /* if vlvf_bypass is set we don't want to use an empty slot, we 3013 * will simply bypass the VLVF if there are no entries present in the 3014 * VLVF that contain our VLAN 3015 */ 3016 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0; 3017 3018 /* add VLAN enable bit for comparison */ 3019 vlan |= IXGBE_VLVF_VIEN; 3020 3021 /* Search for the vlan id in the VLVF entries. Save off the first empty 3022 * slot found along the way. 3023 * 3024 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 3025 */ 3026 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { 3027 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3028 if (bits == vlan) 3029 return regindex; 3030 if (!first_empty_slot && !bits) 3031 first_empty_slot = regindex; 3032 } 3033 3034 /* If we are here then we didn't find the VLAN. Return first empty 3035 * slot we found during our search, else error. 3036 */ 3037 if (!first_empty_slot) 3038 hw_dbg(hw, "No space in VLVF.\n"); 3039 3040 return first_empty_slot ? : IXGBE_ERR_NO_SPACE; 3041 } 3042 3043 /** 3044 * ixgbe_set_vfta_generic - Set VLAN filter table 3045 * @hw: pointer to hardware structure 3046 * @vlan: VLAN id to write to VLAN filter 3047 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 3048 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 3049 * @vlvf_bypass: boolean flag indicating updating default pool is okay 3050 * 3051 * Turn on/off specified VLAN in the VLAN filter table. 3052 **/ 3053 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3054 bool vlan_on, bool vlvf_bypass) 3055 { 3056 u32 regidx, vfta_delta, vfta, bits; 3057 s32 vlvf_index; 3058 3059 if ((vlan > 4095) || (vind > 63)) 3060 return IXGBE_ERR_PARAM; 3061 3062 /* 3063 * this is a 2 part operation - first the VFTA, then the 3064 * VLVF and VLVFB if VT Mode is set 3065 * We don't write the VFTA until we know the VLVF part succeeded. 3066 */ 3067 3068 /* Part 1 3069 * The VFTA is a bitstring made up of 128 32-bit registers 3070 * that enable the particular VLAN id, much like the MTA: 3071 * bits[11-5]: which register 3072 * bits[4-0]: which bit in the register 3073 */ 3074 regidx = vlan / 32; 3075 vfta_delta = 1 << (vlan % 32); 3076 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); 3077 3078 /* vfta_delta represents the difference between the current value 3079 * of vfta and the value we want in the register. Since the diff 3080 * is an XOR mask we can just update vfta using an XOR. 3081 */ 3082 vfta_delta &= vlan_on ? ~vfta : vfta; 3083 vfta ^= vfta_delta; 3084 3085 /* Part 2 3086 * If VT Mode is set 3087 * Either vlan_on 3088 * make sure the vlan is in VLVF 3089 * set the vind bit in the matching VLVFB 3090 * Or !vlan_on 3091 * clear the pool bit and possibly the vind 3092 */ 3093 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) 3094 goto vfta_update; 3095 3096 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 3097 if (vlvf_index < 0) { 3098 if (vlvf_bypass) 3099 goto vfta_update; 3100 return vlvf_index; 3101 } 3102 3103 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); 3104 3105 /* set the pool bit */ 3106 bits |= 1 << (vind % 32); 3107 if (vlan_on) 3108 goto vlvf_update; 3109 3110 /* clear the pool bit */ 3111 bits ^= 1 << (vind % 32); 3112 3113 if (!bits && 3114 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 3115 /* Clear VFTA first, then disable VLVF. Otherwise 3116 * we run the risk of stray packets leaking into 3117 * the PF via the default pool 3118 */ 3119 if (vfta_delta) 3120 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 3121 3122 /* disable VLVF and clear remaining bit from pool */ 3123 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 3124 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); 3125 3126 return 0; 3127 } 3128 3129 /* If there are still bits set in the VLVFB registers 3130 * for the VLAN ID indicated we need to see if the 3131 * caller is requesting that we clear the VFTA entry bit. 3132 * If the caller has requested that we clear the VFTA 3133 * entry bit but there are still pools/VFs using this VLAN 3134 * ID entry then ignore the request. We're not worried 3135 * about the case where we're turning the VFTA VLAN ID 3136 * entry bit on, only when requested to turn it off as 3137 * there may be multiple pools and/or VFs using the 3138 * VLAN ID entry. In that case we cannot clear the 3139 * VFTA bit until all pools/VFs using that VLAN ID have also 3140 * been cleared. This will be indicated by "bits" being 3141 * zero. 3142 */ 3143 vfta_delta = 0; 3144 3145 vlvf_update: 3146 /* record pool change and enable VLAN ID if not already enabled */ 3147 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); 3148 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); 3149 3150 vfta_update: 3151 /* Update VFTA now that we are ready for traffic */ 3152 if (vfta_delta) 3153 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 3154 3155 return 0; 3156 } 3157 3158 /** 3159 * ixgbe_clear_vfta_generic - Clear VLAN filter table 3160 * @hw: pointer to hardware structure 3161 * 3162 * Clears the VLAN filer table, and the VMDq index associated with the filter 3163 **/ 3164 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 3165 { 3166 u32 offset; 3167 3168 for (offset = 0; offset < hw->mac.vft_size; offset++) 3169 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 3170 3171 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 3172 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 3173 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 3174 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); 3175 } 3176 3177 return 0; 3178 } 3179 3180 /** 3181 * ixgbe_check_mac_link_generic - Determine link and speed status 3182 * @hw: pointer to hardware structure 3183 * @speed: pointer to link speed 3184 * @link_up: true when link is up 3185 * @link_up_wait_to_complete: bool used to wait for link up or not 3186 * 3187 * Reads the links register to determine if link is up and the current speed 3188 **/ 3189 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3190 bool *link_up, bool link_up_wait_to_complete) 3191 { 3192 u32 links_reg, links_orig; 3193 u32 i; 3194 3195 /* clear the old state */ 3196 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 3197 3198 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3199 3200 if (links_orig != links_reg) { 3201 hw_dbg(hw, "LINKS changed from %08X to %08X\n", 3202 links_orig, links_reg); 3203 } 3204 3205 if (link_up_wait_to_complete) { 3206 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 3207 if (links_reg & IXGBE_LINKS_UP) { 3208 *link_up = true; 3209 break; 3210 } else { 3211 *link_up = false; 3212 } 3213 msleep(100); 3214 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3215 } 3216 } else { 3217 if (links_reg & IXGBE_LINKS_UP) 3218 *link_up = true; 3219 else 3220 *link_up = false; 3221 } 3222 3223 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 3224 case IXGBE_LINKS_SPEED_10G_82599: 3225 if ((hw->mac.type >= ixgbe_mac_X550) && 3226 (links_reg & IXGBE_LINKS_SPEED_NON_STD)) 3227 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 3228 else 3229 *speed = IXGBE_LINK_SPEED_10GB_FULL; 3230 break; 3231 case IXGBE_LINKS_SPEED_1G_82599: 3232 *speed = IXGBE_LINK_SPEED_1GB_FULL; 3233 break; 3234 case IXGBE_LINKS_SPEED_100_82599: 3235 if ((hw->mac.type >= ixgbe_mac_X550) && 3236 (links_reg & IXGBE_LINKS_SPEED_NON_STD)) 3237 *speed = IXGBE_LINK_SPEED_5GB_FULL; 3238 else 3239 *speed = IXGBE_LINK_SPEED_100_FULL; 3240 break; 3241 default: 3242 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3243 } 3244 3245 return 0; 3246 } 3247 3248 /** 3249 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 3250 * the EEPROM 3251 * @hw: pointer to hardware structure 3252 * @wwnn_prefix: the alternative WWNN prefix 3253 * @wwpn_prefix: the alternative WWPN prefix 3254 * 3255 * This function will read the EEPROM from the alternative SAN MAC address 3256 * block to check the support for the alternative WWNN/WWPN prefix support. 3257 **/ 3258 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 3259 u16 *wwpn_prefix) 3260 { 3261 u16 offset, caps; 3262 u16 alt_san_mac_blk_offset; 3263 3264 /* clear output first */ 3265 *wwnn_prefix = 0xFFFF; 3266 *wwpn_prefix = 0xFFFF; 3267 3268 /* check if alternative SAN MAC is supported */ 3269 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 3270 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 3271 goto wwn_prefix_err; 3272 3273 if ((alt_san_mac_blk_offset == 0) || 3274 (alt_san_mac_blk_offset == 0xFFFF)) 3275 return 0; 3276 3277 /* check capability in alternative san mac address block */ 3278 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 3279 if (hw->eeprom.ops.read(hw, offset, &caps)) 3280 goto wwn_prefix_err; 3281 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 3282 return 0; 3283 3284 /* get the corresponding prefix for WWNN/WWPN */ 3285 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 3286 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) 3287 hw_err(hw, "eeprom read at offset %d failed\n", offset); 3288 3289 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 3290 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 3291 goto wwn_prefix_err; 3292 3293 return 0; 3294 3295 wwn_prefix_err: 3296 hw_err(hw, "eeprom read at offset %d failed\n", offset); 3297 return 0; 3298 } 3299 3300 /** 3301 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 3302 * @hw: pointer to hardware structure 3303 * @enable: enable or disable switch for anti-spoofing 3304 * @pf: Physical Function pool - do not enable anti-spoofing for the PF 3305 * 3306 **/ 3307 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf) 3308 { 3309 int j; 3310 int pf_target_reg = pf >> 3; 3311 int pf_target_shift = pf % 8; 3312 u32 pfvfspoof = 0; 3313 3314 if (hw->mac.type == ixgbe_mac_82598EB) 3315 return; 3316 3317 if (enable) 3318 pfvfspoof = IXGBE_SPOOF_MACAS_MASK; 3319 3320 /* 3321 * PFVFSPOOF register array is size 8 with 8 bits assigned to 3322 * MAC anti-spoof enables in each register array element. 3323 */ 3324 for (j = 0; j < pf_target_reg; j++) 3325 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof); 3326 3327 /* 3328 * The PF should be allowed to spoof so that it can support 3329 * emulation mode NICs. Do not set the bits assigned to the PF 3330 */ 3331 pfvfspoof &= (1 << pf_target_shift) - 1; 3332 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof); 3333 3334 /* 3335 * Remaining pools belong to the PF so they do not need to have 3336 * anti-spoofing enabled. 3337 */ 3338 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++) 3339 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0); 3340 } 3341 3342 /** 3343 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 3344 * @hw: pointer to hardware structure 3345 * @enable: enable or disable switch for VLAN anti-spoofing 3346 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 3347 * 3348 **/ 3349 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 3350 { 3351 int vf_target_reg = vf >> 3; 3352 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 3353 u32 pfvfspoof; 3354 3355 if (hw->mac.type == ixgbe_mac_82598EB) 3356 return; 3357 3358 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3359 if (enable) 3360 pfvfspoof |= (1 << vf_target_shift); 3361 else 3362 pfvfspoof &= ~(1 << vf_target_shift); 3363 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3364 } 3365 3366 /** 3367 * ixgbe_get_device_caps_generic - Get additional device capabilities 3368 * @hw: pointer to hardware structure 3369 * @device_caps: the EEPROM word with the extra device capabilities 3370 * 3371 * This function will read the EEPROM location for the device capabilities, 3372 * and return the word through device_caps. 3373 **/ 3374 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 3375 { 3376 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 3377 3378 return 0; 3379 } 3380 3381 /** 3382 * ixgbe_set_rxpba_generic - Initialize RX packet buffer 3383 * @hw: pointer to hardware structure 3384 * @num_pb: number of packet buffers to allocate 3385 * @headroom: reserve n KB of headroom 3386 * @strategy: packet buffer allocation strategy 3387 **/ 3388 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, 3389 int num_pb, 3390 u32 headroom, 3391 int strategy) 3392 { 3393 u32 pbsize = hw->mac.rx_pb_size; 3394 int i = 0; 3395 u32 rxpktsize, txpktsize, txpbthresh; 3396 3397 /* Reserve headroom */ 3398 pbsize -= headroom; 3399 3400 if (!num_pb) 3401 num_pb = 1; 3402 3403 /* Divide remaining packet buffer space amongst the number 3404 * of packet buffers requested using supplied strategy. 3405 */ 3406 switch (strategy) { 3407 case (PBA_STRATEGY_WEIGHTED): 3408 /* pba_80_48 strategy weight first half of packet buffer with 3409 * 5/8 of the packet buffer space. 3410 */ 3411 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8)); 3412 pbsize -= rxpktsize * (num_pb / 2); 3413 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 3414 for (; i < (num_pb / 2); i++) 3415 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3416 /* Fall through to configure remaining packet buffers */ 3417 case (PBA_STRATEGY_EQUAL): 3418 /* Divide the remaining Rx packet buffer evenly among the TCs */ 3419 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 3420 for (; i < num_pb; i++) 3421 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3422 break; 3423 default: 3424 break; 3425 } 3426 3427 /* 3428 * Setup Tx packet buffer and threshold equally for all TCs 3429 * TXPBTHRESH register is set in K so divide by 1024 and subtract 3430 * 10 since the largest packet we support is just over 9K. 3431 */ 3432 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 3433 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 3434 for (i = 0; i < num_pb; i++) { 3435 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 3436 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 3437 } 3438 3439 /* Clear unused TCs, if any, to zero buffer size*/ 3440 for (; i < IXGBE_MAX_PB; i++) { 3441 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 3442 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 3443 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 3444 } 3445 } 3446 3447 /** 3448 * ixgbe_calculate_checksum - Calculate checksum for buffer 3449 * @buffer: pointer to EEPROM 3450 * @length: size of EEPROM to calculate a checksum for 3451 * 3452 * Calculates the checksum for some buffer on a specified length. The 3453 * checksum calculated is returned. 3454 **/ 3455 static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 3456 { 3457 u32 i; 3458 u8 sum = 0; 3459 3460 if (!buffer) 3461 return 0; 3462 3463 for (i = 0; i < length; i++) 3464 sum += buffer[i]; 3465 3466 return (u8) (0 - sum); 3467 } 3468 3469 /** 3470 * ixgbe_host_interface_command - Issue command to manageability block 3471 * @hw: pointer to the HW structure 3472 * @buffer: contains the command to write and where the return status will 3473 * be placed 3474 * @length: length of buffer, must be multiple of 4 bytes 3475 * @timeout: time in ms to wait for command completion 3476 * @return_data: read and return data from the buffer (true) or not (false) 3477 * Needed because FW structures are big endian and decoding of 3478 * these fields can be 8 bit or 16 bit based on command. Decoding 3479 * is not easily understood without making a table of commands. 3480 * So we will leave this up to the caller to read back the data 3481 * in these cases. 3482 * 3483 * Communicates with the manageability block. On success return 0 3484 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND. 3485 **/ 3486 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 3487 u32 length, u32 timeout, 3488 bool return_data) 3489 { 3490 u32 hicr, i, bi, fwsts; 3491 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 3492 u16 buf_len, dword_len; 3493 3494 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 3495 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); 3496 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3497 } 3498 3499 /* Set bit 9 of FWSTS clearing FW reset indication */ 3500 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 3501 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 3502 3503 /* Check that the host interface is enabled. */ 3504 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3505 if ((hicr & IXGBE_HICR_EN) == 0) { 3506 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n"); 3507 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3508 } 3509 3510 /* Calculate length in DWORDs. We must be DWORD aligned */ 3511 if ((length % (sizeof(u32))) != 0) { 3512 hw_dbg(hw, "Buffer length failure, not aligned to dword"); 3513 return IXGBE_ERR_INVALID_ARGUMENT; 3514 } 3515 3516 dword_len = length >> 2; 3517 3518 /* 3519 * The device driver writes the relevant command block 3520 * into the ram area. 3521 */ 3522 for (i = 0; i < dword_len; i++) 3523 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 3524 i, cpu_to_le32(buffer[i])); 3525 3526 /* Setting this bit tells the ARC that a new command is pending. */ 3527 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 3528 3529 for (i = 0; i < timeout; i++) { 3530 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3531 if (!(hicr & IXGBE_HICR_C)) 3532 break; 3533 usleep_range(1000, 2000); 3534 } 3535 3536 /* Check command successful completion. */ 3537 if ((timeout != 0 && i == timeout) || 3538 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) { 3539 hw_dbg(hw, "Command has failed with no status valid.\n"); 3540 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3541 } 3542 3543 if (!return_data) 3544 return 0; 3545 3546 /* Calculate length in DWORDs */ 3547 dword_len = hdr_size >> 2; 3548 3549 /* first pull in the header so we know the buffer length */ 3550 for (bi = 0; bi < dword_len; bi++) { 3551 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3552 le32_to_cpus(&buffer[bi]); 3553 } 3554 3555 /* If there is any thing in data position pull it in */ 3556 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len; 3557 if (buf_len == 0) 3558 return 0; 3559 3560 if (length < (buf_len + hdr_size)) { 3561 hw_dbg(hw, "Buffer not large enough for reply message.\n"); 3562 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3563 } 3564 3565 /* Calculate length in DWORDs, add 3 for odd lengths */ 3566 dword_len = (buf_len + 3) >> 2; 3567 3568 /* Pull in the rest of the buffer (bi is where we left off)*/ 3569 for (; bi <= dword_len; bi++) { 3570 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3571 le32_to_cpus(&buffer[bi]); 3572 } 3573 3574 return 0; 3575 } 3576 3577 /** 3578 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 3579 * @hw: pointer to the HW structure 3580 * @maj: driver version major number 3581 * @min: driver version minor number 3582 * @build: driver version build number 3583 * @sub: driver version sub build number 3584 * 3585 * Sends driver version number to firmware through the manageability 3586 * block. On success return 0 3587 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 3588 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 3589 **/ 3590 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 3591 u8 build, u8 sub) 3592 { 3593 struct ixgbe_hic_drv_info fw_cmd; 3594 int i; 3595 s32 ret_val; 3596 3597 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)) 3598 return IXGBE_ERR_SWFW_SYNC; 3599 3600 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 3601 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 3602 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 3603 fw_cmd.port_num = (u8)hw->bus.func; 3604 fw_cmd.ver_maj = maj; 3605 fw_cmd.ver_min = min; 3606 fw_cmd.ver_build = build; 3607 fw_cmd.ver_sub = sub; 3608 fw_cmd.hdr.checksum = 0; 3609 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 3610 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 3611 fw_cmd.pad = 0; 3612 fw_cmd.pad2 = 0; 3613 3614 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 3615 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 3616 sizeof(fw_cmd), 3617 IXGBE_HI_COMMAND_TIMEOUT, 3618 true); 3619 if (ret_val != 0) 3620 continue; 3621 3622 if (fw_cmd.hdr.cmd_or_resp.ret_status == 3623 FW_CEM_RESP_STATUS_SUCCESS) 3624 ret_val = 0; 3625 else 3626 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3627 3628 break; 3629 } 3630 3631 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 3632 return ret_val; 3633 } 3634 3635 /** 3636 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 3637 * @hw: pointer to the hardware structure 3638 * 3639 * The 82599 and x540 MACs can experience issues if TX work is still pending 3640 * when a reset occurs. This function prevents this by flushing the PCIe 3641 * buffers on the system. 3642 **/ 3643 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 3644 { 3645 u32 gcr_ext, hlreg0, i, poll; 3646 u16 value; 3647 3648 /* 3649 * If double reset is not requested then all transactions should 3650 * already be clear and as such there is no work to do 3651 */ 3652 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 3653 return; 3654 3655 /* 3656 * Set loopback enable to prevent any transmits from being sent 3657 * should the link come up. This assumes that the RXCTRL.RXEN bit 3658 * has already been cleared. 3659 */ 3660 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3661 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 3662 3663 /* wait for a last completion before clearing buffers */ 3664 IXGBE_WRITE_FLUSH(hw); 3665 usleep_range(3000, 6000); 3666 3667 /* Before proceeding, make sure that the PCIe block does not have 3668 * transactions pending. 3669 */ 3670 poll = ixgbe_pcie_timeout_poll(hw); 3671 for (i = 0; i < poll; i++) { 3672 usleep_range(100, 200); 3673 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); 3674 if (ixgbe_removed(hw->hw_addr)) 3675 break; 3676 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3677 break; 3678 } 3679 3680 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 3681 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 3682 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 3683 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 3684 3685 /* Flush all writes and allow 20usec for all transactions to clear */ 3686 IXGBE_WRITE_FLUSH(hw); 3687 udelay(20); 3688 3689 /* restore previous register values */ 3690 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 3691 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3692 } 3693 3694 static const u8 ixgbe_emc_temp_data[4] = { 3695 IXGBE_EMC_INTERNAL_DATA, 3696 IXGBE_EMC_DIODE1_DATA, 3697 IXGBE_EMC_DIODE2_DATA, 3698 IXGBE_EMC_DIODE3_DATA 3699 }; 3700 static const u8 ixgbe_emc_therm_limit[4] = { 3701 IXGBE_EMC_INTERNAL_THERM_LIMIT, 3702 IXGBE_EMC_DIODE1_THERM_LIMIT, 3703 IXGBE_EMC_DIODE2_THERM_LIMIT, 3704 IXGBE_EMC_DIODE3_THERM_LIMIT 3705 }; 3706 3707 /** 3708 * ixgbe_get_ets_data - Extracts the ETS bit data 3709 * @hw: pointer to hardware structure 3710 * @ets_cfg: extected ETS data 3711 * @ets_offset: offset of ETS data 3712 * 3713 * Returns error code. 3714 **/ 3715 static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg, 3716 u16 *ets_offset) 3717 { 3718 s32 status; 3719 3720 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset); 3721 if (status) 3722 return status; 3723 3724 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF)) 3725 return IXGBE_NOT_IMPLEMENTED; 3726 3727 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg); 3728 if (status) 3729 return status; 3730 3731 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED) 3732 return IXGBE_NOT_IMPLEMENTED; 3733 3734 return 0; 3735 } 3736 3737 /** 3738 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data 3739 * @hw: pointer to hardware structure 3740 * 3741 * Returns the thermal sensor data structure 3742 **/ 3743 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) 3744 { 3745 s32 status; 3746 u16 ets_offset; 3747 u16 ets_cfg; 3748 u16 ets_sensor; 3749 u8 num_sensors; 3750 u8 i; 3751 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 3752 3753 /* Only support thermal sensors attached to physical port 0 */ 3754 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 3755 return IXGBE_NOT_IMPLEMENTED; 3756 3757 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); 3758 if (status) 3759 return status; 3760 3761 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 3762 if (num_sensors > IXGBE_MAX_SENSORS) 3763 num_sensors = IXGBE_MAX_SENSORS; 3764 3765 for (i = 0; i < num_sensors; i++) { 3766 u8 sensor_index; 3767 u8 sensor_location; 3768 3769 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), 3770 &ets_sensor); 3771 if (status) 3772 return status; 3773 3774 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 3775 IXGBE_ETS_DATA_INDEX_SHIFT); 3776 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 3777 IXGBE_ETS_DATA_LOC_SHIFT); 3778 3779 if (sensor_location != 0) { 3780 status = hw->phy.ops.read_i2c_byte(hw, 3781 ixgbe_emc_temp_data[sensor_index], 3782 IXGBE_I2C_THERMAL_SENSOR_ADDR, 3783 &data->sensor[i].temp); 3784 if (status) 3785 return status; 3786 } 3787 } 3788 3789 return 0; 3790 } 3791 3792 /** 3793 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds 3794 * @hw: pointer to hardware structure 3795 * 3796 * Inits the thermal sensor thresholds according to the NVM map 3797 * and save off the threshold and location values into mac.thermal_sensor_data 3798 **/ 3799 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) 3800 { 3801 s32 status; 3802 u16 ets_offset; 3803 u16 ets_cfg; 3804 u16 ets_sensor; 3805 u8 low_thresh_delta; 3806 u8 num_sensors; 3807 u8 therm_limit; 3808 u8 i; 3809 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 3810 3811 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data)); 3812 3813 /* Only support thermal sensors attached to physical port 0 */ 3814 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 3815 return IXGBE_NOT_IMPLEMENTED; 3816 3817 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); 3818 if (status) 3819 return status; 3820 3821 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >> 3822 IXGBE_ETS_LTHRES_DELTA_SHIFT); 3823 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 3824 if (num_sensors > IXGBE_MAX_SENSORS) 3825 num_sensors = IXGBE_MAX_SENSORS; 3826 3827 for (i = 0; i < num_sensors; i++) { 3828 u8 sensor_index; 3829 u8 sensor_location; 3830 3831 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) { 3832 hw_err(hw, "eeprom read at offset %d failed\n", 3833 ets_offset + 1 + i); 3834 continue; 3835 } 3836 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 3837 IXGBE_ETS_DATA_INDEX_SHIFT); 3838 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 3839 IXGBE_ETS_DATA_LOC_SHIFT); 3840 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK; 3841 3842 hw->phy.ops.write_i2c_byte(hw, 3843 ixgbe_emc_therm_limit[sensor_index], 3844 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit); 3845 3846 if (sensor_location == 0) 3847 continue; 3848 3849 data->sensor[i].location = sensor_location; 3850 data->sensor[i].caution_thresh = therm_limit; 3851 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta; 3852 } 3853 3854 return 0; 3855 } 3856 3857 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 3858 { 3859 u32 rxctrl; 3860 3861 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3862 if (rxctrl & IXGBE_RXCTRL_RXEN) { 3863 if (hw->mac.type != ixgbe_mac_82598EB) { 3864 u32 pfdtxgswc; 3865 3866 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 3867 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 3868 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 3869 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 3870 hw->mac.set_lben = true; 3871 } else { 3872 hw->mac.set_lben = false; 3873 } 3874 } 3875 rxctrl &= ~IXGBE_RXCTRL_RXEN; 3876 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 3877 } 3878 } 3879 3880 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 3881 { 3882 u32 rxctrl; 3883 3884 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3885 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 3886 3887 if (hw->mac.type != ixgbe_mac_82598EB) { 3888 if (hw->mac.set_lben) { 3889 u32 pfdtxgswc; 3890 3891 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 3892 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 3893 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 3894 hw->mac.set_lben = false; 3895 } 3896 } 3897 } 3898 3899 /** ixgbe_mng_present - returns true when management capability is present 3900 * @hw: pointer to hardware structure 3901 **/ 3902 bool ixgbe_mng_present(struct ixgbe_hw *hw) 3903 { 3904 u32 fwsm; 3905 3906 if (hw->mac.type < ixgbe_mac_82599EB) 3907 return false; 3908 3909 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 3910 fwsm &= IXGBE_FWSM_MODE_MASK; 3911 return fwsm == IXGBE_FWSM_FW_MODE_PT; 3912 } 3913 3914 /** 3915 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 3916 * @hw: pointer to hardware structure 3917 * @speed: new link speed 3918 * @autoneg_wait_to_complete: true when waiting for completion is needed 3919 * 3920 * Set the link speed in the MAC and/or PHY register and restarts link. 3921 */ 3922 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 3923 ixgbe_link_speed speed, 3924 bool autoneg_wait_to_complete) 3925 { 3926 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 3927 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 3928 s32 status = 0; 3929 u32 speedcnt = 0; 3930 u32 i = 0; 3931 bool autoneg, link_up = false; 3932 3933 /* Mask off requested but non-supported speeds */ 3934 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg); 3935 if (status) 3936 return status; 3937 3938 speed &= link_speed; 3939 3940 /* Try each speed one by one, highest priority first. We do this in 3941 * software because 10Gb fiber doesn't support speed autonegotiation. 3942 */ 3943 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 3944 speedcnt++; 3945 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 3946 3947 /* If we already have link at this speed, just jump out */ 3948 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 3949 false); 3950 if (status) 3951 return status; 3952 3953 if (link_speed == IXGBE_LINK_SPEED_10GB_FULL && link_up) 3954 goto out; 3955 3956 /* Set the module link speed */ 3957 switch (hw->phy.media_type) { 3958 case ixgbe_media_type_fiber: 3959 hw->mac.ops.set_rate_select_speed(hw, 3960 IXGBE_LINK_SPEED_10GB_FULL); 3961 break; 3962 case ixgbe_media_type_fiber_qsfp: 3963 /* QSFP module automatically detects MAC link speed */ 3964 break; 3965 default: 3966 hw_dbg(hw, "Unexpected media type\n"); 3967 break; 3968 } 3969 3970 /* Allow module to change analog characteristics (1G->10G) */ 3971 msleep(40); 3972 3973 status = hw->mac.ops.setup_mac_link(hw, 3974 IXGBE_LINK_SPEED_10GB_FULL, 3975 autoneg_wait_to_complete); 3976 if (status) 3977 return status; 3978 3979 /* Flap the Tx laser if it has not already been done */ 3980 if (hw->mac.ops.flap_tx_laser) 3981 hw->mac.ops.flap_tx_laser(hw); 3982 3983 /* Wait for the controller to acquire link. Per IEEE 802.3ap, 3984 * Section 73.10.2, we may have to wait up to 500ms if KR is 3985 * attempted. 82599 uses the same timing for 10g SFI. 3986 */ 3987 for (i = 0; i < 5; i++) { 3988 /* Wait for the link partner to also set speed */ 3989 msleep(100); 3990 3991 /* If we have link, just jump out */ 3992 status = hw->mac.ops.check_link(hw, &link_speed, 3993 &link_up, false); 3994 if (status) 3995 return status; 3996 3997 if (link_up) 3998 goto out; 3999 } 4000 } 4001 4002 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 4003 speedcnt++; 4004 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 4005 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 4006 4007 /* If we already have link at this speed, just jump out */ 4008 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 4009 false); 4010 if (status) 4011 return status; 4012 4013 if (link_speed == IXGBE_LINK_SPEED_1GB_FULL && link_up) 4014 goto out; 4015 4016 /* Set the module link speed */ 4017 switch (hw->phy.media_type) { 4018 case ixgbe_media_type_fiber: 4019 hw->mac.ops.set_rate_select_speed(hw, 4020 IXGBE_LINK_SPEED_1GB_FULL); 4021 break; 4022 case ixgbe_media_type_fiber_qsfp: 4023 /* QSFP module automatically detects link speed */ 4024 break; 4025 default: 4026 hw_dbg(hw, "Unexpected media type\n"); 4027 break; 4028 } 4029 4030 /* Allow module to change analog characteristics (10G->1G) */ 4031 msleep(40); 4032 4033 status = hw->mac.ops.setup_mac_link(hw, 4034 IXGBE_LINK_SPEED_1GB_FULL, 4035 autoneg_wait_to_complete); 4036 if (status) 4037 return status; 4038 4039 /* Flap the Tx laser if it has not already been done */ 4040 if (hw->mac.ops.flap_tx_laser) 4041 hw->mac.ops.flap_tx_laser(hw); 4042 4043 /* Wait for the link partner to also set speed */ 4044 msleep(100); 4045 4046 /* If we have link, just jump out */ 4047 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 4048 false); 4049 if (status) 4050 return status; 4051 4052 if (link_up) 4053 goto out; 4054 } 4055 4056 /* We didn't get link. Configure back to the highest speed we tried, 4057 * (if there was more than one). We call ourselves back with just the 4058 * single highest speed that the user requested. 4059 */ 4060 if (speedcnt > 1) 4061 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 4062 highest_link_speed, 4063 autoneg_wait_to_complete); 4064 4065 out: 4066 /* Set autoneg_advertised value based on input link speed */ 4067 hw->phy.autoneg_advertised = 0; 4068 4069 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 4070 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 4071 4072 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 4073 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 4074 4075 return status; 4076 } 4077 4078 /** 4079 * ixgbe_set_soft_rate_select_speed - Set module link speed 4080 * @hw: pointer to hardware structure 4081 * @speed: link speed to set 4082 * 4083 * Set module link speed via the soft rate select. 4084 */ 4085 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 4086 ixgbe_link_speed speed) 4087 { 4088 s32 status; 4089 u8 rs, eeprom_data; 4090 4091 switch (speed) { 4092 case IXGBE_LINK_SPEED_10GB_FULL: 4093 /* one bit mask same as setting on */ 4094 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 4095 break; 4096 case IXGBE_LINK_SPEED_1GB_FULL: 4097 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 4098 break; 4099 default: 4100 hw_dbg(hw, "Invalid fixed module speed\n"); 4101 return; 4102 } 4103 4104 /* Set RS0 */ 4105 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4106 IXGBE_I2C_EEPROM_DEV_ADDR2, 4107 &eeprom_data); 4108 if (status) { 4109 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n"); 4110 return; 4111 } 4112 4113 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 4114 4115 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4116 IXGBE_I2C_EEPROM_DEV_ADDR2, 4117 eeprom_data); 4118 if (status) { 4119 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n"); 4120 return; 4121 } 4122 } 4123