1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/pci.h> 30 #include <linux/delay.h> 31 #include <linux/sched.h> 32 #include <linux/netdevice.h> 33 34 #include "ixgbe.h" 35 #include "ixgbe_common.h" 36 #include "ixgbe_phy.h" 37 38 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 39 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 40 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 41 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 42 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 43 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 44 u16 count); 45 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 46 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 47 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 48 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 49 50 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 51 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg); 52 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 53 u16 words, u16 *data); 54 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 55 u16 words, u16 *data); 56 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 57 u16 offset); 58 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw); 59 60 /* Base table for registers values that change by MAC */ 61 const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = { 62 IXGBE_MVALS_INIT(8259X) 63 }; 64 65 /** 66 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow 67 * control 68 * @hw: pointer to hardware structure 69 * 70 * There are several phys that do not support autoneg flow control. This 71 * function check the device id to see if the associated phy supports 72 * autoneg flow control. 73 **/ 74 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 75 { 76 bool supported = false; 77 ixgbe_link_speed speed; 78 bool link_up; 79 80 switch (hw->phy.media_type) { 81 case ixgbe_media_type_fiber: 82 /* flow control autoneg black list */ 83 switch (hw->device_id) { 84 case IXGBE_DEV_ID_X550EM_A_SFP: 85 case IXGBE_DEV_ID_X550EM_A_SFP_N: 86 supported = false; 87 break; 88 default: 89 hw->mac.ops.check_link(hw, &speed, &link_up, false); 90 /* if link is down, assume supported */ 91 if (link_up) 92 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? 93 true : false; 94 else 95 supported = true; 96 } 97 98 break; 99 case ixgbe_media_type_backplane: 100 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) 101 supported = false; 102 else 103 supported = true; 104 break; 105 case ixgbe_media_type_copper: 106 /* only some copper devices support flow control autoneg */ 107 switch (hw->device_id) { 108 case IXGBE_DEV_ID_82599_T3_LOM: 109 case IXGBE_DEV_ID_X540T: 110 case IXGBE_DEV_ID_X540T1: 111 case IXGBE_DEV_ID_X550T: 112 case IXGBE_DEV_ID_X550T1: 113 case IXGBE_DEV_ID_X550EM_X_10G_T: 114 case IXGBE_DEV_ID_X550EM_A_10G_T: 115 case IXGBE_DEV_ID_X550EM_A_1G_T: 116 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 117 supported = true; 118 break; 119 default: 120 break; 121 } 122 default: 123 break; 124 } 125 126 if (!supported) 127 hw_dbg(hw, "Device %x does not support flow control autoneg\n", 128 hw->device_id); 129 130 return supported; 131 } 132 133 /** 134 * ixgbe_setup_fc_generic - Set up flow control 135 * @hw: pointer to hardware structure 136 * 137 * Called at init time to set up flow control. 138 **/ 139 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) 140 { 141 s32 ret_val = 0; 142 u32 reg = 0, reg_bp = 0; 143 u16 reg_cu = 0; 144 bool locked = false; 145 146 /* 147 * Validate the requested mode. Strict IEEE mode does not allow 148 * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 149 */ 150 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 151 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 152 return IXGBE_ERR_INVALID_LINK_SETTINGS; 153 } 154 155 /* 156 * 10gig parts do not have a word in the EEPROM to determine the 157 * default flow control setting, so we explicitly set it to full. 158 */ 159 if (hw->fc.requested_mode == ixgbe_fc_default) 160 hw->fc.requested_mode = ixgbe_fc_full; 161 162 /* 163 * Set up the 1G and 10G flow control advertisement registers so the 164 * HW will be able to do fc autoneg once the cable is plugged in. If 165 * we link at 10G, the 1G advertisement is harmless and vice versa. 166 */ 167 switch (hw->phy.media_type) { 168 case ixgbe_media_type_backplane: 169 /* some MAC's need RMW protection on AUTOC */ 170 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 171 if (ret_val) 172 return ret_val; 173 174 /* fall through - only backplane uses autoc */ 175 case ixgbe_media_type_fiber: 176 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 177 178 break; 179 case ixgbe_media_type_copper: 180 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 181 MDIO_MMD_AN, ®_cu); 182 break; 183 default: 184 break; 185 } 186 187 /* 188 * The possible values of fc.requested_mode are: 189 * 0: Flow control is completely disabled 190 * 1: Rx flow control is enabled (we can receive pause frames, 191 * but not send pause frames). 192 * 2: Tx flow control is enabled (we can send pause frames but 193 * we do not support receiving pause frames). 194 * 3: Both Rx and Tx flow control (symmetric) are enabled. 195 * other: Invalid. 196 */ 197 switch (hw->fc.requested_mode) { 198 case ixgbe_fc_none: 199 /* Flow control completely disabled by software override. */ 200 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 201 if (hw->phy.media_type == ixgbe_media_type_backplane) 202 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 203 IXGBE_AUTOC_ASM_PAUSE); 204 else if (hw->phy.media_type == ixgbe_media_type_copper) 205 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 206 break; 207 case ixgbe_fc_tx_pause: 208 /* 209 * Tx Flow control is enabled, and Rx Flow control is 210 * disabled by software override. 211 */ 212 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 213 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 214 if (hw->phy.media_type == ixgbe_media_type_backplane) { 215 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 216 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 217 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 218 reg_cu |= IXGBE_TAF_ASM_PAUSE; 219 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 220 } 221 break; 222 case ixgbe_fc_rx_pause: 223 /* 224 * Rx Flow control is enabled and Tx Flow control is 225 * disabled by software override. Since there really 226 * isn't a way to advertise that we are capable of RX 227 * Pause ONLY, we will advertise that we support both 228 * symmetric and asymmetric Rx PAUSE, as such we fall 229 * through to the fc_full statement. Later, we will 230 * disable the adapter's ability to send PAUSE frames. 231 */ 232 case ixgbe_fc_full: 233 /* Flow control (both Rx and Tx) is enabled by SW override. */ 234 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 235 if (hw->phy.media_type == ixgbe_media_type_backplane) 236 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 237 IXGBE_AUTOC_ASM_PAUSE; 238 else if (hw->phy.media_type == ixgbe_media_type_copper) 239 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 240 break; 241 default: 242 hw_dbg(hw, "Flow control param set incorrectly\n"); 243 return IXGBE_ERR_CONFIG; 244 } 245 246 if (hw->mac.type != ixgbe_mac_X540) { 247 /* 248 * Enable auto-negotiation between the MAC & PHY; 249 * the MAC will advertise clause 37 flow control. 250 */ 251 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 252 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 253 254 /* Disable AN timeout */ 255 if (hw->fc.strict_ieee) 256 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 257 258 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 259 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); 260 } 261 262 /* 263 * AUTOC restart handles negotiation of 1G and 10G on backplane 264 * and copper. There is no need to set the PCS1GCTL register. 265 * 266 */ 267 if (hw->phy.media_type == ixgbe_media_type_backplane) { 268 /* Need the SW/FW semaphore around AUTOC writes if 82599 and 269 * LESM is on, likewise reset_pipeline requries the lock as 270 * it also writes AUTOC. 271 */ 272 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 273 if (ret_val) 274 return ret_val; 275 276 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 277 ixgbe_device_supports_autoneg_fc(hw)) { 278 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 279 MDIO_MMD_AN, reg_cu); 280 } 281 282 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); 283 return ret_val; 284 } 285 286 /** 287 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 288 * @hw: pointer to hardware structure 289 * 290 * Starts the hardware by filling the bus info structure and media type, clears 291 * all on chip counters, initializes receive address registers, multicast 292 * table, VLAN filter table, calls routine to set up link and flow control 293 * settings, and leaves transmit and receive units disabled and uninitialized 294 **/ 295 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 296 { 297 s32 ret_val; 298 u32 ctrl_ext; 299 u16 device_caps; 300 301 /* Set the media type */ 302 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 303 304 /* Identify the PHY */ 305 hw->phy.ops.identify(hw); 306 307 /* Clear the VLAN filter table */ 308 hw->mac.ops.clear_vfta(hw); 309 310 /* Clear statistics registers */ 311 hw->mac.ops.clear_hw_cntrs(hw); 312 313 /* Set No Snoop Disable */ 314 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 315 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 316 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 317 IXGBE_WRITE_FLUSH(hw); 318 319 /* Setup flow control if method for doing so */ 320 if (hw->mac.ops.setup_fc) { 321 ret_val = hw->mac.ops.setup_fc(hw); 322 if (ret_val) 323 return ret_val; 324 } 325 326 /* Cashe bit indicating need for crosstalk fix */ 327 switch (hw->mac.type) { 328 case ixgbe_mac_82599EB: 329 case ixgbe_mac_X550EM_x: 330 case ixgbe_mac_x550em_a: 331 hw->mac.ops.get_device_caps(hw, &device_caps); 332 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) 333 hw->need_crosstalk_fix = false; 334 else 335 hw->need_crosstalk_fix = true; 336 break; 337 default: 338 hw->need_crosstalk_fix = false; 339 break; 340 } 341 342 /* Clear adapter stopped flag */ 343 hw->adapter_stopped = false; 344 345 return 0; 346 } 347 348 /** 349 * ixgbe_start_hw_gen2 - Init sequence for common device family 350 * @hw: pointer to hw structure 351 * 352 * Performs the init sequence common to the second generation 353 * of 10 GbE devices. 354 * Devices in the second generation: 355 * 82599 356 * X540 357 **/ 358 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 359 { 360 u32 i; 361 362 /* Clear the rate limiters */ 363 for (i = 0; i < hw->mac.max_tx_queues; i++) { 364 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 365 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 366 } 367 IXGBE_WRITE_FLUSH(hw); 368 369 return 0; 370 } 371 372 /** 373 * ixgbe_init_hw_generic - Generic hardware initialization 374 * @hw: pointer to hardware structure 375 * 376 * Initialize the hardware by resetting the hardware, filling the bus info 377 * structure and media type, clears all on chip counters, initializes receive 378 * address registers, multicast table, VLAN filter table, calls routine to set 379 * up link and flow control settings, and leaves transmit and receive units 380 * disabled and uninitialized 381 **/ 382 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 383 { 384 s32 status; 385 386 /* Reset the hardware */ 387 status = hw->mac.ops.reset_hw(hw); 388 389 if (status == 0) { 390 /* Start the HW */ 391 status = hw->mac.ops.start_hw(hw); 392 } 393 394 /* Initialize the LED link active for LED blink support */ 395 if (hw->mac.ops.init_led_link_act) 396 hw->mac.ops.init_led_link_act(hw); 397 398 return status; 399 } 400 401 /** 402 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 403 * @hw: pointer to hardware structure 404 * 405 * Clears all hardware statistics counters by reading them from the hardware 406 * Statistics counters are clear on read. 407 **/ 408 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 409 { 410 u16 i = 0; 411 412 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 413 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 414 IXGBE_READ_REG(hw, IXGBE_ERRBC); 415 IXGBE_READ_REG(hw, IXGBE_MSPDC); 416 for (i = 0; i < 8; i++) 417 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 418 419 IXGBE_READ_REG(hw, IXGBE_MLFC); 420 IXGBE_READ_REG(hw, IXGBE_MRFC); 421 IXGBE_READ_REG(hw, IXGBE_RLEC); 422 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 423 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 424 if (hw->mac.type >= ixgbe_mac_82599EB) { 425 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 426 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 427 } else { 428 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 429 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 430 } 431 432 for (i = 0; i < 8; i++) { 433 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 434 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 435 if (hw->mac.type >= ixgbe_mac_82599EB) { 436 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 437 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 438 } else { 439 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 440 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 441 } 442 } 443 if (hw->mac.type >= ixgbe_mac_82599EB) 444 for (i = 0; i < 8; i++) 445 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 446 IXGBE_READ_REG(hw, IXGBE_PRC64); 447 IXGBE_READ_REG(hw, IXGBE_PRC127); 448 IXGBE_READ_REG(hw, IXGBE_PRC255); 449 IXGBE_READ_REG(hw, IXGBE_PRC511); 450 IXGBE_READ_REG(hw, IXGBE_PRC1023); 451 IXGBE_READ_REG(hw, IXGBE_PRC1522); 452 IXGBE_READ_REG(hw, IXGBE_GPRC); 453 IXGBE_READ_REG(hw, IXGBE_BPRC); 454 IXGBE_READ_REG(hw, IXGBE_MPRC); 455 IXGBE_READ_REG(hw, IXGBE_GPTC); 456 IXGBE_READ_REG(hw, IXGBE_GORCL); 457 IXGBE_READ_REG(hw, IXGBE_GORCH); 458 IXGBE_READ_REG(hw, IXGBE_GOTCL); 459 IXGBE_READ_REG(hw, IXGBE_GOTCH); 460 if (hw->mac.type == ixgbe_mac_82598EB) 461 for (i = 0; i < 8; i++) 462 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 463 IXGBE_READ_REG(hw, IXGBE_RUC); 464 IXGBE_READ_REG(hw, IXGBE_RFC); 465 IXGBE_READ_REG(hw, IXGBE_ROC); 466 IXGBE_READ_REG(hw, IXGBE_RJC); 467 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 468 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 469 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 470 IXGBE_READ_REG(hw, IXGBE_TORL); 471 IXGBE_READ_REG(hw, IXGBE_TORH); 472 IXGBE_READ_REG(hw, IXGBE_TPR); 473 IXGBE_READ_REG(hw, IXGBE_TPT); 474 IXGBE_READ_REG(hw, IXGBE_PTC64); 475 IXGBE_READ_REG(hw, IXGBE_PTC127); 476 IXGBE_READ_REG(hw, IXGBE_PTC255); 477 IXGBE_READ_REG(hw, IXGBE_PTC511); 478 IXGBE_READ_REG(hw, IXGBE_PTC1023); 479 IXGBE_READ_REG(hw, IXGBE_PTC1522); 480 IXGBE_READ_REG(hw, IXGBE_MPTC); 481 IXGBE_READ_REG(hw, IXGBE_BPTC); 482 for (i = 0; i < 16; i++) { 483 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 484 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 485 if (hw->mac.type >= ixgbe_mac_82599EB) { 486 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 487 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 488 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 489 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 490 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 491 } else { 492 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 493 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 494 } 495 } 496 497 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { 498 if (hw->phy.id == 0) 499 hw->phy.ops.identify(hw); 500 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i); 501 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i); 502 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i); 503 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i); 504 } 505 506 return 0; 507 } 508 509 /** 510 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 511 * @hw: pointer to hardware structure 512 * @pba_num: stores the part number string from the EEPROM 513 * @pba_num_size: part number string buffer length 514 * 515 * Reads the part number string from the EEPROM. 516 **/ 517 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 518 u32 pba_num_size) 519 { 520 s32 ret_val; 521 u16 data; 522 u16 pba_ptr; 523 u16 offset; 524 u16 length; 525 526 if (pba_num == NULL) { 527 hw_dbg(hw, "PBA string buffer was null\n"); 528 return IXGBE_ERR_INVALID_ARGUMENT; 529 } 530 531 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 532 if (ret_val) { 533 hw_dbg(hw, "NVM Read Error\n"); 534 return ret_val; 535 } 536 537 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 538 if (ret_val) { 539 hw_dbg(hw, "NVM Read Error\n"); 540 return ret_val; 541 } 542 543 /* 544 * if data is not ptr guard the PBA must be in legacy format which 545 * means pba_ptr is actually our second data word for the PBA number 546 * and we can decode it into an ascii string 547 */ 548 if (data != IXGBE_PBANUM_PTR_GUARD) { 549 hw_dbg(hw, "NVM PBA number is not stored as string\n"); 550 551 /* we will need 11 characters to store the PBA */ 552 if (pba_num_size < 11) { 553 hw_dbg(hw, "PBA string buffer too small\n"); 554 return IXGBE_ERR_NO_SPACE; 555 } 556 557 /* extract hex string from data and pba_ptr */ 558 pba_num[0] = (data >> 12) & 0xF; 559 pba_num[1] = (data >> 8) & 0xF; 560 pba_num[2] = (data >> 4) & 0xF; 561 pba_num[3] = data & 0xF; 562 pba_num[4] = (pba_ptr >> 12) & 0xF; 563 pba_num[5] = (pba_ptr >> 8) & 0xF; 564 pba_num[6] = '-'; 565 pba_num[7] = 0; 566 pba_num[8] = (pba_ptr >> 4) & 0xF; 567 pba_num[9] = pba_ptr & 0xF; 568 569 /* put a null character on the end of our string */ 570 pba_num[10] = '\0'; 571 572 /* switch all the data but the '-' to hex char */ 573 for (offset = 0; offset < 10; offset++) { 574 if (pba_num[offset] < 0xA) 575 pba_num[offset] += '0'; 576 else if (pba_num[offset] < 0x10) 577 pba_num[offset] += 'A' - 0xA; 578 } 579 580 return 0; 581 } 582 583 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 584 if (ret_val) { 585 hw_dbg(hw, "NVM Read Error\n"); 586 return ret_val; 587 } 588 589 if (length == 0xFFFF || length == 0) { 590 hw_dbg(hw, "NVM PBA number section invalid length\n"); 591 return IXGBE_ERR_PBA_SECTION; 592 } 593 594 /* check if pba_num buffer is big enough */ 595 if (pba_num_size < (((u32)length * 2) - 1)) { 596 hw_dbg(hw, "PBA string buffer too small\n"); 597 return IXGBE_ERR_NO_SPACE; 598 } 599 600 /* trim pba length from start of string */ 601 pba_ptr++; 602 length--; 603 604 for (offset = 0; offset < length; offset++) { 605 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 606 if (ret_val) { 607 hw_dbg(hw, "NVM Read Error\n"); 608 return ret_val; 609 } 610 pba_num[offset * 2] = (u8)(data >> 8); 611 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 612 } 613 pba_num[offset * 2] = '\0'; 614 615 return 0; 616 } 617 618 /** 619 * ixgbe_get_mac_addr_generic - Generic get MAC address 620 * @hw: pointer to hardware structure 621 * @mac_addr: Adapter MAC address 622 * 623 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 624 * A reset of the adapter must be performed prior to calling this function 625 * in order for the MAC address to have been loaded from the EEPROM into RAR0 626 **/ 627 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 628 { 629 u32 rar_high; 630 u32 rar_low; 631 u16 i; 632 633 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 634 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 635 636 for (i = 0; i < 4; i++) 637 mac_addr[i] = (u8)(rar_low >> (i*8)); 638 639 for (i = 0; i < 2; i++) 640 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 641 642 return 0; 643 } 644 645 enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status) 646 { 647 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 648 case IXGBE_PCI_LINK_WIDTH_1: 649 return ixgbe_bus_width_pcie_x1; 650 case IXGBE_PCI_LINK_WIDTH_2: 651 return ixgbe_bus_width_pcie_x2; 652 case IXGBE_PCI_LINK_WIDTH_4: 653 return ixgbe_bus_width_pcie_x4; 654 case IXGBE_PCI_LINK_WIDTH_8: 655 return ixgbe_bus_width_pcie_x8; 656 default: 657 return ixgbe_bus_width_unknown; 658 } 659 } 660 661 enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status) 662 { 663 switch (link_status & IXGBE_PCI_LINK_SPEED) { 664 case IXGBE_PCI_LINK_SPEED_2500: 665 return ixgbe_bus_speed_2500; 666 case IXGBE_PCI_LINK_SPEED_5000: 667 return ixgbe_bus_speed_5000; 668 case IXGBE_PCI_LINK_SPEED_8000: 669 return ixgbe_bus_speed_8000; 670 default: 671 return ixgbe_bus_speed_unknown; 672 } 673 } 674 675 /** 676 * ixgbe_get_bus_info_generic - Generic set PCI bus info 677 * @hw: pointer to hardware structure 678 * 679 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 680 **/ 681 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 682 { 683 u16 link_status; 684 685 hw->bus.type = ixgbe_bus_type_pci_express; 686 687 /* Get the negotiated link width and speed from PCI config space */ 688 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS); 689 690 hw->bus.width = ixgbe_convert_bus_width(link_status); 691 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 692 693 hw->mac.ops.set_lan_id(hw); 694 695 return 0; 696 } 697 698 /** 699 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 700 * @hw: pointer to the HW structure 701 * 702 * Determines the LAN function id by reading memory-mapped registers 703 * and swaps the port value if requested. 704 **/ 705 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 706 { 707 struct ixgbe_bus_info *bus = &hw->bus; 708 u16 ee_ctrl_4; 709 u32 reg; 710 711 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 712 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 713 bus->lan_id = bus->func; 714 715 /* check for a port swap */ 716 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); 717 if (reg & IXGBE_FACTPS_LFS) 718 bus->func ^= 0x1; 719 720 /* Get MAC instance from EEPROM for configuring CS4227 */ 721 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { 722 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); 723 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> 724 IXGBE_EE_CTRL_4_INST_ID_SHIFT; 725 } 726 } 727 728 /** 729 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 730 * @hw: pointer to hardware structure 731 * 732 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 733 * disables transmit and receive units. The adapter_stopped flag is used by 734 * the shared code and drivers to determine if the adapter is in a stopped 735 * state and should not touch the hardware. 736 **/ 737 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 738 { 739 u32 reg_val; 740 u16 i; 741 742 /* 743 * Set the adapter_stopped flag so other driver functions stop touching 744 * the hardware 745 */ 746 hw->adapter_stopped = true; 747 748 /* Disable the receive unit */ 749 hw->mac.ops.disable_rx(hw); 750 751 /* Clear interrupt mask to stop interrupts from being generated */ 752 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 753 754 /* Clear any pending interrupts, flush previous writes */ 755 IXGBE_READ_REG(hw, IXGBE_EICR); 756 757 /* Disable the transmit unit. Each queue must be disabled. */ 758 for (i = 0; i < hw->mac.max_tx_queues; i++) 759 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 760 761 /* Disable the receive unit by stopping each queue */ 762 for (i = 0; i < hw->mac.max_rx_queues; i++) { 763 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 764 reg_val &= ~IXGBE_RXDCTL_ENABLE; 765 reg_val |= IXGBE_RXDCTL_SWFLSH; 766 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 767 } 768 769 /* flush all queues disables */ 770 IXGBE_WRITE_FLUSH(hw); 771 usleep_range(1000, 2000); 772 773 /* 774 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 775 * access and verify no pending requests 776 */ 777 return ixgbe_disable_pcie_master(hw); 778 } 779 780 /** 781 * ixgbe_init_led_link_act_generic - Store the LED index link/activity. 782 * @hw: pointer to hardware structure 783 * 784 * Store the index for the link active LED. This will be used to support 785 * blinking the LED. 786 **/ 787 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) 788 { 789 struct ixgbe_mac_info *mac = &hw->mac; 790 u32 led_reg, led_mode; 791 u16 i; 792 793 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 794 795 /* Get LED link active from the LEDCTL register */ 796 for (i = 0; i < 4; i++) { 797 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i); 798 799 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) == 800 IXGBE_LED_LINK_ACTIVE) { 801 mac->led_link_act = i; 802 return 0; 803 } 804 } 805 806 /* If LEDCTL register does not have the LED link active set, then use 807 * known MAC defaults. 808 */ 809 switch (hw->mac.type) { 810 case ixgbe_mac_x550em_a: 811 mac->led_link_act = 0; 812 break; 813 case ixgbe_mac_X550EM_x: 814 mac->led_link_act = 1; 815 break; 816 default: 817 mac->led_link_act = 2; 818 } 819 820 return 0; 821 } 822 823 /** 824 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 825 * @hw: pointer to hardware structure 826 * @index: led number to turn on 827 **/ 828 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 829 { 830 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 831 832 if (index > 3) 833 return IXGBE_ERR_PARAM; 834 835 /* To turn on the LED, set mode to ON. */ 836 led_reg &= ~IXGBE_LED_MODE_MASK(index); 837 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 838 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 839 IXGBE_WRITE_FLUSH(hw); 840 841 return 0; 842 } 843 844 /** 845 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 846 * @hw: pointer to hardware structure 847 * @index: led number to turn off 848 **/ 849 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 850 { 851 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 852 853 if (index > 3) 854 return IXGBE_ERR_PARAM; 855 856 /* To turn off the LED, set mode to OFF. */ 857 led_reg &= ~IXGBE_LED_MODE_MASK(index); 858 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 859 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 860 IXGBE_WRITE_FLUSH(hw); 861 862 return 0; 863 } 864 865 /** 866 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 867 * @hw: pointer to hardware structure 868 * 869 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 870 * ixgbe_hw struct in order to set up EEPROM access. 871 **/ 872 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 873 { 874 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 875 u32 eec; 876 u16 eeprom_size; 877 878 if (eeprom->type == ixgbe_eeprom_uninitialized) { 879 eeprom->type = ixgbe_eeprom_none; 880 /* Set default semaphore delay to 10ms which is a well 881 * tested value */ 882 eeprom->semaphore_delay = 10; 883 /* Clear EEPROM page size, it will be initialized as needed */ 884 eeprom->word_page_size = 0; 885 886 /* 887 * Check for EEPROM present first. 888 * If not present leave as none 889 */ 890 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 891 if (eec & IXGBE_EEC_PRES) { 892 eeprom->type = ixgbe_eeprom_spi; 893 894 /* 895 * SPI EEPROM is assumed here. This code would need to 896 * change if a future EEPROM is not SPI. 897 */ 898 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 899 IXGBE_EEC_SIZE_SHIFT); 900 eeprom->word_size = BIT(eeprom_size + 901 IXGBE_EEPROM_WORD_SIZE_SHIFT); 902 } 903 904 if (eec & IXGBE_EEC_ADDR_SIZE) 905 eeprom->address_bits = 16; 906 else 907 eeprom->address_bits = 8; 908 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n", 909 eeprom->type, eeprom->word_size, eeprom->address_bits); 910 } 911 912 return 0; 913 } 914 915 /** 916 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 917 * @hw: pointer to hardware structure 918 * @offset: offset within the EEPROM to write 919 * @words: number of words 920 * @data: 16 bit word(s) to write to EEPROM 921 * 922 * Reads 16 bit word(s) from EEPROM through bit-bang method 923 **/ 924 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 925 u16 words, u16 *data) 926 { 927 s32 status; 928 u16 i, count; 929 930 hw->eeprom.ops.init_params(hw); 931 932 if (words == 0) 933 return IXGBE_ERR_INVALID_ARGUMENT; 934 935 if (offset + words > hw->eeprom.word_size) 936 return IXGBE_ERR_EEPROM; 937 938 /* 939 * The EEPROM page size cannot be queried from the chip. We do lazy 940 * initialization. It is worth to do that when we write large buffer. 941 */ 942 if ((hw->eeprom.word_page_size == 0) && 943 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 944 ixgbe_detect_eeprom_page_size_generic(hw, offset); 945 946 /* 947 * We cannot hold synchronization semaphores for too long 948 * to avoid other entity starvation. However it is more efficient 949 * to read in bursts than synchronizing access for each word. 950 */ 951 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 952 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 953 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 954 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 955 count, &data[i]); 956 957 if (status != 0) 958 break; 959 } 960 961 return status; 962 } 963 964 /** 965 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 966 * @hw: pointer to hardware structure 967 * @offset: offset within the EEPROM to be written to 968 * @words: number of word(s) 969 * @data: 16 bit word(s) to be written to the EEPROM 970 * 971 * If ixgbe_eeprom_update_checksum is not called after this function, the 972 * EEPROM will most likely contain an invalid checksum. 973 **/ 974 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 975 u16 words, u16 *data) 976 { 977 s32 status; 978 u16 word; 979 u16 page_size; 980 u16 i; 981 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 982 983 /* Prepare the EEPROM for writing */ 984 status = ixgbe_acquire_eeprom(hw); 985 if (status) 986 return status; 987 988 if (ixgbe_ready_eeprom(hw) != 0) { 989 ixgbe_release_eeprom(hw); 990 return IXGBE_ERR_EEPROM; 991 } 992 993 for (i = 0; i < words; i++) { 994 ixgbe_standby_eeprom(hw); 995 996 /* Send the WRITE ENABLE command (8 bit opcode) */ 997 ixgbe_shift_out_eeprom_bits(hw, 998 IXGBE_EEPROM_WREN_OPCODE_SPI, 999 IXGBE_EEPROM_OPCODE_BITS); 1000 1001 ixgbe_standby_eeprom(hw); 1002 1003 /* Some SPI eeproms use the 8th address bit embedded 1004 * in the opcode 1005 */ 1006 if ((hw->eeprom.address_bits == 8) && 1007 ((offset + i) >= 128)) 1008 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1009 1010 /* Send the Write command (8-bit opcode + addr) */ 1011 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 1012 IXGBE_EEPROM_OPCODE_BITS); 1013 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1014 hw->eeprom.address_bits); 1015 1016 page_size = hw->eeprom.word_page_size; 1017 1018 /* Send the data in burst via SPI */ 1019 do { 1020 word = data[i]; 1021 word = (word >> 8) | (word << 8); 1022 ixgbe_shift_out_eeprom_bits(hw, word, 16); 1023 1024 if (page_size == 0) 1025 break; 1026 1027 /* do not wrap around page */ 1028 if (((offset + i) & (page_size - 1)) == 1029 (page_size - 1)) 1030 break; 1031 } while (++i < words); 1032 1033 ixgbe_standby_eeprom(hw); 1034 usleep_range(10000, 20000); 1035 } 1036 /* Done with writing - release the EEPROM */ 1037 ixgbe_release_eeprom(hw); 1038 1039 return 0; 1040 } 1041 1042 /** 1043 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1044 * @hw: pointer to hardware structure 1045 * @offset: offset within the EEPROM to be written to 1046 * @data: 16 bit word to be written to the EEPROM 1047 * 1048 * If ixgbe_eeprom_update_checksum is not called after this function, the 1049 * EEPROM will most likely contain an invalid checksum. 1050 **/ 1051 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1052 { 1053 hw->eeprom.ops.init_params(hw); 1054 1055 if (offset >= hw->eeprom.word_size) 1056 return IXGBE_ERR_EEPROM; 1057 1058 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1059 } 1060 1061 /** 1062 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1063 * @hw: pointer to hardware structure 1064 * @offset: offset within the EEPROM to be read 1065 * @words: number of word(s) 1066 * @data: read 16 bit words(s) from EEPROM 1067 * 1068 * Reads 16 bit word(s) from EEPROM through bit-bang method 1069 **/ 1070 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1071 u16 words, u16 *data) 1072 { 1073 s32 status; 1074 u16 i, count; 1075 1076 hw->eeprom.ops.init_params(hw); 1077 1078 if (words == 0) 1079 return IXGBE_ERR_INVALID_ARGUMENT; 1080 1081 if (offset + words > hw->eeprom.word_size) 1082 return IXGBE_ERR_EEPROM; 1083 1084 /* 1085 * We cannot hold synchronization semaphores for too long 1086 * to avoid other entity starvation. However it is more efficient 1087 * to read in bursts than synchronizing access for each word. 1088 */ 1089 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1090 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1091 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1092 1093 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1094 count, &data[i]); 1095 1096 if (status) 1097 return status; 1098 } 1099 1100 return 0; 1101 } 1102 1103 /** 1104 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1105 * @hw: pointer to hardware structure 1106 * @offset: offset within the EEPROM to be read 1107 * @words: number of word(s) 1108 * @data: read 16 bit word(s) from EEPROM 1109 * 1110 * Reads 16 bit word(s) from EEPROM through bit-bang method 1111 **/ 1112 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1113 u16 words, u16 *data) 1114 { 1115 s32 status; 1116 u16 word_in; 1117 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1118 u16 i; 1119 1120 /* Prepare the EEPROM for reading */ 1121 status = ixgbe_acquire_eeprom(hw); 1122 if (status) 1123 return status; 1124 1125 if (ixgbe_ready_eeprom(hw) != 0) { 1126 ixgbe_release_eeprom(hw); 1127 return IXGBE_ERR_EEPROM; 1128 } 1129 1130 for (i = 0; i < words; i++) { 1131 ixgbe_standby_eeprom(hw); 1132 /* Some SPI eeproms use the 8th address bit embedded 1133 * in the opcode 1134 */ 1135 if ((hw->eeprom.address_bits == 8) && 1136 ((offset + i) >= 128)) 1137 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1138 1139 /* Send the READ command (opcode + addr) */ 1140 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1141 IXGBE_EEPROM_OPCODE_BITS); 1142 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1143 hw->eeprom.address_bits); 1144 1145 /* Read the data. */ 1146 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1147 data[i] = (word_in >> 8) | (word_in << 8); 1148 } 1149 1150 /* End this read operation */ 1151 ixgbe_release_eeprom(hw); 1152 1153 return 0; 1154 } 1155 1156 /** 1157 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1158 * @hw: pointer to hardware structure 1159 * @offset: offset within the EEPROM to be read 1160 * @data: read 16 bit value from EEPROM 1161 * 1162 * Reads 16 bit value from EEPROM through bit-bang method 1163 **/ 1164 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1165 u16 *data) 1166 { 1167 hw->eeprom.ops.init_params(hw); 1168 1169 if (offset >= hw->eeprom.word_size) 1170 return IXGBE_ERR_EEPROM; 1171 1172 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1173 } 1174 1175 /** 1176 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1177 * @hw: pointer to hardware structure 1178 * @offset: offset of word in the EEPROM to read 1179 * @words: number of word(s) 1180 * @data: 16 bit word(s) from the EEPROM 1181 * 1182 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1183 **/ 1184 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1185 u16 words, u16 *data) 1186 { 1187 u32 eerd; 1188 s32 status; 1189 u32 i; 1190 1191 hw->eeprom.ops.init_params(hw); 1192 1193 if (words == 0) 1194 return IXGBE_ERR_INVALID_ARGUMENT; 1195 1196 if (offset >= hw->eeprom.word_size) 1197 return IXGBE_ERR_EEPROM; 1198 1199 for (i = 0; i < words; i++) { 1200 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1201 IXGBE_EEPROM_RW_REG_START; 1202 1203 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1204 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1205 1206 if (status == 0) { 1207 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1208 IXGBE_EEPROM_RW_REG_DATA); 1209 } else { 1210 hw_dbg(hw, "Eeprom read timed out\n"); 1211 return status; 1212 } 1213 } 1214 1215 return 0; 1216 } 1217 1218 /** 1219 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1220 * @hw: pointer to hardware structure 1221 * @offset: offset within the EEPROM to be used as a scratch pad 1222 * 1223 * Discover EEPROM page size by writing marching data at given offset. 1224 * This function is called only when we are writing a new large buffer 1225 * at given offset so the data would be overwritten anyway. 1226 **/ 1227 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1228 u16 offset) 1229 { 1230 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1231 s32 status; 1232 u16 i; 1233 1234 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1235 data[i] = i; 1236 1237 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1238 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1239 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1240 hw->eeprom.word_page_size = 0; 1241 if (status) 1242 return status; 1243 1244 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1245 if (status) 1246 return status; 1247 1248 /* 1249 * When writing in burst more than the actual page size 1250 * EEPROM address wraps around current page. 1251 */ 1252 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1253 1254 hw_dbg(hw, "Detected EEPROM page size = %d words.\n", 1255 hw->eeprom.word_page_size); 1256 return 0; 1257 } 1258 1259 /** 1260 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1261 * @hw: pointer to hardware structure 1262 * @offset: offset of word in the EEPROM to read 1263 * @data: word read from the EEPROM 1264 * 1265 * Reads a 16 bit word from the EEPROM using the EERD register. 1266 **/ 1267 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1268 { 1269 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1270 } 1271 1272 /** 1273 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1274 * @hw: pointer to hardware structure 1275 * @offset: offset of word in the EEPROM to write 1276 * @words: number of words 1277 * @data: word(s) write to the EEPROM 1278 * 1279 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1280 **/ 1281 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1282 u16 words, u16 *data) 1283 { 1284 u32 eewr; 1285 s32 status; 1286 u16 i; 1287 1288 hw->eeprom.ops.init_params(hw); 1289 1290 if (words == 0) 1291 return IXGBE_ERR_INVALID_ARGUMENT; 1292 1293 if (offset >= hw->eeprom.word_size) 1294 return IXGBE_ERR_EEPROM; 1295 1296 for (i = 0; i < words; i++) { 1297 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1298 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1299 IXGBE_EEPROM_RW_REG_START; 1300 1301 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1302 if (status) { 1303 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1304 return status; 1305 } 1306 1307 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1308 1309 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1310 if (status) { 1311 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1312 return status; 1313 } 1314 } 1315 1316 return 0; 1317 } 1318 1319 /** 1320 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1321 * @hw: pointer to hardware structure 1322 * @offset: offset of word in the EEPROM to write 1323 * @data: word write to the EEPROM 1324 * 1325 * Write a 16 bit word to the EEPROM using the EEWR register. 1326 **/ 1327 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1328 { 1329 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1330 } 1331 1332 /** 1333 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1334 * @hw: pointer to hardware structure 1335 * @ee_reg: EEPROM flag for polling 1336 * 1337 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1338 * read or write is done respectively. 1339 **/ 1340 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1341 { 1342 u32 i; 1343 u32 reg; 1344 1345 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1346 if (ee_reg == IXGBE_NVM_POLL_READ) 1347 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1348 else 1349 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1350 1351 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1352 return 0; 1353 } 1354 udelay(5); 1355 } 1356 return IXGBE_ERR_EEPROM; 1357 } 1358 1359 /** 1360 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1361 * @hw: pointer to hardware structure 1362 * 1363 * Prepares EEPROM for access using bit-bang method. This function should 1364 * be called before issuing a command to the EEPROM. 1365 **/ 1366 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1367 { 1368 u32 eec; 1369 u32 i; 1370 1371 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) 1372 return IXGBE_ERR_SWFW_SYNC; 1373 1374 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1375 1376 /* Request EEPROM Access */ 1377 eec |= IXGBE_EEC_REQ; 1378 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1379 1380 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1381 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1382 if (eec & IXGBE_EEC_GNT) 1383 break; 1384 udelay(5); 1385 } 1386 1387 /* Release if grant not acquired */ 1388 if (!(eec & IXGBE_EEC_GNT)) { 1389 eec &= ~IXGBE_EEC_REQ; 1390 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1391 hw_dbg(hw, "Could not acquire EEPROM grant\n"); 1392 1393 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1394 return IXGBE_ERR_EEPROM; 1395 } 1396 1397 /* Setup EEPROM for Read/Write */ 1398 /* Clear CS and SK */ 1399 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1400 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1401 IXGBE_WRITE_FLUSH(hw); 1402 udelay(1); 1403 return 0; 1404 } 1405 1406 /** 1407 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1408 * @hw: pointer to hardware structure 1409 * 1410 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1411 **/ 1412 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1413 { 1414 u32 timeout = 2000; 1415 u32 i; 1416 u32 swsm; 1417 1418 /* Get SMBI software semaphore between device drivers first */ 1419 for (i = 0; i < timeout; i++) { 1420 /* 1421 * If the SMBI bit is 0 when we read it, then the bit will be 1422 * set and we have the semaphore 1423 */ 1424 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1425 if (!(swsm & IXGBE_SWSM_SMBI)) 1426 break; 1427 usleep_range(50, 100); 1428 } 1429 1430 if (i == timeout) { 1431 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n"); 1432 /* this release is particularly important because our attempts 1433 * above to get the semaphore may have succeeded, and if there 1434 * was a timeout, we should unconditionally clear the semaphore 1435 * bits to free the driver to make progress 1436 */ 1437 ixgbe_release_eeprom_semaphore(hw); 1438 1439 usleep_range(50, 100); 1440 /* one last try 1441 * If the SMBI bit is 0 when we read it, then the bit will be 1442 * set and we have the semaphore 1443 */ 1444 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1445 if (swsm & IXGBE_SWSM_SMBI) { 1446 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n"); 1447 return IXGBE_ERR_EEPROM; 1448 } 1449 } 1450 1451 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1452 for (i = 0; i < timeout; i++) { 1453 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1454 1455 /* Set the SW EEPROM semaphore bit to request access */ 1456 swsm |= IXGBE_SWSM_SWESMBI; 1457 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); 1458 1459 /* If we set the bit successfully then we got the 1460 * semaphore. 1461 */ 1462 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1463 if (swsm & IXGBE_SWSM_SWESMBI) 1464 break; 1465 1466 usleep_range(50, 100); 1467 } 1468 1469 /* Release semaphores and return error if SW EEPROM semaphore 1470 * was not granted because we don't have access to the EEPROM 1471 */ 1472 if (i >= timeout) { 1473 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n"); 1474 ixgbe_release_eeprom_semaphore(hw); 1475 return IXGBE_ERR_EEPROM; 1476 } 1477 1478 return 0; 1479 } 1480 1481 /** 1482 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1483 * @hw: pointer to hardware structure 1484 * 1485 * This function clears hardware semaphore bits. 1486 **/ 1487 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1488 { 1489 u32 swsm; 1490 1491 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1492 1493 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1494 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1495 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); 1496 IXGBE_WRITE_FLUSH(hw); 1497 } 1498 1499 /** 1500 * ixgbe_ready_eeprom - Polls for EEPROM ready 1501 * @hw: pointer to hardware structure 1502 **/ 1503 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1504 { 1505 u16 i; 1506 u8 spi_stat_reg; 1507 1508 /* 1509 * Read "Status Register" repeatedly until the LSB is cleared. The 1510 * EEPROM will signal that the command has been completed by clearing 1511 * bit 0 of the internal status register. If it's not cleared within 1512 * 5 milliseconds, then error out. 1513 */ 1514 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 1515 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1516 IXGBE_EEPROM_OPCODE_BITS); 1517 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 1518 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 1519 break; 1520 1521 udelay(5); 1522 ixgbe_standby_eeprom(hw); 1523 } 1524 1525 /* 1526 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 1527 * devices (and only 0-5mSec on 5V devices) 1528 */ 1529 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 1530 hw_dbg(hw, "SPI EEPROM Status error\n"); 1531 return IXGBE_ERR_EEPROM; 1532 } 1533 1534 return 0; 1535 } 1536 1537 /** 1538 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 1539 * @hw: pointer to hardware structure 1540 **/ 1541 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 1542 { 1543 u32 eec; 1544 1545 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1546 1547 /* Toggle CS to flush commands */ 1548 eec |= IXGBE_EEC_CS; 1549 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1550 IXGBE_WRITE_FLUSH(hw); 1551 udelay(1); 1552 eec &= ~IXGBE_EEC_CS; 1553 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1554 IXGBE_WRITE_FLUSH(hw); 1555 udelay(1); 1556 } 1557 1558 /** 1559 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 1560 * @hw: pointer to hardware structure 1561 * @data: data to send to the EEPROM 1562 * @count: number of bits to shift out 1563 **/ 1564 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 1565 u16 count) 1566 { 1567 u32 eec; 1568 u32 mask; 1569 u32 i; 1570 1571 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1572 1573 /* 1574 * Mask is used to shift "count" bits of "data" out to the EEPROM 1575 * one bit at a time. Determine the starting bit based on count 1576 */ 1577 mask = BIT(count - 1); 1578 1579 for (i = 0; i < count; i++) { 1580 /* 1581 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 1582 * "1", and then raising and then lowering the clock (the SK 1583 * bit controls the clock input to the EEPROM). A "0" is 1584 * shifted out to the EEPROM by setting "DI" to "0" and then 1585 * raising and then lowering the clock. 1586 */ 1587 if (data & mask) 1588 eec |= IXGBE_EEC_DI; 1589 else 1590 eec &= ~IXGBE_EEC_DI; 1591 1592 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1593 IXGBE_WRITE_FLUSH(hw); 1594 1595 udelay(1); 1596 1597 ixgbe_raise_eeprom_clk(hw, &eec); 1598 ixgbe_lower_eeprom_clk(hw, &eec); 1599 1600 /* 1601 * Shift mask to signify next bit of data to shift in to the 1602 * EEPROM 1603 */ 1604 mask = mask >> 1; 1605 } 1606 1607 /* We leave the "DI" bit set to "0" when we leave this routine. */ 1608 eec &= ~IXGBE_EEC_DI; 1609 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1610 IXGBE_WRITE_FLUSH(hw); 1611 } 1612 1613 /** 1614 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 1615 * @hw: pointer to hardware structure 1616 * @count: number of bits to shift 1617 **/ 1618 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 1619 { 1620 u32 eec; 1621 u32 i; 1622 u16 data = 0; 1623 1624 /* 1625 * In order to read a register from the EEPROM, we need to shift 1626 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 1627 * the clock input to the EEPROM (setting the SK bit), and then reading 1628 * the value of the "DO" bit. During this "shifting in" process the 1629 * "DI" bit should always be clear. 1630 */ 1631 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1632 1633 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 1634 1635 for (i = 0; i < count; i++) { 1636 data = data << 1; 1637 ixgbe_raise_eeprom_clk(hw, &eec); 1638 1639 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1640 1641 eec &= ~(IXGBE_EEC_DI); 1642 if (eec & IXGBE_EEC_DO) 1643 data |= 1; 1644 1645 ixgbe_lower_eeprom_clk(hw, &eec); 1646 } 1647 1648 return data; 1649 } 1650 1651 /** 1652 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1653 * @hw: pointer to hardware structure 1654 * @eec: EEC register's current value 1655 **/ 1656 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1657 { 1658 /* 1659 * Raise the clock input to the EEPROM 1660 * (setting the SK bit), then delay 1661 */ 1662 *eec = *eec | IXGBE_EEC_SK; 1663 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); 1664 IXGBE_WRITE_FLUSH(hw); 1665 udelay(1); 1666 } 1667 1668 /** 1669 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1670 * @hw: pointer to hardware structure 1671 * @eec: EEC's current value 1672 **/ 1673 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1674 { 1675 /* 1676 * Lower the clock input to the EEPROM (clearing the SK bit), then 1677 * delay 1678 */ 1679 *eec = *eec & ~IXGBE_EEC_SK; 1680 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); 1681 IXGBE_WRITE_FLUSH(hw); 1682 udelay(1); 1683 } 1684 1685 /** 1686 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1687 * @hw: pointer to hardware structure 1688 **/ 1689 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 1690 { 1691 u32 eec; 1692 1693 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1694 1695 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1696 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1697 1698 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1699 IXGBE_WRITE_FLUSH(hw); 1700 1701 udelay(1); 1702 1703 /* Stop requesting EEPROM access */ 1704 eec &= ~IXGBE_EEC_REQ; 1705 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1706 1707 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1708 1709 /* 1710 * Delay before attempt to obtain semaphore again to allow FW 1711 * access. semaphore_delay is in ms we need us for usleep_range 1712 */ 1713 usleep_range(hw->eeprom.semaphore_delay * 1000, 1714 hw->eeprom.semaphore_delay * 2000); 1715 } 1716 1717 /** 1718 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 1719 * @hw: pointer to hardware structure 1720 **/ 1721 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 1722 { 1723 u16 i; 1724 u16 j; 1725 u16 checksum = 0; 1726 u16 length = 0; 1727 u16 pointer = 0; 1728 u16 word = 0; 1729 1730 /* Include 0x0-0x3F in the checksum */ 1731 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1732 if (hw->eeprom.ops.read(hw, i, &word)) { 1733 hw_dbg(hw, "EEPROM read failed\n"); 1734 break; 1735 } 1736 checksum += word; 1737 } 1738 1739 /* Include all data from pointers except for the fw pointer */ 1740 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1741 if (hw->eeprom.ops.read(hw, i, &pointer)) { 1742 hw_dbg(hw, "EEPROM read failed\n"); 1743 return IXGBE_ERR_EEPROM; 1744 } 1745 1746 /* If the pointer seems invalid */ 1747 if (pointer == 0xFFFF || pointer == 0) 1748 continue; 1749 1750 if (hw->eeprom.ops.read(hw, pointer, &length)) { 1751 hw_dbg(hw, "EEPROM read failed\n"); 1752 return IXGBE_ERR_EEPROM; 1753 } 1754 1755 if (length == 0xFFFF || length == 0) 1756 continue; 1757 1758 for (j = pointer + 1; j <= pointer + length; j++) { 1759 if (hw->eeprom.ops.read(hw, j, &word)) { 1760 hw_dbg(hw, "EEPROM read failed\n"); 1761 return IXGBE_ERR_EEPROM; 1762 } 1763 checksum += word; 1764 } 1765 } 1766 1767 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1768 1769 return (s32)checksum; 1770 } 1771 1772 /** 1773 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1774 * @hw: pointer to hardware structure 1775 * @checksum_val: calculated checksum 1776 * 1777 * Performs checksum calculation and validates the EEPROM checksum. If the 1778 * caller does not need checksum_val, the value can be NULL. 1779 **/ 1780 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1781 u16 *checksum_val) 1782 { 1783 s32 status; 1784 u16 checksum; 1785 u16 read_checksum = 0; 1786 1787 /* 1788 * Read the first word from the EEPROM. If this times out or fails, do 1789 * not continue or we could be in for a very long wait while every 1790 * EEPROM read fails 1791 */ 1792 status = hw->eeprom.ops.read(hw, 0, &checksum); 1793 if (status) { 1794 hw_dbg(hw, "EEPROM read failed\n"); 1795 return status; 1796 } 1797 1798 status = hw->eeprom.ops.calc_checksum(hw); 1799 if (status < 0) 1800 return status; 1801 1802 checksum = (u16)(status & 0xffff); 1803 1804 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1805 if (status) { 1806 hw_dbg(hw, "EEPROM read failed\n"); 1807 return status; 1808 } 1809 1810 /* Verify read checksum from EEPROM is the same as 1811 * calculated checksum 1812 */ 1813 if (read_checksum != checksum) 1814 status = IXGBE_ERR_EEPROM_CHECKSUM; 1815 1816 /* If the user cares, return the calculated checksum */ 1817 if (checksum_val) 1818 *checksum_val = checksum; 1819 1820 return status; 1821 } 1822 1823 /** 1824 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1825 * @hw: pointer to hardware structure 1826 **/ 1827 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1828 { 1829 s32 status; 1830 u16 checksum; 1831 1832 /* 1833 * Read the first word from the EEPROM. If this times out or fails, do 1834 * not continue or we could be in for a very long wait while every 1835 * EEPROM read fails 1836 */ 1837 status = hw->eeprom.ops.read(hw, 0, &checksum); 1838 if (status) { 1839 hw_dbg(hw, "EEPROM read failed\n"); 1840 return status; 1841 } 1842 1843 status = hw->eeprom.ops.calc_checksum(hw); 1844 if (status < 0) 1845 return status; 1846 1847 checksum = (u16)(status & 0xffff); 1848 1849 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 1850 1851 return status; 1852 } 1853 1854 /** 1855 * ixgbe_set_rar_generic - Set Rx address register 1856 * @hw: pointer to hardware structure 1857 * @index: Receive address register to write 1858 * @addr: Address to put into receive address register 1859 * @vmdq: VMDq "set" or "pool" index 1860 * @enable_addr: set flag that address is active 1861 * 1862 * Puts an ethernet address into a receive address register. 1863 **/ 1864 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1865 u32 enable_addr) 1866 { 1867 u32 rar_low, rar_high; 1868 u32 rar_entries = hw->mac.num_rar_entries; 1869 1870 /* Make sure we are using a valid rar index range */ 1871 if (index >= rar_entries) { 1872 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1873 return IXGBE_ERR_INVALID_ARGUMENT; 1874 } 1875 1876 /* setup VMDq pool selection before this RAR gets enabled */ 1877 hw->mac.ops.set_vmdq(hw, index, vmdq); 1878 1879 /* 1880 * HW expects these in little endian so we reverse the byte 1881 * order from network order (big endian) to little endian 1882 */ 1883 rar_low = ((u32)addr[0] | 1884 ((u32)addr[1] << 8) | 1885 ((u32)addr[2] << 16) | 1886 ((u32)addr[3] << 24)); 1887 /* 1888 * Some parts put the VMDq setting in the extra RAH bits, 1889 * so save everything except the lower 16 bits that hold part 1890 * of the address and the address valid bit. 1891 */ 1892 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1893 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1894 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1895 1896 if (enable_addr != 0) 1897 rar_high |= IXGBE_RAH_AV; 1898 1899 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1900 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1901 1902 return 0; 1903 } 1904 1905 /** 1906 * ixgbe_clear_rar_generic - Remove Rx address register 1907 * @hw: pointer to hardware structure 1908 * @index: Receive address register to write 1909 * 1910 * Clears an ethernet address from a receive address register. 1911 **/ 1912 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1913 { 1914 u32 rar_high; 1915 u32 rar_entries = hw->mac.num_rar_entries; 1916 1917 /* Make sure we are using a valid rar index range */ 1918 if (index >= rar_entries) { 1919 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1920 return IXGBE_ERR_INVALID_ARGUMENT; 1921 } 1922 1923 /* 1924 * Some parts put the VMDq setting in the extra RAH bits, 1925 * so save everything except the lower 16 bits that hold part 1926 * of the address and the address valid bit. 1927 */ 1928 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1929 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1930 1931 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1932 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1933 1934 /* clear VMDq pool/queue selection for this RAR */ 1935 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1936 1937 return 0; 1938 } 1939 1940 /** 1941 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1942 * @hw: pointer to hardware structure 1943 * 1944 * Places the MAC address in receive address register 0 and clears the rest 1945 * of the receive address registers. Clears the multicast table. Assumes 1946 * the receiver is in reset when the routine is called. 1947 **/ 1948 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1949 { 1950 u32 i; 1951 u32 rar_entries = hw->mac.num_rar_entries; 1952 1953 /* 1954 * If the current mac address is valid, assume it is a software override 1955 * to the permanent address. 1956 * Otherwise, use the permanent address from the eeprom. 1957 */ 1958 if (!is_valid_ether_addr(hw->mac.addr)) { 1959 /* Get the MAC address from the RAR0 for later reference */ 1960 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1961 1962 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr); 1963 } else { 1964 /* Setup the receive address. */ 1965 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); 1966 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr); 1967 1968 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1969 } 1970 1971 /* clear VMDq pool/queue selection for RAR 0 */ 1972 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 1973 1974 hw->addr_ctrl.overflow_promisc = 0; 1975 1976 hw->addr_ctrl.rar_used_count = 1; 1977 1978 /* Zero out the other receive addresses. */ 1979 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); 1980 for (i = 1; i < rar_entries; i++) { 1981 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1982 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1983 } 1984 1985 /* Clear the MTA */ 1986 hw->addr_ctrl.mta_in_use = 0; 1987 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1988 1989 hw_dbg(hw, " Clearing MTA\n"); 1990 for (i = 0; i < hw->mac.mcft_size; i++) 1991 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1992 1993 if (hw->mac.ops.init_uta_tables) 1994 hw->mac.ops.init_uta_tables(hw); 1995 1996 return 0; 1997 } 1998 1999 /** 2000 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 2001 * @hw: pointer to hardware structure 2002 * @mc_addr: the multicast address 2003 * 2004 * Extracts the 12 bits, from a multicast address, to determine which 2005 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 2006 * incoming rx multicast addresses, to determine the bit-vector to check in 2007 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 2008 * by the MO field of the MCSTCTRL. The MO field is set during initialization 2009 * to mc_filter_type. 2010 **/ 2011 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 2012 { 2013 u32 vector = 0; 2014 2015 switch (hw->mac.mc_filter_type) { 2016 case 0: /* use bits [47:36] of the address */ 2017 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 2018 break; 2019 case 1: /* use bits [46:35] of the address */ 2020 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 2021 break; 2022 case 2: /* use bits [45:34] of the address */ 2023 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 2024 break; 2025 case 3: /* use bits [43:32] of the address */ 2026 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 2027 break; 2028 default: /* Invalid mc_filter_type */ 2029 hw_dbg(hw, "MC filter type param set incorrectly\n"); 2030 break; 2031 } 2032 2033 /* vector can only be 12-bits or boundary will be exceeded */ 2034 vector &= 0xFFF; 2035 return vector; 2036 } 2037 2038 /** 2039 * ixgbe_set_mta - Set bit-vector in multicast table 2040 * @hw: pointer to hardware structure 2041 * @mc_addr: Multicast address 2042 * 2043 * Sets the bit-vector in the multicast table. 2044 **/ 2045 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2046 { 2047 u32 vector; 2048 u32 vector_bit; 2049 u32 vector_reg; 2050 2051 hw->addr_ctrl.mta_in_use++; 2052 2053 vector = ixgbe_mta_vector(hw, mc_addr); 2054 hw_dbg(hw, " bit-vector = 0x%03X\n", vector); 2055 2056 /* 2057 * The MTA is a register array of 128 32-bit registers. It is treated 2058 * like an array of 4096 bits. We want to set bit 2059 * BitArray[vector_value]. So we figure out what register the bit is 2060 * in, read it, OR in the new bit, then write back the new value. The 2061 * register is determined by the upper 7 bits of the vector value and 2062 * the bit within that register are determined by the lower 5 bits of 2063 * the value. 2064 */ 2065 vector_reg = (vector >> 5) & 0x7F; 2066 vector_bit = vector & 0x1F; 2067 hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit); 2068 } 2069 2070 /** 2071 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2072 * @hw: pointer to hardware structure 2073 * @netdev: pointer to net device structure 2074 * 2075 * The given list replaces any existing list. Clears the MC addrs from receive 2076 * address registers and the multicast table. Uses unused receive address 2077 * registers for the first multicast addresses, and hashes the rest into the 2078 * multicast table. 2079 **/ 2080 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, 2081 struct net_device *netdev) 2082 { 2083 struct netdev_hw_addr *ha; 2084 u32 i; 2085 2086 /* 2087 * Set the new number of MC addresses that we are being requested to 2088 * use. 2089 */ 2090 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); 2091 hw->addr_ctrl.mta_in_use = 0; 2092 2093 /* Clear mta_shadow */ 2094 hw_dbg(hw, " Clearing MTA\n"); 2095 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2096 2097 /* Update mta shadow */ 2098 netdev_for_each_mc_addr(ha, netdev) { 2099 hw_dbg(hw, " Adding the multicast addresses:\n"); 2100 ixgbe_set_mta(hw, ha->addr); 2101 } 2102 2103 /* Enable mta */ 2104 for (i = 0; i < hw->mac.mcft_size; i++) 2105 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2106 hw->mac.mta_shadow[i]); 2107 2108 if (hw->addr_ctrl.mta_in_use > 0) 2109 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2110 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2111 2112 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); 2113 return 0; 2114 } 2115 2116 /** 2117 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2118 * @hw: pointer to hardware structure 2119 * 2120 * Enables multicast address in RAR and the use of the multicast hash table. 2121 **/ 2122 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2123 { 2124 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2125 2126 if (a->mta_in_use > 0) 2127 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2128 hw->mac.mc_filter_type); 2129 2130 return 0; 2131 } 2132 2133 /** 2134 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2135 * @hw: pointer to hardware structure 2136 * 2137 * Disables multicast address in RAR and the use of the multicast hash table. 2138 **/ 2139 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2140 { 2141 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2142 2143 if (a->mta_in_use > 0) 2144 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2145 2146 return 0; 2147 } 2148 2149 /** 2150 * ixgbe_fc_enable_generic - Enable flow control 2151 * @hw: pointer to hardware structure 2152 * 2153 * Enable flow control according to the current settings. 2154 **/ 2155 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2156 { 2157 u32 mflcn_reg, fccfg_reg; 2158 u32 reg; 2159 u32 fcrtl, fcrth; 2160 int i; 2161 2162 /* Validate the water mark configuration. */ 2163 if (!hw->fc.pause_time) 2164 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2165 2166 /* Low water mark of zero causes XOFF floods */ 2167 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 2168 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2169 hw->fc.high_water[i]) { 2170 if (!hw->fc.low_water[i] || 2171 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2172 hw_dbg(hw, "Invalid water mark configuration\n"); 2173 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2174 } 2175 } 2176 } 2177 2178 /* Negotiate the fc mode to use */ 2179 hw->mac.ops.fc_autoneg(hw); 2180 2181 /* Disable any previous flow control settings */ 2182 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2183 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2184 2185 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2186 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2187 2188 /* 2189 * The possible values of fc.current_mode are: 2190 * 0: Flow control is completely disabled 2191 * 1: Rx flow control is enabled (we can receive pause frames, 2192 * but not send pause frames). 2193 * 2: Tx flow control is enabled (we can send pause frames but 2194 * we do not support receiving pause frames). 2195 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2196 * other: Invalid. 2197 */ 2198 switch (hw->fc.current_mode) { 2199 case ixgbe_fc_none: 2200 /* 2201 * Flow control is disabled by software override or autoneg. 2202 * The code below will actually disable it in the HW. 2203 */ 2204 break; 2205 case ixgbe_fc_rx_pause: 2206 /* 2207 * Rx Flow control is enabled and Tx Flow control is 2208 * disabled by software override. Since there really 2209 * isn't a way to advertise that we are capable of RX 2210 * Pause ONLY, we will advertise that we support both 2211 * symmetric and asymmetric Rx PAUSE. Later, we will 2212 * disable the adapter's ability to send PAUSE frames. 2213 */ 2214 mflcn_reg |= IXGBE_MFLCN_RFCE; 2215 break; 2216 case ixgbe_fc_tx_pause: 2217 /* 2218 * Tx Flow control is enabled, and Rx Flow control is 2219 * disabled by software override. 2220 */ 2221 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2222 break; 2223 case ixgbe_fc_full: 2224 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2225 mflcn_reg |= IXGBE_MFLCN_RFCE; 2226 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2227 break; 2228 default: 2229 hw_dbg(hw, "Flow control param set incorrectly\n"); 2230 return IXGBE_ERR_CONFIG; 2231 } 2232 2233 /* Set 802.3x based flow control settings. */ 2234 mflcn_reg |= IXGBE_MFLCN_DPF; 2235 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2236 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2237 2238 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2239 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 2240 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2241 hw->fc.high_water[i]) { 2242 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2243 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2244 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2245 } else { 2246 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2247 /* 2248 * In order to prevent Tx hangs when the internal Tx 2249 * switch is enabled we must set the high water mark 2250 * to the Rx packet buffer size - 24KB. This allows 2251 * the Tx switch to function even under heavy Rx 2252 * workloads. 2253 */ 2254 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2255 } 2256 2257 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2258 } 2259 2260 /* Configure pause time (2 TCs per register) */ 2261 reg = hw->fc.pause_time * 0x00010001; 2262 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 2263 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2264 2265 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2266 2267 return 0; 2268 } 2269 2270 /** 2271 * ixgbe_negotiate_fc - Negotiate flow control 2272 * @hw: pointer to hardware structure 2273 * @adv_reg: flow control advertised settings 2274 * @lp_reg: link partner's flow control settings 2275 * @adv_sym: symmetric pause bit in advertisement 2276 * @adv_asm: asymmetric pause bit in advertisement 2277 * @lp_sym: symmetric pause bit in link partner advertisement 2278 * @lp_asm: asymmetric pause bit in link partner advertisement 2279 * 2280 * Find the intersection between advertised settings and link partner's 2281 * advertised settings 2282 **/ 2283 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2284 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2285 { 2286 if ((!(adv_reg)) || (!(lp_reg))) 2287 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2288 2289 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2290 /* 2291 * Now we need to check if the user selected Rx ONLY 2292 * of pause frames. In this case, we had to advertise 2293 * FULL flow control because we could not advertise RX 2294 * ONLY. Hence, we must now check to see if we need to 2295 * turn OFF the TRANSMISSION of PAUSE frames. 2296 */ 2297 if (hw->fc.requested_mode == ixgbe_fc_full) { 2298 hw->fc.current_mode = ixgbe_fc_full; 2299 hw_dbg(hw, "Flow Control = FULL.\n"); 2300 } else { 2301 hw->fc.current_mode = ixgbe_fc_rx_pause; 2302 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n"); 2303 } 2304 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2305 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2306 hw->fc.current_mode = ixgbe_fc_tx_pause; 2307 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); 2308 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2309 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2310 hw->fc.current_mode = ixgbe_fc_rx_pause; 2311 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); 2312 } else { 2313 hw->fc.current_mode = ixgbe_fc_none; 2314 hw_dbg(hw, "Flow Control = NONE.\n"); 2315 } 2316 return 0; 2317 } 2318 2319 /** 2320 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 2321 * @hw: pointer to hardware structure 2322 * 2323 * Enable flow control according on 1 gig fiber. 2324 **/ 2325 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 2326 { 2327 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 2328 s32 ret_val; 2329 2330 /* 2331 * On multispeed fiber at 1g, bail out if 2332 * - link is up but AN did not complete, or if 2333 * - link is up and AN completed but timed out 2334 */ 2335 2336 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 2337 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 2338 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) 2339 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2340 2341 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2342 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 2343 2344 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 2345 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 2346 IXGBE_PCS1GANA_ASM_PAUSE, 2347 IXGBE_PCS1GANA_SYM_PAUSE, 2348 IXGBE_PCS1GANA_ASM_PAUSE); 2349 2350 return ret_val; 2351 } 2352 2353 /** 2354 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 2355 * @hw: pointer to hardware structure 2356 * 2357 * Enable flow control according to IEEE clause 37. 2358 **/ 2359 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 2360 { 2361 u32 links2, anlp1_reg, autoc_reg, links; 2362 s32 ret_val; 2363 2364 /* 2365 * On backplane, bail out if 2366 * - backplane autoneg was not completed, or if 2367 * - we are 82599 and link partner is not AN enabled 2368 */ 2369 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 2370 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) 2371 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2372 2373 if (hw->mac.type == ixgbe_mac_82599EB) { 2374 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 2375 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) 2376 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2377 } 2378 /* 2379 * Read the 10g AN autoc and LP ability registers and resolve 2380 * local flow control settings accordingly 2381 */ 2382 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2383 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2384 2385 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 2386 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 2387 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 2388 2389 return ret_val; 2390 } 2391 2392 /** 2393 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 2394 * @hw: pointer to hardware structure 2395 * 2396 * Enable flow control according to IEEE clause 37. 2397 **/ 2398 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 2399 { 2400 u16 technology_ability_reg = 0; 2401 u16 lp_technology_ability_reg = 0; 2402 2403 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 2404 MDIO_MMD_AN, 2405 &technology_ability_reg); 2406 hw->phy.ops.read_reg(hw, MDIO_AN_LPA, 2407 MDIO_MMD_AN, 2408 &lp_technology_ability_reg); 2409 2410 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 2411 (u32)lp_technology_ability_reg, 2412 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 2413 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 2414 } 2415 2416 /** 2417 * ixgbe_fc_autoneg - Configure flow control 2418 * @hw: pointer to hardware structure 2419 * 2420 * Compares our advertised flow control capabilities to those advertised by 2421 * our link partner, and determines the proper flow control mode to use. 2422 **/ 2423 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 2424 { 2425 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2426 ixgbe_link_speed speed; 2427 bool link_up; 2428 2429 /* 2430 * AN should have completed when the cable was plugged in. 2431 * Look for reasons to bail out. Bail out if: 2432 * - FC autoneg is disabled, or if 2433 * - link is not up. 2434 * 2435 * Since we're being called from an LSC, link is already known to be up. 2436 * So use link_up_wait_to_complete=false. 2437 */ 2438 if (hw->fc.disable_fc_autoneg) 2439 goto out; 2440 2441 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2442 if (!link_up) 2443 goto out; 2444 2445 switch (hw->phy.media_type) { 2446 /* Autoneg flow control on fiber adapters */ 2447 case ixgbe_media_type_fiber: 2448 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 2449 ret_val = ixgbe_fc_autoneg_fiber(hw); 2450 break; 2451 2452 /* Autoneg flow control on backplane adapters */ 2453 case ixgbe_media_type_backplane: 2454 ret_val = ixgbe_fc_autoneg_backplane(hw); 2455 break; 2456 2457 /* Autoneg flow control on copper adapters */ 2458 case ixgbe_media_type_copper: 2459 if (ixgbe_device_supports_autoneg_fc(hw)) 2460 ret_val = ixgbe_fc_autoneg_copper(hw); 2461 break; 2462 2463 default: 2464 break; 2465 } 2466 2467 out: 2468 if (ret_val == 0) { 2469 hw->fc.fc_was_autonegged = true; 2470 } else { 2471 hw->fc.fc_was_autonegged = false; 2472 hw->fc.current_mode = hw->fc.requested_mode; 2473 } 2474 } 2475 2476 /** 2477 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 2478 * @hw: pointer to hardware structure 2479 * 2480 * System-wide timeout range is encoded in PCIe Device Control2 register. 2481 * 2482 * Add 10% to specified maximum and return the number of times to poll for 2483 * completion timeout, in units of 100 microsec. Never return less than 2484 * 800 = 80 millisec. 2485 **/ 2486 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 2487 { 2488 s16 devctl2; 2489 u32 pollcnt; 2490 2491 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); 2492 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 2493 2494 switch (devctl2) { 2495 case IXGBE_PCIDEVCTRL2_65_130ms: 2496 pollcnt = 1300; /* 130 millisec */ 2497 break; 2498 case IXGBE_PCIDEVCTRL2_260_520ms: 2499 pollcnt = 5200; /* 520 millisec */ 2500 break; 2501 case IXGBE_PCIDEVCTRL2_1_2s: 2502 pollcnt = 20000; /* 2 sec */ 2503 break; 2504 case IXGBE_PCIDEVCTRL2_4_8s: 2505 pollcnt = 80000; /* 8 sec */ 2506 break; 2507 case IXGBE_PCIDEVCTRL2_17_34s: 2508 pollcnt = 34000; /* 34 sec */ 2509 break; 2510 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 2511 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 2512 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 2513 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 2514 default: 2515 pollcnt = 800; /* 80 millisec minimum */ 2516 break; 2517 } 2518 2519 /* add 10% to spec maximum */ 2520 return (pollcnt * 11) / 10; 2521 } 2522 2523 /** 2524 * ixgbe_disable_pcie_master - Disable PCI-express master access 2525 * @hw: pointer to hardware structure 2526 * 2527 * Disables PCI-Express master access and verifies there are no pending 2528 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 2529 * bit hasn't caused the master requests to be disabled, else 0 2530 * is returned signifying master requests disabled. 2531 **/ 2532 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 2533 { 2534 u32 i, poll; 2535 u16 value; 2536 2537 /* Always set this bit to ensure any future transactions are blocked */ 2538 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 2539 2540 /* Poll for bit to read as set */ 2541 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2542 if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS) 2543 break; 2544 usleep_range(100, 120); 2545 } 2546 if (i >= IXGBE_PCI_MASTER_DISABLE_TIMEOUT) { 2547 hw_dbg(hw, "GIO disable did not set - requesting resets\n"); 2548 goto gio_disable_fail; 2549 } 2550 2551 /* Exit if master requests are blocked */ 2552 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 2553 ixgbe_removed(hw->hw_addr)) 2554 return 0; 2555 2556 /* Poll for master request bit to clear */ 2557 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2558 udelay(100); 2559 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2560 return 0; 2561 } 2562 2563 /* 2564 * Two consecutive resets are required via CTRL.RST per datasheet 2565 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 2566 * of this need. The first reset prevents new master requests from 2567 * being issued by our device. We then must wait 1usec or more for any 2568 * remaining completions from the PCIe bus to trickle in, and then reset 2569 * again to clear out any effects they may have had on our device. 2570 */ 2571 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n"); 2572 gio_disable_fail: 2573 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2574 2575 if (hw->mac.type >= ixgbe_mac_X550) 2576 return 0; 2577 2578 /* 2579 * Before proceeding, make sure that the PCIe block does not have 2580 * transactions pending. 2581 */ 2582 poll = ixgbe_pcie_timeout_poll(hw); 2583 for (i = 0; i < poll; i++) { 2584 udelay(100); 2585 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); 2586 if (ixgbe_removed(hw->hw_addr)) 2587 return 0; 2588 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 2589 return 0; 2590 } 2591 2592 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n"); 2593 return IXGBE_ERR_MASTER_REQUESTS_PENDING; 2594 } 2595 2596 /** 2597 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 2598 * @hw: pointer to hardware structure 2599 * @mask: Mask to specify which semaphore to acquire 2600 * 2601 * Acquires the SWFW semaphore through the GSSR register for the specified 2602 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2603 **/ 2604 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 2605 { 2606 u32 gssr = 0; 2607 u32 swmask = mask; 2608 u32 fwmask = mask << 5; 2609 u32 timeout = 200; 2610 u32 i; 2611 2612 for (i = 0; i < timeout; i++) { 2613 /* 2614 * SW NVM semaphore bit is used for access to all 2615 * SW_FW_SYNC bits (not just NVM) 2616 */ 2617 if (ixgbe_get_eeprom_semaphore(hw)) 2618 return IXGBE_ERR_SWFW_SYNC; 2619 2620 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2621 if (!(gssr & (fwmask | swmask))) { 2622 gssr |= swmask; 2623 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2624 ixgbe_release_eeprom_semaphore(hw); 2625 return 0; 2626 } else { 2627 /* Resource is currently in use by FW or SW */ 2628 ixgbe_release_eeprom_semaphore(hw); 2629 usleep_range(5000, 10000); 2630 } 2631 } 2632 2633 /* If time expired clear the bits holding the lock and retry */ 2634 if (gssr & (fwmask | swmask)) 2635 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 2636 2637 usleep_range(5000, 10000); 2638 return IXGBE_ERR_SWFW_SYNC; 2639 } 2640 2641 /** 2642 * ixgbe_release_swfw_sync - Release SWFW semaphore 2643 * @hw: pointer to hardware structure 2644 * @mask: Mask to specify which semaphore to release 2645 * 2646 * Releases the SWFW semaphore through the GSSR register for the specified 2647 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2648 **/ 2649 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 2650 { 2651 u32 gssr; 2652 u32 swmask = mask; 2653 2654 ixgbe_get_eeprom_semaphore(hw); 2655 2656 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2657 gssr &= ~swmask; 2658 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2659 2660 ixgbe_release_eeprom_semaphore(hw); 2661 } 2662 2663 /** 2664 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 2665 * @hw: pointer to hardware structure 2666 * @reg_val: Value we read from AUTOC 2667 * @locked: bool to indicate whether the SW/FW lock should be taken. Never 2668 * true in this the generic case. 2669 * 2670 * The default case requires no protection so just to the register read. 2671 **/ 2672 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 2673 { 2674 *locked = false; 2675 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2676 return 0; 2677 } 2678 2679 /** 2680 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 2681 * @hw: pointer to hardware structure 2682 * @reg_val: value to write to AUTOC 2683 * @locked: bool to indicate whether the SW/FW lock was already taken by 2684 * previous read. 2685 **/ 2686 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 2687 { 2688 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 2689 return 0; 2690 } 2691 2692 /** 2693 * ixgbe_disable_rx_buff_generic - Stops the receive data path 2694 * @hw: pointer to hardware structure 2695 * 2696 * Stops the receive data path and waits for the HW to internally 2697 * empty the Rx security block. 2698 **/ 2699 s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw) 2700 { 2701 #define IXGBE_MAX_SECRX_POLL 40 2702 int i; 2703 int secrxreg; 2704 2705 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2706 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 2707 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2708 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 2709 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 2710 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 2711 break; 2712 else 2713 /* Use interrupt-safe sleep just in case */ 2714 udelay(1000); 2715 } 2716 2717 /* For informational purposes only */ 2718 if (i >= IXGBE_MAX_SECRX_POLL) 2719 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n"); 2720 2721 return 0; 2722 2723 } 2724 2725 /** 2726 * ixgbe_enable_rx_buff - Enables the receive data path 2727 * @hw: pointer to hardware structure 2728 * 2729 * Enables the receive data path 2730 **/ 2731 s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw) 2732 { 2733 u32 secrxreg; 2734 2735 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2736 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 2737 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2738 IXGBE_WRITE_FLUSH(hw); 2739 2740 return 0; 2741 } 2742 2743 /** 2744 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 2745 * @hw: pointer to hardware structure 2746 * @regval: register value to write to RXCTRL 2747 * 2748 * Enables the Rx DMA unit 2749 **/ 2750 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 2751 { 2752 if (regval & IXGBE_RXCTRL_RXEN) 2753 hw->mac.ops.enable_rx(hw); 2754 else 2755 hw->mac.ops.disable_rx(hw); 2756 2757 return 0; 2758 } 2759 2760 /** 2761 * ixgbe_blink_led_start_generic - Blink LED based on index. 2762 * @hw: pointer to hardware structure 2763 * @index: led number to blink 2764 **/ 2765 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 2766 { 2767 ixgbe_link_speed speed = 0; 2768 bool link_up = false; 2769 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2770 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2771 bool locked = false; 2772 s32 ret_val; 2773 2774 if (index > 3) 2775 return IXGBE_ERR_PARAM; 2776 2777 /* 2778 * Link must be up to auto-blink the LEDs; 2779 * Force it if link is down. 2780 */ 2781 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2782 2783 if (!link_up) { 2784 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 2785 if (ret_val) 2786 return ret_val; 2787 2788 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2789 autoc_reg |= IXGBE_AUTOC_FLU; 2790 2791 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 2792 if (ret_val) 2793 return ret_val; 2794 2795 IXGBE_WRITE_FLUSH(hw); 2796 2797 usleep_range(10000, 20000); 2798 } 2799 2800 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2801 led_reg |= IXGBE_LED_BLINK(index); 2802 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2803 IXGBE_WRITE_FLUSH(hw); 2804 2805 return 0; 2806 } 2807 2808 /** 2809 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 2810 * @hw: pointer to hardware structure 2811 * @index: led number to stop blinking 2812 **/ 2813 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 2814 { 2815 u32 autoc_reg = 0; 2816 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2817 bool locked = false; 2818 s32 ret_val; 2819 2820 if (index > 3) 2821 return IXGBE_ERR_PARAM; 2822 2823 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 2824 if (ret_val) 2825 return ret_val; 2826 2827 autoc_reg &= ~IXGBE_AUTOC_FLU; 2828 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2829 2830 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 2831 if (ret_val) 2832 return ret_val; 2833 2834 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2835 led_reg &= ~IXGBE_LED_BLINK(index); 2836 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 2837 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2838 IXGBE_WRITE_FLUSH(hw); 2839 2840 return 0; 2841 } 2842 2843 /** 2844 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 2845 * @hw: pointer to hardware structure 2846 * @san_mac_offset: SAN MAC address offset 2847 * 2848 * This function will read the EEPROM location for the SAN MAC address 2849 * pointer, and returns the value at that location. This is used in both 2850 * get and set mac_addr routines. 2851 **/ 2852 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 2853 u16 *san_mac_offset) 2854 { 2855 s32 ret_val; 2856 2857 /* 2858 * First read the EEPROM pointer to see if the MAC addresses are 2859 * available. 2860 */ 2861 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 2862 san_mac_offset); 2863 if (ret_val) 2864 hw_err(hw, "eeprom read at offset %d failed\n", 2865 IXGBE_SAN_MAC_ADDR_PTR); 2866 2867 return ret_val; 2868 } 2869 2870 /** 2871 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 2872 * @hw: pointer to hardware structure 2873 * @san_mac_addr: SAN MAC address 2874 * 2875 * Reads the SAN MAC address from the EEPROM, if it's available. This is 2876 * per-port, so set_lan_id() must be called before reading the addresses. 2877 * set_lan_id() is called by identify_sfp(), but this cannot be relied 2878 * upon for non-SFP connections, so we must call it here. 2879 **/ 2880 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2881 { 2882 u16 san_mac_data, san_mac_offset; 2883 u8 i; 2884 s32 ret_val; 2885 2886 /* 2887 * First read the EEPROM pointer to see if the MAC addresses are 2888 * available. If they're not, no point in calling set_lan_id() here. 2889 */ 2890 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2891 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 2892 2893 goto san_mac_addr_clr; 2894 2895 /* make sure we know which port we need to program */ 2896 hw->mac.ops.set_lan_id(hw); 2897 /* apply the port offset to the address offset */ 2898 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2899 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2900 for (i = 0; i < 3; i++) { 2901 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 2902 &san_mac_data); 2903 if (ret_val) { 2904 hw_err(hw, "eeprom read at offset %d failed\n", 2905 san_mac_offset); 2906 goto san_mac_addr_clr; 2907 } 2908 san_mac_addr[i * 2] = (u8)(san_mac_data); 2909 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 2910 san_mac_offset++; 2911 } 2912 return 0; 2913 2914 san_mac_addr_clr: 2915 /* No addresses available in this EEPROM. It's not necessarily an 2916 * error though, so just wipe the local address and return. 2917 */ 2918 for (i = 0; i < 6; i++) 2919 san_mac_addr[i] = 0xFF; 2920 return ret_val; 2921 } 2922 2923 /** 2924 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 2925 * @hw: pointer to hardware structure 2926 * 2927 * Read PCIe configuration space, and get the MSI-X vector count from 2928 * the capabilities table. 2929 **/ 2930 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 2931 { 2932 u16 msix_count; 2933 u16 max_msix_count; 2934 u16 pcie_offset; 2935 2936 switch (hw->mac.type) { 2937 case ixgbe_mac_82598EB: 2938 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 2939 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 2940 break; 2941 case ixgbe_mac_82599EB: 2942 case ixgbe_mac_X540: 2943 case ixgbe_mac_X550: 2944 case ixgbe_mac_X550EM_x: 2945 case ixgbe_mac_x550em_a: 2946 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 2947 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 2948 break; 2949 default: 2950 return 1; 2951 } 2952 2953 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset); 2954 if (ixgbe_removed(hw->hw_addr)) 2955 msix_count = 0; 2956 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 2957 2958 /* MSI-X count is zero-based in HW */ 2959 msix_count++; 2960 2961 if (msix_count > max_msix_count) 2962 msix_count = max_msix_count; 2963 2964 return msix_count; 2965 } 2966 2967 /** 2968 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 2969 * @hw: pointer to hardware struct 2970 * @rar: receive address register index to disassociate 2971 * @vmdq: VMDq pool index to remove from the rar 2972 **/ 2973 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2974 { 2975 u32 mpsar_lo, mpsar_hi; 2976 u32 rar_entries = hw->mac.num_rar_entries; 2977 2978 /* Make sure we are using a valid rar index range */ 2979 if (rar >= rar_entries) { 2980 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 2981 return IXGBE_ERR_INVALID_ARGUMENT; 2982 } 2983 2984 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2985 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2986 2987 if (ixgbe_removed(hw->hw_addr)) 2988 return 0; 2989 2990 if (!mpsar_lo && !mpsar_hi) 2991 return 0; 2992 2993 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 2994 if (mpsar_lo) { 2995 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 2996 mpsar_lo = 0; 2997 } 2998 if (mpsar_hi) { 2999 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3000 mpsar_hi = 0; 3001 } 3002 } else if (vmdq < 32) { 3003 mpsar_lo &= ~BIT(vmdq); 3004 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 3005 } else { 3006 mpsar_hi &= ~BIT(vmdq - 32); 3007 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 3008 } 3009 3010 /* was that the last pool using this rar? */ 3011 if (mpsar_lo == 0 && mpsar_hi == 0 && 3012 rar != 0 && rar != hw->mac.san_mac_rar_index) 3013 hw->mac.ops.clear_rar(hw, rar); 3014 3015 return 0; 3016 } 3017 3018 /** 3019 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 3020 * @hw: pointer to hardware struct 3021 * @rar: receive address register index to associate with a VMDq index 3022 * @vmdq: VMDq pool index 3023 **/ 3024 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3025 { 3026 u32 mpsar; 3027 u32 rar_entries = hw->mac.num_rar_entries; 3028 3029 /* Make sure we are using a valid rar index range */ 3030 if (rar >= rar_entries) { 3031 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 3032 return IXGBE_ERR_INVALID_ARGUMENT; 3033 } 3034 3035 if (vmdq < 32) { 3036 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3037 mpsar |= BIT(vmdq); 3038 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3039 } else { 3040 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3041 mpsar |= BIT(vmdq - 32); 3042 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3043 } 3044 return 0; 3045 } 3046 3047 /** 3048 * This function should only be involved in the IOV mode. 3049 * In IOV mode, Default pool is next pool after the number of 3050 * VFs advertized and not 0. 3051 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3052 * 3053 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address 3054 * @hw: pointer to hardware struct 3055 * @vmdq: VMDq pool index 3056 **/ 3057 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3058 { 3059 u32 rar = hw->mac.san_mac_rar_index; 3060 3061 if (vmdq < 32) { 3062 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq)); 3063 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3064 } else { 3065 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3066 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32)); 3067 } 3068 3069 return 0; 3070 } 3071 3072 /** 3073 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3074 * @hw: pointer to hardware structure 3075 **/ 3076 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3077 { 3078 int i; 3079 3080 for (i = 0; i < 128; i++) 3081 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3082 3083 return 0; 3084 } 3085 3086 /** 3087 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3088 * @hw: pointer to hardware structure 3089 * @vlan: VLAN id to write to VLAN filter 3090 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if 3091 * vlanid not found 3092 * 3093 * return the VLVF index where this VLAN id should be placed 3094 * 3095 **/ 3096 static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) 3097 { 3098 s32 regindex, first_empty_slot; 3099 u32 bits; 3100 3101 /* short cut the special case */ 3102 if (vlan == 0) 3103 return 0; 3104 3105 /* if vlvf_bypass is set we don't want to use an empty slot, we 3106 * will simply bypass the VLVF if there are no entries present in the 3107 * VLVF that contain our VLAN 3108 */ 3109 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0; 3110 3111 /* add VLAN enable bit for comparison */ 3112 vlan |= IXGBE_VLVF_VIEN; 3113 3114 /* Search for the vlan id in the VLVF entries. Save off the first empty 3115 * slot found along the way. 3116 * 3117 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 3118 */ 3119 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { 3120 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3121 if (bits == vlan) 3122 return regindex; 3123 if (!first_empty_slot && !bits) 3124 first_empty_slot = regindex; 3125 } 3126 3127 /* If we are here then we didn't find the VLAN. Return first empty 3128 * slot we found during our search, else error. 3129 */ 3130 if (!first_empty_slot) 3131 hw_dbg(hw, "No space in VLVF.\n"); 3132 3133 return first_empty_slot ? : IXGBE_ERR_NO_SPACE; 3134 } 3135 3136 /** 3137 * ixgbe_set_vfta_generic - Set VLAN filter table 3138 * @hw: pointer to hardware structure 3139 * @vlan: VLAN id to write to VLAN filter 3140 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 3141 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 3142 * @vlvf_bypass: boolean flag indicating updating default pool is okay 3143 * 3144 * Turn on/off specified VLAN in the VLAN filter table. 3145 **/ 3146 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3147 bool vlan_on, bool vlvf_bypass) 3148 { 3149 u32 regidx, vfta_delta, vfta, bits; 3150 s32 vlvf_index; 3151 3152 if ((vlan > 4095) || (vind > 63)) 3153 return IXGBE_ERR_PARAM; 3154 3155 /* 3156 * this is a 2 part operation - first the VFTA, then the 3157 * VLVF and VLVFB if VT Mode is set 3158 * We don't write the VFTA until we know the VLVF part succeeded. 3159 */ 3160 3161 /* Part 1 3162 * The VFTA is a bitstring made up of 128 32-bit registers 3163 * that enable the particular VLAN id, much like the MTA: 3164 * bits[11-5]: which register 3165 * bits[4-0]: which bit in the register 3166 */ 3167 regidx = vlan / 32; 3168 vfta_delta = BIT(vlan % 32); 3169 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); 3170 3171 /* vfta_delta represents the difference between the current value 3172 * of vfta and the value we want in the register. Since the diff 3173 * is an XOR mask we can just update vfta using an XOR. 3174 */ 3175 vfta_delta &= vlan_on ? ~vfta : vfta; 3176 vfta ^= vfta_delta; 3177 3178 /* Part 2 3179 * If VT Mode is set 3180 * Either vlan_on 3181 * make sure the vlan is in VLVF 3182 * set the vind bit in the matching VLVFB 3183 * Or !vlan_on 3184 * clear the pool bit and possibly the vind 3185 */ 3186 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) 3187 goto vfta_update; 3188 3189 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 3190 if (vlvf_index < 0) { 3191 if (vlvf_bypass) 3192 goto vfta_update; 3193 return vlvf_index; 3194 } 3195 3196 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); 3197 3198 /* set the pool bit */ 3199 bits |= BIT(vind % 32); 3200 if (vlan_on) 3201 goto vlvf_update; 3202 3203 /* clear the pool bit */ 3204 bits ^= BIT(vind % 32); 3205 3206 if (!bits && 3207 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 3208 /* Clear VFTA first, then disable VLVF. Otherwise 3209 * we run the risk of stray packets leaking into 3210 * the PF via the default pool 3211 */ 3212 if (vfta_delta) 3213 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 3214 3215 /* disable VLVF and clear remaining bit from pool */ 3216 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 3217 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); 3218 3219 return 0; 3220 } 3221 3222 /* If there are still bits set in the VLVFB registers 3223 * for the VLAN ID indicated we need to see if the 3224 * caller is requesting that we clear the VFTA entry bit. 3225 * If the caller has requested that we clear the VFTA 3226 * entry bit but there are still pools/VFs using this VLAN 3227 * ID entry then ignore the request. We're not worried 3228 * about the case where we're turning the VFTA VLAN ID 3229 * entry bit on, only when requested to turn it off as 3230 * there may be multiple pools and/or VFs using the 3231 * VLAN ID entry. In that case we cannot clear the 3232 * VFTA bit until all pools/VFs using that VLAN ID have also 3233 * been cleared. This will be indicated by "bits" being 3234 * zero. 3235 */ 3236 vfta_delta = 0; 3237 3238 vlvf_update: 3239 /* record pool change and enable VLAN ID if not already enabled */ 3240 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); 3241 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); 3242 3243 vfta_update: 3244 /* Update VFTA now that we are ready for traffic */ 3245 if (vfta_delta) 3246 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 3247 3248 return 0; 3249 } 3250 3251 /** 3252 * ixgbe_clear_vfta_generic - Clear VLAN filter table 3253 * @hw: pointer to hardware structure 3254 * 3255 * Clears the VLAN filer table, and the VMDq index associated with the filter 3256 **/ 3257 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 3258 { 3259 u32 offset; 3260 3261 for (offset = 0; offset < hw->mac.vft_size; offset++) 3262 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 3263 3264 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 3265 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 3266 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 3267 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); 3268 } 3269 3270 return 0; 3271 } 3272 3273 /** 3274 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix 3275 * @hw: pointer to hardware structure 3276 * 3277 * Contains the logic to identify if we need to verify link for the 3278 * crosstalk fix 3279 **/ 3280 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) 3281 { 3282 /* Does FW say we need the fix */ 3283 if (!hw->need_crosstalk_fix) 3284 return false; 3285 3286 /* Only consider SFP+ PHYs i.e. media type fiber */ 3287 switch (hw->mac.ops.get_media_type(hw)) { 3288 case ixgbe_media_type_fiber: 3289 case ixgbe_media_type_fiber_qsfp: 3290 break; 3291 default: 3292 return false; 3293 } 3294 3295 return true; 3296 } 3297 3298 /** 3299 * ixgbe_check_mac_link_generic - Determine link and speed status 3300 * @hw: pointer to hardware structure 3301 * @speed: pointer to link speed 3302 * @link_up: true when link is up 3303 * @link_up_wait_to_complete: bool used to wait for link up or not 3304 * 3305 * Reads the links register to determine if link is up and the current speed 3306 **/ 3307 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3308 bool *link_up, bool link_up_wait_to_complete) 3309 { 3310 u32 links_reg, links_orig; 3311 u32 i; 3312 3313 /* If Crosstalk fix enabled do the sanity check of making sure 3314 * the SFP+ cage is full. 3315 */ 3316 if (ixgbe_need_crosstalk_fix(hw)) { 3317 u32 sfp_cage_full; 3318 3319 switch (hw->mac.type) { 3320 case ixgbe_mac_82599EB: 3321 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3322 IXGBE_ESDP_SDP2; 3323 break; 3324 case ixgbe_mac_X550EM_x: 3325 case ixgbe_mac_x550em_a: 3326 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3327 IXGBE_ESDP_SDP0; 3328 break; 3329 default: 3330 /* sanity check - No SFP+ devices here */ 3331 sfp_cage_full = false; 3332 break; 3333 } 3334 3335 if (!sfp_cage_full) { 3336 *link_up = false; 3337 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3338 return 0; 3339 } 3340 } 3341 3342 /* clear the old state */ 3343 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 3344 3345 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3346 3347 if (links_orig != links_reg) { 3348 hw_dbg(hw, "LINKS changed from %08X to %08X\n", 3349 links_orig, links_reg); 3350 } 3351 3352 if (link_up_wait_to_complete) { 3353 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 3354 if (links_reg & IXGBE_LINKS_UP) { 3355 *link_up = true; 3356 break; 3357 } else { 3358 *link_up = false; 3359 } 3360 msleep(100); 3361 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3362 } 3363 } else { 3364 if (links_reg & IXGBE_LINKS_UP) 3365 *link_up = true; 3366 else 3367 *link_up = false; 3368 } 3369 3370 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 3371 case IXGBE_LINKS_SPEED_10G_82599: 3372 if ((hw->mac.type >= ixgbe_mac_X550) && 3373 (links_reg & IXGBE_LINKS_SPEED_NON_STD)) 3374 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 3375 else 3376 *speed = IXGBE_LINK_SPEED_10GB_FULL; 3377 break; 3378 case IXGBE_LINKS_SPEED_1G_82599: 3379 *speed = IXGBE_LINK_SPEED_1GB_FULL; 3380 break; 3381 case IXGBE_LINKS_SPEED_100_82599: 3382 if ((hw->mac.type >= ixgbe_mac_X550) && 3383 (links_reg & IXGBE_LINKS_SPEED_NON_STD)) 3384 *speed = IXGBE_LINK_SPEED_5GB_FULL; 3385 else 3386 *speed = IXGBE_LINK_SPEED_100_FULL; 3387 break; 3388 case IXGBE_LINKS_SPEED_10_X550EM_A: 3389 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3390 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 3391 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) { 3392 *speed = IXGBE_LINK_SPEED_10_FULL; 3393 } 3394 break; 3395 default: 3396 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3397 } 3398 3399 return 0; 3400 } 3401 3402 /** 3403 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 3404 * the EEPROM 3405 * @hw: pointer to hardware structure 3406 * @wwnn_prefix: the alternative WWNN prefix 3407 * @wwpn_prefix: the alternative WWPN prefix 3408 * 3409 * This function will read the EEPROM from the alternative SAN MAC address 3410 * block to check the support for the alternative WWNN/WWPN prefix support. 3411 **/ 3412 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 3413 u16 *wwpn_prefix) 3414 { 3415 u16 offset, caps; 3416 u16 alt_san_mac_blk_offset; 3417 3418 /* clear output first */ 3419 *wwnn_prefix = 0xFFFF; 3420 *wwpn_prefix = 0xFFFF; 3421 3422 /* check if alternative SAN MAC is supported */ 3423 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 3424 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 3425 goto wwn_prefix_err; 3426 3427 if ((alt_san_mac_blk_offset == 0) || 3428 (alt_san_mac_blk_offset == 0xFFFF)) 3429 return 0; 3430 3431 /* check capability in alternative san mac address block */ 3432 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 3433 if (hw->eeprom.ops.read(hw, offset, &caps)) 3434 goto wwn_prefix_err; 3435 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 3436 return 0; 3437 3438 /* get the corresponding prefix for WWNN/WWPN */ 3439 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 3440 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) 3441 hw_err(hw, "eeprom read at offset %d failed\n", offset); 3442 3443 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 3444 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 3445 goto wwn_prefix_err; 3446 3447 return 0; 3448 3449 wwn_prefix_err: 3450 hw_err(hw, "eeprom read at offset %d failed\n", offset); 3451 return 0; 3452 } 3453 3454 /** 3455 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 3456 * @hw: pointer to hardware structure 3457 * @enable: enable or disable switch for MAC anti-spoofing 3458 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing 3459 * 3460 **/ 3461 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 3462 { 3463 int vf_target_reg = vf >> 3; 3464 int vf_target_shift = vf % 8; 3465 u32 pfvfspoof; 3466 3467 if (hw->mac.type == ixgbe_mac_82598EB) 3468 return; 3469 3470 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3471 if (enable) 3472 pfvfspoof |= BIT(vf_target_shift); 3473 else 3474 pfvfspoof &= ~BIT(vf_target_shift); 3475 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3476 } 3477 3478 /** 3479 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 3480 * @hw: pointer to hardware structure 3481 * @enable: enable or disable switch for VLAN anti-spoofing 3482 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 3483 * 3484 **/ 3485 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 3486 { 3487 int vf_target_reg = vf >> 3; 3488 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 3489 u32 pfvfspoof; 3490 3491 if (hw->mac.type == ixgbe_mac_82598EB) 3492 return; 3493 3494 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3495 if (enable) 3496 pfvfspoof |= BIT(vf_target_shift); 3497 else 3498 pfvfspoof &= ~BIT(vf_target_shift); 3499 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3500 } 3501 3502 /** 3503 * ixgbe_get_device_caps_generic - Get additional device capabilities 3504 * @hw: pointer to hardware structure 3505 * @device_caps: the EEPROM word with the extra device capabilities 3506 * 3507 * This function will read the EEPROM location for the device capabilities, 3508 * and return the word through device_caps. 3509 **/ 3510 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 3511 { 3512 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 3513 3514 return 0; 3515 } 3516 3517 /** 3518 * ixgbe_set_rxpba_generic - Initialize RX packet buffer 3519 * @hw: pointer to hardware structure 3520 * @num_pb: number of packet buffers to allocate 3521 * @headroom: reserve n KB of headroom 3522 * @strategy: packet buffer allocation strategy 3523 **/ 3524 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, 3525 int num_pb, 3526 u32 headroom, 3527 int strategy) 3528 { 3529 u32 pbsize = hw->mac.rx_pb_size; 3530 int i = 0; 3531 u32 rxpktsize, txpktsize, txpbthresh; 3532 3533 /* Reserve headroom */ 3534 pbsize -= headroom; 3535 3536 if (!num_pb) 3537 num_pb = 1; 3538 3539 /* Divide remaining packet buffer space amongst the number 3540 * of packet buffers requested using supplied strategy. 3541 */ 3542 switch (strategy) { 3543 case (PBA_STRATEGY_WEIGHTED): 3544 /* pba_80_48 strategy weight first half of packet buffer with 3545 * 5/8 of the packet buffer space. 3546 */ 3547 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8)); 3548 pbsize -= rxpktsize * (num_pb / 2); 3549 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 3550 for (; i < (num_pb / 2); i++) 3551 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3552 /* fall through - configure remaining packet buffers */ 3553 case (PBA_STRATEGY_EQUAL): 3554 /* Divide the remaining Rx packet buffer evenly among the TCs */ 3555 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 3556 for (; i < num_pb; i++) 3557 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3558 break; 3559 default: 3560 break; 3561 } 3562 3563 /* 3564 * Setup Tx packet buffer and threshold equally for all TCs 3565 * TXPBTHRESH register is set in K so divide by 1024 and subtract 3566 * 10 since the largest packet we support is just over 9K. 3567 */ 3568 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 3569 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 3570 for (i = 0; i < num_pb; i++) { 3571 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 3572 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 3573 } 3574 3575 /* Clear unused TCs, if any, to zero buffer size*/ 3576 for (; i < IXGBE_MAX_PB; i++) { 3577 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 3578 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 3579 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 3580 } 3581 } 3582 3583 /** 3584 * ixgbe_calculate_checksum - Calculate checksum for buffer 3585 * @buffer: pointer to EEPROM 3586 * @length: size of EEPROM to calculate a checksum for 3587 * 3588 * Calculates the checksum for some buffer on a specified length. The 3589 * checksum calculated is returned. 3590 **/ 3591 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 3592 { 3593 u32 i; 3594 u8 sum = 0; 3595 3596 if (!buffer) 3597 return 0; 3598 3599 for (i = 0; i < length; i++) 3600 sum += buffer[i]; 3601 3602 return (u8) (0 - sum); 3603 } 3604 3605 /** 3606 * ixgbe_hic_unlocked - Issue command to manageability block unlocked 3607 * @hw: pointer to the HW structure 3608 * @buffer: command to write and where the return status will be placed 3609 * @length: length of buffer, must be multiple of 4 bytes 3610 * @timeout: time in ms to wait for command completion 3611 * 3612 * Communicates with the manageability block. On success return 0 3613 * else returns semaphore error when encountering an error acquiring 3614 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 3615 * 3616 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held 3617 * by the caller. 3618 **/ 3619 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, 3620 u32 timeout) 3621 { 3622 u32 hicr, i, fwsts; 3623 u16 dword_len; 3624 3625 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 3626 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); 3627 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3628 } 3629 3630 /* Set bit 9 of FWSTS clearing FW reset indication */ 3631 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 3632 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 3633 3634 /* Check that the host interface is enabled. */ 3635 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3636 if (!(hicr & IXGBE_HICR_EN)) { 3637 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n"); 3638 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3639 } 3640 3641 /* Calculate length in DWORDs. We must be DWORD aligned */ 3642 if (length % sizeof(u32)) { 3643 hw_dbg(hw, "Buffer length failure, not aligned to dword"); 3644 return IXGBE_ERR_INVALID_ARGUMENT; 3645 } 3646 3647 dword_len = length >> 2; 3648 3649 /* The device driver writes the relevant command block 3650 * into the ram area. 3651 */ 3652 for (i = 0; i < dword_len; i++) 3653 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 3654 i, cpu_to_le32(buffer[i])); 3655 3656 /* Setting this bit tells the ARC that a new command is pending. */ 3657 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 3658 3659 for (i = 0; i < timeout; i++) { 3660 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3661 if (!(hicr & IXGBE_HICR_C)) 3662 break; 3663 usleep_range(1000, 2000); 3664 } 3665 3666 /* Check command successful completion. */ 3667 if ((timeout && i == timeout) || 3668 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) 3669 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3670 3671 return 0; 3672 } 3673 3674 /** 3675 * ixgbe_host_interface_command - Issue command to manageability block 3676 * @hw: pointer to the HW structure 3677 * @buffer: contains the command to write and where the return status will 3678 * be placed 3679 * @length: length of buffer, must be multiple of 4 bytes 3680 * @timeout: time in ms to wait for command completion 3681 * @return_data: read and return data from the buffer (true) or not (false) 3682 * Needed because FW structures are big endian and decoding of 3683 * these fields can be 8 bit or 16 bit based on command. Decoding 3684 * is not easily understood without making a table of commands. 3685 * So we will leave this up to the caller to read back the data 3686 * in these cases. 3687 * 3688 * Communicates with the manageability block. On success return 0 3689 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND. 3690 **/ 3691 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer, 3692 u32 length, u32 timeout, 3693 bool return_data) 3694 { 3695 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 3696 union { 3697 struct ixgbe_hic_hdr hdr; 3698 u32 u32arr[1]; 3699 } *bp = buffer; 3700 u16 buf_len, dword_len; 3701 s32 status; 3702 u32 bi; 3703 3704 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 3705 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); 3706 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3707 } 3708 /* Take management host interface semaphore */ 3709 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 3710 if (status) 3711 return status; 3712 3713 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); 3714 if (status) 3715 goto rel_out; 3716 3717 if (!return_data) 3718 goto rel_out; 3719 3720 /* Calculate length in DWORDs */ 3721 dword_len = hdr_size >> 2; 3722 3723 /* first pull in the header so we know the buffer length */ 3724 for (bi = 0; bi < dword_len; bi++) { 3725 bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3726 le32_to_cpus(&bp->u32arr[bi]); 3727 } 3728 3729 /* If there is any thing in data position pull it in */ 3730 buf_len = bp->hdr.buf_len; 3731 if (!buf_len) 3732 goto rel_out; 3733 3734 if (length < round_up(buf_len, 4) + hdr_size) { 3735 hw_dbg(hw, "Buffer not large enough for reply message.\n"); 3736 status = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3737 goto rel_out; 3738 } 3739 3740 /* Calculate length in DWORDs, add 3 for odd lengths */ 3741 dword_len = (buf_len + 3) >> 2; 3742 3743 /* Pull in the rest of the buffer (bi is where we left off) */ 3744 for (; bi <= dword_len; bi++) { 3745 bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3746 le32_to_cpus(&bp->u32arr[bi]); 3747 } 3748 3749 rel_out: 3750 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 3751 3752 return status; 3753 } 3754 3755 /** 3756 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 3757 * @hw: pointer to the HW structure 3758 * @maj: driver version major number 3759 * @min: driver version minor number 3760 * @build: driver version build number 3761 * @sub: driver version sub build number 3762 * @len: length of driver_ver string 3763 * @driver_ver: driver string 3764 * 3765 * Sends driver version number to firmware through the manageability 3766 * block. On success return 0 3767 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 3768 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 3769 **/ 3770 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 3771 u8 build, u8 sub, __always_unused u16 len, 3772 __always_unused const char *driver_ver) 3773 { 3774 struct ixgbe_hic_drv_info fw_cmd; 3775 int i; 3776 s32 ret_val; 3777 3778 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 3779 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 3780 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 3781 fw_cmd.port_num = hw->bus.func; 3782 fw_cmd.ver_maj = maj; 3783 fw_cmd.ver_min = min; 3784 fw_cmd.ver_build = build; 3785 fw_cmd.ver_sub = sub; 3786 fw_cmd.hdr.checksum = 0; 3787 fw_cmd.pad = 0; 3788 fw_cmd.pad2 = 0; 3789 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 3790 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 3791 3792 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 3793 ret_val = ixgbe_host_interface_command(hw, &fw_cmd, 3794 sizeof(fw_cmd), 3795 IXGBE_HI_COMMAND_TIMEOUT, 3796 true); 3797 if (ret_val != 0) 3798 continue; 3799 3800 if (fw_cmd.hdr.cmd_or_resp.ret_status == 3801 FW_CEM_RESP_STATUS_SUCCESS) 3802 ret_val = 0; 3803 else 3804 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3805 3806 break; 3807 } 3808 3809 return ret_val; 3810 } 3811 3812 /** 3813 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 3814 * @hw: pointer to the hardware structure 3815 * 3816 * The 82599 and x540 MACs can experience issues if TX work is still pending 3817 * when a reset occurs. This function prevents this by flushing the PCIe 3818 * buffers on the system. 3819 **/ 3820 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 3821 { 3822 u32 gcr_ext, hlreg0, i, poll; 3823 u16 value; 3824 3825 /* 3826 * If double reset is not requested then all transactions should 3827 * already be clear and as such there is no work to do 3828 */ 3829 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 3830 return; 3831 3832 /* 3833 * Set loopback enable to prevent any transmits from being sent 3834 * should the link come up. This assumes that the RXCTRL.RXEN bit 3835 * has already been cleared. 3836 */ 3837 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3838 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 3839 3840 /* wait for a last completion before clearing buffers */ 3841 IXGBE_WRITE_FLUSH(hw); 3842 usleep_range(3000, 6000); 3843 3844 /* Before proceeding, make sure that the PCIe block does not have 3845 * transactions pending. 3846 */ 3847 poll = ixgbe_pcie_timeout_poll(hw); 3848 for (i = 0; i < poll; i++) { 3849 usleep_range(100, 200); 3850 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); 3851 if (ixgbe_removed(hw->hw_addr)) 3852 break; 3853 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3854 break; 3855 } 3856 3857 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 3858 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 3859 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 3860 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 3861 3862 /* Flush all writes and allow 20usec for all transactions to clear */ 3863 IXGBE_WRITE_FLUSH(hw); 3864 udelay(20); 3865 3866 /* restore previous register values */ 3867 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 3868 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3869 } 3870 3871 static const u8 ixgbe_emc_temp_data[4] = { 3872 IXGBE_EMC_INTERNAL_DATA, 3873 IXGBE_EMC_DIODE1_DATA, 3874 IXGBE_EMC_DIODE2_DATA, 3875 IXGBE_EMC_DIODE3_DATA 3876 }; 3877 static const u8 ixgbe_emc_therm_limit[4] = { 3878 IXGBE_EMC_INTERNAL_THERM_LIMIT, 3879 IXGBE_EMC_DIODE1_THERM_LIMIT, 3880 IXGBE_EMC_DIODE2_THERM_LIMIT, 3881 IXGBE_EMC_DIODE3_THERM_LIMIT 3882 }; 3883 3884 /** 3885 * ixgbe_get_ets_data - Extracts the ETS bit data 3886 * @hw: pointer to hardware structure 3887 * @ets_cfg: extected ETS data 3888 * @ets_offset: offset of ETS data 3889 * 3890 * Returns error code. 3891 **/ 3892 static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg, 3893 u16 *ets_offset) 3894 { 3895 s32 status; 3896 3897 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset); 3898 if (status) 3899 return status; 3900 3901 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF)) 3902 return IXGBE_NOT_IMPLEMENTED; 3903 3904 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg); 3905 if (status) 3906 return status; 3907 3908 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED) 3909 return IXGBE_NOT_IMPLEMENTED; 3910 3911 return 0; 3912 } 3913 3914 /** 3915 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data 3916 * @hw: pointer to hardware structure 3917 * 3918 * Returns the thermal sensor data structure 3919 **/ 3920 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) 3921 { 3922 s32 status; 3923 u16 ets_offset; 3924 u16 ets_cfg; 3925 u16 ets_sensor; 3926 u8 num_sensors; 3927 u8 i; 3928 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 3929 3930 /* Only support thermal sensors attached to physical port 0 */ 3931 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 3932 return IXGBE_NOT_IMPLEMENTED; 3933 3934 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); 3935 if (status) 3936 return status; 3937 3938 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 3939 if (num_sensors > IXGBE_MAX_SENSORS) 3940 num_sensors = IXGBE_MAX_SENSORS; 3941 3942 for (i = 0; i < num_sensors; i++) { 3943 u8 sensor_index; 3944 u8 sensor_location; 3945 3946 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), 3947 &ets_sensor); 3948 if (status) 3949 return status; 3950 3951 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 3952 IXGBE_ETS_DATA_INDEX_SHIFT); 3953 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 3954 IXGBE_ETS_DATA_LOC_SHIFT); 3955 3956 if (sensor_location != 0) { 3957 status = hw->phy.ops.read_i2c_byte(hw, 3958 ixgbe_emc_temp_data[sensor_index], 3959 IXGBE_I2C_THERMAL_SENSOR_ADDR, 3960 &data->sensor[i].temp); 3961 if (status) 3962 return status; 3963 } 3964 } 3965 3966 return 0; 3967 } 3968 3969 /** 3970 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds 3971 * @hw: pointer to hardware structure 3972 * 3973 * Inits the thermal sensor thresholds according to the NVM map 3974 * and save off the threshold and location values into mac.thermal_sensor_data 3975 **/ 3976 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) 3977 { 3978 s32 status; 3979 u16 ets_offset; 3980 u16 ets_cfg; 3981 u16 ets_sensor; 3982 u8 low_thresh_delta; 3983 u8 num_sensors; 3984 u8 therm_limit; 3985 u8 i; 3986 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 3987 3988 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data)); 3989 3990 /* Only support thermal sensors attached to physical port 0 */ 3991 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 3992 return IXGBE_NOT_IMPLEMENTED; 3993 3994 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); 3995 if (status) 3996 return status; 3997 3998 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >> 3999 IXGBE_ETS_LTHRES_DELTA_SHIFT); 4000 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 4001 if (num_sensors > IXGBE_MAX_SENSORS) 4002 num_sensors = IXGBE_MAX_SENSORS; 4003 4004 for (i = 0; i < num_sensors; i++) { 4005 u8 sensor_index; 4006 u8 sensor_location; 4007 4008 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) { 4009 hw_err(hw, "eeprom read at offset %d failed\n", 4010 ets_offset + 1 + i); 4011 continue; 4012 } 4013 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 4014 IXGBE_ETS_DATA_INDEX_SHIFT); 4015 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 4016 IXGBE_ETS_DATA_LOC_SHIFT); 4017 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK; 4018 4019 hw->phy.ops.write_i2c_byte(hw, 4020 ixgbe_emc_therm_limit[sensor_index], 4021 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit); 4022 4023 if (sensor_location == 0) 4024 continue; 4025 4026 data->sensor[i].location = sensor_location; 4027 data->sensor[i].caution_thresh = therm_limit; 4028 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta; 4029 } 4030 4031 return 0; 4032 } 4033 4034 /** 4035 * ixgbe_get_orom_version - Return option ROM from EEPROM 4036 * 4037 * @hw: pointer to hardware structure 4038 * @nvm_ver: pointer to output structure 4039 * 4040 * if valid option ROM version, nvm_ver->or_valid set to true 4041 * else nvm_ver->or_valid is false. 4042 **/ 4043 void ixgbe_get_orom_version(struct ixgbe_hw *hw, 4044 struct ixgbe_nvm_version *nvm_ver) 4045 { 4046 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl; 4047 4048 nvm_ver->or_valid = false; 4049 /* Option Rom may or may not be present. Start with pointer */ 4050 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset); 4051 4052 /* make sure offset is valid */ 4053 if (offset == 0x0 || offset == NVM_INVALID_PTR) 4054 return; 4055 4056 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh); 4057 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl); 4058 4059 /* option rom exists and is valid */ 4060 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 || 4061 eeprom_cfg_blkl == NVM_VER_INVALID || 4062 eeprom_cfg_blkh == NVM_VER_INVALID) 4063 return; 4064 4065 nvm_ver->or_valid = true; 4066 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT; 4067 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) | 4068 (eeprom_cfg_blkh >> NVM_OROM_SHIFT); 4069 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK; 4070 } 4071 4072 /** 4073 * ixgbe_get_oem_prod_version Etrack ID from EEPROM 4074 * 4075 * @hw: pointer to hardware structure 4076 * @nvm_ver: pointer to output structure 4077 * 4078 * if valid OEM product version, nvm_ver->oem_valid set to true 4079 * else nvm_ver->oem_valid is false. 4080 **/ 4081 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, 4082 struct ixgbe_nvm_version *nvm_ver) 4083 { 4084 u16 rel_num, prod_ver, mod_len, cap, offset; 4085 4086 nvm_ver->oem_valid = false; 4087 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset); 4088 4089 /* Return is offset to OEM Product Version block is invalid */ 4090 if (offset == 0x0 || offset == NVM_INVALID_PTR) 4091 return; 4092 4093 /* Read product version block */ 4094 hw->eeprom.ops.read(hw, offset, &mod_len); 4095 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap); 4096 4097 /* Return if OEM product version block is invalid */ 4098 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN || 4099 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0) 4100 return; 4101 4102 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver); 4103 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num); 4104 4105 /* Return if version is invalid */ 4106 if ((rel_num | prod_ver) == 0x0 || 4107 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID) 4108 return; 4109 4110 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT; 4111 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK; 4112 nvm_ver->oem_release = rel_num; 4113 nvm_ver->oem_valid = true; 4114 } 4115 4116 /** 4117 * ixgbe_get_etk_id - Return Etrack ID from EEPROM 4118 * 4119 * @hw: pointer to hardware structure 4120 * @nvm_ver: pointer to output structure 4121 * 4122 * word read errors will return 0xFFFF 4123 **/ 4124 void ixgbe_get_etk_id(struct ixgbe_hw *hw, 4125 struct ixgbe_nvm_version *nvm_ver) 4126 { 4127 u16 etk_id_l, etk_id_h; 4128 4129 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l)) 4130 etk_id_l = NVM_VER_INVALID; 4131 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h)) 4132 etk_id_h = NVM_VER_INVALID; 4133 4134 /* The word order for the version format is determined by high order 4135 * word bit 15. 4136 */ 4137 if ((etk_id_h & NVM_ETK_VALID) == 0) { 4138 nvm_ver->etk_id = etk_id_h; 4139 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT); 4140 } else { 4141 nvm_ver->etk_id = etk_id_l; 4142 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT); 4143 } 4144 } 4145 4146 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 4147 { 4148 u32 rxctrl; 4149 4150 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4151 if (rxctrl & IXGBE_RXCTRL_RXEN) { 4152 if (hw->mac.type != ixgbe_mac_82598EB) { 4153 u32 pfdtxgswc; 4154 4155 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 4156 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 4157 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 4158 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 4159 hw->mac.set_lben = true; 4160 } else { 4161 hw->mac.set_lben = false; 4162 } 4163 } 4164 rxctrl &= ~IXGBE_RXCTRL_RXEN; 4165 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 4166 } 4167 } 4168 4169 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 4170 { 4171 u32 rxctrl; 4172 4173 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4174 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 4175 4176 if (hw->mac.type != ixgbe_mac_82598EB) { 4177 if (hw->mac.set_lben) { 4178 u32 pfdtxgswc; 4179 4180 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 4181 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 4182 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 4183 hw->mac.set_lben = false; 4184 } 4185 } 4186 } 4187 4188 /** ixgbe_mng_present - returns true when management capability is present 4189 * @hw: pointer to hardware structure 4190 **/ 4191 bool ixgbe_mng_present(struct ixgbe_hw *hw) 4192 { 4193 u32 fwsm; 4194 4195 if (hw->mac.type < ixgbe_mac_82599EB) 4196 return false; 4197 4198 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 4199 4200 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT); 4201 } 4202 4203 /** 4204 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 4205 * @hw: pointer to hardware structure 4206 * @speed: new link speed 4207 * @autoneg_wait_to_complete: true when waiting for completion is needed 4208 * 4209 * Set the link speed in the MAC and/or PHY register and restarts link. 4210 */ 4211 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 4212 ixgbe_link_speed speed, 4213 bool autoneg_wait_to_complete) 4214 { 4215 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4216 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4217 s32 status = 0; 4218 u32 speedcnt = 0; 4219 u32 i = 0; 4220 bool autoneg, link_up = false; 4221 4222 /* Mask off requested but non-supported speeds */ 4223 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg); 4224 if (status) 4225 return status; 4226 4227 speed &= link_speed; 4228 4229 /* Try each speed one by one, highest priority first. We do this in 4230 * software because 10Gb fiber doesn't support speed autonegotiation. 4231 */ 4232 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 4233 speedcnt++; 4234 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 4235 4236 /* Set the module link speed */ 4237 switch (hw->phy.media_type) { 4238 case ixgbe_media_type_fiber: 4239 hw->mac.ops.set_rate_select_speed(hw, 4240 IXGBE_LINK_SPEED_10GB_FULL); 4241 break; 4242 case ixgbe_media_type_fiber_qsfp: 4243 /* QSFP module automatically detects MAC link speed */ 4244 break; 4245 default: 4246 hw_dbg(hw, "Unexpected media type\n"); 4247 break; 4248 } 4249 4250 /* Allow module to change analog characteristics (1G->10G) */ 4251 msleep(40); 4252 4253 status = hw->mac.ops.setup_mac_link(hw, 4254 IXGBE_LINK_SPEED_10GB_FULL, 4255 autoneg_wait_to_complete); 4256 if (status) 4257 return status; 4258 4259 /* Flap the Tx laser if it has not already been done */ 4260 if (hw->mac.ops.flap_tx_laser) 4261 hw->mac.ops.flap_tx_laser(hw); 4262 4263 /* Wait for the controller to acquire link. Per IEEE 802.3ap, 4264 * Section 73.10.2, we may have to wait up to 500ms if KR is 4265 * attempted. 82599 uses the same timing for 10g SFI. 4266 */ 4267 for (i = 0; i < 5; i++) { 4268 /* Wait for the link partner to also set speed */ 4269 msleep(100); 4270 4271 /* If we have link, just jump out */ 4272 status = hw->mac.ops.check_link(hw, &link_speed, 4273 &link_up, false); 4274 if (status) 4275 return status; 4276 4277 if (link_up) 4278 goto out; 4279 } 4280 } 4281 4282 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 4283 speedcnt++; 4284 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 4285 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 4286 4287 /* Set the module link speed */ 4288 switch (hw->phy.media_type) { 4289 case ixgbe_media_type_fiber: 4290 hw->mac.ops.set_rate_select_speed(hw, 4291 IXGBE_LINK_SPEED_1GB_FULL); 4292 break; 4293 case ixgbe_media_type_fiber_qsfp: 4294 /* QSFP module automatically detects link speed */ 4295 break; 4296 default: 4297 hw_dbg(hw, "Unexpected media type\n"); 4298 break; 4299 } 4300 4301 /* Allow module to change analog characteristics (10G->1G) */ 4302 msleep(40); 4303 4304 status = hw->mac.ops.setup_mac_link(hw, 4305 IXGBE_LINK_SPEED_1GB_FULL, 4306 autoneg_wait_to_complete); 4307 if (status) 4308 return status; 4309 4310 /* Flap the Tx laser if it has not already been done */ 4311 if (hw->mac.ops.flap_tx_laser) 4312 hw->mac.ops.flap_tx_laser(hw); 4313 4314 /* Wait for the link partner to also set speed */ 4315 msleep(100); 4316 4317 /* If we have link, just jump out */ 4318 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 4319 false); 4320 if (status) 4321 return status; 4322 4323 if (link_up) 4324 goto out; 4325 } 4326 4327 /* We didn't get link. Configure back to the highest speed we tried, 4328 * (if there was more than one). We call ourselves back with just the 4329 * single highest speed that the user requested. 4330 */ 4331 if (speedcnt > 1) 4332 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 4333 highest_link_speed, 4334 autoneg_wait_to_complete); 4335 4336 out: 4337 /* Set autoneg_advertised value based on input link speed */ 4338 hw->phy.autoneg_advertised = 0; 4339 4340 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 4341 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 4342 4343 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 4344 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 4345 4346 return status; 4347 } 4348 4349 /** 4350 * ixgbe_set_soft_rate_select_speed - Set module link speed 4351 * @hw: pointer to hardware structure 4352 * @speed: link speed to set 4353 * 4354 * Set module link speed via the soft rate select. 4355 */ 4356 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 4357 ixgbe_link_speed speed) 4358 { 4359 s32 status; 4360 u8 rs, eeprom_data; 4361 4362 switch (speed) { 4363 case IXGBE_LINK_SPEED_10GB_FULL: 4364 /* one bit mask same as setting on */ 4365 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 4366 break; 4367 case IXGBE_LINK_SPEED_1GB_FULL: 4368 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 4369 break; 4370 default: 4371 hw_dbg(hw, "Invalid fixed module speed\n"); 4372 return; 4373 } 4374 4375 /* Set RS0 */ 4376 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4377 IXGBE_I2C_EEPROM_DEV_ADDR2, 4378 &eeprom_data); 4379 if (status) { 4380 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n"); 4381 return; 4382 } 4383 4384 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 4385 4386 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4387 IXGBE_I2C_EEPROM_DEV_ADDR2, 4388 eeprom_data); 4389 if (status) { 4390 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n"); 4391 return; 4392 } 4393 4394 /* Set RS1 */ 4395 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 4396 IXGBE_I2C_EEPROM_DEV_ADDR2, 4397 &eeprom_data); 4398 if (status) { 4399 hw_dbg(hw, "Failed to read Rx Rate Select RS1\n"); 4400 return; 4401 } 4402 4403 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 4404 4405 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 4406 IXGBE_I2C_EEPROM_DEV_ADDR2, 4407 eeprom_data); 4408 if (status) { 4409 hw_dbg(hw, "Failed to write Rx Rate Select RS1\n"); 4410 return; 4411 } 4412 } 4413