1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/pci.h> 30 #include <linux/delay.h> 31 #include <linux/sched.h> 32 #include <linux/netdevice.h> 33 34 #include "ixgbe.h" 35 #include "ixgbe_common.h" 36 #include "ixgbe_phy.h" 37 38 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 39 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 40 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 41 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 42 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 43 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 44 u16 count); 45 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 46 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 47 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 48 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 49 50 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 51 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg); 52 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 53 u16 words, u16 *data); 54 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 55 u16 words, u16 *data); 56 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 57 u16 offset); 58 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw); 59 60 /* Base table for registers values that change by MAC */ 61 const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = { 62 IXGBE_MVALS_INIT(8259X) 63 }; 64 65 /** 66 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow 67 * control 68 * @hw: pointer to hardware structure 69 * 70 * There are several phys that do not support autoneg flow control. This 71 * function check the device id to see if the associated phy supports 72 * autoneg flow control. 73 **/ 74 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 75 { 76 bool supported = false; 77 ixgbe_link_speed speed; 78 bool link_up; 79 80 switch (hw->phy.media_type) { 81 case ixgbe_media_type_fiber: 82 hw->mac.ops.check_link(hw, &speed, &link_up, false); 83 /* if link is down, assume supported */ 84 if (link_up) 85 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? 86 true : false; 87 else 88 supported = true; 89 break; 90 case ixgbe_media_type_backplane: 91 supported = true; 92 break; 93 case ixgbe_media_type_copper: 94 /* only some copper devices support flow control autoneg */ 95 switch (hw->device_id) { 96 case IXGBE_DEV_ID_82599_T3_LOM: 97 case IXGBE_DEV_ID_X540T: 98 case IXGBE_DEV_ID_X540T1: 99 case IXGBE_DEV_ID_X550T: 100 case IXGBE_DEV_ID_X550T1: 101 case IXGBE_DEV_ID_X550EM_X_10G_T: 102 case IXGBE_DEV_ID_X550EM_A_10G_T: 103 case IXGBE_DEV_ID_X550EM_A_1G_T: 104 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 105 supported = true; 106 break; 107 default: 108 break; 109 } 110 default: 111 break; 112 } 113 114 return supported; 115 } 116 117 /** 118 * ixgbe_setup_fc_generic - Set up flow control 119 * @hw: pointer to hardware structure 120 * 121 * Called at init time to set up flow control. 122 **/ 123 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) 124 { 125 s32 ret_val = 0; 126 u32 reg = 0, reg_bp = 0; 127 u16 reg_cu = 0; 128 bool locked = false; 129 130 /* 131 * Validate the requested mode. Strict IEEE mode does not allow 132 * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 133 */ 134 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 135 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 136 return IXGBE_ERR_INVALID_LINK_SETTINGS; 137 } 138 139 /* 140 * 10gig parts do not have a word in the EEPROM to determine the 141 * default flow control setting, so we explicitly set it to full. 142 */ 143 if (hw->fc.requested_mode == ixgbe_fc_default) 144 hw->fc.requested_mode = ixgbe_fc_full; 145 146 /* 147 * Set up the 1G and 10G flow control advertisement registers so the 148 * HW will be able to do fc autoneg once the cable is plugged in. If 149 * we link at 10G, the 1G advertisement is harmless and vice versa. 150 */ 151 switch (hw->phy.media_type) { 152 case ixgbe_media_type_backplane: 153 /* some MAC's need RMW protection on AUTOC */ 154 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 155 if (ret_val) 156 return ret_val; 157 158 /* fall through - only backplane uses autoc */ 159 case ixgbe_media_type_fiber: 160 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 161 162 break; 163 case ixgbe_media_type_copper: 164 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 165 MDIO_MMD_AN, ®_cu); 166 break; 167 default: 168 break; 169 } 170 171 /* 172 * The possible values of fc.requested_mode are: 173 * 0: Flow control is completely disabled 174 * 1: Rx flow control is enabled (we can receive pause frames, 175 * but not send pause frames). 176 * 2: Tx flow control is enabled (we can send pause frames but 177 * we do not support receiving pause frames). 178 * 3: Both Rx and Tx flow control (symmetric) are enabled. 179 * other: Invalid. 180 */ 181 switch (hw->fc.requested_mode) { 182 case ixgbe_fc_none: 183 /* Flow control completely disabled by software override. */ 184 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 185 if (hw->phy.media_type == ixgbe_media_type_backplane) 186 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 187 IXGBE_AUTOC_ASM_PAUSE); 188 else if (hw->phy.media_type == ixgbe_media_type_copper) 189 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 190 break; 191 case ixgbe_fc_tx_pause: 192 /* 193 * Tx Flow control is enabled, and Rx Flow control is 194 * disabled by software override. 195 */ 196 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 197 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 198 if (hw->phy.media_type == ixgbe_media_type_backplane) { 199 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 200 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 201 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 202 reg_cu |= IXGBE_TAF_ASM_PAUSE; 203 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 204 } 205 break; 206 case ixgbe_fc_rx_pause: 207 /* 208 * Rx Flow control is enabled and Tx Flow control is 209 * disabled by software override. Since there really 210 * isn't a way to advertise that we are capable of RX 211 * Pause ONLY, we will advertise that we support both 212 * symmetric and asymmetric Rx PAUSE, as such we fall 213 * through to the fc_full statement. Later, we will 214 * disable the adapter's ability to send PAUSE frames. 215 */ 216 case ixgbe_fc_full: 217 /* Flow control (both Rx and Tx) is enabled by SW override. */ 218 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 219 if (hw->phy.media_type == ixgbe_media_type_backplane) 220 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 221 IXGBE_AUTOC_ASM_PAUSE; 222 else if (hw->phy.media_type == ixgbe_media_type_copper) 223 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 224 break; 225 default: 226 hw_dbg(hw, "Flow control param set incorrectly\n"); 227 return IXGBE_ERR_CONFIG; 228 } 229 230 if (hw->mac.type != ixgbe_mac_X540) { 231 /* 232 * Enable auto-negotiation between the MAC & PHY; 233 * the MAC will advertise clause 37 flow control. 234 */ 235 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 236 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 237 238 /* Disable AN timeout */ 239 if (hw->fc.strict_ieee) 240 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 241 242 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 243 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); 244 } 245 246 /* 247 * AUTOC restart handles negotiation of 1G and 10G on backplane 248 * and copper. There is no need to set the PCS1GCTL register. 249 * 250 */ 251 if (hw->phy.media_type == ixgbe_media_type_backplane) { 252 /* Need the SW/FW semaphore around AUTOC writes if 82599 and 253 * LESM is on, likewise reset_pipeline requries the lock as 254 * it also writes AUTOC. 255 */ 256 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 257 if (ret_val) 258 return ret_val; 259 260 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 261 ixgbe_device_supports_autoneg_fc(hw)) { 262 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 263 MDIO_MMD_AN, reg_cu); 264 } 265 266 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); 267 return ret_val; 268 } 269 270 /** 271 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 272 * @hw: pointer to hardware structure 273 * 274 * Starts the hardware by filling the bus info structure and media type, clears 275 * all on chip counters, initializes receive address registers, multicast 276 * table, VLAN filter table, calls routine to set up link and flow control 277 * settings, and leaves transmit and receive units disabled and uninitialized 278 **/ 279 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 280 { 281 s32 ret_val; 282 u32 ctrl_ext; 283 u16 device_caps; 284 285 /* Set the media type */ 286 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 287 288 /* Identify the PHY */ 289 hw->phy.ops.identify(hw); 290 291 /* Clear the VLAN filter table */ 292 hw->mac.ops.clear_vfta(hw); 293 294 /* Clear statistics registers */ 295 hw->mac.ops.clear_hw_cntrs(hw); 296 297 /* Set No Snoop Disable */ 298 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 299 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 300 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 301 IXGBE_WRITE_FLUSH(hw); 302 303 /* Setup flow control if method for doing so */ 304 if (hw->mac.ops.setup_fc) { 305 ret_val = hw->mac.ops.setup_fc(hw); 306 if (ret_val) 307 return ret_val; 308 } 309 310 /* Cashe bit indicating need for crosstalk fix */ 311 switch (hw->mac.type) { 312 case ixgbe_mac_82599EB: 313 case ixgbe_mac_X550EM_x: 314 case ixgbe_mac_x550em_a: 315 hw->mac.ops.get_device_caps(hw, &device_caps); 316 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) 317 hw->need_crosstalk_fix = false; 318 else 319 hw->need_crosstalk_fix = true; 320 break; 321 default: 322 hw->need_crosstalk_fix = false; 323 break; 324 } 325 326 /* Clear adapter stopped flag */ 327 hw->adapter_stopped = false; 328 329 return 0; 330 } 331 332 /** 333 * ixgbe_start_hw_gen2 - Init sequence for common device family 334 * @hw: pointer to hw structure 335 * 336 * Performs the init sequence common to the second generation 337 * of 10 GbE devices. 338 * Devices in the second generation: 339 * 82599 340 * X540 341 **/ 342 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 343 { 344 u32 i; 345 346 /* Clear the rate limiters */ 347 for (i = 0; i < hw->mac.max_tx_queues; i++) { 348 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 349 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 350 } 351 IXGBE_WRITE_FLUSH(hw); 352 353 #ifndef CONFIG_ARCH_WANT_RELAX_ORDER 354 /* Disable relaxed ordering */ 355 for (i = 0; i < hw->mac.max_tx_queues; i++) { 356 u32 regval; 357 358 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 359 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 360 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 361 } 362 363 for (i = 0; i < hw->mac.max_rx_queues; i++) { 364 u32 regval; 365 366 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 367 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 368 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 369 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 370 } 371 #endif 372 return 0; 373 } 374 375 /** 376 * ixgbe_init_hw_generic - Generic hardware initialization 377 * @hw: pointer to hardware structure 378 * 379 * Initialize the hardware by resetting the hardware, filling the bus info 380 * structure and media type, clears all on chip counters, initializes receive 381 * address registers, multicast table, VLAN filter table, calls routine to set 382 * up link and flow control settings, and leaves transmit and receive units 383 * disabled and uninitialized 384 **/ 385 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 386 { 387 s32 status; 388 389 /* Reset the hardware */ 390 status = hw->mac.ops.reset_hw(hw); 391 392 if (status == 0) { 393 /* Start the HW */ 394 status = hw->mac.ops.start_hw(hw); 395 } 396 397 /* Initialize the LED link active for LED blink support */ 398 if (hw->mac.ops.init_led_link_act) 399 hw->mac.ops.init_led_link_act(hw); 400 401 return status; 402 } 403 404 /** 405 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 406 * @hw: pointer to hardware structure 407 * 408 * Clears all hardware statistics counters by reading them from the hardware 409 * Statistics counters are clear on read. 410 **/ 411 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 412 { 413 u16 i = 0; 414 415 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 416 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 417 IXGBE_READ_REG(hw, IXGBE_ERRBC); 418 IXGBE_READ_REG(hw, IXGBE_MSPDC); 419 for (i = 0; i < 8; i++) 420 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 421 422 IXGBE_READ_REG(hw, IXGBE_MLFC); 423 IXGBE_READ_REG(hw, IXGBE_MRFC); 424 IXGBE_READ_REG(hw, IXGBE_RLEC); 425 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 426 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 427 if (hw->mac.type >= ixgbe_mac_82599EB) { 428 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 429 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 430 } else { 431 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 432 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 433 } 434 435 for (i = 0; i < 8; i++) { 436 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 437 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 438 if (hw->mac.type >= ixgbe_mac_82599EB) { 439 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 440 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 441 } else { 442 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 443 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 444 } 445 } 446 if (hw->mac.type >= ixgbe_mac_82599EB) 447 for (i = 0; i < 8; i++) 448 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 449 IXGBE_READ_REG(hw, IXGBE_PRC64); 450 IXGBE_READ_REG(hw, IXGBE_PRC127); 451 IXGBE_READ_REG(hw, IXGBE_PRC255); 452 IXGBE_READ_REG(hw, IXGBE_PRC511); 453 IXGBE_READ_REG(hw, IXGBE_PRC1023); 454 IXGBE_READ_REG(hw, IXGBE_PRC1522); 455 IXGBE_READ_REG(hw, IXGBE_GPRC); 456 IXGBE_READ_REG(hw, IXGBE_BPRC); 457 IXGBE_READ_REG(hw, IXGBE_MPRC); 458 IXGBE_READ_REG(hw, IXGBE_GPTC); 459 IXGBE_READ_REG(hw, IXGBE_GORCL); 460 IXGBE_READ_REG(hw, IXGBE_GORCH); 461 IXGBE_READ_REG(hw, IXGBE_GOTCL); 462 IXGBE_READ_REG(hw, IXGBE_GOTCH); 463 if (hw->mac.type == ixgbe_mac_82598EB) 464 for (i = 0; i < 8; i++) 465 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 466 IXGBE_READ_REG(hw, IXGBE_RUC); 467 IXGBE_READ_REG(hw, IXGBE_RFC); 468 IXGBE_READ_REG(hw, IXGBE_ROC); 469 IXGBE_READ_REG(hw, IXGBE_RJC); 470 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 471 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 472 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 473 IXGBE_READ_REG(hw, IXGBE_TORL); 474 IXGBE_READ_REG(hw, IXGBE_TORH); 475 IXGBE_READ_REG(hw, IXGBE_TPR); 476 IXGBE_READ_REG(hw, IXGBE_TPT); 477 IXGBE_READ_REG(hw, IXGBE_PTC64); 478 IXGBE_READ_REG(hw, IXGBE_PTC127); 479 IXGBE_READ_REG(hw, IXGBE_PTC255); 480 IXGBE_READ_REG(hw, IXGBE_PTC511); 481 IXGBE_READ_REG(hw, IXGBE_PTC1023); 482 IXGBE_READ_REG(hw, IXGBE_PTC1522); 483 IXGBE_READ_REG(hw, IXGBE_MPTC); 484 IXGBE_READ_REG(hw, IXGBE_BPTC); 485 for (i = 0; i < 16; i++) { 486 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 487 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 488 if (hw->mac.type >= ixgbe_mac_82599EB) { 489 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 490 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 491 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 492 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 493 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 494 } else { 495 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 496 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 497 } 498 } 499 500 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { 501 if (hw->phy.id == 0) 502 hw->phy.ops.identify(hw); 503 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i); 504 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i); 505 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i); 506 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i); 507 } 508 509 return 0; 510 } 511 512 /** 513 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 514 * @hw: pointer to hardware structure 515 * @pba_num: stores the part number string from the EEPROM 516 * @pba_num_size: part number string buffer length 517 * 518 * Reads the part number string from the EEPROM. 519 **/ 520 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 521 u32 pba_num_size) 522 { 523 s32 ret_val; 524 u16 data; 525 u16 pba_ptr; 526 u16 offset; 527 u16 length; 528 529 if (pba_num == NULL) { 530 hw_dbg(hw, "PBA string buffer was null\n"); 531 return IXGBE_ERR_INVALID_ARGUMENT; 532 } 533 534 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 535 if (ret_val) { 536 hw_dbg(hw, "NVM Read Error\n"); 537 return ret_val; 538 } 539 540 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 541 if (ret_val) { 542 hw_dbg(hw, "NVM Read Error\n"); 543 return ret_val; 544 } 545 546 /* 547 * if data is not ptr guard the PBA must be in legacy format which 548 * means pba_ptr is actually our second data word for the PBA number 549 * and we can decode it into an ascii string 550 */ 551 if (data != IXGBE_PBANUM_PTR_GUARD) { 552 hw_dbg(hw, "NVM PBA number is not stored as string\n"); 553 554 /* we will need 11 characters to store the PBA */ 555 if (pba_num_size < 11) { 556 hw_dbg(hw, "PBA string buffer too small\n"); 557 return IXGBE_ERR_NO_SPACE; 558 } 559 560 /* extract hex string from data and pba_ptr */ 561 pba_num[0] = (data >> 12) & 0xF; 562 pba_num[1] = (data >> 8) & 0xF; 563 pba_num[2] = (data >> 4) & 0xF; 564 pba_num[3] = data & 0xF; 565 pba_num[4] = (pba_ptr >> 12) & 0xF; 566 pba_num[5] = (pba_ptr >> 8) & 0xF; 567 pba_num[6] = '-'; 568 pba_num[7] = 0; 569 pba_num[8] = (pba_ptr >> 4) & 0xF; 570 pba_num[9] = pba_ptr & 0xF; 571 572 /* put a null character on the end of our string */ 573 pba_num[10] = '\0'; 574 575 /* switch all the data but the '-' to hex char */ 576 for (offset = 0; offset < 10; offset++) { 577 if (pba_num[offset] < 0xA) 578 pba_num[offset] += '0'; 579 else if (pba_num[offset] < 0x10) 580 pba_num[offset] += 'A' - 0xA; 581 } 582 583 return 0; 584 } 585 586 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 587 if (ret_val) { 588 hw_dbg(hw, "NVM Read Error\n"); 589 return ret_val; 590 } 591 592 if (length == 0xFFFF || length == 0) { 593 hw_dbg(hw, "NVM PBA number section invalid length\n"); 594 return IXGBE_ERR_PBA_SECTION; 595 } 596 597 /* check if pba_num buffer is big enough */ 598 if (pba_num_size < (((u32)length * 2) - 1)) { 599 hw_dbg(hw, "PBA string buffer too small\n"); 600 return IXGBE_ERR_NO_SPACE; 601 } 602 603 /* trim pba length from start of string */ 604 pba_ptr++; 605 length--; 606 607 for (offset = 0; offset < length; offset++) { 608 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 609 if (ret_val) { 610 hw_dbg(hw, "NVM Read Error\n"); 611 return ret_val; 612 } 613 pba_num[offset * 2] = (u8)(data >> 8); 614 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 615 } 616 pba_num[offset * 2] = '\0'; 617 618 return 0; 619 } 620 621 /** 622 * ixgbe_get_mac_addr_generic - Generic get MAC address 623 * @hw: pointer to hardware structure 624 * @mac_addr: Adapter MAC address 625 * 626 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 627 * A reset of the adapter must be performed prior to calling this function 628 * in order for the MAC address to have been loaded from the EEPROM into RAR0 629 **/ 630 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 631 { 632 u32 rar_high; 633 u32 rar_low; 634 u16 i; 635 636 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 637 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 638 639 for (i = 0; i < 4; i++) 640 mac_addr[i] = (u8)(rar_low >> (i*8)); 641 642 for (i = 0; i < 2; i++) 643 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 644 645 return 0; 646 } 647 648 enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status) 649 { 650 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 651 case IXGBE_PCI_LINK_WIDTH_1: 652 return ixgbe_bus_width_pcie_x1; 653 case IXGBE_PCI_LINK_WIDTH_2: 654 return ixgbe_bus_width_pcie_x2; 655 case IXGBE_PCI_LINK_WIDTH_4: 656 return ixgbe_bus_width_pcie_x4; 657 case IXGBE_PCI_LINK_WIDTH_8: 658 return ixgbe_bus_width_pcie_x8; 659 default: 660 return ixgbe_bus_width_unknown; 661 } 662 } 663 664 enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status) 665 { 666 switch (link_status & IXGBE_PCI_LINK_SPEED) { 667 case IXGBE_PCI_LINK_SPEED_2500: 668 return ixgbe_bus_speed_2500; 669 case IXGBE_PCI_LINK_SPEED_5000: 670 return ixgbe_bus_speed_5000; 671 case IXGBE_PCI_LINK_SPEED_8000: 672 return ixgbe_bus_speed_8000; 673 default: 674 return ixgbe_bus_speed_unknown; 675 } 676 } 677 678 /** 679 * ixgbe_get_bus_info_generic - Generic set PCI bus info 680 * @hw: pointer to hardware structure 681 * 682 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 683 **/ 684 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 685 { 686 u16 link_status; 687 688 hw->bus.type = ixgbe_bus_type_pci_express; 689 690 /* Get the negotiated link width and speed from PCI config space */ 691 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS); 692 693 hw->bus.width = ixgbe_convert_bus_width(link_status); 694 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 695 696 hw->mac.ops.set_lan_id(hw); 697 698 return 0; 699 } 700 701 /** 702 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 703 * @hw: pointer to the HW structure 704 * 705 * Determines the LAN function id by reading memory-mapped registers 706 * and swaps the port value if requested. 707 **/ 708 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 709 { 710 struct ixgbe_bus_info *bus = &hw->bus; 711 u16 ee_ctrl_4; 712 u32 reg; 713 714 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 715 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 716 bus->lan_id = bus->func; 717 718 /* check for a port swap */ 719 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); 720 if (reg & IXGBE_FACTPS_LFS) 721 bus->func ^= 0x1; 722 723 /* Get MAC instance from EEPROM for configuring CS4227 */ 724 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { 725 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); 726 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> 727 IXGBE_EE_CTRL_4_INST_ID_SHIFT; 728 } 729 } 730 731 /** 732 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 733 * @hw: pointer to hardware structure 734 * 735 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 736 * disables transmit and receive units. The adapter_stopped flag is used by 737 * the shared code and drivers to determine if the adapter is in a stopped 738 * state and should not touch the hardware. 739 **/ 740 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 741 { 742 u32 reg_val; 743 u16 i; 744 745 /* 746 * Set the adapter_stopped flag so other driver functions stop touching 747 * the hardware 748 */ 749 hw->adapter_stopped = true; 750 751 /* Disable the receive unit */ 752 hw->mac.ops.disable_rx(hw); 753 754 /* Clear interrupt mask to stop interrupts from being generated */ 755 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 756 757 /* Clear any pending interrupts, flush previous writes */ 758 IXGBE_READ_REG(hw, IXGBE_EICR); 759 760 /* Disable the transmit unit. Each queue must be disabled. */ 761 for (i = 0; i < hw->mac.max_tx_queues; i++) 762 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 763 764 /* Disable the receive unit by stopping each queue */ 765 for (i = 0; i < hw->mac.max_rx_queues; i++) { 766 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 767 reg_val &= ~IXGBE_RXDCTL_ENABLE; 768 reg_val |= IXGBE_RXDCTL_SWFLSH; 769 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 770 } 771 772 /* flush all queues disables */ 773 IXGBE_WRITE_FLUSH(hw); 774 usleep_range(1000, 2000); 775 776 /* 777 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 778 * access and verify no pending requests 779 */ 780 return ixgbe_disable_pcie_master(hw); 781 } 782 783 /** 784 * ixgbe_init_led_link_act_generic - Store the LED index link/activity. 785 * @hw: pointer to hardware structure 786 * 787 * Store the index for the link active LED. This will be used to support 788 * blinking the LED. 789 **/ 790 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) 791 { 792 struct ixgbe_mac_info *mac = &hw->mac; 793 u32 led_reg, led_mode; 794 u16 i; 795 796 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 797 798 /* Get LED link active from the LEDCTL register */ 799 for (i = 0; i < 4; i++) { 800 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i); 801 802 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) == 803 IXGBE_LED_LINK_ACTIVE) { 804 mac->led_link_act = i; 805 return 0; 806 } 807 } 808 809 /* If LEDCTL register does not have the LED link active set, then use 810 * known MAC defaults. 811 */ 812 switch (hw->mac.type) { 813 case ixgbe_mac_x550em_a: 814 mac->led_link_act = 0; 815 break; 816 case ixgbe_mac_X550EM_x: 817 mac->led_link_act = 1; 818 break; 819 default: 820 mac->led_link_act = 2; 821 } 822 823 return 0; 824 } 825 826 /** 827 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 828 * @hw: pointer to hardware structure 829 * @index: led number to turn on 830 **/ 831 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 832 { 833 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 834 835 if (index > 3) 836 return IXGBE_ERR_PARAM; 837 838 /* To turn on the LED, set mode to ON. */ 839 led_reg &= ~IXGBE_LED_MODE_MASK(index); 840 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 841 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 842 IXGBE_WRITE_FLUSH(hw); 843 844 return 0; 845 } 846 847 /** 848 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 849 * @hw: pointer to hardware structure 850 * @index: led number to turn off 851 **/ 852 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 853 { 854 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 855 856 if (index > 3) 857 return IXGBE_ERR_PARAM; 858 859 /* To turn off the LED, set mode to OFF. */ 860 led_reg &= ~IXGBE_LED_MODE_MASK(index); 861 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 862 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 863 IXGBE_WRITE_FLUSH(hw); 864 865 return 0; 866 } 867 868 /** 869 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 870 * @hw: pointer to hardware structure 871 * 872 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 873 * ixgbe_hw struct in order to set up EEPROM access. 874 **/ 875 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 876 { 877 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 878 u32 eec; 879 u16 eeprom_size; 880 881 if (eeprom->type == ixgbe_eeprom_uninitialized) { 882 eeprom->type = ixgbe_eeprom_none; 883 /* Set default semaphore delay to 10ms which is a well 884 * tested value */ 885 eeprom->semaphore_delay = 10; 886 /* Clear EEPROM page size, it will be initialized as needed */ 887 eeprom->word_page_size = 0; 888 889 /* 890 * Check for EEPROM present first. 891 * If not present leave as none 892 */ 893 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 894 if (eec & IXGBE_EEC_PRES) { 895 eeprom->type = ixgbe_eeprom_spi; 896 897 /* 898 * SPI EEPROM is assumed here. This code would need to 899 * change if a future EEPROM is not SPI. 900 */ 901 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 902 IXGBE_EEC_SIZE_SHIFT); 903 eeprom->word_size = BIT(eeprom_size + 904 IXGBE_EEPROM_WORD_SIZE_SHIFT); 905 } 906 907 if (eec & IXGBE_EEC_ADDR_SIZE) 908 eeprom->address_bits = 16; 909 else 910 eeprom->address_bits = 8; 911 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n", 912 eeprom->type, eeprom->word_size, eeprom->address_bits); 913 } 914 915 return 0; 916 } 917 918 /** 919 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 920 * @hw: pointer to hardware structure 921 * @offset: offset within the EEPROM to write 922 * @words: number of words 923 * @data: 16 bit word(s) to write to EEPROM 924 * 925 * Reads 16 bit word(s) from EEPROM through bit-bang method 926 **/ 927 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 928 u16 words, u16 *data) 929 { 930 s32 status; 931 u16 i, count; 932 933 hw->eeprom.ops.init_params(hw); 934 935 if (words == 0) 936 return IXGBE_ERR_INVALID_ARGUMENT; 937 938 if (offset + words > hw->eeprom.word_size) 939 return IXGBE_ERR_EEPROM; 940 941 /* 942 * The EEPROM page size cannot be queried from the chip. We do lazy 943 * initialization. It is worth to do that when we write large buffer. 944 */ 945 if ((hw->eeprom.word_page_size == 0) && 946 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 947 ixgbe_detect_eeprom_page_size_generic(hw, offset); 948 949 /* 950 * We cannot hold synchronization semaphores for too long 951 * to avoid other entity starvation. However it is more efficient 952 * to read in bursts than synchronizing access for each word. 953 */ 954 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 955 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 956 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 957 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 958 count, &data[i]); 959 960 if (status != 0) 961 break; 962 } 963 964 return status; 965 } 966 967 /** 968 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 969 * @hw: pointer to hardware structure 970 * @offset: offset within the EEPROM to be written to 971 * @words: number of word(s) 972 * @data: 16 bit word(s) to be written to the EEPROM 973 * 974 * If ixgbe_eeprom_update_checksum is not called after this function, the 975 * EEPROM will most likely contain an invalid checksum. 976 **/ 977 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 978 u16 words, u16 *data) 979 { 980 s32 status; 981 u16 word; 982 u16 page_size; 983 u16 i; 984 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 985 986 /* Prepare the EEPROM for writing */ 987 status = ixgbe_acquire_eeprom(hw); 988 if (status) 989 return status; 990 991 if (ixgbe_ready_eeprom(hw) != 0) { 992 ixgbe_release_eeprom(hw); 993 return IXGBE_ERR_EEPROM; 994 } 995 996 for (i = 0; i < words; i++) { 997 ixgbe_standby_eeprom(hw); 998 999 /* Send the WRITE ENABLE command (8 bit opcode) */ 1000 ixgbe_shift_out_eeprom_bits(hw, 1001 IXGBE_EEPROM_WREN_OPCODE_SPI, 1002 IXGBE_EEPROM_OPCODE_BITS); 1003 1004 ixgbe_standby_eeprom(hw); 1005 1006 /* Some SPI eeproms use the 8th address bit embedded 1007 * in the opcode 1008 */ 1009 if ((hw->eeprom.address_bits == 8) && 1010 ((offset + i) >= 128)) 1011 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1012 1013 /* Send the Write command (8-bit opcode + addr) */ 1014 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 1015 IXGBE_EEPROM_OPCODE_BITS); 1016 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1017 hw->eeprom.address_bits); 1018 1019 page_size = hw->eeprom.word_page_size; 1020 1021 /* Send the data in burst via SPI */ 1022 do { 1023 word = data[i]; 1024 word = (word >> 8) | (word << 8); 1025 ixgbe_shift_out_eeprom_bits(hw, word, 16); 1026 1027 if (page_size == 0) 1028 break; 1029 1030 /* do not wrap around page */ 1031 if (((offset + i) & (page_size - 1)) == 1032 (page_size - 1)) 1033 break; 1034 } while (++i < words); 1035 1036 ixgbe_standby_eeprom(hw); 1037 usleep_range(10000, 20000); 1038 } 1039 /* Done with writing - release the EEPROM */ 1040 ixgbe_release_eeprom(hw); 1041 1042 return 0; 1043 } 1044 1045 /** 1046 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1047 * @hw: pointer to hardware structure 1048 * @offset: offset within the EEPROM to be written to 1049 * @data: 16 bit word to be written to the EEPROM 1050 * 1051 * If ixgbe_eeprom_update_checksum is not called after this function, the 1052 * EEPROM will most likely contain an invalid checksum. 1053 **/ 1054 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1055 { 1056 hw->eeprom.ops.init_params(hw); 1057 1058 if (offset >= hw->eeprom.word_size) 1059 return IXGBE_ERR_EEPROM; 1060 1061 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1062 } 1063 1064 /** 1065 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1066 * @hw: pointer to hardware structure 1067 * @offset: offset within the EEPROM to be read 1068 * @words: number of word(s) 1069 * @data: read 16 bit words(s) from EEPROM 1070 * 1071 * Reads 16 bit word(s) from EEPROM through bit-bang method 1072 **/ 1073 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1074 u16 words, u16 *data) 1075 { 1076 s32 status; 1077 u16 i, count; 1078 1079 hw->eeprom.ops.init_params(hw); 1080 1081 if (words == 0) 1082 return IXGBE_ERR_INVALID_ARGUMENT; 1083 1084 if (offset + words > hw->eeprom.word_size) 1085 return IXGBE_ERR_EEPROM; 1086 1087 /* 1088 * We cannot hold synchronization semaphores for too long 1089 * to avoid other entity starvation. However it is more efficient 1090 * to read in bursts than synchronizing access for each word. 1091 */ 1092 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1093 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1094 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1095 1096 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1097 count, &data[i]); 1098 1099 if (status) 1100 return status; 1101 } 1102 1103 return 0; 1104 } 1105 1106 /** 1107 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1108 * @hw: pointer to hardware structure 1109 * @offset: offset within the EEPROM to be read 1110 * @words: number of word(s) 1111 * @data: read 16 bit word(s) from EEPROM 1112 * 1113 * Reads 16 bit word(s) from EEPROM through bit-bang method 1114 **/ 1115 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1116 u16 words, u16 *data) 1117 { 1118 s32 status; 1119 u16 word_in; 1120 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1121 u16 i; 1122 1123 /* Prepare the EEPROM for reading */ 1124 status = ixgbe_acquire_eeprom(hw); 1125 if (status) 1126 return status; 1127 1128 if (ixgbe_ready_eeprom(hw) != 0) { 1129 ixgbe_release_eeprom(hw); 1130 return IXGBE_ERR_EEPROM; 1131 } 1132 1133 for (i = 0; i < words; i++) { 1134 ixgbe_standby_eeprom(hw); 1135 /* Some SPI eeproms use the 8th address bit embedded 1136 * in the opcode 1137 */ 1138 if ((hw->eeprom.address_bits == 8) && 1139 ((offset + i) >= 128)) 1140 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1141 1142 /* Send the READ command (opcode + addr) */ 1143 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1144 IXGBE_EEPROM_OPCODE_BITS); 1145 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1146 hw->eeprom.address_bits); 1147 1148 /* Read the data. */ 1149 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1150 data[i] = (word_in >> 8) | (word_in << 8); 1151 } 1152 1153 /* End this read operation */ 1154 ixgbe_release_eeprom(hw); 1155 1156 return 0; 1157 } 1158 1159 /** 1160 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1161 * @hw: pointer to hardware structure 1162 * @offset: offset within the EEPROM to be read 1163 * @data: read 16 bit value from EEPROM 1164 * 1165 * Reads 16 bit value from EEPROM through bit-bang method 1166 **/ 1167 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1168 u16 *data) 1169 { 1170 hw->eeprom.ops.init_params(hw); 1171 1172 if (offset >= hw->eeprom.word_size) 1173 return IXGBE_ERR_EEPROM; 1174 1175 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1176 } 1177 1178 /** 1179 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1180 * @hw: pointer to hardware structure 1181 * @offset: offset of word in the EEPROM to read 1182 * @words: number of word(s) 1183 * @data: 16 bit word(s) from the EEPROM 1184 * 1185 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1186 **/ 1187 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1188 u16 words, u16 *data) 1189 { 1190 u32 eerd; 1191 s32 status; 1192 u32 i; 1193 1194 hw->eeprom.ops.init_params(hw); 1195 1196 if (words == 0) 1197 return IXGBE_ERR_INVALID_ARGUMENT; 1198 1199 if (offset >= hw->eeprom.word_size) 1200 return IXGBE_ERR_EEPROM; 1201 1202 for (i = 0; i < words; i++) { 1203 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1204 IXGBE_EEPROM_RW_REG_START; 1205 1206 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1207 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1208 1209 if (status == 0) { 1210 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1211 IXGBE_EEPROM_RW_REG_DATA); 1212 } else { 1213 hw_dbg(hw, "Eeprom read timed out\n"); 1214 return status; 1215 } 1216 } 1217 1218 return 0; 1219 } 1220 1221 /** 1222 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1223 * @hw: pointer to hardware structure 1224 * @offset: offset within the EEPROM to be used as a scratch pad 1225 * 1226 * Discover EEPROM page size by writing marching data at given offset. 1227 * This function is called only when we are writing a new large buffer 1228 * at given offset so the data would be overwritten anyway. 1229 **/ 1230 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1231 u16 offset) 1232 { 1233 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1234 s32 status; 1235 u16 i; 1236 1237 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1238 data[i] = i; 1239 1240 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1241 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1242 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1243 hw->eeprom.word_page_size = 0; 1244 if (status) 1245 return status; 1246 1247 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1248 if (status) 1249 return status; 1250 1251 /* 1252 * When writing in burst more than the actual page size 1253 * EEPROM address wraps around current page. 1254 */ 1255 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1256 1257 hw_dbg(hw, "Detected EEPROM page size = %d words.\n", 1258 hw->eeprom.word_page_size); 1259 return 0; 1260 } 1261 1262 /** 1263 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1264 * @hw: pointer to hardware structure 1265 * @offset: offset of word in the EEPROM to read 1266 * @data: word read from the EEPROM 1267 * 1268 * Reads a 16 bit word from the EEPROM using the EERD register. 1269 **/ 1270 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1271 { 1272 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1273 } 1274 1275 /** 1276 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1277 * @hw: pointer to hardware structure 1278 * @offset: offset of word in the EEPROM to write 1279 * @words: number of words 1280 * @data: word(s) write to the EEPROM 1281 * 1282 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1283 **/ 1284 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1285 u16 words, u16 *data) 1286 { 1287 u32 eewr; 1288 s32 status; 1289 u16 i; 1290 1291 hw->eeprom.ops.init_params(hw); 1292 1293 if (words == 0) 1294 return IXGBE_ERR_INVALID_ARGUMENT; 1295 1296 if (offset >= hw->eeprom.word_size) 1297 return IXGBE_ERR_EEPROM; 1298 1299 for (i = 0; i < words; i++) { 1300 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1301 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1302 IXGBE_EEPROM_RW_REG_START; 1303 1304 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1305 if (status) { 1306 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1307 return status; 1308 } 1309 1310 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1311 1312 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1313 if (status) { 1314 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1315 return status; 1316 } 1317 } 1318 1319 return 0; 1320 } 1321 1322 /** 1323 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1324 * @hw: pointer to hardware structure 1325 * @offset: offset of word in the EEPROM to write 1326 * @data: word write to the EEPROM 1327 * 1328 * Write a 16 bit word to the EEPROM using the EEWR register. 1329 **/ 1330 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1331 { 1332 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1333 } 1334 1335 /** 1336 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1337 * @hw: pointer to hardware structure 1338 * @ee_reg: EEPROM flag for polling 1339 * 1340 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1341 * read or write is done respectively. 1342 **/ 1343 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1344 { 1345 u32 i; 1346 u32 reg; 1347 1348 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1349 if (ee_reg == IXGBE_NVM_POLL_READ) 1350 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1351 else 1352 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1353 1354 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1355 return 0; 1356 } 1357 udelay(5); 1358 } 1359 return IXGBE_ERR_EEPROM; 1360 } 1361 1362 /** 1363 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1364 * @hw: pointer to hardware structure 1365 * 1366 * Prepares EEPROM for access using bit-bang method. This function should 1367 * be called before issuing a command to the EEPROM. 1368 **/ 1369 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1370 { 1371 u32 eec; 1372 u32 i; 1373 1374 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) 1375 return IXGBE_ERR_SWFW_SYNC; 1376 1377 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1378 1379 /* Request EEPROM Access */ 1380 eec |= IXGBE_EEC_REQ; 1381 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1382 1383 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1384 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1385 if (eec & IXGBE_EEC_GNT) 1386 break; 1387 udelay(5); 1388 } 1389 1390 /* Release if grant not acquired */ 1391 if (!(eec & IXGBE_EEC_GNT)) { 1392 eec &= ~IXGBE_EEC_REQ; 1393 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1394 hw_dbg(hw, "Could not acquire EEPROM grant\n"); 1395 1396 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1397 return IXGBE_ERR_EEPROM; 1398 } 1399 1400 /* Setup EEPROM for Read/Write */ 1401 /* Clear CS and SK */ 1402 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1403 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1404 IXGBE_WRITE_FLUSH(hw); 1405 udelay(1); 1406 return 0; 1407 } 1408 1409 /** 1410 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1411 * @hw: pointer to hardware structure 1412 * 1413 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1414 **/ 1415 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1416 { 1417 u32 timeout = 2000; 1418 u32 i; 1419 u32 swsm; 1420 1421 /* Get SMBI software semaphore between device drivers first */ 1422 for (i = 0; i < timeout; i++) { 1423 /* 1424 * If the SMBI bit is 0 when we read it, then the bit will be 1425 * set and we have the semaphore 1426 */ 1427 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1428 if (!(swsm & IXGBE_SWSM_SMBI)) 1429 break; 1430 usleep_range(50, 100); 1431 } 1432 1433 if (i == timeout) { 1434 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n"); 1435 /* this release is particularly important because our attempts 1436 * above to get the semaphore may have succeeded, and if there 1437 * was a timeout, we should unconditionally clear the semaphore 1438 * bits to free the driver to make progress 1439 */ 1440 ixgbe_release_eeprom_semaphore(hw); 1441 1442 usleep_range(50, 100); 1443 /* one last try 1444 * If the SMBI bit is 0 when we read it, then the bit will be 1445 * set and we have the semaphore 1446 */ 1447 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1448 if (swsm & IXGBE_SWSM_SMBI) { 1449 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n"); 1450 return IXGBE_ERR_EEPROM; 1451 } 1452 } 1453 1454 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1455 for (i = 0; i < timeout; i++) { 1456 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1457 1458 /* Set the SW EEPROM semaphore bit to request access */ 1459 swsm |= IXGBE_SWSM_SWESMBI; 1460 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); 1461 1462 /* If we set the bit successfully then we got the 1463 * semaphore. 1464 */ 1465 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1466 if (swsm & IXGBE_SWSM_SWESMBI) 1467 break; 1468 1469 usleep_range(50, 100); 1470 } 1471 1472 /* Release semaphores and return error if SW EEPROM semaphore 1473 * was not granted because we don't have access to the EEPROM 1474 */ 1475 if (i >= timeout) { 1476 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n"); 1477 ixgbe_release_eeprom_semaphore(hw); 1478 return IXGBE_ERR_EEPROM; 1479 } 1480 1481 return 0; 1482 } 1483 1484 /** 1485 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1486 * @hw: pointer to hardware structure 1487 * 1488 * This function clears hardware semaphore bits. 1489 **/ 1490 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1491 { 1492 u32 swsm; 1493 1494 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 1495 1496 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1497 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1498 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); 1499 IXGBE_WRITE_FLUSH(hw); 1500 } 1501 1502 /** 1503 * ixgbe_ready_eeprom - Polls for EEPROM ready 1504 * @hw: pointer to hardware structure 1505 **/ 1506 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1507 { 1508 u16 i; 1509 u8 spi_stat_reg; 1510 1511 /* 1512 * Read "Status Register" repeatedly until the LSB is cleared. The 1513 * EEPROM will signal that the command has been completed by clearing 1514 * bit 0 of the internal status register. If it's not cleared within 1515 * 5 milliseconds, then error out. 1516 */ 1517 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 1518 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1519 IXGBE_EEPROM_OPCODE_BITS); 1520 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 1521 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 1522 break; 1523 1524 udelay(5); 1525 ixgbe_standby_eeprom(hw); 1526 } 1527 1528 /* 1529 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 1530 * devices (and only 0-5mSec on 5V devices) 1531 */ 1532 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 1533 hw_dbg(hw, "SPI EEPROM Status error\n"); 1534 return IXGBE_ERR_EEPROM; 1535 } 1536 1537 return 0; 1538 } 1539 1540 /** 1541 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 1542 * @hw: pointer to hardware structure 1543 **/ 1544 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 1545 { 1546 u32 eec; 1547 1548 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1549 1550 /* Toggle CS to flush commands */ 1551 eec |= IXGBE_EEC_CS; 1552 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1553 IXGBE_WRITE_FLUSH(hw); 1554 udelay(1); 1555 eec &= ~IXGBE_EEC_CS; 1556 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1557 IXGBE_WRITE_FLUSH(hw); 1558 udelay(1); 1559 } 1560 1561 /** 1562 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 1563 * @hw: pointer to hardware structure 1564 * @data: data to send to the EEPROM 1565 * @count: number of bits to shift out 1566 **/ 1567 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 1568 u16 count) 1569 { 1570 u32 eec; 1571 u32 mask; 1572 u32 i; 1573 1574 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1575 1576 /* 1577 * Mask is used to shift "count" bits of "data" out to the EEPROM 1578 * one bit at a time. Determine the starting bit based on count 1579 */ 1580 mask = BIT(count - 1); 1581 1582 for (i = 0; i < count; i++) { 1583 /* 1584 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 1585 * "1", and then raising and then lowering the clock (the SK 1586 * bit controls the clock input to the EEPROM). A "0" is 1587 * shifted out to the EEPROM by setting "DI" to "0" and then 1588 * raising and then lowering the clock. 1589 */ 1590 if (data & mask) 1591 eec |= IXGBE_EEC_DI; 1592 else 1593 eec &= ~IXGBE_EEC_DI; 1594 1595 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1596 IXGBE_WRITE_FLUSH(hw); 1597 1598 udelay(1); 1599 1600 ixgbe_raise_eeprom_clk(hw, &eec); 1601 ixgbe_lower_eeprom_clk(hw, &eec); 1602 1603 /* 1604 * Shift mask to signify next bit of data to shift in to the 1605 * EEPROM 1606 */ 1607 mask = mask >> 1; 1608 } 1609 1610 /* We leave the "DI" bit set to "0" when we leave this routine. */ 1611 eec &= ~IXGBE_EEC_DI; 1612 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1613 IXGBE_WRITE_FLUSH(hw); 1614 } 1615 1616 /** 1617 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 1618 * @hw: pointer to hardware structure 1619 **/ 1620 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 1621 { 1622 u32 eec; 1623 u32 i; 1624 u16 data = 0; 1625 1626 /* 1627 * In order to read a register from the EEPROM, we need to shift 1628 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 1629 * the clock input to the EEPROM (setting the SK bit), and then reading 1630 * the value of the "DO" bit. During this "shifting in" process the 1631 * "DI" bit should always be clear. 1632 */ 1633 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1634 1635 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 1636 1637 for (i = 0; i < count; i++) { 1638 data = data << 1; 1639 ixgbe_raise_eeprom_clk(hw, &eec); 1640 1641 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1642 1643 eec &= ~(IXGBE_EEC_DI); 1644 if (eec & IXGBE_EEC_DO) 1645 data |= 1; 1646 1647 ixgbe_lower_eeprom_clk(hw, &eec); 1648 } 1649 1650 return data; 1651 } 1652 1653 /** 1654 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1655 * @hw: pointer to hardware structure 1656 * @eec: EEC register's current value 1657 **/ 1658 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1659 { 1660 /* 1661 * Raise the clock input to the EEPROM 1662 * (setting the SK bit), then delay 1663 */ 1664 *eec = *eec | IXGBE_EEC_SK; 1665 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); 1666 IXGBE_WRITE_FLUSH(hw); 1667 udelay(1); 1668 } 1669 1670 /** 1671 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1672 * @hw: pointer to hardware structure 1673 * @eecd: EECD's current value 1674 **/ 1675 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1676 { 1677 /* 1678 * Lower the clock input to the EEPROM (clearing the SK bit), then 1679 * delay 1680 */ 1681 *eec = *eec & ~IXGBE_EEC_SK; 1682 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); 1683 IXGBE_WRITE_FLUSH(hw); 1684 udelay(1); 1685 } 1686 1687 /** 1688 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1689 * @hw: pointer to hardware structure 1690 **/ 1691 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 1692 { 1693 u32 eec; 1694 1695 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 1696 1697 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1698 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1699 1700 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1701 IXGBE_WRITE_FLUSH(hw); 1702 1703 udelay(1); 1704 1705 /* Stop requesting EEPROM access */ 1706 eec &= ~IXGBE_EEC_REQ; 1707 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); 1708 1709 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1710 1711 /* 1712 * Delay before attempt to obtain semaphore again to allow FW 1713 * access. semaphore_delay is in ms we need us for usleep_range 1714 */ 1715 usleep_range(hw->eeprom.semaphore_delay * 1000, 1716 hw->eeprom.semaphore_delay * 2000); 1717 } 1718 1719 /** 1720 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 1721 * @hw: pointer to hardware structure 1722 **/ 1723 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 1724 { 1725 u16 i; 1726 u16 j; 1727 u16 checksum = 0; 1728 u16 length = 0; 1729 u16 pointer = 0; 1730 u16 word = 0; 1731 1732 /* Include 0x0-0x3F in the checksum */ 1733 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1734 if (hw->eeprom.ops.read(hw, i, &word)) { 1735 hw_dbg(hw, "EEPROM read failed\n"); 1736 break; 1737 } 1738 checksum += word; 1739 } 1740 1741 /* Include all data from pointers except for the fw pointer */ 1742 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1743 if (hw->eeprom.ops.read(hw, i, &pointer)) { 1744 hw_dbg(hw, "EEPROM read failed\n"); 1745 return IXGBE_ERR_EEPROM; 1746 } 1747 1748 /* If the pointer seems invalid */ 1749 if (pointer == 0xFFFF || pointer == 0) 1750 continue; 1751 1752 if (hw->eeprom.ops.read(hw, pointer, &length)) { 1753 hw_dbg(hw, "EEPROM read failed\n"); 1754 return IXGBE_ERR_EEPROM; 1755 } 1756 1757 if (length == 0xFFFF || length == 0) 1758 continue; 1759 1760 for (j = pointer + 1; j <= pointer + length; j++) { 1761 if (hw->eeprom.ops.read(hw, j, &word)) { 1762 hw_dbg(hw, "EEPROM read failed\n"); 1763 return IXGBE_ERR_EEPROM; 1764 } 1765 checksum += word; 1766 } 1767 } 1768 1769 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1770 1771 return (s32)checksum; 1772 } 1773 1774 /** 1775 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1776 * @hw: pointer to hardware structure 1777 * @checksum_val: calculated checksum 1778 * 1779 * Performs checksum calculation and validates the EEPROM checksum. If the 1780 * caller does not need checksum_val, the value can be NULL. 1781 **/ 1782 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1783 u16 *checksum_val) 1784 { 1785 s32 status; 1786 u16 checksum; 1787 u16 read_checksum = 0; 1788 1789 /* 1790 * Read the first word from the EEPROM. If this times out or fails, do 1791 * not continue or we could be in for a very long wait while every 1792 * EEPROM read fails 1793 */ 1794 status = hw->eeprom.ops.read(hw, 0, &checksum); 1795 if (status) { 1796 hw_dbg(hw, "EEPROM read failed\n"); 1797 return status; 1798 } 1799 1800 status = hw->eeprom.ops.calc_checksum(hw); 1801 if (status < 0) 1802 return status; 1803 1804 checksum = (u16)(status & 0xffff); 1805 1806 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1807 if (status) { 1808 hw_dbg(hw, "EEPROM read failed\n"); 1809 return status; 1810 } 1811 1812 /* Verify read checksum from EEPROM is the same as 1813 * calculated checksum 1814 */ 1815 if (read_checksum != checksum) 1816 status = IXGBE_ERR_EEPROM_CHECKSUM; 1817 1818 /* If the user cares, return the calculated checksum */ 1819 if (checksum_val) 1820 *checksum_val = checksum; 1821 1822 return status; 1823 } 1824 1825 /** 1826 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1827 * @hw: pointer to hardware structure 1828 **/ 1829 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1830 { 1831 s32 status; 1832 u16 checksum; 1833 1834 /* 1835 * Read the first word from the EEPROM. If this times out or fails, do 1836 * not continue or we could be in for a very long wait while every 1837 * EEPROM read fails 1838 */ 1839 status = hw->eeprom.ops.read(hw, 0, &checksum); 1840 if (status) { 1841 hw_dbg(hw, "EEPROM read failed\n"); 1842 return status; 1843 } 1844 1845 status = hw->eeprom.ops.calc_checksum(hw); 1846 if (status < 0) 1847 return status; 1848 1849 checksum = (u16)(status & 0xffff); 1850 1851 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 1852 1853 return status; 1854 } 1855 1856 /** 1857 * ixgbe_set_rar_generic - Set Rx address register 1858 * @hw: pointer to hardware structure 1859 * @index: Receive address register to write 1860 * @addr: Address to put into receive address register 1861 * @vmdq: VMDq "set" or "pool" index 1862 * @enable_addr: set flag that address is active 1863 * 1864 * Puts an ethernet address into a receive address register. 1865 **/ 1866 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1867 u32 enable_addr) 1868 { 1869 u32 rar_low, rar_high; 1870 u32 rar_entries = hw->mac.num_rar_entries; 1871 1872 /* Make sure we are using a valid rar index range */ 1873 if (index >= rar_entries) { 1874 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1875 return IXGBE_ERR_INVALID_ARGUMENT; 1876 } 1877 1878 /* setup VMDq pool selection before this RAR gets enabled */ 1879 hw->mac.ops.set_vmdq(hw, index, vmdq); 1880 1881 /* 1882 * HW expects these in little endian so we reverse the byte 1883 * order from network order (big endian) to little endian 1884 */ 1885 rar_low = ((u32)addr[0] | 1886 ((u32)addr[1] << 8) | 1887 ((u32)addr[2] << 16) | 1888 ((u32)addr[3] << 24)); 1889 /* 1890 * Some parts put the VMDq setting in the extra RAH bits, 1891 * so save everything except the lower 16 bits that hold part 1892 * of the address and the address valid bit. 1893 */ 1894 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1895 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1896 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1897 1898 if (enable_addr != 0) 1899 rar_high |= IXGBE_RAH_AV; 1900 1901 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1902 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1903 1904 return 0; 1905 } 1906 1907 /** 1908 * ixgbe_clear_rar_generic - Remove Rx address register 1909 * @hw: pointer to hardware structure 1910 * @index: Receive address register to write 1911 * 1912 * Clears an ethernet address from a receive address register. 1913 **/ 1914 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1915 { 1916 u32 rar_high; 1917 u32 rar_entries = hw->mac.num_rar_entries; 1918 1919 /* Make sure we are using a valid rar index range */ 1920 if (index >= rar_entries) { 1921 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1922 return IXGBE_ERR_INVALID_ARGUMENT; 1923 } 1924 1925 /* 1926 * Some parts put the VMDq setting in the extra RAH bits, 1927 * so save everything except the lower 16 bits that hold part 1928 * of the address and the address valid bit. 1929 */ 1930 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1931 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1932 1933 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1934 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1935 1936 /* clear VMDq pool/queue selection for this RAR */ 1937 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1938 1939 return 0; 1940 } 1941 1942 /** 1943 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1944 * @hw: pointer to hardware structure 1945 * 1946 * Places the MAC address in receive address register 0 and clears the rest 1947 * of the receive address registers. Clears the multicast table. Assumes 1948 * the receiver is in reset when the routine is called. 1949 **/ 1950 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1951 { 1952 u32 i; 1953 u32 rar_entries = hw->mac.num_rar_entries; 1954 1955 /* 1956 * If the current mac address is valid, assume it is a software override 1957 * to the permanent address. 1958 * Otherwise, use the permanent address from the eeprom. 1959 */ 1960 if (!is_valid_ether_addr(hw->mac.addr)) { 1961 /* Get the MAC address from the RAR0 for later reference */ 1962 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1963 1964 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr); 1965 } else { 1966 /* Setup the receive address. */ 1967 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); 1968 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr); 1969 1970 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1971 } 1972 1973 /* clear VMDq pool/queue selection for RAR 0 */ 1974 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 1975 1976 hw->addr_ctrl.overflow_promisc = 0; 1977 1978 hw->addr_ctrl.rar_used_count = 1; 1979 1980 /* Zero out the other receive addresses. */ 1981 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); 1982 for (i = 1; i < rar_entries; i++) { 1983 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1984 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1985 } 1986 1987 /* Clear the MTA */ 1988 hw->addr_ctrl.mta_in_use = 0; 1989 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1990 1991 hw_dbg(hw, " Clearing MTA\n"); 1992 for (i = 0; i < hw->mac.mcft_size; i++) 1993 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1994 1995 if (hw->mac.ops.init_uta_tables) 1996 hw->mac.ops.init_uta_tables(hw); 1997 1998 return 0; 1999 } 2000 2001 /** 2002 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 2003 * @hw: pointer to hardware structure 2004 * @mc_addr: the multicast address 2005 * 2006 * Extracts the 12 bits, from a multicast address, to determine which 2007 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 2008 * incoming rx multicast addresses, to determine the bit-vector to check in 2009 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 2010 * by the MO field of the MCSTCTRL. The MO field is set during initialization 2011 * to mc_filter_type. 2012 **/ 2013 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 2014 { 2015 u32 vector = 0; 2016 2017 switch (hw->mac.mc_filter_type) { 2018 case 0: /* use bits [47:36] of the address */ 2019 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 2020 break; 2021 case 1: /* use bits [46:35] of the address */ 2022 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 2023 break; 2024 case 2: /* use bits [45:34] of the address */ 2025 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 2026 break; 2027 case 3: /* use bits [43:32] of the address */ 2028 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 2029 break; 2030 default: /* Invalid mc_filter_type */ 2031 hw_dbg(hw, "MC filter type param set incorrectly\n"); 2032 break; 2033 } 2034 2035 /* vector can only be 12-bits or boundary will be exceeded */ 2036 vector &= 0xFFF; 2037 return vector; 2038 } 2039 2040 /** 2041 * ixgbe_set_mta - Set bit-vector in multicast table 2042 * @hw: pointer to hardware structure 2043 * @hash_value: Multicast address hash value 2044 * 2045 * Sets the bit-vector in the multicast table. 2046 **/ 2047 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2048 { 2049 u32 vector; 2050 u32 vector_bit; 2051 u32 vector_reg; 2052 2053 hw->addr_ctrl.mta_in_use++; 2054 2055 vector = ixgbe_mta_vector(hw, mc_addr); 2056 hw_dbg(hw, " bit-vector = 0x%03X\n", vector); 2057 2058 /* 2059 * The MTA is a register array of 128 32-bit registers. It is treated 2060 * like an array of 4096 bits. We want to set bit 2061 * BitArray[vector_value]. So we figure out what register the bit is 2062 * in, read it, OR in the new bit, then write back the new value. The 2063 * register is determined by the upper 7 bits of the vector value and 2064 * the bit within that register are determined by the lower 5 bits of 2065 * the value. 2066 */ 2067 vector_reg = (vector >> 5) & 0x7F; 2068 vector_bit = vector & 0x1F; 2069 hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit); 2070 } 2071 2072 /** 2073 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2074 * @hw: pointer to hardware structure 2075 * @netdev: pointer to net device structure 2076 * 2077 * The given list replaces any existing list. Clears the MC addrs from receive 2078 * address registers and the multicast table. Uses unused receive address 2079 * registers for the first multicast addresses, and hashes the rest into the 2080 * multicast table. 2081 **/ 2082 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, 2083 struct net_device *netdev) 2084 { 2085 struct netdev_hw_addr *ha; 2086 u32 i; 2087 2088 /* 2089 * Set the new number of MC addresses that we are being requested to 2090 * use. 2091 */ 2092 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); 2093 hw->addr_ctrl.mta_in_use = 0; 2094 2095 /* Clear mta_shadow */ 2096 hw_dbg(hw, " Clearing MTA\n"); 2097 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2098 2099 /* Update mta shadow */ 2100 netdev_for_each_mc_addr(ha, netdev) { 2101 hw_dbg(hw, " Adding the multicast addresses:\n"); 2102 ixgbe_set_mta(hw, ha->addr); 2103 } 2104 2105 /* Enable mta */ 2106 for (i = 0; i < hw->mac.mcft_size; i++) 2107 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2108 hw->mac.mta_shadow[i]); 2109 2110 if (hw->addr_ctrl.mta_in_use > 0) 2111 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2112 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2113 2114 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); 2115 return 0; 2116 } 2117 2118 /** 2119 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2120 * @hw: pointer to hardware structure 2121 * 2122 * Enables multicast address in RAR and the use of the multicast hash table. 2123 **/ 2124 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2125 { 2126 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2127 2128 if (a->mta_in_use > 0) 2129 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2130 hw->mac.mc_filter_type); 2131 2132 return 0; 2133 } 2134 2135 /** 2136 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2137 * @hw: pointer to hardware structure 2138 * 2139 * Disables multicast address in RAR and the use of the multicast hash table. 2140 **/ 2141 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2142 { 2143 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2144 2145 if (a->mta_in_use > 0) 2146 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2147 2148 return 0; 2149 } 2150 2151 /** 2152 * ixgbe_fc_enable_generic - Enable flow control 2153 * @hw: pointer to hardware structure 2154 * 2155 * Enable flow control according to the current settings. 2156 **/ 2157 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2158 { 2159 u32 mflcn_reg, fccfg_reg; 2160 u32 reg; 2161 u32 fcrtl, fcrth; 2162 int i; 2163 2164 /* Validate the water mark configuration. */ 2165 if (!hw->fc.pause_time) 2166 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2167 2168 /* Low water mark of zero causes XOFF floods */ 2169 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 2170 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2171 hw->fc.high_water[i]) { 2172 if (!hw->fc.low_water[i] || 2173 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2174 hw_dbg(hw, "Invalid water mark configuration\n"); 2175 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2176 } 2177 } 2178 } 2179 2180 /* Negotiate the fc mode to use */ 2181 hw->mac.ops.fc_autoneg(hw); 2182 2183 /* Disable any previous flow control settings */ 2184 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2185 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2186 2187 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2188 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2189 2190 /* 2191 * The possible values of fc.current_mode are: 2192 * 0: Flow control is completely disabled 2193 * 1: Rx flow control is enabled (we can receive pause frames, 2194 * but not send pause frames). 2195 * 2: Tx flow control is enabled (we can send pause frames but 2196 * we do not support receiving pause frames). 2197 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2198 * other: Invalid. 2199 */ 2200 switch (hw->fc.current_mode) { 2201 case ixgbe_fc_none: 2202 /* 2203 * Flow control is disabled by software override or autoneg. 2204 * The code below will actually disable it in the HW. 2205 */ 2206 break; 2207 case ixgbe_fc_rx_pause: 2208 /* 2209 * Rx Flow control is enabled and Tx Flow control is 2210 * disabled by software override. Since there really 2211 * isn't a way to advertise that we are capable of RX 2212 * Pause ONLY, we will advertise that we support both 2213 * symmetric and asymmetric Rx PAUSE. Later, we will 2214 * disable the adapter's ability to send PAUSE frames. 2215 */ 2216 mflcn_reg |= IXGBE_MFLCN_RFCE; 2217 break; 2218 case ixgbe_fc_tx_pause: 2219 /* 2220 * Tx Flow control is enabled, and Rx Flow control is 2221 * disabled by software override. 2222 */ 2223 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2224 break; 2225 case ixgbe_fc_full: 2226 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2227 mflcn_reg |= IXGBE_MFLCN_RFCE; 2228 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2229 break; 2230 default: 2231 hw_dbg(hw, "Flow control param set incorrectly\n"); 2232 return IXGBE_ERR_CONFIG; 2233 } 2234 2235 /* Set 802.3x based flow control settings. */ 2236 mflcn_reg |= IXGBE_MFLCN_DPF; 2237 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2238 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2239 2240 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2241 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 2242 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2243 hw->fc.high_water[i]) { 2244 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2245 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2246 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2247 } else { 2248 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2249 /* 2250 * In order to prevent Tx hangs when the internal Tx 2251 * switch is enabled we must set the high water mark 2252 * to the Rx packet buffer size - 24KB. This allows 2253 * the Tx switch to function even under heavy Rx 2254 * workloads. 2255 */ 2256 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2257 } 2258 2259 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2260 } 2261 2262 /* Configure pause time (2 TCs per register) */ 2263 reg = hw->fc.pause_time * 0x00010001; 2264 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 2265 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2266 2267 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2268 2269 return 0; 2270 } 2271 2272 /** 2273 * ixgbe_negotiate_fc - Negotiate flow control 2274 * @hw: pointer to hardware structure 2275 * @adv_reg: flow control advertised settings 2276 * @lp_reg: link partner's flow control settings 2277 * @adv_sym: symmetric pause bit in advertisement 2278 * @adv_asm: asymmetric pause bit in advertisement 2279 * @lp_sym: symmetric pause bit in link partner advertisement 2280 * @lp_asm: asymmetric pause bit in link partner advertisement 2281 * 2282 * Find the intersection between advertised settings and link partner's 2283 * advertised settings 2284 **/ 2285 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2286 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2287 { 2288 if ((!(adv_reg)) || (!(lp_reg))) 2289 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2290 2291 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2292 /* 2293 * Now we need to check if the user selected Rx ONLY 2294 * of pause frames. In this case, we had to advertise 2295 * FULL flow control because we could not advertise RX 2296 * ONLY. Hence, we must now check to see if we need to 2297 * turn OFF the TRANSMISSION of PAUSE frames. 2298 */ 2299 if (hw->fc.requested_mode == ixgbe_fc_full) { 2300 hw->fc.current_mode = ixgbe_fc_full; 2301 hw_dbg(hw, "Flow Control = FULL.\n"); 2302 } else { 2303 hw->fc.current_mode = ixgbe_fc_rx_pause; 2304 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n"); 2305 } 2306 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2307 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2308 hw->fc.current_mode = ixgbe_fc_tx_pause; 2309 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); 2310 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2311 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2312 hw->fc.current_mode = ixgbe_fc_rx_pause; 2313 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); 2314 } else { 2315 hw->fc.current_mode = ixgbe_fc_none; 2316 hw_dbg(hw, "Flow Control = NONE.\n"); 2317 } 2318 return 0; 2319 } 2320 2321 /** 2322 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 2323 * @hw: pointer to hardware structure 2324 * 2325 * Enable flow control according on 1 gig fiber. 2326 **/ 2327 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 2328 { 2329 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 2330 s32 ret_val; 2331 2332 /* 2333 * On multispeed fiber at 1g, bail out if 2334 * - link is up but AN did not complete, or if 2335 * - link is up and AN completed but timed out 2336 */ 2337 2338 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 2339 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 2340 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) 2341 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2342 2343 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2344 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 2345 2346 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 2347 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 2348 IXGBE_PCS1GANA_ASM_PAUSE, 2349 IXGBE_PCS1GANA_SYM_PAUSE, 2350 IXGBE_PCS1GANA_ASM_PAUSE); 2351 2352 return ret_val; 2353 } 2354 2355 /** 2356 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 2357 * @hw: pointer to hardware structure 2358 * 2359 * Enable flow control according to IEEE clause 37. 2360 **/ 2361 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 2362 { 2363 u32 links2, anlp1_reg, autoc_reg, links; 2364 s32 ret_val; 2365 2366 /* 2367 * On backplane, bail out if 2368 * - backplane autoneg was not completed, or if 2369 * - we are 82599 and link partner is not AN enabled 2370 */ 2371 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 2372 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) 2373 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2374 2375 if (hw->mac.type == ixgbe_mac_82599EB) { 2376 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 2377 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) 2378 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2379 } 2380 /* 2381 * Read the 10g AN autoc and LP ability registers and resolve 2382 * local flow control settings accordingly 2383 */ 2384 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2385 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2386 2387 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 2388 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 2389 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 2390 2391 return ret_val; 2392 } 2393 2394 /** 2395 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 2396 * @hw: pointer to hardware structure 2397 * 2398 * Enable flow control according to IEEE clause 37. 2399 **/ 2400 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 2401 { 2402 u16 technology_ability_reg = 0; 2403 u16 lp_technology_ability_reg = 0; 2404 2405 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 2406 MDIO_MMD_AN, 2407 &technology_ability_reg); 2408 hw->phy.ops.read_reg(hw, MDIO_AN_LPA, 2409 MDIO_MMD_AN, 2410 &lp_technology_ability_reg); 2411 2412 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 2413 (u32)lp_technology_ability_reg, 2414 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 2415 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 2416 } 2417 2418 /** 2419 * ixgbe_fc_autoneg - Configure flow control 2420 * @hw: pointer to hardware structure 2421 * 2422 * Compares our advertised flow control capabilities to those advertised by 2423 * our link partner, and determines the proper flow control mode to use. 2424 **/ 2425 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 2426 { 2427 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2428 ixgbe_link_speed speed; 2429 bool link_up; 2430 2431 /* 2432 * AN should have completed when the cable was plugged in. 2433 * Look for reasons to bail out. Bail out if: 2434 * - FC autoneg is disabled, or if 2435 * - link is not up. 2436 * 2437 * Since we're being called from an LSC, link is already known to be up. 2438 * So use link_up_wait_to_complete=false. 2439 */ 2440 if (hw->fc.disable_fc_autoneg) 2441 goto out; 2442 2443 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2444 if (!link_up) 2445 goto out; 2446 2447 switch (hw->phy.media_type) { 2448 /* Autoneg flow control on fiber adapters */ 2449 case ixgbe_media_type_fiber: 2450 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 2451 ret_val = ixgbe_fc_autoneg_fiber(hw); 2452 break; 2453 2454 /* Autoneg flow control on backplane adapters */ 2455 case ixgbe_media_type_backplane: 2456 ret_val = ixgbe_fc_autoneg_backplane(hw); 2457 break; 2458 2459 /* Autoneg flow control on copper adapters */ 2460 case ixgbe_media_type_copper: 2461 if (ixgbe_device_supports_autoneg_fc(hw)) 2462 ret_val = ixgbe_fc_autoneg_copper(hw); 2463 break; 2464 2465 default: 2466 break; 2467 } 2468 2469 out: 2470 if (ret_val == 0) { 2471 hw->fc.fc_was_autonegged = true; 2472 } else { 2473 hw->fc.fc_was_autonegged = false; 2474 hw->fc.current_mode = hw->fc.requested_mode; 2475 } 2476 } 2477 2478 /** 2479 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 2480 * @hw: pointer to hardware structure 2481 * 2482 * System-wide timeout range is encoded in PCIe Device Control2 register. 2483 * 2484 * Add 10% to specified maximum and return the number of times to poll for 2485 * completion timeout, in units of 100 microsec. Never return less than 2486 * 800 = 80 millisec. 2487 **/ 2488 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 2489 { 2490 s16 devctl2; 2491 u32 pollcnt; 2492 2493 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); 2494 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 2495 2496 switch (devctl2) { 2497 case IXGBE_PCIDEVCTRL2_65_130ms: 2498 pollcnt = 1300; /* 130 millisec */ 2499 break; 2500 case IXGBE_PCIDEVCTRL2_260_520ms: 2501 pollcnt = 5200; /* 520 millisec */ 2502 break; 2503 case IXGBE_PCIDEVCTRL2_1_2s: 2504 pollcnt = 20000; /* 2 sec */ 2505 break; 2506 case IXGBE_PCIDEVCTRL2_4_8s: 2507 pollcnt = 80000; /* 8 sec */ 2508 break; 2509 case IXGBE_PCIDEVCTRL2_17_34s: 2510 pollcnt = 34000; /* 34 sec */ 2511 break; 2512 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 2513 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 2514 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 2515 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 2516 default: 2517 pollcnt = 800; /* 80 millisec minimum */ 2518 break; 2519 } 2520 2521 /* add 10% to spec maximum */ 2522 return (pollcnt * 11) / 10; 2523 } 2524 2525 /** 2526 * ixgbe_disable_pcie_master - Disable PCI-express master access 2527 * @hw: pointer to hardware structure 2528 * 2529 * Disables PCI-Express master access and verifies there are no pending 2530 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 2531 * bit hasn't caused the master requests to be disabled, else 0 2532 * is returned signifying master requests disabled. 2533 **/ 2534 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 2535 { 2536 u32 i, poll; 2537 u16 value; 2538 2539 /* Always set this bit to ensure any future transactions are blocked */ 2540 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 2541 2542 /* Poll for bit to read as set */ 2543 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2544 if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS) 2545 break; 2546 usleep_range(100, 120); 2547 } 2548 if (i >= IXGBE_PCI_MASTER_DISABLE_TIMEOUT) { 2549 hw_dbg(hw, "GIO disable did not set - requesting resets\n"); 2550 goto gio_disable_fail; 2551 } 2552 2553 /* Exit if master requests are blocked */ 2554 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 2555 ixgbe_removed(hw->hw_addr)) 2556 return 0; 2557 2558 /* Poll for master request bit to clear */ 2559 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2560 udelay(100); 2561 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2562 return 0; 2563 } 2564 2565 /* 2566 * Two consecutive resets are required via CTRL.RST per datasheet 2567 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 2568 * of this need. The first reset prevents new master requests from 2569 * being issued by our device. We then must wait 1usec or more for any 2570 * remaining completions from the PCIe bus to trickle in, and then reset 2571 * again to clear out any effects they may have had on our device. 2572 */ 2573 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n"); 2574 gio_disable_fail: 2575 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2576 2577 if (hw->mac.type >= ixgbe_mac_X550) 2578 return 0; 2579 2580 /* 2581 * Before proceeding, make sure that the PCIe block does not have 2582 * transactions pending. 2583 */ 2584 poll = ixgbe_pcie_timeout_poll(hw); 2585 for (i = 0; i < poll; i++) { 2586 udelay(100); 2587 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); 2588 if (ixgbe_removed(hw->hw_addr)) 2589 return 0; 2590 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 2591 return 0; 2592 } 2593 2594 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n"); 2595 return IXGBE_ERR_MASTER_REQUESTS_PENDING; 2596 } 2597 2598 /** 2599 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 2600 * @hw: pointer to hardware structure 2601 * @mask: Mask to specify which semaphore to acquire 2602 * 2603 * Acquires the SWFW semaphore through the GSSR register for the specified 2604 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2605 **/ 2606 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 2607 { 2608 u32 gssr = 0; 2609 u32 swmask = mask; 2610 u32 fwmask = mask << 5; 2611 u32 timeout = 200; 2612 u32 i; 2613 2614 for (i = 0; i < timeout; i++) { 2615 /* 2616 * SW NVM semaphore bit is used for access to all 2617 * SW_FW_SYNC bits (not just NVM) 2618 */ 2619 if (ixgbe_get_eeprom_semaphore(hw)) 2620 return IXGBE_ERR_SWFW_SYNC; 2621 2622 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2623 if (!(gssr & (fwmask | swmask))) { 2624 gssr |= swmask; 2625 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2626 ixgbe_release_eeprom_semaphore(hw); 2627 return 0; 2628 } else { 2629 /* Resource is currently in use by FW or SW */ 2630 ixgbe_release_eeprom_semaphore(hw); 2631 usleep_range(5000, 10000); 2632 } 2633 } 2634 2635 /* If time expired clear the bits holding the lock and retry */ 2636 if (gssr & (fwmask | swmask)) 2637 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 2638 2639 usleep_range(5000, 10000); 2640 return IXGBE_ERR_SWFW_SYNC; 2641 } 2642 2643 /** 2644 * ixgbe_release_swfw_sync - Release SWFW semaphore 2645 * @hw: pointer to hardware structure 2646 * @mask: Mask to specify which semaphore to release 2647 * 2648 * Releases the SWFW semaphore through the GSSR register for the specified 2649 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2650 **/ 2651 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 2652 { 2653 u32 gssr; 2654 u32 swmask = mask; 2655 2656 ixgbe_get_eeprom_semaphore(hw); 2657 2658 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2659 gssr &= ~swmask; 2660 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2661 2662 ixgbe_release_eeprom_semaphore(hw); 2663 } 2664 2665 /** 2666 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 2667 * @hw: pointer to hardware structure 2668 * @reg_val: Value we read from AUTOC 2669 * @locked: bool to indicate whether the SW/FW lock should be taken. Never 2670 * true in this the generic case. 2671 * 2672 * The default case requires no protection so just to the register read. 2673 **/ 2674 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 2675 { 2676 *locked = false; 2677 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2678 return 0; 2679 } 2680 2681 /** 2682 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 2683 * @hw: pointer to hardware structure 2684 * @reg_val: value to write to AUTOC 2685 * @locked: bool to indicate whether the SW/FW lock was already taken by 2686 * previous read. 2687 **/ 2688 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 2689 { 2690 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 2691 return 0; 2692 } 2693 2694 /** 2695 * ixgbe_disable_rx_buff_generic - Stops the receive data path 2696 * @hw: pointer to hardware structure 2697 * 2698 * Stops the receive data path and waits for the HW to internally 2699 * empty the Rx security block. 2700 **/ 2701 s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw) 2702 { 2703 #define IXGBE_MAX_SECRX_POLL 40 2704 int i; 2705 int secrxreg; 2706 2707 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2708 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 2709 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2710 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 2711 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 2712 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 2713 break; 2714 else 2715 /* Use interrupt-safe sleep just in case */ 2716 udelay(1000); 2717 } 2718 2719 /* For informational purposes only */ 2720 if (i >= IXGBE_MAX_SECRX_POLL) 2721 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n"); 2722 2723 return 0; 2724 2725 } 2726 2727 /** 2728 * ixgbe_enable_rx_buff - Enables the receive data path 2729 * @hw: pointer to hardware structure 2730 * 2731 * Enables the receive data path 2732 **/ 2733 s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw) 2734 { 2735 u32 secrxreg; 2736 2737 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2738 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 2739 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2740 IXGBE_WRITE_FLUSH(hw); 2741 2742 return 0; 2743 } 2744 2745 /** 2746 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 2747 * @hw: pointer to hardware structure 2748 * @regval: register value to write to RXCTRL 2749 * 2750 * Enables the Rx DMA unit 2751 **/ 2752 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 2753 { 2754 if (regval & IXGBE_RXCTRL_RXEN) 2755 hw->mac.ops.enable_rx(hw); 2756 else 2757 hw->mac.ops.disable_rx(hw); 2758 2759 return 0; 2760 } 2761 2762 /** 2763 * ixgbe_blink_led_start_generic - Blink LED based on index. 2764 * @hw: pointer to hardware structure 2765 * @index: led number to blink 2766 **/ 2767 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 2768 { 2769 ixgbe_link_speed speed = 0; 2770 bool link_up = false; 2771 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2772 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2773 bool locked = false; 2774 s32 ret_val; 2775 2776 if (index > 3) 2777 return IXGBE_ERR_PARAM; 2778 2779 /* 2780 * Link must be up to auto-blink the LEDs; 2781 * Force it if link is down. 2782 */ 2783 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2784 2785 if (!link_up) { 2786 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 2787 if (ret_val) 2788 return ret_val; 2789 2790 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2791 autoc_reg |= IXGBE_AUTOC_FLU; 2792 2793 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 2794 if (ret_val) 2795 return ret_val; 2796 2797 IXGBE_WRITE_FLUSH(hw); 2798 2799 usleep_range(10000, 20000); 2800 } 2801 2802 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2803 led_reg |= IXGBE_LED_BLINK(index); 2804 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2805 IXGBE_WRITE_FLUSH(hw); 2806 2807 return 0; 2808 } 2809 2810 /** 2811 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 2812 * @hw: pointer to hardware structure 2813 * @index: led number to stop blinking 2814 **/ 2815 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 2816 { 2817 u32 autoc_reg = 0; 2818 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2819 bool locked = false; 2820 s32 ret_val; 2821 2822 if (index > 3) 2823 return IXGBE_ERR_PARAM; 2824 2825 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 2826 if (ret_val) 2827 return ret_val; 2828 2829 autoc_reg &= ~IXGBE_AUTOC_FLU; 2830 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2831 2832 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 2833 if (ret_val) 2834 return ret_val; 2835 2836 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2837 led_reg &= ~IXGBE_LED_BLINK(index); 2838 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 2839 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2840 IXGBE_WRITE_FLUSH(hw); 2841 2842 return 0; 2843 } 2844 2845 /** 2846 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 2847 * @hw: pointer to hardware structure 2848 * @san_mac_offset: SAN MAC address offset 2849 * 2850 * This function will read the EEPROM location for the SAN MAC address 2851 * pointer, and returns the value at that location. This is used in both 2852 * get and set mac_addr routines. 2853 **/ 2854 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 2855 u16 *san_mac_offset) 2856 { 2857 s32 ret_val; 2858 2859 /* 2860 * First read the EEPROM pointer to see if the MAC addresses are 2861 * available. 2862 */ 2863 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 2864 san_mac_offset); 2865 if (ret_val) 2866 hw_err(hw, "eeprom read at offset %d failed\n", 2867 IXGBE_SAN_MAC_ADDR_PTR); 2868 2869 return ret_val; 2870 } 2871 2872 /** 2873 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 2874 * @hw: pointer to hardware structure 2875 * @san_mac_addr: SAN MAC address 2876 * 2877 * Reads the SAN MAC address from the EEPROM, if it's available. This is 2878 * per-port, so set_lan_id() must be called before reading the addresses. 2879 * set_lan_id() is called by identify_sfp(), but this cannot be relied 2880 * upon for non-SFP connections, so we must call it here. 2881 **/ 2882 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2883 { 2884 u16 san_mac_data, san_mac_offset; 2885 u8 i; 2886 s32 ret_val; 2887 2888 /* 2889 * First read the EEPROM pointer to see if the MAC addresses are 2890 * available. If they're not, no point in calling set_lan_id() here. 2891 */ 2892 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2893 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 2894 2895 goto san_mac_addr_clr; 2896 2897 /* make sure we know which port we need to program */ 2898 hw->mac.ops.set_lan_id(hw); 2899 /* apply the port offset to the address offset */ 2900 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2901 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2902 for (i = 0; i < 3; i++) { 2903 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 2904 &san_mac_data); 2905 if (ret_val) { 2906 hw_err(hw, "eeprom read at offset %d failed\n", 2907 san_mac_offset); 2908 goto san_mac_addr_clr; 2909 } 2910 san_mac_addr[i * 2] = (u8)(san_mac_data); 2911 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 2912 san_mac_offset++; 2913 } 2914 return 0; 2915 2916 san_mac_addr_clr: 2917 /* No addresses available in this EEPROM. It's not necessarily an 2918 * error though, so just wipe the local address and return. 2919 */ 2920 for (i = 0; i < 6; i++) 2921 san_mac_addr[i] = 0xFF; 2922 return ret_val; 2923 } 2924 2925 /** 2926 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 2927 * @hw: pointer to hardware structure 2928 * 2929 * Read PCIe configuration space, and get the MSI-X vector count from 2930 * the capabilities table. 2931 **/ 2932 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 2933 { 2934 u16 msix_count; 2935 u16 max_msix_count; 2936 u16 pcie_offset; 2937 2938 switch (hw->mac.type) { 2939 case ixgbe_mac_82598EB: 2940 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 2941 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 2942 break; 2943 case ixgbe_mac_82599EB: 2944 case ixgbe_mac_X540: 2945 case ixgbe_mac_X550: 2946 case ixgbe_mac_X550EM_x: 2947 case ixgbe_mac_x550em_a: 2948 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 2949 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 2950 break; 2951 default: 2952 return 1; 2953 } 2954 2955 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset); 2956 if (ixgbe_removed(hw->hw_addr)) 2957 msix_count = 0; 2958 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 2959 2960 /* MSI-X count is zero-based in HW */ 2961 msix_count++; 2962 2963 if (msix_count > max_msix_count) 2964 msix_count = max_msix_count; 2965 2966 return msix_count; 2967 } 2968 2969 /** 2970 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 2971 * @hw: pointer to hardware struct 2972 * @rar: receive address register index to disassociate 2973 * @vmdq: VMDq pool index to remove from the rar 2974 **/ 2975 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2976 { 2977 u32 mpsar_lo, mpsar_hi; 2978 u32 rar_entries = hw->mac.num_rar_entries; 2979 2980 /* Make sure we are using a valid rar index range */ 2981 if (rar >= rar_entries) { 2982 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 2983 return IXGBE_ERR_INVALID_ARGUMENT; 2984 } 2985 2986 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2987 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2988 2989 if (ixgbe_removed(hw->hw_addr)) 2990 return 0; 2991 2992 if (!mpsar_lo && !mpsar_hi) 2993 return 0; 2994 2995 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 2996 if (mpsar_lo) { 2997 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 2998 mpsar_lo = 0; 2999 } 3000 if (mpsar_hi) { 3001 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3002 mpsar_hi = 0; 3003 } 3004 } else if (vmdq < 32) { 3005 mpsar_lo &= ~BIT(vmdq); 3006 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 3007 } else { 3008 mpsar_hi &= ~BIT(vmdq - 32); 3009 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 3010 } 3011 3012 /* was that the last pool using this rar? */ 3013 if (mpsar_lo == 0 && mpsar_hi == 0 && 3014 rar != 0 && rar != hw->mac.san_mac_rar_index) 3015 hw->mac.ops.clear_rar(hw, rar); 3016 3017 return 0; 3018 } 3019 3020 /** 3021 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 3022 * @hw: pointer to hardware struct 3023 * @rar: receive address register index to associate with a VMDq index 3024 * @vmdq: VMDq pool index 3025 **/ 3026 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3027 { 3028 u32 mpsar; 3029 u32 rar_entries = hw->mac.num_rar_entries; 3030 3031 /* Make sure we are using a valid rar index range */ 3032 if (rar >= rar_entries) { 3033 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 3034 return IXGBE_ERR_INVALID_ARGUMENT; 3035 } 3036 3037 if (vmdq < 32) { 3038 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3039 mpsar |= BIT(vmdq); 3040 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3041 } else { 3042 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3043 mpsar |= BIT(vmdq - 32); 3044 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3045 } 3046 return 0; 3047 } 3048 3049 /** 3050 * This function should only be involved in the IOV mode. 3051 * In IOV mode, Default pool is next pool after the number of 3052 * VFs advertized and not 0. 3053 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3054 * 3055 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address 3056 * @hw: pointer to hardware struct 3057 * @vmdq: VMDq pool index 3058 **/ 3059 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3060 { 3061 u32 rar = hw->mac.san_mac_rar_index; 3062 3063 if (vmdq < 32) { 3064 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq)); 3065 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3066 } else { 3067 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3068 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32)); 3069 } 3070 3071 return 0; 3072 } 3073 3074 /** 3075 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3076 * @hw: pointer to hardware structure 3077 **/ 3078 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3079 { 3080 int i; 3081 3082 for (i = 0; i < 128; i++) 3083 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3084 3085 return 0; 3086 } 3087 3088 /** 3089 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3090 * @hw: pointer to hardware structure 3091 * @vlan: VLAN id to write to VLAN filter 3092 * 3093 * return the VLVF index where this VLAN id should be placed 3094 * 3095 **/ 3096 static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) 3097 { 3098 s32 regindex, first_empty_slot; 3099 u32 bits; 3100 3101 /* short cut the special case */ 3102 if (vlan == 0) 3103 return 0; 3104 3105 /* if vlvf_bypass is set we don't want to use an empty slot, we 3106 * will simply bypass the VLVF if there are no entries present in the 3107 * VLVF that contain our VLAN 3108 */ 3109 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0; 3110 3111 /* add VLAN enable bit for comparison */ 3112 vlan |= IXGBE_VLVF_VIEN; 3113 3114 /* Search for the vlan id in the VLVF entries. Save off the first empty 3115 * slot found along the way. 3116 * 3117 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 3118 */ 3119 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { 3120 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3121 if (bits == vlan) 3122 return regindex; 3123 if (!first_empty_slot && !bits) 3124 first_empty_slot = regindex; 3125 } 3126 3127 /* If we are here then we didn't find the VLAN. Return first empty 3128 * slot we found during our search, else error. 3129 */ 3130 if (!first_empty_slot) 3131 hw_dbg(hw, "No space in VLVF.\n"); 3132 3133 return first_empty_slot ? : IXGBE_ERR_NO_SPACE; 3134 } 3135 3136 /** 3137 * ixgbe_set_vfta_generic - Set VLAN filter table 3138 * @hw: pointer to hardware structure 3139 * @vlan: VLAN id to write to VLAN filter 3140 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 3141 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 3142 * @vlvf_bypass: boolean flag indicating updating default pool is okay 3143 * 3144 * Turn on/off specified VLAN in the VLAN filter table. 3145 **/ 3146 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3147 bool vlan_on, bool vlvf_bypass) 3148 { 3149 u32 regidx, vfta_delta, vfta, bits; 3150 s32 vlvf_index; 3151 3152 if ((vlan > 4095) || (vind > 63)) 3153 return IXGBE_ERR_PARAM; 3154 3155 /* 3156 * this is a 2 part operation - first the VFTA, then the 3157 * VLVF and VLVFB if VT Mode is set 3158 * We don't write the VFTA until we know the VLVF part succeeded. 3159 */ 3160 3161 /* Part 1 3162 * The VFTA is a bitstring made up of 128 32-bit registers 3163 * that enable the particular VLAN id, much like the MTA: 3164 * bits[11-5]: which register 3165 * bits[4-0]: which bit in the register 3166 */ 3167 regidx = vlan / 32; 3168 vfta_delta = BIT(vlan % 32); 3169 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); 3170 3171 /* vfta_delta represents the difference between the current value 3172 * of vfta and the value we want in the register. Since the diff 3173 * is an XOR mask we can just update vfta using an XOR. 3174 */ 3175 vfta_delta &= vlan_on ? ~vfta : vfta; 3176 vfta ^= vfta_delta; 3177 3178 /* Part 2 3179 * If VT Mode is set 3180 * Either vlan_on 3181 * make sure the vlan is in VLVF 3182 * set the vind bit in the matching VLVFB 3183 * Or !vlan_on 3184 * clear the pool bit and possibly the vind 3185 */ 3186 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) 3187 goto vfta_update; 3188 3189 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 3190 if (vlvf_index < 0) { 3191 if (vlvf_bypass) 3192 goto vfta_update; 3193 return vlvf_index; 3194 } 3195 3196 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); 3197 3198 /* set the pool bit */ 3199 bits |= BIT(vind % 32); 3200 if (vlan_on) 3201 goto vlvf_update; 3202 3203 /* clear the pool bit */ 3204 bits ^= BIT(vind % 32); 3205 3206 if (!bits && 3207 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 3208 /* Clear VFTA first, then disable VLVF. Otherwise 3209 * we run the risk of stray packets leaking into 3210 * the PF via the default pool 3211 */ 3212 if (vfta_delta) 3213 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 3214 3215 /* disable VLVF and clear remaining bit from pool */ 3216 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 3217 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); 3218 3219 return 0; 3220 } 3221 3222 /* If there are still bits set in the VLVFB registers 3223 * for the VLAN ID indicated we need to see if the 3224 * caller is requesting that we clear the VFTA entry bit. 3225 * If the caller has requested that we clear the VFTA 3226 * entry bit but there are still pools/VFs using this VLAN 3227 * ID entry then ignore the request. We're not worried 3228 * about the case where we're turning the VFTA VLAN ID 3229 * entry bit on, only when requested to turn it off as 3230 * there may be multiple pools and/or VFs using the 3231 * VLAN ID entry. In that case we cannot clear the 3232 * VFTA bit until all pools/VFs using that VLAN ID have also 3233 * been cleared. This will be indicated by "bits" being 3234 * zero. 3235 */ 3236 vfta_delta = 0; 3237 3238 vlvf_update: 3239 /* record pool change and enable VLAN ID if not already enabled */ 3240 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); 3241 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); 3242 3243 vfta_update: 3244 /* Update VFTA now that we are ready for traffic */ 3245 if (vfta_delta) 3246 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 3247 3248 return 0; 3249 } 3250 3251 /** 3252 * ixgbe_clear_vfta_generic - Clear VLAN filter table 3253 * @hw: pointer to hardware structure 3254 * 3255 * Clears the VLAN filer table, and the VMDq index associated with the filter 3256 **/ 3257 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 3258 { 3259 u32 offset; 3260 3261 for (offset = 0; offset < hw->mac.vft_size; offset++) 3262 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 3263 3264 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 3265 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 3266 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 3267 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); 3268 } 3269 3270 return 0; 3271 } 3272 3273 /** 3274 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix 3275 * @hw: pointer to hardware structure 3276 * 3277 * Contains the logic to identify if we need to verify link for the 3278 * crosstalk fix 3279 **/ 3280 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) 3281 { 3282 /* Does FW say we need the fix */ 3283 if (!hw->need_crosstalk_fix) 3284 return false; 3285 3286 /* Only consider SFP+ PHYs i.e. media type fiber */ 3287 switch (hw->mac.ops.get_media_type(hw)) { 3288 case ixgbe_media_type_fiber: 3289 case ixgbe_media_type_fiber_qsfp: 3290 break; 3291 default: 3292 return false; 3293 } 3294 3295 return true; 3296 } 3297 3298 /** 3299 * ixgbe_check_mac_link_generic - Determine link and speed status 3300 * @hw: pointer to hardware structure 3301 * @speed: pointer to link speed 3302 * @link_up: true when link is up 3303 * @link_up_wait_to_complete: bool used to wait for link up or not 3304 * 3305 * Reads the links register to determine if link is up and the current speed 3306 **/ 3307 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3308 bool *link_up, bool link_up_wait_to_complete) 3309 { 3310 u32 links_reg, links_orig; 3311 u32 i; 3312 3313 /* If Crosstalk fix enabled do the sanity check of making sure 3314 * the SFP+ cage is full. 3315 */ 3316 if (ixgbe_need_crosstalk_fix(hw)) { 3317 u32 sfp_cage_full; 3318 3319 switch (hw->mac.type) { 3320 case ixgbe_mac_82599EB: 3321 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3322 IXGBE_ESDP_SDP2; 3323 break; 3324 case ixgbe_mac_X550EM_x: 3325 case ixgbe_mac_x550em_a: 3326 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 3327 IXGBE_ESDP_SDP0; 3328 break; 3329 default: 3330 /* sanity check - No SFP+ devices here */ 3331 sfp_cage_full = false; 3332 break; 3333 } 3334 3335 if (!sfp_cage_full) { 3336 *link_up = false; 3337 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3338 return 0; 3339 } 3340 } 3341 3342 /* clear the old state */ 3343 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 3344 3345 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3346 3347 if (links_orig != links_reg) { 3348 hw_dbg(hw, "LINKS changed from %08X to %08X\n", 3349 links_orig, links_reg); 3350 } 3351 3352 if (link_up_wait_to_complete) { 3353 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 3354 if (links_reg & IXGBE_LINKS_UP) { 3355 *link_up = true; 3356 break; 3357 } else { 3358 *link_up = false; 3359 } 3360 msleep(100); 3361 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3362 } 3363 } else { 3364 if (links_reg & IXGBE_LINKS_UP) 3365 *link_up = true; 3366 else 3367 *link_up = false; 3368 } 3369 3370 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 3371 case IXGBE_LINKS_SPEED_10G_82599: 3372 if ((hw->mac.type >= ixgbe_mac_X550) && 3373 (links_reg & IXGBE_LINKS_SPEED_NON_STD)) 3374 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 3375 else 3376 *speed = IXGBE_LINK_SPEED_10GB_FULL; 3377 break; 3378 case IXGBE_LINKS_SPEED_1G_82599: 3379 *speed = IXGBE_LINK_SPEED_1GB_FULL; 3380 break; 3381 case IXGBE_LINKS_SPEED_100_82599: 3382 if ((hw->mac.type >= ixgbe_mac_X550) && 3383 (links_reg & IXGBE_LINKS_SPEED_NON_STD)) 3384 *speed = IXGBE_LINK_SPEED_5GB_FULL; 3385 else 3386 *speed = IXGBE_LINK_SPEED_100_FULL; 3387 break; 3388 case IXGBE_LINKS_SPEED_10_X550EM_A: 3389 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3390 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 3391 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) { 3392 *speed = IXGBE_LINK_SPEED_10_FULL; 3393 } 3394 break; 3395 default: 3396 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3397 } 3398 3399 return 0; 3400 } 3401 3402 /** 3403 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 3404 * the EEPROM 3405 * @hw: pointer to hardware structure 3406 * @wwnn_prefix: the alternative WWNN prefix 3407 * @wwpn_prefix: the alternative WWPN prefix 3408 * 3409 * This function will read the EEPROM from the alternative SAN MAC address 3410 * block to check the support for the alternative WWNN/WWPN prefix support. 3411 **/ 3412 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 3413 u16 *wwpn_prefix) 3414 { 3415 u16 offset, caps; 3416 u16 alt_san_mac_blk_offset; 3417 3418 /* clear output first */ 3419 *wwnn_prefix = 0xFFFF; 3420 *wwpn_prefix = 0xFFFF; 3421 3422 /* check if alternative SAN MAC is supported */ 3423 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 3424 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 3425 goto wwn_prefix_err; 3426 3427 if ((alt_san_mac_blk_offset == 0) || 3428 (alt_san_mac_blk_offset == 0xFFFF)) 3429 return 0; 3430 3431 /* check capability in alternative san mac address block */ 3432 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 3433 if (hw->eeprom.ops.read(hw, offset, &caps)) 3434 goto wwn_prefix_err; 3435 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 3436 return 0; 3437 3438 /* get the corresponding prefix for WWNN/WWPN */ 3439 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 3440 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) 3441 hw_err(hw, "eeprom read at offset %d failed\n", offset); 3442 3443 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 3444 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 3445 goto wwn_prefix_err; 3446 3447 return 0; 3448 3449 wwn_prefix_err: 3450 hw_err(hw, "eeprom read at offset %d failed\n", offset); 3451 return 0; 3452 } 3453 3454 /** 3455 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 3456 * @hw: pointer to hardware structure 3457 * @enable: enable or disable switch for MAC anti-spoofing 3458 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing 3459 * 3460 **/ 3461 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 3462 { 3463 int vf_target_reg = vf >> 3; 3464 int vf_target_shift = vf % 8; 3465 u32 pfvfspoof; 3466 3467 if (hw->mac.type == ixgbe_mac_82598EB) 3468 return; 3469 3470 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3471 if (enable) 3472 pfvfspoof |= BIT(vf_target_shift); 3473 else 3474 pfvfspoof &= ~BIT(vf_target_shift); 3475 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3476 } 3477 3478 /** 3479 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 3480 * @hw: pointer to hardware structure 3481 * @enable: enable or disable switch for VLAN anti-spoofing 3482 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 3483 * 3484 **/ 3485 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 3486 { 3487 int vf_target_reg = vf >> 3; 3488 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 3489 u32 pfvfspoof; 3490 3491 if (hw->mac.type == ixgbe_mac_82598EB) 3492 return; 3493 3494 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3495 if (enable) 3496 pfvfspoof |= BIT(vf_target_shift); 3497 else 3498 pfvfspoof &= ~BIT(vf_target_shift); 3499 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3500 } 3501 3502 /** 3503 * ixgbe_get_device_caps_generic - Get additional device capabilities 3504 * @hw: pointer to hardware structure 3505 * @device_caps: the EEPROM word with the extra device capabilities 3506 * 3507 * This function will read the EEPROM location for the device capabilities, 3508 * and return the word through device_caps. 3509 **/ 3510 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 3511 { 3512 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 3513 3514 return 0; 3515 } 3516 3517 /** 3518 * ixgbe_set_rxpba_generic - Initialize RX packet buffer 3519 * @hw: pointer to hardware structure 3520 * @num_pb: number of packet buffers to allocate 3521 * @headroom: reserve n KB of headroom 3522 * @strategy: packet buffer allocation strategy 3523 **/ 3524 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, 3525 int num_pb, 3526 u32 headroom, 3527 int strategy) 3528 { 3529 u32 pbsize = hw->mac.rx_pb_size; 3530 int i = 0; 3531 u32 rxpktsize, txpktsize, txpbthresh; 3532 3533 /* Reserve headroom */ 3534 pbsize -= headroom; 3535 3536 if (!num_pb) 3537 num_pb = 1; 3538 3539 /* Divide remaining packet buffer space amongst the number 3540 * of packet buffers requested using supplied strategy. 3541 */ 3542 switch (strategy) { 3543 case (PBA_STRATEGY_WEIGHTED): 3544 /* pba_80_48 strategy weight first half of packet buffer with 3545 * 5/8 of the packet buffer space. 3546 */ 3547 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8)); 3548 pbsize -= rxpktsize * (num_pb / 2); 3549 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 3550 for (; i < (num_pb / 2); i++) 3551 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3552 /* fall through - configure remaining packet buffers */ 3553 case (PBA_STRATEGY_EQUAL): 3554 /* Divide the remaining Rx packet buffer evenly among the TCs */ 3555 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 3556 for (; i < num_pb; i++) 3557 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3558 break; 3559 default: 3560 break; 3561 } 3562 3563 /* 3564 * Setup Tx packet buffer and threshold equally for all TCs 3565 * TXPBTHRESH register is set in K so divide by 1024 and subtract 3566 * 10 since the largest packet we support is just over 9K. 3567 */ 3568 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 3569 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 3570 for (i = 0; i < num_pb; i++) { 3571 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 3572 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 3573 } 3574 3575 /* Clear unused TCs, if any, to zero buffer size*/ 3576 for (; i < IXGBE_MAX_PB; i++) { 3577 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 3578 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 3579 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 3580 } 3581 } 3582 3583 /** 3584 * ixgbe_calculate_checksum - Calculate checksum for buffer 3585 * @buffer: pointer to EEPROM 3586 * @length: size of EEPROM to calculate a checksum for 3587 * 3588 * Calculates the checksum for some buffer on a specified length. The 3589 * checksum calculated is returned. 3590 **/ 3591 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 3592 { 3593 u32 i; 3594 u8 sum = 0; 3595 3596 if (!buffer) 3597 return 0; 3598 3599 for (i = 0; i < length; i++) 3600 sum += buffer[i]; 3601 3602 return (u8) (0 - sum); 3603 } 3604 3605 /** 3606 * ixgbe_hic_unlocked - Issue command to manageability block unlocked 3607 * @hw: pointer to the HW structure 3608 * @buffer: command to write and where the return status will be placed 3609 * @length: length of buffer, must be multiple of 4 bytes 3610 * @timeout: time in ms to wait for command completion 3611 * 3612 * Communicates with the manageability block. On success return 0 3613 * else returns semaphore error when encountering an error acquiring 3614 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 3615 * 3616 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held 3617 * by the caller. 3618 **/ 3619 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, 3620 u32 timeout) 3621 { 3622 u32 hicr, i, fwsts; 3623 u16 dword_len; 3624 3625 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 3626 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); 3627 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3628 } 3629 3630 /* Set bit 9 of FWSTS clearing FW reset indication */ 3631 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 3632 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 3633 3634 /* Check that the host interface is enabled. */ 3635 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3636 if (!(hicr & IXGBE_HICR_EN)) { 3637 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n"); 3638 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3639 } 3640 3641 /* Calculate length in DWORDs. We must be DWORD aligned */ 3642 if (length % sizeof(u32)) { 3643 hw_dbg(hw, "Buffer length failure, not aligned to dword"); 3644 return IXGBE_ERR_INVALID_ARGUMENT; 3645 } 3646 3647 dword_len = length >> 2; 3648 3649 /* The device driver writes the relevant command block 3650 * into the ram area. 3651 */ 3652 for (i = 0; i < dword_len; i++) 3653 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 3654 i, cpu_to_le32(buffer[i])); 3655 3656 /* Setting this bit tells the ARC that a new command is pending. */ 3657 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 3658 3659 for (i = 0; i < timeout; i++) { 3660 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3661 if (!(hicr & IXGBE_HICR_C)) 3662 break; 3663 usleep_range(1000, 2000); 3664 } 3665 3666 /* Check command successful completion. */ 3667 if ((timeout && i == timeout) || 3668 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) 3669 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3670 3671 return 0; 3672 } 3673 3674 /** 3675 * ixgbe_host_interface_command - Issue command to manageability block 3676 * @hw: pointer to the HW structure 3677 * @buffer: contains the command to write and where the return status will 3678 * be placed 3679 * @length: length of buffer, must be multiple of 4 bytes 3680 * @timeout: time in ms to wait for command completion 3681 * @return_data: read and return data from the buffer (true) or not (false) 3682 * Needed because FW structures are big endian and decoding of 3683 * these fields can be 8 bit or 16 bit based on command. Decoding 3684 * is not easily understood without making a table of commands. 3685 * So we will leave this up to the caller to read back the data 3686 * in these cases. 3687 * 3688 * Communicates with the manageability block. On success return 0 3689 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND. 3690 **/ 3691 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer, 3692 u32 length, u32 timeout, 3693 bool return_data) 3694 { 3695 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 3696 union { 3697 struct ixgbe_hic_hdr hdr; 3698 u32 u32arr[1]; 3699 } *bp = buffer; 3700 u16 buf_len, dword_len; 3701 s32 status; 3702 u32 bi; 3703 3704 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 3705 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); 3706 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 3707 } 3708 /* Take management host interface semaphore */ 3709 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 3710 if (status) 3711 return status; 3712 3713 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); 3714 if (status) 3715 goto rel_out; 3716 3717 if (!return_data) 3718 goto rel_out; 3719 3720 /* Calculate length in DWORDs */ 3721 dword_len = hdr_size >> 2; 3722 3723 /* first pull in the header so we know the buffer length */ 3724 for (bi = 0; bi < dword_len; bi++) { 3725 bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3726 le32_to_cpus(&bp->u32arr[bi]); 3727 } 3728 3729 /* If there is any thing in data position pull it in */ 3730 buf_len = bp->hdr.buf_len; 3731 if (!buf_len) 3732 goto rel_out; 3733 3734 if (length < round_up(buf_len, 4) + hdr_size) { 3735 hw_dbg(hw, "Buffer not large enough for reply message.\n"); 3736 status = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3737 goto rel_out; 3738 } 3739 3740 /* Calculate length in DWORDs, add 3 for odd lengths */ 3741 dword_len = (buf_len + 3) >> 2; 3742 3743 /* Pull in the rest of the buffer (bi is where we left off) */ 3744 for (; bi <= dword_len; bi++) { 3745 bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3746 le32_to_cpus(&bp->u32arr[bi]); 3747 } 3748 3749 rel_out: 3750 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 3751 3752 return status; 3753 } 3754 3755 /** 3756 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 3757 * @hw: pointer to the HW structure 3758 * @maj: driver version major number 3759 * @min: driver version minor number 3760 * @build: driver version build number 3761 * @sub: driver version sub build number 3762 * @len: length of driver_ver string 3763 * @driver_ver: driver string 3764 * 3765 * Sends driver version number to firmware through the manageability 3766 * block. On success return 0 3767 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 3768 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 3769 **/ 3770 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 3771 u8 build, u8 sub, __always_unused u16 len, 3772 __always_unused const char *driver_ver) 3773 { 3774 struct ixgbe_hic_drv_info fw_cmd; 3775 int i; 3776 s32 ret_val; 3777 3778 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 3779 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 3780 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 3781 fw_cmd.port_num = hw->bus.func; 3782 fw_cmd.ver_maj = maj; 3783 fw_cmd.ver_min = min; 3784 fw_cmd.ver_build = build; 3785 fw_cmd.ver_sub = sub; 3786 fw_cmd.hdr.checksum = 0; 3787 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 3788 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 3789 fw_cmd.pad = 0; 3790 fw_cmd.pad2 = 0; 3791 3792 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 3793 ret_val = ixgbe_host_interface_command(hw, &fw_cmd, 3794 sizeof(fw_cmd), 3795 IXGBE_HI_COMMAND_TIMEOUT, 3796 true); 3797 if (ret_val != 0) 3798 continue; 3799 3800 if (fw_cmd.hdr.cmd_or_resp.ret_status == 3801 FW_CEM_RESP_STATUS_SUCCESS) 3802 ret_val = 0; 3803 else 3804 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3805 3806 break; 3807 } 3808 3809 return ret_val; 3810 } 3811 3812 /** 3813 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 3814 * @hw: pointer to the hardware structure 3815 * 3816 * The 82599 and x540 MACs can experience issues if TX work is still pending 3817 * when a reset occurs. This function prevents this by flushing the PCIe 3818 * buffers on the system. 3819 **/ 3820 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 3821 { 3822 u32 gcr_ext, hlreg0, i, poll; 3823 u16 value; 3824 3825 /* 3826 * If double reset is not requested then all transactions should 3827 * already be clear and as such there is no work to do 3828 */ 3829 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 3830 return; 3831 3832 /* 3833 * Set loopback enable to prevent any transmits from being sent 3834 * should the link come up. This assumes that the RXCTRL.RXEN bit 3835 * has already been cleared. 3836 */ 3837 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3838 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 3839 3840 /* wait for a last completion before clearing buffers */ 3841 IXGBE_WRITE_FLUSH(hw); 3842 usleep_range(3000, 6000); 3843 3844 /* Before proceeding, make sure that the PCIe block does not have 3845 * transactions pending. 3846 */ 3847 poll = ixgbe_pcie_timeout_poll(hw); 3848 for (i = 0; i < poll; i++) { 3849 usleep_range(100, 200); 3850 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); 3851 if (ixgbe_removed(hw->hw_addr)) 3852 break; 3853 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3854 break; 3855 } 3856 3857 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 3858 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 3859 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 3860 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 3861 3862 /* Flush all writes and allow 20usec for all transactions to clear */ 3863 IXGBE_WRITE_FLUSH(hw); 3864 udelay(20); 3865 3866 /* restore previous register values */ 3867 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 3868 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3869 } 3870 3871 static const u8 ixgbe_emc_temp_data[4] = { 3872 IXGBE_EMC_INTERNAL_DATA, 3873 IXGBE_EMC_DIODE1_DATA, 3874 IXGBE_EMC_DIODE2_DATA, 3875 IXGBE_EMC_DIODE3_DATA 3876 }; 3877 static const u8 ixgbe_emc_therm_limit[4] = { 3878 IXGBE_EMC_INTERNAL_THERM_LIMIT, 3879 IXGBE_EMC_DIODE1_THERM_LIMIT, 3880 IXGBE_EMC_DIODE2_THERM_LIMIT, 3881 IXGBE_EMC_DIODE3_THERM_LIMIT 3882 }; 3883 3884 /** 3885 * ixgbe_get_ets_data - Extracts the ETS bit data 3886 * @hw: pointer to hardware structure 3887 * @ets_cfg: extected ETS data 3888 * @ets_offset: offset of ETS data 3889 * 3890 * Returns error code. 3891 **/ 3892 static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg, 3893 u16 *ets_offset) 3894 { 3895 s32 status; 3896 3897 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset); 3898 if (status) 3899 return status; 3900 3901 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF)) 3902 return IXGBE_NOT_IMPLEMENTED; 3903 3904 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg); 3905 if (status) 3906 return status; 3907 3908 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED) 3909 return IXGBE_NOT_IMPLEMENTED; 3910 3911 return 0; 3912 } 3913 3914 /** 3915 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data 3916 * @hw: pointer to hardware structure 3917 * 3918 * Returns the thermal sensor data structure 3919 **/ 3920 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) 3921 { 3922 s32 status; 3923 u16 ets_offset; 3924 u16 ets_cfg; 3925 u16 ets_sensor; 3926 u8 num_sensors; 3927 u8 i; 3928 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 3929 3930 /* Only support thermal sensors attached to physical port 0 */ 3931 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 3932 return IXGBE_NOT_IMPLEMENTED; 3933 3934 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); 3935 if (status) 3936 return status; 3937 3938 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 3939 if (num_sensors > IXGBE_MAX_SENSORS) 3940 num_sensors = IXGBE_MAX_SENSORS; 3941 3942 for (i = 0; i < num_sensors; i++) { 3943 u8 sensor_index; 3944 u8 sensor_location; 3945 3946 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), 3947 &ets_sensor); 3948 if (status) 3949 return status; 3950 3951 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 3952 IXGBE_ETS_DATA_INDEX_SHIFT); 3953 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 3954 IXGBE_ETS_DATA_LOC_SHIFT); 3955 3956 if (sensor_location != 0) { 3957 status = hw->phy.ops.read_i2c_byte(hw, 3958 ixgbe_emc_temp_data[sensor_index], 3959 IXGBE_I2C_THERMAL_SENSOR_ADDR, 3960 &data->sensor[i].temp); 3961 if (status) 3962 return status; 3963 } 3964 } 3965 3966 return 0; 3967 } 3968 3969 /** 3970 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds 3971 * @hw: pointer to hardware structure 3972 * 3973 * Inits the thermal sensor thresholds according to the NVM map 3974 * and save off the threshold and location values into mac.thermal_sensor_data 3975 **/ 3976 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) 3977 { 3978 s32 status; 3979 u16 ets_offset; 3980 u16 ets_cfg; 3981 u16 ets_sensor; 3982 u8 low_thresh_delta; 3983 u8 num_sensors; 3984 u8 therm_limit; 3985 u8 i; 3986 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 3987 3988 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data)); 3989 3990 /* Only support thermal sensors attached to physical port 0 */ 3991 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) 3992 return IXGBE_NOT_IMPLEMENTED; 3993 3994 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); 3995 if (status) 3996 return status; 3997 3998 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >> 3999 IXGBE_ETS_LTHRES_DELTA_SHIFT); 4000 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 4001 if (num_sensors > IXGBE_MAX_SENSORS) 4002 num_sensors = IXGBE_MAX_SENSORS; 4003 4004 for (i = 0; i < num_sensors; i++) { 4005 u8 sensor_index; 4006 u8 sensor_location; 4007 4008 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) { 4009 hw_err(hw, "eeprom read at offset %d failed\n", 4010 ets_offset + 1 + i); 4011 continue; 4012 } 4013 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 4014 IXGBE_ETS_DATA_INDEX_SHIFT); 4015 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 4016 IXGBE_ETS_DATA_LOC_SHIFT); 4017 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK; 4018 4019 hw->phy.ops.write_i2c_byte(hw, 4020 ixgbe_emc_therm_limit[sensor_index], 4021 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit); 4022 4023 if (sensor_location == 0) 4024 continue; 4025 4026 data->sensor[i].location = sensor_location; 4027 data->sensor[i].caution_thresh = therm_limit; 4028 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta; 4029 } 4030 4031 return 0; 4032 } 4033 4034 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 4035 { 4036 u32 rxctrl; 4037 4038 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4039 if (rxctrl & IXGBE_RXCTRL_RXEN) { 4040 if (hw->mac.type != ixgbe_mac_82598EB) { 4041 u32 pfdtxgswc; 4042 4043 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 4044 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 4045 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 4046 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 4047 hw->mac.set_lben = true; 4048 } else { 4049 hw->mac.set_lben = false; 4050 } 4051 } 4052 rxctrl &= ~IXGBE_RXCTRL_RXEN; 4053 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 4054 } 4055 } 4056 4057 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 4058 { 4059 u32 rxctrl; 4060 4061 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4062 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 4063 4064 if (hw->mac.type != ixgbe_mac_82598EB) { 4065 if (hw->mac.set_lben) { 4066 u32 pfdtxgswc; 4067 4068 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 4069 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 4070 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 4071 hw->mac.set_lben = false; 4072 } 4073 } 4074 } 4075 4076 /** ixgbe_mng_present - returns true when management capability is present 4077 * @hw: pointer to hardware structure 4078 **/ 4079 bool ixgbe_mng_present(struct ixgbe_hw *hw) 4080 { 4081 u32 fwsm; 4082 4083 if (hw->mac.type < ixgbe_mac_82599EB) 4084 return false; 4085 4086 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 4087 fwsm &= IXGBE_FWSM_MODE_MASK; 4088 return fwsm == IXGBE_FWSM_FW_MODE_PT; 4089 } 4090 4091 /** 4092 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 4093 * @hw: pointer to hardware structure 4094 * @speed: new link speed 4095 * @autoneg_wait_to_complete: true when waiting for completion is needed 4096 * 4097 * Set the link speed in the MAC and/or PHY register and restarts link. 4098 */ 4099 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 4100 ixgbe_link_speed speed, 4101 bool autoneg_wait_to_complete) 4102 { 4103 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4104 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 4105 s32 status = 0; 4106 u32 speedcnt = 0; 4107 u32 i = 0; 4108 bool autoneg, link_up = false; 4109 4110 /* Mask off requested but non-supported speeds */ 4111 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg); 4112 if (status) 4113 return status; 4114 4115 speed &= link_speed; 4116 4117 /* Try each speed one by one, highest priority first. We do this in 4118 * software because 10Gb fiber doesn't support speed autonegotiation. 4119 */ 4120 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 4121 speedcnt++; 4122 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 4123 4124 /* Set the module link speed */ 4125 switch (hw->phy.media_type) { 4126 case ixgbe_media_type_fiber: 4127 hw->mac.ops.set_rate_select_speed(hw, 4128 IXGBE_LINK_SPEED_10GB_FULL); 4129 break; 4130 case ixgbe_media_type_fiber_qsfp: 4131 /* QSFP module automatically detects MAC link speed */ 4132 break; 4133 default: 4134 hw_dbg(hw, "Unexpected media type\n"); 4135 break; 4136 } 4137 4138 /* Allow module to change analog characteristics (1G->10G) */ 4139 msleep(40); 4140 4141 status = hw->mac.ops.setup_mac_link(hw, 4142 IXGBE_LINK_SPEED_10GB_FULL, 4143 autoneg_wait_to_complete); 4144 if (status) 4145 return status; 4146 4147 /* Flap the Tx laser if it has not already been done */ 4148 if (hw->mac.ops.flap_tx_laser) 4149 hw->mac.ops.flap_tx_laser(hw); 4150 4151 /* Wait for the controller to acquire link. Per IEEE 802.3ap, 4152 * Section 73.10.2, we may have to wait up to 500ms if KR is 4153 * attempted. 82599 uses the same timing for 10g SFI. 4154 */ 4155 for (i = 0; i < 5; i++) { 4156 /* Wait for the link partner to also set speed */ 4157 msleep(100); 4158 4159 /* If we have link, just jump out */ 4160 status = hw->mac.ops.check_link(hw, &link_speed, 4161 &link_up, false); 4162 if (status) 4163 return status; 4164 4165 if (link_up) 4166 goto out; 4167 } 4168 } 4169 4170 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 4171 speedcnt++; 4172 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 4173 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 4174 4175 /* Set the module link speed */ 4176 switch (hw->phy.media_type) { 4177 case ixgbe_media_type_fiber: 4178 hw->mac.ops.set_rate_select_speed(hw, 4179 IXGBE_LINK_SPEED_1GB_FULL); 4180 break; 4181 case ixgbe_media_type_fiber_qsfp: 4182 /* QSFP module automatically detects link speed */ 4183 break; 4184 default: 4185 hw_dbg(hw, "Unexpected media type\n"); 4186 break; 4187 } 4188 4189 /* Allow module to change analog characteristics (10G->1G) */ 4190 msleep(40); 4191 4192 status = hw->mac.ops.setup_mac_link(hw, 4193 IXGBE_LINK_SPEED_1GB_FULL, 4194 autoneg_wait_to_complete); 4195 if (status) 4196 return status; 4197 4198 /* Flap the Tx laser if it has not already been done */ 4199 if (hw->mac.ops.flap_tx_laser) 4200 hw->mac.ops.flap_tx_laser(hw); 4201 4202 /* Wait for the link partner to also set speed */ 4203 msleep(100); 4204 4205 /* If we have link, just jump out */ 4206 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 4207 false); 4208 if (status) 4209 return status; 4210 4211 if (link_up) 4212 goto out; 4213 } 4214 4215 /* We didn't get link. Configure back to the highest speed we tried, 4216 * (if there was more than one). We call ourselves back with just the 4217 * single highest speed that the user requested. 4218 */ 4219 if (speedcnt > 1) 4220 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 4221 highest_link_speed, 4222 autoneg_wait_to_complete); 4223 4224 out: 4225 /* Set autoneg_advertised value based on input link speed */ 4226 hw->phy.autoneg_advertised = 0; 4227 4228 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 4229 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 4230 4231 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 4232 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 4233 4234 return status; 4235 } 4236 4237 /** 4238 * ixgbe_set_soft_rate_select_speed - Set module link speed 4239 * @hw: pointer to hardware structure 4240 * @speed: link speed to set 4241 * 4242 * Set module link speed via the soft rate select. 4243 */ 4244 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 4245 ixgbe_link_speed speed) 4246 { 4247 s32 status; 4248 u8 rs, eeprom_data; 4249 4250 switch (speed) { 4251 case IXGBE_LINK_SPEED_10GB_FULL: 4252 /* one bit mask same as setting on */ 4253 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 4254 break; 4255 case IXGBE_LINK_SPEED_1GB_FULL: 4256 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 4257 break; 4258 default: 4259 hw_dbg(hw, "Invalid fixed module speed\n"); 4260 return; 4261 } 4262 4263 /* Set RS0 */ 4264 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4265 IXGBE_I2C_EEPROM_DEV_ADDR2, 4266 &eeprom_data); 4267 if (status) { 4268 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n"); 4269 return; 4270 } 4271 4272 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 4273 4274 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 4275 IXGBE_I2C_EEPROM_DEV_ADDR2, 4276 eeprom_data); 4277 if (status) { 4278 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n"); 4279 return; 4280 } 4281 4282 /* Set RS1 */ 4283 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 4284 IXGBE_I2C_EEPROM_DEV_ADDR2, 4285 &eeprom_data); 4286 if (status) { 4287 hw_dbg(hw, "Failed to read Rx Rate Select RS1\n"); 4288 return; 4289 } 4290 4291 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 4292 4293 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 4294 IXGBE_I2C_EEPROM_DEV_ADDR2, 4295 eeprom_data); 4296 if (status) { 4297 hw_dbg(hw, "Failed to write Rx Rate Select RS1\n"); 4298 return; 4299 } 4300 } 4301