1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include <linux/pci.h> 29 #include <linux/delay.h> 30 #include <linux/sched.h> 31 #include <linux/netdevice.h> 32 33 #include "ixgbe.h" 34 #include "ixgbe_common.h" 35 #include "ixgbe_phy.h" 36 37 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 38 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 39 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 40 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 41 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 42 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 43 u16 count); 44 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 45 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 46 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 47 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 48 49 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 50 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg); 51 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 52 u16 words, u16 *data); 53 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 54 u16 words, u16 *data); 55 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 56 u16 offset); 57 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw); 58 59 /** 60 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow 61 * control 62 * @hw: pointer to hardware structure 63 * 64 * There are several phys that do not support autoneg flow control. This 65 * function check the device id to see if the associated phy supports 66 * autoneg flow control. 67 **/ 68 static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 69 { 70 71 switch (hw->device_id) { 72 case IXGBE_DEV_ID_X540T: 73 case IXGBE_DEV_ID_X540T1: 74 return 0; 75 case IXGBE_DEV_ID_82599_T3_LOM: 76 return 0; 77 default: 78 return IXGBE_ERR_FC_NOT_SUPPORTED; 79 } 80 } 81 82 /** 83 * ixgbe_setup_fc - Set up flow control 84 * @hw: pointer to hardware structure 85 * 86 * Called at init time to set up flow control. 87 **/ 88 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 89 { 90 s32 ret_val = 0; 91 u32 reg = 0, reg_bp = 0; 92 u16 reg_cu = 0; 93 94 /* 95 * Validate the requested mode. Strict IEEE mode does not allow 96 * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 97 */ 98 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 99 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 100 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 101 goto out; 102 } 103 104 /* 105 * 10gig parts do not have a word in the EEPROM to determine the 106 * default flow control setting, so we explicitly set it to full. 107 */ 108 if (hw->fc.requested_mode == ixgbe_fc_default) 109 hw->fc.requested_mode = ixgbe_fc_full; 110 111 /* 112 * Set up the 1G and 10G flow control advertisement registers so the 113 * HW will be able to do fc autoneg once the cable is plugged in. If 114 * we link at 10G, the 1G advertisement is harmless and vice versa. 115 */ 116 switch (hw->phy.media_type) { 117 case ixgbe_media_type_fiber: 118 case ixgbe_media_type_backplane: 119 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 120 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC); 121 break; 122 case ixgbe_media_type_copper: 123 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 124 MDIO_MMD_AN, ®_cu); 125 break; 126 default: 127 break; 128 } 129 130 /* 131 * The possible values of fc.requested_mode are: 132 * 0: Flow control is completely disabled 133 * 1: Rx flow control is enabled (we can receive pause frames, 134 * but not send pause frames). 135 * 2: Tx flow control is enabled (we can send pause frames but 136 * we do not support receiving pause frames). 137 * 3: Both Rx and Tx flow control (symmetric) are enabled. 138 * other: Invalid. 139 */ 140 switch (hw->fc.requested_mode) { 141 case ixgbe_fc_none: 142 /* Flow control completely disabled by software override. */ 143 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 144 if (hw->phy.media_type == ixgbe_media_type_backplane) 145 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 146 IXGBE_AUTOC_ASM_PAUSE); 147 else if (hw->phy.media_type == ixgbe_media_type_copper) 148 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 149 break; 150 case ixgbe_fc_tx_pause: 151 /* 152 * Tx Flow control is enabled, and Rx Flow control is 153 * disabled by software override. 154 */ 155 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 156 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 157 if (hw->phy.media_type == ixgbe_media_type_backplane) { 158 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 159 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 160 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 161 reg_cu |= IXGBE_TAF_ASM_PAUSE; 162 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 163 } 164 break; 165 case ixgbe_fc_rx_pause: 166 /* 167 * Rx Flow control is enabled and Tx Flow control is 168 * disabled by software override. Since there really 169 * isn't a way to advertise that we are capable of RX 170 * Pause ONLY, we will advertise that we support both 171 * symmetric and asymmetric Rx PAUSE, as such we fall 172 * through to the fc_full statement. Later, we will 173 * disable the adapter's ability to send PAUSE frames. 174 */ 175 case ixgbe_fc_full: 176 /* Flow control (both Rx and Tx) is enabled by SW override. */ 177 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 178 if (hw->phy.media_type == ixgbe_media_type_backplane) 179 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 180 IXGBE_AUTOC_ASM_PAUSE; 181 else if (hw->phy.media_type == ixgbe_media_type_copper) 182 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 183 break; 184 default: 185 hw_dbg(hw, "Flow control param set incorrectly\n"); 186 ret_val = IXGBE_ERR_CONFIG; 187 goto out; 188 break; 189 } 190 191 if (hw->mac.type != ixgbe_mac_X540) { 192 /* 193 * Enable auto-negotiation between the MAC & PHY; 194 * the MAC will advertise clause 37 flow control. 195 */ 196 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 197 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 198 199 /* Disable AN timeout */ 200 if (hw->fc.strict_ieee) 201 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 202 203 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 204 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); 205 } 206 207 /* 208 * AUTOC restart handles negotiation of 1G and 10G on backplane 209 * and copper. There is no need to set the PCS1GCTL register. 210 * 211 */ 212 if (hw->phy.media_type == ixgbe_media_type_backplane) { 213 reg_bp |= IXGBE_AUTOC_AN_RESTART; 214 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp); 215 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 216 (ixgbe_device_supports_autoneg_fc(hw) == 0)) { 217 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 218 MDIO_MMD_AN, reg_cu); 219 } 220 221 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); 222 out: 223 return ret_val; 224 } 225 226 /** 227 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 228 * @hw: pointer to hardware structure 229 * 230 * Starts the hardware by filling the bus info structure and media type, clears 231 * all on chip counters, initializes receive address registers, multicast 232 * table, VLAN filter table, calls routine to set up link and flow control 233 * settings, and leaves transmit and receive units disabled and uninitialized 234 **/ 235 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 236 { 237 u32 ctrl_ext; 238 239 /* Set the media type */ 240 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 241 242 /* Identify the PHY */ 243 hw->phy.ops.identify(hw); 244 245 /* Clear the VLAN filter table */ 246 hw->mac.ops.clear_vfta(hw); 247 248 /* Clear statistics registers */ 249 hw->mac.ops.clear_hw_cntrs(hw); 250 251 /* Set No Snoop Disable */ 252 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 253 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 254 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 255 IXGBE_WRITE_FLUSH(hw); 256 257 /* Setup flow control */ 258 ixgbe_setup_fc(hw); 259 260 /* Clear adapter stopped flag */ 261 hw->adapter_stopped = false; 262 263 return 0; 264 } 265 266 /** 267 * ixgbe_start_hw_gen2 - Init sequence for common device family 268 * @hw: pointer to hw structure 269 * 270 * Performs the init sequence common to the second generation 271 * of 10 GbE devices. 272 * Devices in the second generation: 273 * 82599 274 * X540 275 **/ 276 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 277 { 278 u32 i; 279 u32 regval; 280 281 /* Clear the rate limiters */ 282 for (i = 0; i < hw->mac.max_tx_queues; i++) { 283 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 284 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 285 } 286 IXGBE_WRITE_FLUSH(hw); 287 288 /* Disable relaxed ordering */ 289 for (i = 0; i < hw->mac.max_tx_queues; i++) { 290 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 291 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 292 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 293 } 294 295 for (i = 0; i < hw->mac.max_rx_queues; i++) { 296 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 297 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 298 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 299 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 300 } 301 302 return 0; 303 } 304 305 /** 306 * ixgbe_init_hw_generic - Generic hardware initialization 307 * @hw: pointer to hardware structure 308 * 309 * Initialize the hardware by resetting the hardware, filling the bus info 310 * structure and media type, clears all on chip counters, initializes receive 311 * address registers, multicast table, VLAN filter table, calls routine to set 312 * up link and flow control settings, and leaves transmit and receive units 313 * disabled and uninitialized 314 **/ 315 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 316 { 317 s32 status; 318 319 /* Reset the hardware */ 320 status = hw->mac.ops.reset_hw(hw); 321 322 if (status == 0) { 323 /* Start the HW */ 324 status = hw->mac.ops.start_hw(hw); 325 } 326 327 return status; 328 } 329 330 /** 331 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 332 * @hw: pointer to hardware structure 333 * 334 * Clears all hardware statistics counters by reading them from the hardware 335 * Statistics counters are clear on read. 336 **/ 337 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 338 { 339 u16 i = 0; 340 341 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 342 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 343 IXGBE_READ_REG(hw, IXGBE_ERRBC); 344 IXGBE_READ_REG(hw, IXGBE_MSPDC); 345 for (i = 0; i < 8; i++) 346 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 347 348 IXGBE_READ_REG(hw, IXGBE_MLFC); 349 IXGBE_READ_REG(hw, IXGBE_MRFC); 350 IXGBE_READ_REG(hw, IXGBE_RLEC); 351 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 352 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 353 if (hw->mac.type >= ixgbe_mac_82599EB) { 354 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 355 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 356 } else { 357 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 358 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 359 } 360 361 for (i = 0; i < 8; i++) { 362 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 363 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 364 if (hw->mac.type >= ixgbe_mac_82599EB) { 365 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 366 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 367 } else { 368 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 369 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 370 } 371 } 372 if (hw->mac.type >= ixgbe_mac_82599EB) 373 for (i = 0; i < 8; i++) 374 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 375 IXGBE_READ_REG(hw, IXGBE_PRC64); 376 IXGBE_READ_REG(hw, IXGBE_PRC127); 377 IXGBE_READ_REG(hw, IXGBE_PRC255); 378 IXGBE_READ_REG(hw, IXGBE_PRC511); 379 IXGBE_READ_REG(hw, IXGBE_PRC1023); 380 IXGBE_READ_REG(hw, IXGBE_PRC1522); 381 IXGBE_READ_REG(hw, IXGBE_GPRC); 382 IXGBE_READ_REG(hw, IXGBE_BPRC); 383 IXGBE_READ_REG(hw, IXGBE_MPRC); 384 IXGBE_READ_REG(hw, IXGBE_GPTC); 385 IXGBE_READ_REG(hw, IXGBE_GORCL); 386 IXGBE_READ_REG(hw, IXGBE_GORCH); 387 IXGBE_READ_REG(hw, IXGBE_GOTCL); 388 IXGBE_READ_REG(hw, IXGBE_GOTCH); 389 if (hw->mac.type == ixgbe_mac_82598EB) 390 for (i = 0; i < 8; i++) 391 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 392 IXGBE_READ_REG(hw, IXGBE_RUC); 393 IXGBE_READ_REG(hw, IXGBE_RFC); 394 IXGBE_READ_REG(hw, IXGBE_ROC); 395 IXGBE_READ_REG(hw, IXGBE_RJC); 396 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 397 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 398 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 399 IXGBE_READ_REG(hw, IXGBE_TORL); 400 IXGBE_READ_REG(hw, IXGBE_TORH); 401 IXGBE_READ_REG(hw, IXGBE_TPR); 402 IXGBE_READ_REG(hw, IXGBE_TPT); 403 IXGBE_READ_REG(hw, IXGBE_PTC64); 404 IXGBE_READ_REG(hw, IXGBE_PTC127); 405 IXGBE_READ_REG(hw, IXGBE_PTC255); 406 IXGBE_READ_REG(hw, IXGBE_PTC511); 407 IXGBE_READ_REG(hw, IXGBE_PTC1023); 408 IXGBE_READ_REG(hw, IXGBE_PTC1522); 409 IXGBE_READ_REG(hw, IXGBE_MPTC); 410 IXGBE_READ_REG(hw, IXGBE_BPTC); 411 for (i = 0; i < 16; i++) { 412 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 413 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 414 if (hw->mac.type >= ixgbe_mac_82599EB) { 415 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 416 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 417 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 418 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 419 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 420 } else { 421 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 422 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 423 } 424 } 425 426 if (hw->mac.type == ixgbe_mac_X540) { 427 if (hw->phy.id == 0) 428 hw->phy.ops.identify(hw); 429 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i); 430 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i); 431 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i); 432 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i); 433 } 434 435 return 0; 436 } 437 438 /** 439 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 440 * @hw: pointer to hardware structure 441 * @pba_num: stores the part number string from the EEPROM 442 * @pba_num_size: part number string buffer length 443 * 444 * Reads the part number string from the EEPROM. 445 **/ 446 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 447 u32 pba_num_size) 448 { 449 s32 ret_val; 450 u16 data; 451 u16 pba_ptr; 452 u16 offset; 453 u16 length; 454 455 if (pba_num == NULL) { 456 hw_dbg(hw, "PBA string buffer was null\n"); 457 return IXGBE_ERR_INVALID_ARGUMENT; 458 } 459 460 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 461 if (ret_val) { 462 hw_dbg(hw, "NVM Read Error\n"); 463 return ret_val; 464 } 465 466 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 467 if (ret_val) { 468 hw_dbg(hw, "NVM Read Error\n"); 469 return ret_val; 470 } 471 472 /* 473 * if data is not ptr guard the PBA must be in legacy format which 474 * means pba_ptr is actually our second data word for the PBA number 475 * and we can decode it into an ascii string 476 */ 477 if (data != IXGBE_PBANUM_PTR_GUARD) { 478 hw_dbg(hw, "NVM PBA number is not stored as string\n"); 479 480 /* we will need 11 characters to store the PBA */ 481 if (pba_num_size < 11) { 482 hw_dbg(hw, "PBA string buffer too small\n"); 483 return IXGBE_ERR_NO_SPACE; 484 } 485 486 /* extract hex string from data and pba_ptr */ 487 pba_num[0] = (data >> 12) & 0xF; 488 pba_num[1] = (data >> 8) & 0xF; 489 pba_num[2] = (data >> 4) & 0xF; 490 pba_num[3] = data & 0xF; 491 pba_num[4] = (pba_ptr >> 12) & 0xF; 492 pba_num[5] = (pba_ptr >> 8) & 0xF; 493 pba_num[6] = '-'; 494 pba_num[7] = 0; 495 pba_num[8] = (pba_ptr >> 4) & 0xF; 496 pba_num[9] = pba_ptr & 0xF; 497 498 /* put a null character on the end of our string */ 499 pba_num[10] = '\0'; 500 501 /* switch all the data but the '-' to hex char */ 502 for (offset = 0; offset < 10; offset++) { 503 if (pba_num[offset] < 0xA) 504 pba_num[offset] += '0'; 505 else if (pba_num[offset] < 0x10) 506 pba_num[offset] += 'A' - 0xA; 507 } 508 509 return 0; 510 } 511 512 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 513 if (ret_val) { 514 hw_dbg(hw, "NVM Read Error\n"); 515 return ret_val; 516 } 517 518 if (length == 0xFFFF || length == 0) { 519 hw_dbg(hw, "NVM PBA number section invalid length\n"); 520 return IXGBE_ERR_PBA_SECTION; 521 } 522 523 /* check if pba_num buffer is big enough */ 524 if (pba_num_size < (((u32)length * 2) - 1)) { 525 hw_dbg(hw, "PBA string buffer too small\n"); 526 return IXGBE_ERR_NO_SPACE; 527 } 528 529 /* trim pba length from start of string */ 530 pba_ptr++; 531 length--; 532 533 for (offset = 0; offset < length; offset++) { 534 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 535 if (ret_val) { 536 hw_dbg(hw, "NVM Read Error\n"); 537 return ret_val; 538 } 539 pba_num[offset * 2] = (u8)(data >> 8); 540 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 541 } 542 pba_num[offset * 2] = '\0'; 543 544 return 0; 545 } 546 547 /** 548 * ixgbe_get_mac_addr_generic - Generic get MAC address 549 * @hw: pointer to hardware structure 550 * @mac_addr: Adapter MAC address 551 * 552 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 553 * A reset of the adapter must be performed prior to calling this function 554 * in order for the MAC address to have been loaded from the EEPROM into RAR0 555 **/ 556 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 557 { 558 u32 rar_high; 559 u32 rar_low; 560 u16 i; 561 562 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 563 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 564 565 for (i = 0; i < 4; i++) 566 mac_addr[i] = (u8)(rar_low >> (i*8)); 567 568 for (i = 0; i < 2; i++) 569 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 570 571 return 0; 572 } 573 574 /** 575 * ixgbe_get_bus_info_generic - Generic set PCI bus info 576 * @hw: pointer to hardware structure 577 * 578 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 579 **/ 580 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 581 { 582 struct ixgbe_adapter *adapter = hw->back; 583 struct ixgbe_mac_info *mac = &hw->mac; 584 u16 link_status; 585 586 hw->bus.type = ixgbe_bus_type_pci_express; 587 588 /* Get the negotiated link width and speed from PCI config space */ 589 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS, 590 &link_status); 591 592 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 593 case IXGBE_PCI_LINK_WIDTH_1: 594 hw->bus.width = ixgbe_bus_width_pcie_x1; 595 break; 596 case IXGBE_PCI_LINK_WIDTH_2: 597 hw->bus.width = ixgbe_bus_width_pcie_x2; 598 break; 599 case IXGBE_PCI_LINK_WIDTH_4: 600 hw->bus.width = ixgbe_bus_width_pcie_x4; 601 break; 602 case IXGBE_PCI_LINK_WIDTH_8: 603 hw->bus.width = ixgbe_bus_width_pcie_x8; 604 break; 605 default: 606 hw->bus.width = ixgbe_bus_width_unknown; 607 break; 608 } 609 610 switch (link_status & IXGBE_PCI_LINK_SPEED) { 611 case IXGBE_PCI_LINK_SPEED_2500: 612 hw->bus.speed = ixgbe_bus_speed_2500; 613 break; 614 case IXGBE_PCI_LINK_SPEED_5000: 615 hw->bus.speed = ixgbe_bus_speed_5000; 616 break; 617 default: 618 hw->bus.speed = ixgbe_bus_speed_unknown; 619 break; 620 } 621 622 mac->ops.set_lan_id(hw); 623 624 return 0; 625 } 626 627 /** 628 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 629 * @hw: pointer to the HW structure 630 * 631 * Determines the LAN function id by reading memory-mapped registers 632 * and swaps the port value if requested. 633 **/ 634 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 635 { 636 struct ixgbe_bus_info *bus = &hw->bus; 637 u32 reg; 638 639 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 640 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 641 bus->lan_id = bus->func; 642 643 /* check for a port swap */ 644 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS); 645 if (reg & IXGBE_FACTPS_LFS) 646 bus->func ^= 0x1; 647 } 648 649 /** 650 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 651 * @hw: pointer to hardware structure 652 * 653 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 654 * disables transmit and receive units. The adapter_stopped flag is used by 655 * the shared code and drivers to determine if the adapter is in a stopped 656 * state and should not touch the hardware. 657 **/ 658 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 659 { 660 u32 reg_val; 661 u16 i; 662 663 /* 664 * Set the adapter_stopped flag so other driver functions stop touching 665 * the hardware 666 */ 667 hw->adapter_stopped = true; 668 669 /* Disable the receive unit */ 670 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0); 671 672 /* Clear interrupt mask to stop interrupts from being generated */ 673 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 674 675 /* Clear any pending interrupts, flush previous writes */ 676 IXGBE_READ_REG(hw, IXGBE_EICR); 677 678 /* Disable the transmit unit. Each queue must be disabled. */ 679 for (i = 0; i < hw->mac.max_tx_queues; i++) 680 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 681 682 /* Disable the receive unit by stopping each queue */ 683 for (i = 0; i < hw->mac.max_rx_queues; i++) { 684 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 685 reg_val &= ~IXGBE_RXDCTL_ENABLE; 686 reg_val |= IXGBE_RXDCTL_SWFLSH; 687 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 688 } 689 690 /* flush all queues disables */ 691 IXGBE_WRITE_FLUSH(hw); 692 usleep_range(1000, 2000); 693 694 /* 695 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 696 * access and verify no pending requests 697 */ 698 return ixgbe_disable_pcie_master(hw); 699 } 700 701 /** 702 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 703 * @hw: pointer to hardware structure 704 * @index: led number to turn on 705 **/ 706 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 707 { 708 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 709 710 /* To turn on the LED, set mode to ON. */ 711 led_reg &= ~IXGBE_LED_MODE_MASK(index); 712 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 713 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 714 IXGBE_WRITE_FLUSH(hw); 715 716 return 0; 717 } 718 719 /** 720 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 721 * @hw: pointer to hardware structure 722 * @index: led number to turn off 723 **/ 724 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 725 { 726 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 727 728 /* To turn off the LED, set mode to OFF. */ 729 led_reg &= ~IXGBE_LED_MODE_MASK(index); 730 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 731 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 732 IXGBE_WRITE_FLUSH(hw); 733 734 return 0; 735 } 736 737 /** 738 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 739 * @hw: pointer to hardware structure 740 * 741 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 742 * ixgbe_hw struct in order to set up EEPROM access. 743 **/ 744 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 745 { 746 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 747 u32 eec; 748 u16 eeprom_size; 749 750 if (eeprom->type == ixgbe_eeprom_uninitialized) { 751 eeprom->type = ixgbe_eeprom_none; 752 /* Set default semaphore delay to 10ms which is a well 753 * tested value */ 754 eeprom->semaphore_delay = 10; 755 /* Clear EEPROM page size, it will be initialized as needed */ 756 eeprom->word_page_size = 0; 757 758 /* 759 * Check for EEPROM present first. 760 * If not present leave as none 761 */ 762 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 763 if (eec & IXGBE_EEC_PRES) { 764 eeprom->type = ixgbe_eeprom_spi; 765 766 /* 767 * SPI EEPROM is assumed here. This code would need to 768 * change if a future EEPROM is not SPI. 769 */ 770 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 771 IXGBE_EEC_SIZE_SHIFT); 772 eeprom->word_size = 1 << (eeprom_size + 773 IXGBE_EEPROM_WORD_SIZE_SHIFT); 774 } 775 776 if (eec & IXGBE_EEC_ADDR_SIZE) 777 eeprom->address_bits = 16; 778 else 779 eeprom->address_bits = 8; 780 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: " 781 "%d\n", eeprom->type, eeprom->word_size, 782 eeprom->address_bits); 783 } 784 785 return 0; 786 } 787 788 /** 789 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 790 * @hw: pointer to hardware structure 791 * @offset: offset within the EEPROM to write 792 * @words: number of words 793 * @data: 16 bit word(s) to write to EEPROM 794 * 795 * Reads 16 bit word(s) from EEPROM through bit-bang method 796 **/ 797 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 798 u16 words, u16 *data) 799 { 800 s32 status = 0; 801 u16 i, count; 802 803 hw->eeprom.ops.init_params(hw); 804 805 if (words == 0) { 806 status = IXGBE_ERR_INVALID_ARGUMENT; 807 goto out; 808 } 809 810 if (offset + words > hw->eeprom.word_size) { 811 status = IXGBE_ERR_EEPROM; 812 goto out; 813 } 814 815 /* 816 * The EEPROM page size cannot be queried from the chip. We do lazy 817 * initialization. It is worth to do that when we write large buffer. 818 */ 819 if ((hw->eeprom.word_page_size == 0) && 820 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 821 ixgbe_detect_eeprom_page_size_generic(hw, offset); 822 823 /* 824 * We cannot hold synchronization semaphores for too long 825 * to avoid other entity starvation. However it is more efficient 826 * to read in bursts than synchronizing access for each word. 827 */ 828 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 829 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 830 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 831 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 832 count, &data[i]); 833 834 if (status != 0) 835 break; 836 } 837 838 out: 839 return status; 840 } 841 842 /** 843 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 844 * @hw: pointer to hardware structure 845 * @offset: offset within the EEPROM to be written to 846 * @words: number of word(s) 847 * @data: 16 bit word(s) to be written to the EEPROM 848 * 849 * If ixgbe_eeprom_update_checksum is not called after this function, the 850 * EEPROM will most likely contain an invalid checksum. 851 **/ 852 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 853 u16 words, u16 *data) 854 { 855 s32 status; 856 u16 word; 857 u16 page_size; 858 u16 i; 859 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 860 861 /* Prepare the EEPROM for writing */ 862 status = ixgbe_acquire_eeprom(hw); 863 864 if (status == 0) { 865 if (ixgbe_ready_eeprom(hw) != 0) { 866 ixgbe_release_eeprom(hw); 867 status = IXGBE_ERR_EEPROM; 868 } 869 } 870 871 if (status == 0) { 872 for (i = 0; i < words; i++) { 873 ixgbe_standby_eeprom(hw); 874 875 /* Send the WRITE ENABLE command (8 bit opcode ) */ 876 ixgbe_shift_out_eeprom_bits(hw, 877 IXGBE_EEPROM_WREN_OPCODE_SPI, 878 IXGBE_EEPROM_OPCODE_BITS); 879 880 ixgbe_standby_eeprom(hw); 881 882 /* 883 * Some SPI eeproms use the 8th address bit embedded 884 * in the opcode 885 */ 886 if ((hw->eeprom.address_bits == 8) && 887 ((offset + i) >= 128)) 888 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 889 890 /* Send the Write command (8-bit opcode + addr) */ 891 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 892 IXGBE_EEPROM_OPCODE_BITS); 893 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 894 hw->eeprom.address_bits); 895 896 page_size = hw->eeprom.word_page_size; 897 898 /* Send the data in burst via SPI*/ 899 do { 900 word = data[i]; 901 word = (word >> 8) | (word << 8); 902 ixgbe_shift_out_eeprom_bits(hw, word, 16); 903 904 if (page_size == 0) 905 break; 906 907 /* do not wrap around page */ 908 if (((offset + i) & (page_size - 1)) == 909 (page_size - 1)) 910 break; 911 } while (++i < words); 912 913 ixgbe_standby_eeprom(hw); 914 usleep_range(10000, 20000); 915 } 916 /* Done with writing - release the EEPROM */ 917 ixgbe_release_eeprom(hw); 918 } 919 920 return status; 921 } 922 923 /** 924 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 925 * @hw: pointer to hardware structure 926 * @offset: offset within the EEPROM to be written to 927 * @data: 16 bit word to be written to the EEPROM 928 * 929 * If ixgbe_eeprom_update_checksum is not called after this function, the 930 * EEPROM will most likely contain an invalid checksum. 931 **/ 932 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 933 { 934 s32 status; 935 936 hw->eeprom.ops.init_params(hw); 937 938 if (offset >= hw->eeprom.word_size) { 939 status = IXGBE_ERR_EEPROM; 940 goto out; 941 } 942 943 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 944 945 out: 946 return status; 947 } 948 949 /** 950 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 951 * @hw: pointer to hardware structure 952 * @offset: offset within the EEPROM to be read 953 * @words: number of word(s) 954 * @data: read 16 bit words(s) from EEPROM 955 * 956 * Reads 16 bit word(s) from EEPROM through bit-bang method 957 **/ 958 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 959 u16 words, u16 *data) 960 { 961 s32 status = 0; 962 u16 i, count; 963 964 hw->eeprom.ops.init_params(hw); 965 966 if (words == 0) { 967 status = IXGBE_ERR_INVALID_ARGUMENT; 968 goto out; 969 } 970 971 if (offset + words > hw->eeprom.word_size) { 972 status = IXGBE_ERR_EEPROM; 973 goto out; 974 } 975 976 /* 977 * We cannot hold synchronization semaphores for too long 978 * to avoid other entity starvation. However it is more efficient 979 * to read in bursts than synchronizing access for each word. 980 */ 981 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 982 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 983 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 984 985 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 986 count, &data[i]); 987 988 if (status != 0) 989 break; 990 } 991 992 out: 993 return status; 994 } 995 996 /** 997 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 998 * @hw: pointer to hardware structure 999 * @offset: offset within the EEPROM to be read 1000 * @words: number of word(s) 1001 * @data: read 16 bit word(s) from EEPROM 1002 * 1003 * Reads 16 bit word(s) from EEPROM through bit-bang method 1004 **/ 1005 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1006 u16 words, u16 *data) 1007 { 1008 s32 status; 1009 u16 word_in; 1010 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1011 u16 i; 1012 1013 /* Prepare the EEPROM for reading */ 1014 status = ixgbe_acquire_eeprom(hw); 1015 1016 if (status == 0) { 1017 if (ixgbe_ready_eeprom(hw) != 0) { 1018 ixgbe_release_eeprom(hw); 1019 status = IXGBE_ERR_EEPROM; 1020 } 1021 } 1022 1023 if (status == 0) { 1024 for (i = 0; i < words; i++) { 1025 ixgbe_standby_eeprom(hw); 1026 /* 1027 * Some SPI eeproms use the 8th address bit embedded 1028 * in the opcode 1029 */ 1030 if ((hw->eeprom.address_bits == 8) && 1031 ((offset + i) >= 128)) 1032 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1033 1034 /* Send the READ command (opcode + addr) */ 1035 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1036 IXGBE_EEPROM_OPCODE_BITS); 1037 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1038 hw->eeprom.address_bits); 1039 1040 /* Read the data. */ 1041 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1042 data[i] = (word_in >> 8) | (word_in << 8); 1043 } 1044 1045 /* End this read operation */ 1046 ixgbe_release_eeprom(hw); 1047 } 1048 1049 return status; 1050 } 1051 1052 /** 1053 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1054 * @hw: pointer to hardware structure 1055 * @offset: offset within the EEPROM to be read 1056 * @data: read 16 bit value from EEPROM 1057 * 1058 * Reads 16 bit value from EEPROM through bit-bang method 1059 **/ 1060 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1061 u16 *data) 1062 { 1063 s32 status; 1064 1065 hw->eeprom.ops.init_params(hw); 1066 1067 if (offset >= hw->eeprom.word_size) { 1068 status = IXGBE_ERR_EEPROM; 1069 goto out; 1070 } 1071 1072 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1073 1074 out: 1075 return status; 1076 } 1077 1078 /** 1079 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1080 * @hw: pointer to hardware structure 1081 * @offset: offset of word in the EEPROM to read 1082 * @words: number of word(s) 1083 * @data: 16 bit word(s) from the EEPROM 1084 * 1085 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1086 **/ 1087 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1088 u16 words, u16 *data) 1089 { 1090 u32 eerd; 1091 s32 status = 0; 1092 u32 i; 1093 1094 hw->eeprom.ops.init_params(hw); 1095 1096 if (words == 0) { 1097 status = IXGBE_ERR_INVALID_ARGUMENT; 1098 goto out; 1099 } 1100 1101 if (offset >= hw->eeprom.word_size) { 1102 status = IXGBE_ERR_EEPROM; 1103 goto out; 1104 } 1105 1106 for (i = 0; i < words; i++) { 1107 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) + 1108 IXGBE_EEPROM_RW_REG_START; 1109 1110 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1111 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1112 1113 if (status == 0) { 1114 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1115 IXGBE_EEPROM_RW_REG_DATA); 1116 } else { 1117 hw_dbg(hw, "Eeprom read timed out\n"); 1118 goto out; 1119 } 1120 } 1121 out: 1122 return status; 1123 } 1124 1125 /** 1126 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1127 * @hw: pointer to hardware structure 1128 * @offset: offset within the EEPROM to be used as a scratch pad 1129 * 1130 * Discover EEPROM page size by writing marching data at given offset. 1131 * This function is called only when we are writing a new large buffer 1132 * at given offset so the data would be overwritten anyway. 1133 **/ 1134 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1135 u16 offset) 1136 { 1137 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1138 s32 status = 0; 1139 u16 i; 1140 1141 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1142 data[i] = i; 1143 1144 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1145 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1146 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1147 hw->eeprom.word_page_size = 0; 1148 if (status != 0) 1149 goto out; 1150 1151 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1152 if (status != 0) 1153 goto out; 1154 1155 /* 1156 * When writing in burst more than the actual page size 1157 * EEPROM address wraps around current page. 1158 */ 1159 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1160 1161 hw_dbg(hw, "Detected EEPROM page size = %d words.", 1162 hw->eeprom.word_page_size); 1163 out: 1164 return status; 1165 } 1166 1167 /** 1168 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1169 * @hw: pointer to hardware structure 1170 * @offset: offset of word in the EEPROM to read 1171 * @data: word read from the EEPROM 1172 * 1173 * Reads a 16 bit word from the EEPROM using the EERD register. 1174 **/ 1175 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1176 { 1177 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1178 } 1179 1180 /** 1181 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1182 * @hw: pointer to hardware structure 1183 * @offset: offset of word in the EEPROM to write 1184 * @words: number of words 1185 * @data: word(s) write to the EEPROM 1186 * 1187 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1188 **/ 1189 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1190 u16 words, u16 *data) 1191 { 1192 u32 eewr; 1193 s32 status = 0; 1194 u16 i; 1195 1196 hw->eeprom.ops.init_params(hw); 1197 1198 if (words == 0) { 1199 status = IXGBE_ERR_INVALID_ARGUMENT; 1200 goto out; 1201 } 1202 1203 if (offset >= hw->eeprom.word_size) { 1204 status = IXGBE_ERR_EEPROM; 1205 goto out; 1206 } 1207 1208 for (i = 0; i < words; i++) { 1209 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1210 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1211 IXGBE_EEPROM_RW_REG_START; 1212 1213 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1214 if (status != 0) { 1215 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1216 goto out; 1217 } 1218 1219 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1220 1221 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1222 if (status != 0) { 1223 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1224 goto out; 1225 } 1226 } 1227 1228 out: 1229 return status; 1230 } 1231 1232 /** 1233 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1234 * @hw: pointer to hardware structure 1235 * @offset: offset of word in the EEPROM to write 1236 * @data: word write to the EEPROM 1237 * 1238 * Write a 16 bit word to the EEPROM using the EEWR register. 1239 **/ 1240 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1241 { 1242 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1243 } 1244 1245 /** 1246 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1247 * @hw: pointer to hardware structure 1248 * @ee_reg: EEPROM flag for polling 1249 * 1250 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1251 * read or write is done respectively. 1252 **/ 1253 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1254 { 1255 u32 i; 1256 u32 reg; 1257 s32 status = IXGBE_ERR_EEPROM; 1258 1259 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1260 if (ee_reg == IXGBE_NVM_POLL_READ) 1261 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1262 else 1263 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1264 1265 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1266 status = 0; 1267 break; 1268 } 1269 udelay(5); 1270 } 1271 return status; 1272 } 1273 1274 /** 1275 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1276 * @hw: pointer to hardware structure 1277 * 1278 * Prepares EEPROM for access using bit-bang method. This function should 1279 * be called before issuing a command to the EEPROM. 1280 **/ 1281 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1282 { 1283 s32 status = 0; 1284 u32 eec; 1285 u32 i; 1286 1287 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) 1288 status = IXGBE_ERR_SWFW_SYNC; 1289 1290 if (status == 0) { 1291 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1292 1293 /* Request EEPROM Access */ 1294 eec |= IXGBE_EEC_REQ; 1295 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1296 1297 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1298 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1299 if (eec & IXGBE_EEC_GNT) 1300 break; 1301 udelay(5); 1302 } 1303 1304 /* Release if grant not acquired */ 1305 if (!(eec & IXGBE_EEC_GNT)) { 1306 eec &= ~IXGBE_EEC_REQ; 1307 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1308 hw_dbg(hw, "Could not acquire EEPROM grant\n"); 1309 1310 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1311 status = IXGBE_ERR_EEPROM; 1312 } 1313 1314 /* Setup EEPROM for Read/Write */ 1315 if (status == 0) { 1316 /* Clear CS and SK */ 1317 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1318 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1319 IXGBE_WRITE_FLUSH(hw); 1320 udelay(1); 1321 } 1322 } 1323 return status; 1324 } 1325 1326 /** 1327 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1328 * @hw: pointer to hardware structure 1329 * 1330 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1331 **/ 1332 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1333 { 1334 s32 status = IXGBE_ERR_EEPROM; 1335 u32 timeout = 2000; 1336 u32 i; 1337 u32 swsm; 1338 1339 /* Get SMBI software semaphore between device drivers first */ 1340 for (i = 0; i < timeout; i++) { 1341 /* 1342 * If the SMBI bit is 0 when we read it, then the bit will be 1343 * set and we have the semaphore 1344 */ 1345 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1346 if (!(swsm & IXGBE_SWSM_SMBI)) { 1347 status = 0; 1348 break; 1349 } 1350 udelay(50); 1351 } 1352 1353 if (i == timeout) { 1354 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore " 1355 "not granted.\n"); 1356 /* 1357 * this release is particularly important because our attempts 1358 * above to get the semaphore may have succeeded, and if there 1359 * was a timeout, we should unconditionally clear the semaphore 1360 * bits to free the driver to make progress 1361 */ 1362 ixgbe_release_eeprom_semaphore(hw); 1363 1364 udelay(50); 1365 /* 1366 * one last try 1367 * If the SMBI bit is 0 when we read it, then the bit will be 1368 * set and we have the semaphore 1369 */ 1370 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1371 if (!(swsm & IXGBE_SWSM_SMBI)) 1372 status = 0; 1373 } 1374 1375 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1376 if (status == 0) { 1377 for (i = 0; i < timeout; i++) { 1378 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1379 1380 /* Set the SW EEPROM semaphore bit to request access */ 1381 swsm |= IXGBE_SWSM_SWESMBI; 1382 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1383 1384 /* 1385 * If we set the bit successfully then we got the 1386 * semaphore. 1387 */ 1388 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1389 if (swsm & IXGBE_SWSM_SWESMBI) 1390 break; 1391 1392 udelay(50); 1393 } 1394 1395 /* 1396 * Release semaphores and return error if SW EEPROM semaphore 1397 * was not granted because we don't have access to the EEPROM 1398 */ 1399 if (i >= timeout) { 1400 hw_dbg(hw, "SWESMBI Software EEPROM semaphore " 1401 "not granted.\n"); 1402 ixgbe_release_eeprom_semaphore(hw); 1403 status = IXGBE_ERR_EEPROM; 1404 } 1405 } else { 1406 hw_dbg(hw, "Software semaphore SMBI between device drivers " 1407 "not granted.\n"); 1408 } 1409 1410 return status; 1411 } 1412 1413 /** 1414 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1415 * @hw: pointer to hardware structure 1416 * 1417 * This function clears hardware semaphore bits. 1418 **/ 1419 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1420 { 1421 u32 swsm; 1422 1423 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1424 1425 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1426 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1427 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1428 IXGBE_WRITE_FLUSH(hw); 1429 } 1430 1431 /** 1432 * ixgbe_ready_eeprom - Polls for EEPROM ready 1433 * @hw: pointer to hardware structure 1434 **/ 1435 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1436 { 1437 s32 status = 0; 1438 u16 i; 1439 u8 spi_stat_reg; 1440 1441 /* 1442 * Read "Status Register" repeatedly until the LSB is cleared. The 1443 * EEPROM will signal that the command has been completed by clearing 1444 * bit 0 of the internal status register. If it's not cleared within 1445 * 5 milliseconds, then error out. 1446 */ 1447 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 1448 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1449 IXGBE_EEPROM_OPCODE_BITS); 1450 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 1451 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 1452 break; 1453 1454 udelay(5); 1455 ixgbe_standby_eeprom(hw); 1456 } 1457 1458 /* 1459 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 1460 * devices (and only 0-5mSec on 5V devices) 1461 */ 1462 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 1463 hw_dbg(hw, "SPI EEPROM Status error\n"); 1464 status = IXGBE_ERR_EEPROM; 1465 } 1466 1467 return status; 1468 } 1469 1470 /** 1471 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 1472 * @hw: pointer to hardware structure 1473 **/ 1474 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 1475 { 1476 u32 eec; 1477 1478 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1479 1480 /* Toggle CS to flush commands */ 1481 eec |= IXGBE_EEC_CS; 1482 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1483 IXGBE_WRITE_FLUSH(hw); 1484 udelay(1); 1485 eec &= ~IXGBE_EEC_CS; 1486 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1487 IXGBE_WRITE_FLUSH(hw); 1488 udelay(1); 1489 } 1490 1491 /** 1492 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 1493 * @hw: pointer to hardware structure 1494 * @data: data to send to the EEPROM 1495 * @count: number of bits to shift out 1496 **/ 1497 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 1498 u16 count) 1499 { 1500 u32 eec; 1501 u32 mask; 1502 u32 i; 1503 1504 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1505 1506 /* 1507 * Mask is used to shift "count" bits of "data" out to the EEPROM 1508 * one bit at a time. Determine the starting bit based on count 1509 */ 1510 mask = 0x01 << (count - 1); 1511 1512 for (i = 0; i < count; i++) { 1513 /* 1514 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 1515 * "1", and then raising and then lowering the clock (the SK 1516 * bit controls the clock input to the EEPROM). A "0" is 1517 * shifted out to the EEPROM by setting "DI" to "0" and then 1518 * raising and then lowering the clock. 1519 */ 1520 if (data & mask) 1521 eec |= IXGBE_EEC_DI; 1522 else 1523 eec &= ~IXGBE_EEC_DI; 1524 1525 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1526 IXGBE_WRITE_FLUSH(hw); 1527 1528 udelay(1); 1529 1530 ixgbe_raise_eeprom_clk(hw, &eec); 1531 ixgbe_lower_eeprom_clk(hw, &eec); 1532 1533 /* 1534 * Shift mask to signify next bit of data to shift in to the 1535 * EEPROM 1536 */ 1537 mask = mask >> 1; 1538 } 1539 1540 /* We leave the "DI" bit set to "0" when we leave this routine. */ 1541 eec &= ~IXGBE_EEC_DI; 1542 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1543 IXGBE_WRITE_FLUSH(hw); 1544 } 1545 1546 /** 1547 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 1548 * @hw: pointer to hardware structure 1549 **/ 1550 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 1551 { 1552 u32 eec; 1553 u32 i; 1554 u16 data = 0; 1555 1556 /* 1557 * In order to read a register from the EEPROM, we need to shift 1558 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 1559 * the clock input to the EEPROM (setting the SK bit), and then reading 1560 * the value of the "DO" bit. During this "shifting in" process the 1561 * "DI" bit should always be clear. 1562 */ 1563 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1564 1565 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 1566 1567 for (i = 0; i < count; i++) { 1568 data = data << 1; 1569 ixgbe_raise_eeprom_clk(hw, &eec); 1570 1571 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1572 1573 eec &= ~(IXGBE_EEC_DI); 1574 if (eec & IXGBE_EEC_DO) 1575 data |= 1; 1576 1577 ixgbe_lower_eeprom_clk(hw, &eec); 1578 } 1579 1580 return data; 1581 } 1582 1583 /** 1584 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1585 * @hw: pointer to hardware structure 1586 * @eec: EEC register's current value 1587 **/ 1588 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1589 { 1590 /* 1591 * Raise the clock input to the EEPROM 1592 * (setting the SK bit), then delay 1593 */ 1594 *eec = *eec | IXGBE_EEC_SK; 1595 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1596 IXGBE_WRITE_FLUSH(hw); 1597 udelay(1); 1598 } 1599 1600 /** 1601 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1602 * @hw: pointer to hardware structure 1603 * @eecd: EECD's current value 1604 **/ 1605 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1606 { 1607 /* 1608 * Lower the clock input to the EEPROM (clearing the SK bit), then 1609 * delay 1610 */ 1611 *eec = *eec & ~IXGBE_EEC_SK; 1612 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1613 IXGBE_WRITE_FLUSH(hw); 1614 udelay(1); 1615 } 1616 1617 /** 1618 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1619 * @hw: pointer to hardware structure 1620 **/ 1621 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 1622 { 1623 u32 eec; 1624 1625 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1626 1627 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1628 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1629 1630 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1631 IXGBE_WRITE_FLUSH(hw); 1632 1633 udelay(1); 1634 1635 /* Stop requesting EEPROM access */ 1636 eec &= ~IXGBE_EEC_REQ; 1637 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1638 1639 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1640 1641 /* 1642 * Delay before attempt to obtain semaphore again to allow FW 1643 * access. semaphore_delay is in ms we need us for usleep_range 1644 */ 1645 usleep_range(hw->eeprom.semaphore_delay * 1000, 1646 hw->eeprom.semaphore_delay * 2000); 1647 } 1648 1649 /** 1650 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 1651 * @hw: pointer to hardware structure 1652 **/ 1653 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 1654 { 1655 u16 i; 1656 u16 j; 1657 u16 checksum = 0; 1658 u16 length = 0; 1659 u16 pointer = 0; 1660 u16 word = 0; 1661 1662 /* Include 0x0-0x3F in the checksum */ 1663 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1664 if (hw->eeprom.ops.read(hw, i, &word) != 0) { 1665 hw_dbg(hw, "EEPROM read failed\n"); 1666 break; 1667 } 1668 checksum += word; 1669 } 1670 1671 /* Include all data from pointers except for the fw pointer */ 1672 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1673 hw->eeprom.ops.read(hw, i, &pointer); 1674 1675 /* Make sure the pointer seems valid */ 1676 if (pointer != 0xFFFF && pointer != 0) { 1677 hw->eeprom.ops.read(hw, pointer, &length); 1678 1679 if (length != 0xFFFF && length != 0) { 1680 for (j = pointer+1; j <= pointer+length; j++) { 1681 hw->eeprom.ops.read(hw, j, &word); 1682 checksum += word; 1683 } 1684 } 1685 } 1686 } 1687 1688 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1689 1690 return checksum; 1691 } 1692 1693 /** 1694 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1695 * @hw: pointer to hardware structure 1696 * @checksum_val: calculated checksum 1697 * 1698 * Performs checksum calculation and validates the EEPROM checksum. If the 1699 * caller does not need checksum_val, the value can be NULL. 1700 **/ 1701 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1702 u16 *checksum_val) 1703 { 1704 s32 status; 1705 u16 checksum; 1706 u16 read_checksum = 0; 1707 1708 /* 1709 * Read the first word from the EEPROM. If this times out or fails, do 1710 * not continue or we could be in for a very long wait while every 1711 * EEPROM read fails 1712 */ 1713 status = hw->eeprom.ops.read(hw, 0, &checksum); 1714 1715 if (status == 0) { 1716 checksum = hw->eeprom.ops.calc_checksum(hw); 1717 1718 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1719 1720 /* 1721 * Verify read checksum from EEPROM is the same as 1722 * calculated checksum 1723 */ 1724 if (read_checksum != checksum) 1725 status = IXGBE_ERR_EEPROM_CHECKSUM; 1726 1727 /* If the user cares, return the calculated checksum */ 1728 if (checksum_val) 1729 *checksum_val = checksum; 1730 } else { 1731 hw_dbg(hw, "EEPROM read failed\n"); 1732 } 1733 1734 return status; 1735 } 1736 1737 /** 1738 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1739 * @hw: pointer to hardware structure 1740 **/ 1741 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1742 { 1743 s32 status; 1744 u16 checksum; 1745 1746 /* 1747 * Read the first word from the EEPROM. If this times out or fails, do 1748 * not continue or we could be in for a very long wait while every 1749 * EEPROM read fails 1750 */ 1751 status = hw->eeprom.ops.read(hw, 0, &checksum); 1752 1753 if (status == 0) { 1754 checksum = hw->eeprom.ops.calc_checksum(hw); 1755 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, 1756 checksum); 1757 } else { 1758 hw_dbg(hw, "EEPROM read failed\n"); 1759 } 1760 1761 return status; 1762 } 1763 1764 /** 1765 * ixgbe_validate_mac_addr - Validate MAC address 1766 * @mac_addr: pointer to MAC address. 1767 * 1768 * Tests a MAC address to ensure it is a valid Individual Address 1769 **/ 1770 s32 ixgbe_validate_mac_addr(u8 *mac_addr) 1771 { 1772 s32 status = 0; 1773 1774 /* Make sure it is not a multicast address */ 1775 if (IXGBE_IS_MULTICAST(mac_addr)) 1776 status = IXGBE_ERR_INVALID_MAC_ADDR; 1777 /* Not a broadcast address */ 1778 else if (IXGBE_IS_BROADCAST(mac_addr)) 1779 status = IXGBE_ERR_INVALID_MAC_ADDR; 1780 /* Reject the zero address */ 1781 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 1782 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) 1783 status = IXGBE_ERR_INVALID_MAC_ADDR; 1784 1785 return status; 1786 } 1787 1788 /** 1789 * ixgbe_set_rar_generic - Set Rx address register 1790 * @hw: pointer to hardware structure 1791 * @index: Receive address register to write 1792 * @addr: Address to put into receive address register 1793 * @vmdq: VMDq "set" or "pool" index 1794 * @enable_addr: set flag that address is active 1795 * 1796 * Puts an ethernet address into a receive address register. 1797 **/ 1798 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1799 u32 enable_addr) 1800 { 1801 u32 rar_low, rar_high; 1802 u32 rar_entries = hw->mac.num_rar_entries; 1803 1804 /* Make sure we are using a valid rar index range */ 1805 if (index >= rar_entries) { 1806 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1807 return IXGBE_ERR_INVALID_ARGUMENT; 1808 } 1809 1810 /* setup VMDq pool selection before this RAR gets enabled */ 1811 hw->mac.ops.set_vmdq(hw, index, vmdq); 1812 1813 /* 1814 * HW expects these in little endian so we reverse the byte 1815 * order from network order (big endian) to little endian 1816 */ 1817 rar_low = ((u32)addr[0] | 1818 ((u32)addr[1] << 8) | 1819 ((u32)addr[2] << 16) | 1820 ((u32)addr[3] << 24)); 1821 /* 1822 * Some parts put the VMDq setting in the extra RAH bits, 1823 * so save everything except the lower 16 bits that hold part 1824 * of the address and the address valid bit. 1825 */ 1826 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1827 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1828 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1829 1830 if (enable_addr != 0) 1831 rar_high |= IXGBE_RAH_AV; 1832 1833 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1834 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1835 1836 return 0; 1837 } 1838 1839 /** 1840 * ixgbe_clear_rar_generic - Remove Rx address register 1841 * @hw: pointer to hardware structure 1842 * @index: Receive address register to write 1843 * 1844 * Clears an ethernet address from a receive address register. 1845 **/ 1846 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1847 { 1848 u32 rar_high; 1849 u32 rar_entries = hw->mac.num_rar_entries; 1850 1851 /* Make sure we are using a valid rar index range */ 1852 if (index >= rar_entries) { 1853 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1854 return IXGBE_ERR_INVALID_ARGUMENT; 1855 } 1856 1857 /* 1858 * Some parts put the VMDq setting in the extra RAH bits, 1859 * so save everything except the lower 16 bits that hold part 1860 * of the address and the address valid bit. 1861 */ 1862 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1863 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1864 1865 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1866 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1867 1868 /* clear VMDq pool/queue selection for this RAR */ 1869 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1870 1871 return 0; 1872 } 1873 1874 /** 1875 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1876 * @hw: pointer to hardware structure 1877 * 1878 * Places the MAC address in receive address register 0 and clears the rest 1879 * of the receive address registers. Clears the multicast table. Assumes 1880 * the receiver is in reset when the routine is called. 1881 **/ 1882 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1883 { 1884 u32 i; 1885 u32 rar_entries = hw->mac.num_rar_entries; 1886 1887 /* 1888 * If the current mac address is valid, assume it is a software override 1889 * to the permanent address. 1890 * Otherwise, use the permanent address from the eeprom. 1891 */ 1892 if (ixgbe_validate_mac_addr(hw->mac.addr) == 1893 IXGBE_ERR_INVALID_MAC_ADDR) { 1894 /* Get the MAC address from the RAR0 for later reference */ 1895 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1896 1897 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr); 1898 } else { 1899 /* Setup the receive address. */ 1900 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); 1901 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr); 1902 1903 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1904 1905 /* clear VMDq pool/queue selection for RAR 0 */ 1906 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 1907 } 1908 hw->addr_ctrl.overflow_promisc = 0; 1909 1910 hw->addr_ctrl.rar_used_count = 1; 1911 1912 /* Zero out the other receive addresses. */ 1913 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); 1914 for (i = 1; i < rar_entries; i++) { 1915 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1916 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1917 } 1918 1919 /* Clear the MTA */ 1920 hw->addr_ctrl.mta_in_use = 0; 1921 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1922 1923 hw_dbg(hw, " Clearing MTA\n"); 1924 for (i = 0; i < hw->mac.mcft_size; i++) 1925 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1926 1927 if (hw->mac.ops.init_uta_tables) 1928 hw->mac.ops.init_uta_tables(hw); 1929 1930 return 0; 1931 } 1932 1933 /** 1934 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1935 * @hw: pointer to hardware structure 1936 * @mc_addr: the multicast address 1937 * 1938 * Extracts the 12 bits, from a multicast address, to determine which 1939 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1940 * incoming rx multicast addresses, to determine the bit-vector to check in 1941 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1942 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1943 * to mc_filter_type. 1944 **/ 1945 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 1946 { 1947 u32 vector = 0; 1948 1949 switch (hw->mac.mc_filter_type) { 1950 case 0: /* use bits [47:36] of the address */ 1951 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1952 break; 1953 case 1: /* use bits [46:35] of the address */ 1954 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1955 break; 1956 case 2: /* use bits [45:34] of the address */ 1957 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1958 break; 1959 case 3: /* use bits [43:32] of the address */ 1960 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1961 break; 1962 default: /* Invalid mc_filter_type */ 1963 hw_dbg(hw, "MC filter type param set incorrectly\n"); 1964 break; 1965 } 1966 1967 /* vector can only be 12-bits or boundary will be exceeded */ 1968 vector &= 0xFFF; 1969 return vector; 1970 } 1971 1972 /** 1973 * ixgbe_set_mta - Set bit-vector in multicast table 1974 * @hw: pointer to hardware structure 1975 * @hash_value: Multicast address hash value 1976 * 1977 * Sets the bit-vector in the multicast table. 1978 **/ 1979 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 1980 { 1981 u32 vector; 1982 u32 vector_bit; 1983 u32 vector_reg; 1984 1985 hw->addr_ctrl.mta_in_use++; 1986 1987 vector = ixgbe_mta_vector(hw, mc_addr); 1988 hw_dbg(hw, " bit-vector = 0x%03X\n", vector); 1989 1990 /* 1991 * The MTA is a register array of 128 32-bit registers. It is treated 1992 * like an array of 4096 bits. We want to set bit 1993 * BitArray[vector_value]. So we figure out what register the bit is 1994 * in, read it, OR in the new bit, then write back the new value. The 1995 * register is determined by the upper 7 bits of the vector value and 1996 * the bit within that register are determined by the lower 5 bits of 1997 * the value. 1998 */ 1999 vector_reg = (vector >> 5) & 0x7F; 2000 vector_bit = vector & 0x1F; 2001 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 2002 } 2003 2004 /** 2005 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2006 * @hw: pointer to hardware structure 2007 * @netdev: pointer to net device structure 2008 * 2009 * The given list replaces any existing list. Clears the MC addrs from receive 2010 * address registers and the multicast table. Uses unused receive address 2011 * registers for the first multicast addresses, and hashes the rest into the 2012 * multicast table. 2013 **/ 2014 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, 2015 struct net_device *netdev) 2016 { 2017 struct netdev_hw_addr *ha; 2018 u32 i; 2019 2020 /* 2021 * Set the new number of MC addresses that we are being requested to 2022 * use. 2023 */ 2024 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); 2025 hw->addr_ctrl.mta_in_use = 0; 2026 2027 /* Clear mta_shadow */ 2028 hw_dbg(hw, " Clearing MTA\n"); 2029 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2030 2031 /* Update mta shadow */ 2032 netdev_for_each_mc_addr(ha, netdev) { 2033 hw_dbg(hw, " Adding the multicast addresses:\n"); 2034 ixgbe_set_mta(hw, ha->addr); 2035 } 2036 2037 /* Enable mta */ 2038 for (i = 0; i < hw->mac.mcft_size; i++) 2039 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2040 hw->mac.mta_shadow[i]); 2041 2042 if (hw->addr_ctrl.mta_in_use > 0) 2043 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2044 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2045 2046 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); 2047 return 0; 2048 } 2049 2050 /** 2051 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2052 * @hw: pointer to hardware structure 2053 * 2054 * Enables multicast address in RAR and the use of the multicast hash table. 2055 **/ 2056 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2057 { 2058 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2059 2060 if (a->mta_in_use > 0) 2061 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2062 hw->mac.mc_filter_type); 2063 2064 return 0; 2065 } 2066 2067 /** 2068 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2069 * @hw: pointer to hardware structure 2070 * 2071 * Disables multicast address in RAR and the use of the multicast hash table. 2072 **/ 2073 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2074 { 2075 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2076 2077 if (a->mta_in_use > 0) 2078 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2079 2080 return 0; 2081 } 2082 2083 /** 2084 * ixgbe_fc_enable_generic - Enable flow control 2085 * @hw: pointer to hardware structure 2086 * 2087 * Enable flow control according to the current settings. 2088 **/ 2089 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2090 { 2091 s32 ret_val = 0; 2092 u32 mflcn_reg, fccfg_reg; 2093 u32 reg; 2094 u32 fcrtl, fcrth; 2095 int i; 2096 2097 /* 2098 * Validate the water mark configuration for packet buffer 0. Zero 2099 * water marks indicate that the packet buffer was not configured 2100 * and the watermarks for packet buffer 0 should always be configured. 2101 */ 2102 if (!hw->fc.low_water || 2103 !hw->fc.high_water[0] || 2104 !hw->fc.pause_time) { 2105 hw_dbg(hw, "Invalid water mark configuration\n"); 2106 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2107 goto out; 2108 } 2109 2110 /* Negotiate the fc mode to use */ 2111 ixgbe_fc_autoneg(hw); 2112 2113 /* Disable any previous flow control settings */ 2114 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2115 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2116 2117 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2118 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2119 2120 /* 2121 * The possible values of fc.current_mode are: 2122 * 0: Flow control is completely disabled 2123 * 1: Rx flow control is enabled (we can receive pause frames, 2124 * but not send pause frames). 2125 * 2: Tx flow control is enabled (we can send pause frames but 2126 * we do not support receiving pause frames). 2127 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2128 * other: Invalid. 2129 */ 2130 switch (hw->fc.current_mode) { 2131 case ixgbe_fc_none: 2132 /* 2133 * Flow control is disabled by software override or autoneg. 2134 * The code below will actually disable it in the HW. 2135 */ 2136 break; 2137 case ixgbe_fc_rx_pause: 2138 /* 2139 * Rx Flow control is enabled and Tx Flow control is 2140 * disabled by software override. Since there really 2141 * isn't a way to advertise that we are capable of RX 2142 * Pause ONLY, we will advertise that we support both 2143 * symmetric and asymmetric Rx PAUSE. Later, we will 2144 * disable the adapter's ability to send PAUSE frames. 2145 */ 2146 mflcn_reg |= IXGBE_MFLCN_RFCE; 2147 break; 2148 case ixgbe_fc_tx_pause: 2149 /* 2150 * Tx Flow control is enabled, and Rx Flow control is 2151 * disabled by software override. 2152 */ 2153 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2154 break; 2155 case ixgbe_fc_full: 2156 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2157 mflcn_reg |= IXGBE_MFLCN_RFCE; 2158 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2159 break; 2160 default: 2161 hw_dbg(hw, "Flow control param set incorrectly\n"); 2162 ret_val = IXGBE_ERR_CONFIG; 2163 goto out; 2164 break; 2165 } 2166 2167 /* Set 802.3x based flow control settings. */ 2168 mflcn_reg |= IXGBE_MFLCN_DPF; 2169 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2170 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2171 2172 fcrtl = (hw->fc.low_water << 10) | IXGBE_FCRTL_XONE; 2173 2174 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2175 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 2176 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2177 hw->fc.high_water[i]) { 2178 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2179 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2180 } else { 2181 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2182 /* 2183 * In order to prevent Tx hangs when the internal Tx 2184 * switch is enabled we must set the high water mark 2185 * to the maximum FCRTH value. This allows the Tx 2186 * switch to function even under heavy Rx workloads. 2187 */ 2188 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32; 2189 } 2190 2191 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2192 } 2193 2194 /* Configure pause time (2 TCs per register) */ 2195 reg = hw->fc.pause_time * 0x00010001; 2196 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 2197 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2198 2199 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2200 2201 out: 2202 return ret_val; 2203 } 2204 2205 /** 2206 * ixgbe_negotiate_fc - Negotiate flow control 2207 * @hw: pointer to hardware structure 2208 * @adv_reg: flow control advertised settings 2209 * @lp_reg: link partner's flow control settings 2210 * @adv_sym: symmetric pause bit in advertisement 2211 * @adv_asm: asymmetric pause bit in advertisement 2212 * @lp_sym: symmetric pause bit in link partner advertisement 2213 * @lp_asm: asymmetric pause bit in link partner advertisement 2214 * 2215 * Find the intersection between advertised settings and link partner's 2216 * advertised settings 2217 **/ 2218 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2219 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2220 { 2221 if ((!(adv_reg)) || (!(lp_reg))) 2222 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2223 2224 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2225 /* 2226 * Now we need to check if the user selected Rx ONLY 2227 * of pause frames. In this case, we had to advertise 2228 * FULL flow control because we could not advertise RX 2229 * ONLY. Hence, we must now check to see if we need to 2230 * turn OFF the TRANSMISSION of PAUSE frames. 2231 */ 2232 if (hw->fc.requested_mode == ixgbe_fc_full) { 2233 hw->fc.current_mode = ixgbe_fc_full; 2234 hw_dbg(hw, "Flow Control = FULL.\n"); 2235 } else { 2236 hw->fc.current_mode = ixgbe_fc_rx_pause; 2237 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n"); 2238 } 2239 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2240 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2241 hw->fc.current_mode = ixgbe_fc_tx_pause; 2242 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); 2243 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2244 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2245 hw->fc.current_mode = ixgbe_fc_rx_pause; 2246 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); 2247 } else { 2248 hw->fc.current_mode = ixgbe_fc_none; 2249 hw_dbg(hw, "Flow Control = NONE.\n"); 2250 } 2251 return 0; 2252 } 2253 2254 /** 2255 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 2256 * @hw: pointer to hardware structure 2257 * 2258 * Enable flow control according on 1 gig fiber. 2259 **/ 2260 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 2261 { 2262 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 2263 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2264 2265 /* 2266 * On multispeed fiber at 1g, bail out if 2267 * - link is up but AN did not complete, or if 2268 * - link is up and AN completed but timed out 2269 */ 2270 2271 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 2272 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 2273 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) 2274 goto out; 2275 2276 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2277 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 2278 2279 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 2280 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 2281 IXGBE_PCS1GANA_ASM_PAUSE, 2282 IXGBE_PCS1GANA_SYM_PAUSE, 2283 IXGBE_PCS1GANA_ASM_PAUSE); 2284 2285 out: 2286 return ret_val; 2287 } 2288 2289 /** 2290 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 2291 * @hw: pointer to hardware structure 2292 * 2293 * Enable flow control according to IEEE clause 37. 2294 **/ 2295 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 2296 { 2297 u32 links2, anlp1_reg, autoc_reg, links; 2298 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2299 2300 /* 2301 * On backplane, bail out if 2302 * - backplane autoneg was not completed, or if 2303 * - we are 82599 and link partner is not AN enabled 2304 */ 2305 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 2306 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) 2307 goto out; 2308 2309 if (hw->mac.type == ixgbe_mac_82599EB) { 2310 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 2311 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) 2312 goto out; 2313 } 2314 /* 2315 * Read the 10g AN autoc and LP ability registers and resolve 2316 * local flow control settings accordingly 2317 */ 2318 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2319 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2320 2321 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 2322 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 2323 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 2324 2325 out: 2326 return ret_val; 2327 } 2328 2329 /** 2330 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 2331 * @hw: pointer to hardware structure 2332 * 2333 * Enable flow control according to IEEE clause 37. 2334 **/ 2335 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 2336 { 2337 u16 technology_ability_reg = 0; 2338 u16 lp_technology_ability_reg = 0; 2339 2340 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 2341 MDIO_MMD_AN, 2342 &technology_ability_reg); 2343 hw->phy.ops.read_reg(hw, MDIO_AN_LPA, 2344 MDIO_MMD_AN, 2345 &lp_technology_ability_reg); 2346 2347 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 2348 (u32)lp_technology_ability_reg, 2349 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 2350 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 2351 } 2352 2353 /** 2354 * ixgbe_fc_autoneg - Configure flow control 2355 * @hw: pointer to hardware structure 2356 * 2357 * Compares our advertised flow control capabilities to those advertised by 2358 * our link partner, and determines the proper flow control mode to use. 2359 **/ 2360 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 2361 { 2362 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2363 ixgbe_link_speed speed; 2364 bool link_up; 2365 2366 /* 2367 * AN should have completed when the cable was plugged in. 2368 * Look for reasons to bail out. Bail out if: 2369 * - FC autoneg is disabled, or if 2370 * - link is not up. 2371 * 2372 * Since we're being called from an LSC, link is already known to be up. 2373 * So use link_up_wait_to_complete=false. 2374 */ 2375 if (hw->fc.disable_fc_autoneg) 2376 goto out; 2377 2378 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2379 if (!link_up) 2380 goto out; 2381 2382 switch (hw->phy.media_type) { 2383 /* Autoneg flow control on fiber adapters */ 2384 case ixgbe_media_type_fiber: 2385 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 2386 ret_val = ixgbe_fc_autoneg_fiber(hw); 2387 break; 2388 2389 /* Autoneg flow control on backplane adapters */ 2390 case ixgbe_media_type_backplane: 2391 ret_val = ixgbe_fc_autoneg_backplane(hw); 2392 break; 2393 2394 /* Autoneg flow control on copper adapters */ 2395 case ixgbe_media_type_copper: 2396 if (ixgbe_device_supports_autoneg_fc(hw) == 0) 2397 ret_val = ixgbe_fc_autoneg_copper(hw); 2398 break; 2399 2400 default: 2401 break; 2402 } 2403 2404 out: 2405 if (ret_val == 0) { 2406 hw->fc.fc_was_autonegged = true; 2407 } else { 2408 hw->fc.fc_was_autonegged = false; 2409 hw->fc.current_mode = hw->fc.requested_mode; 2410 } 2411 } 2412 2413 /** 2414 * ixgbe_disable_pcie_master - Disable PCI-express master access 2415 * @hw: pointer to hardware structure 2416 * 2417 * Disables PCI-Express master access and verifies there are no pending 2418 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 2419 * bit hasn't caused the master requests to be disabled, else 0 2420 * is returned signifying master requests disabled. 2421 **/ 2422 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 2423 { 2424 struct ixgbe_adapter *adapter = hw->back; 2425 s32 status = 0; 2426 u32 i; 2427 u16 value; 2428 2429 /* Always set this bit to ensure any future transactions are blocked */ 2430 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 2431 2432 /* Exit if master requests are blocked */ 2433 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2434 goto out; 2435 2436 /* Poll for master request bit to clear */ 2437 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2438 udelay(100); 2439 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2440 goto out; 2441 } 2442 2443 /* 2444 * Two consecutive resets are required via CTRL.RST per datasheet 2445 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 2446 * of this need. The first reset prevents new master requests from 2447 * being issued by our device. We then must wait 1usec or more for any 2448 * remaining completions from the PCIe bus to trickle in, and then reset 2449 * again to clear out any effects they may have had on our device. 2450 */ 2451 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n"); 2452 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2453 2454 /* 2455 * Before proceeding, make sure that the PCIe block does not have 2456 * transactions pending. 2457 */ 2458 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2459 udelay(100); 2460 pci_read_config_word(adapter->pdev, IXGBE_PCI_DEVICE_STATUS, 2461 &value); 2462 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 2463 goto out; 2464 } 2465 2466 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n"); 2467 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 2468 2469 out: 2470 return status; 2471 } 2472 2473 /** 2474 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 2475 * @hw: pointer to hardware structure 2476 * @mask: Mask to specify which semaphore to acquire 2477 * 2478 * Acquires the SWFW semaphore through the GSSR register for the specified 2479 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2480 **/ 2481 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2482 { 2483 u32 gssr; 2484 u32 swmask = mask; 2485 u32 fwmask = mask << 5; 2486 s32 timeout = 200; 2487 2488 while (timeout) { 2489 /* 2490 * SW EEPROM semaphore bit is used for access to all 2491 * SW_FW_SYNC/GSSR bits (not just EEPROM) 2492 */ 2493 if (ixgbe_get_eeprom_semaphore(hw)) 2494 return IXGBE_ERR_SWFW_SYNC; 2495 2496 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2497 if (!(gssr & (fwmask | swmask))) 2498 break; 2499 2500 /* 2501 * Firmware currently using resource (fwmask) or other software 2502 * thread currently using resource (swmask) 2503 */ 2504 ixgbe_release_eeprom_semaphore(hw); 2505 usleep_range(5000, 10000); 2506 timeout--; 2507 } 2508 2509 if (!timeout) { 2510 hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n"); 2511 return IXGBE_ERR_SWFW_SYNC; 2512 } 2513 2514 gssr |= swmask; 2515 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2516 2517 ixgbe_release_eeprom_semaphore(hw); 2518 return 0; 2519 } 2520 2521 /** 2522 * ixgbe_release_swfw_sync - Release SWFW semaphore 2523 * @hw: pointer to hardware structure 2524 * @mask: Mask to specify which semaphore to release 2525 * 2526 * Releases the SWFW semaphore through the GSSR register for the specified 2527 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2528 **/ 2529 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2530 { 2531 u32 gssr; 2532 u32 swmask = mask; 2533 2534 ixgbe_get_eeprom_semaphore(hw); 2535 2536 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2537 gssr &= ~swmask; 2538 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2539 2540 ixgbe_release_eeprom_semaphore(hw); 2541 } 2542 2543 /** 2544 * ixgbe_disable_rx_buff_generic - Stops the receive data path 2545 * @hw: pointer to hardware structure 2546 * 2547 * Stops the receive data path and waits for the HW to internally 2548 * empty the Rx security block. 2549 **/ 2550 s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw) 2551 { 2552 #define IXGBE_MAX_SECRX_POLL 40 2553 int i; 2554 int secrxreg; 2555 2556 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2557 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 2558 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2559 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 2560 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 2561 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 2562 break; 2563 else 2564 /* Use interrupt-safe sleep just in case */ 2565 udelay(1000); 2566 } 2567 2568 /* For informational purposes only */ 2569 if (i >= IXGBE_MAX_SECRX_POLL) 2570 hw_dbg(hw, "Rx unit being enabled before security " 2571 "path fully disabled. Continuing with init.\n"); 2572 2573 return 0; 2574 2575 } 2576 2577 /** 2578 * ixgbe_enable_rx_buff - Enables the receive data path 2579 * @hw: pointer to hardware structure 2580 * 2581 * Enables the receive data path 2582 **/ 2583 s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw) 2584 { 2585 int secrxreg; 2586 2587 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2588 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 2589 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2590 IXGBE_WRITE_FLUSH(hw); 2591 2592 return 0; 2593 } 2594 2595 /** 2596 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 2597 * @hw: pointer to hardware structure 2598 * @regval: register value to write to RXCTRL 2599 * 2600 * Enables the Rx DMA unit 2601 **/ 2602 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 2603 { 2604 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 2605 2606 return 0; 2607 } 2608 2609 /** 2610 * ixgbe_blink_led_start_generic - Blink LED based on index. 2611 * @hw: pointer to hardware structure 2612 * @index: led number to blink 2613 **/ 2614 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 2615 { 2616 ixgbe_link_speed speed = 0; 2617 bool link_up = false; 2618 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2619 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2620 2621 /* 2622 * Link must be up to auto-blink the LEDs; 2623 * Force it if link is down. 2624 */ 2625 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2626 2627 if (!link_up) { 2628 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2629 autoc_reg |= IXGBE_AUTOC_FLU; 2630 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2631 IXGBE_WRITE_FLUSH(hw); 2632 usleep_range(10000, 20000); 2633 } 2634 2635 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2636 led_reg |= IXGBE_LED_BLINK(index); 2637 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2638 IXGBE_WRITE_FLUSH(hw); 2639 2640 return 0; 2641 } 2642 2643 /** 2644 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 2645 * @hw: pointer to hardware structure 2646 * @index: led number to stop blinking 2647 **/ 2648 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 2649 { 2650 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2651 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2652 2653 autoc_reg &= ~IXGBE_AUTOC_FLU; 2654 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2655 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2656 2657 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2658 led_reg &= ~IXGBE_LED_BLINK(index); 2659 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 2660 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2661 IXGBE_WRITE_FLUSH(hw); 2662 2663 return 0; 2664 } 2665 2666 /** 2667 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 2668 * @hw: pointer to hardware structure 2669 * @san_mac_offset: SAN MAC address offset 2670 * 2671 * This function will read the EEPROM location for the SAN MAC address 2672 * pointer, and returns the value at that location. This is used in both 2673 * get and set mac_addr routines. 2674 **/ 2675 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 2676 u16 *san_mac_offset) 2677 { 2678 /* 2679 * First read the EEPROM pointer to see if the MAC addresses are 2680 * available. 2681 */ 2682 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset); 2683 2684 return 0; 2685 } 2686 2687 /** 2688 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 2689 * @hw: pointer to hardware structure 2690 * @san_mac_addr: SAN MAC address 2691 * 2692 * Reads the SAN MAC address from the EEPROM, if it's available. This is 2693 * per-port, so set_lan_id() must be called before reading the addresses. 2694 * set_lan_id() is called by identify_sfp(), but this cannot be relied 2695 * upon for non-SFP connections, so we must call it here. 2696 **/ 2697 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2698 { 2699 u16 san_mac_data, san_mac_offset; 2700 u8 i; 2701 2702 /* 2703 * First read the EEPROM pointer to see if the MAC addresses are 2704 * available. If they're not, no point in calling set_lan_id() here. 2705 */ 2706 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2707 2708 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { 2709 /* 2710 * No addresses available in this EEPROM. It's not an 2711 * error though, so just wipe the local address and return. 2712 */ 2713 for (i = 0; i < 6; i++) 2714 san_mac_addr[i] = 0xFF; 2715 2716 goto san_mac_addr_out; 2717 } 2718 2719 /* make sure we know which port we need to program */ 2720 hw->mac.ops.set_lan_id(hw); 2721 /* apply the port offset to the address offset */ 2722 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2723 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2724 for (i = 0; i < 3; i++) { 2725 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data); 2726 san_mac_addr[i * 2] = (u8)(san_mac_data); 2727 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 2728 san_mac_offset++; 2729 } 2730 2731 san_mac_addr_out: 2732 return 0; 2733 } 2734 2735 /** 2736 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 2737 * @hw: pointer to hardware structure 2738 * 2739 * Read PCIe configuration space, and get the MSI-X vector count from 2740 * the capabilities table. 2741 **/ 2742 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 2743 { 2744 struct ixgbe_adapter *adapter = hw->back; 2745 u16 msix_count = 1; 2746 u16 max_msix_count; 2747 u16 pcie_offset; 2748 2749 switch (hw->mac.type) { 2750 case ixgbe_mac_82598EB: 2751 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 2752 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 2753 break; 2754 case ixgbe_mac_82599EB: 2755 case ixgbe_mac_X540: 2756 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 2757 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 2758 break; 2759 default: 2760 return msix_count; 2761 } 2762 2763 pci_read_config_word(adapter->pdev, pcie_offset, &msix_count); 2764 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 2765 2766 /* MSI-X count is zero-based in HW */ 2767 msix_count++; 2768 2769 if (msix_count > max_msix_count) 2770 msix_count = max_msix_count; 2771 2772 return msix_count; 2773 } 2774 2775 /** 2776 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 2777 * @hw: pointer to hardware struct 2778 * @rar: receive address register index to disassociate 2779 * @vmdq: VMDq pool index to remove from the rar 2780 **/ 2781 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2782 { 2783 u32 mpsar_lo, mpsar_hi; 2784 u32 rar_entries = hw->mac.num_rar_entries; 2785 2786 /* Make sure we are using a valid rar index range */ 2787 if (rar >= rar_entries) { 2788 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 2789 return IXGBE_ERR_INVALID_ARGUMENT; 2790 } 2791 2792 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2793 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2794 2795 if (!mpsar_lo && !mpsar_hi) 2796 goto done; 2797 2798 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 2799 if (mpsar_lo) { 2800 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 2801 mpsar_lo = 0; 2802 } 2803 if (mpsar_hi) { 2804 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 2805 mpsar_hi = 0; 2806 } 2807 } else if (vmdq < 32) { 2808 mpsar_lo &= ~(1 << vmdq); 2809 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 2810 } else { 2811 mpsar_hi &= ~(1 << (vmdq - 32)); 2812 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 2813 } 2814 2815 /* was that the last pool using this rar? */ 2816 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 2817 hw->mac.ops.clear_rar(hw, rar); 2818 done: 2819 return 0; 2820 } 2821 2822 /** 2823 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 2824 * @hw: pointer to hardware struct 2825 * @rar: receive address register index to associate with a VMDq index 2826 * @vmdq: VMDq pool index 2827 **/ 2828 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2829 { 2830 u32 mpsar; 2831 u32 rar_entries = hw->mac.num_rar_entries; 2832 2833 /* Make sure we are using a valid rar index range */ 2834 if (rar >= rar_entries) { 2835 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 2836 return IXGBE_ERR_INVALID_ARGUMENT; 2837 } 2838 2839 if (vmdq < 32) { 2840 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2841 mpsar |= 1 << vmdq; 2842 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 2843 } else { 2844 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2845 mpsar |= 1 << (vmdq - 32); 2846 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 2847 } 2848 return 0; 2849 } 2850 2851 /** 2852 * This function should only be involved in the IOV mode. 2853 * In IOV mode, Default pool is next pool after the number of 2854 * VFs advertized and not 0. 2855 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 2856 * 2857 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address 2858 * @hw: pointer to hardware struct 2859 * @vmdq: VMDq pool index 2860 **/ 2861 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 2862 { 2863 u32 rar = hw->mac.san_mac_rar_index; 2864 2865 if (vmdq < 32) { 2866 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); 2867 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 2868 } else { 2869 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 2870 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); 2871 } 2872 2873 return 0; 2874 } 2875 2876 /** 2877 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 2878 * @hw: pointer to hardware structure 2879 **/ 2880 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 2881 { 2882 int i; 2883 2884 for (i = 0; i < 128; i++) 2885 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 2886 2887 return 0; 2888 } 2889 2890 /** 2891 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 2892 * @hw: pointer to hardware structure 2893 * @vlan: VLAN id to write to VLAN filter 2894 * 2895 * return the VLVF index where this VLAN id should be placed 2896 * 2897 **/ 2898 static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan) 2899 { 2900 u32 bits = 0; 2901 u32 first_empty_slot = 0; 2902 s32 regindex; 2903 2904 /* short cut the special case */ 2905 if (vlan == 0) 2906 return 0; 2907 2908 /* 2909 * Search for the vlan id in the VLVF entries. Save off the first empty 2910 * slot found along the way 2911 */ 2912 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) { 2913 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 2914 if (!bits && !(first_empty_slot)) 2915 first_empty_slot = regindex; 2916 else if ((bits & 0x0FFF) == vlan) 2917 break; 2918 } 2919 2920 /* 2921 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan 2922 * in the VLVF. Else use the first empty VLVF register for this 2923 * vlan id. 2924 */ 2925 if (regindex >= IXGBE_VLVF_ENTRIES) { 2926 if (first_empty_slot) 2927 regindex = first_empty_slot; 2928 else { 2929 hw_dbg(hw, "No space in VLVF.\n"); 2930 regindex = IXGBE_ERR_NO_SPACE; 2931 } 2932 } 2933 2934 return regindex; 2935 } 2936 2937 /** 2938 * ixgbe_set_vfta_generic - Set VLAN filter table 2939 * @hw: pointer to hardware structure 2940 * @vlan: VLAN id to write to VLAN filter 2941 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 2942 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 2943 * 2944 * Turn on/off specified VLAN in the VLAN filter table. 2945 **/ 2946 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 2947 bool vlan_on) 2948 { 2949 s32 regindex; 2950 u32 bitindex; 2951 u32 vfta; 2952 u32 bits; 2953 u32 vt; 2954 u32 targetbit; 2955 bool vfta_changed = false; 2956 2957 if (vlan > 4095) 2958 return IXGBE_ERR_PARAM; 2959 2960 /* 2961 * this is a 2 part operation - first the VFTA, then the 2962 * VLVF and VLVFB if VT Mode is set 2963 * We don't write the VFTA until we know the VLVF part succeeded. 2964 */ 2965 2966 /* Part 1 2967 * The VFTA is a bitstring made up of 128 32-bit registers 2968 * that enable the particular VLAN id, much like the MTA: 2969 * bits[11-5]: which register 2970 * bits[4-0]: which bit in the register 2971 */ 2972 regindex = (vlan >> 5) & 0x7F; 2973 bitindex = vlan & 0x1F; 2974 targetbit = (1 << bitindex); 2975 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 2976 2977 if (vlan_on) { 2978 if (!(vfta & targetbit)) { 2979 vfta |= targetbit; 2980 vfta_changed = true; 2981 } 2982 } else { 2983 if ((vfta & targetbit)) { 2984 vfta &= ~targetbit; 2985 vfta_changed = true; 2986 } 2987 } 2988 2989 /* Part 2 2990 * If VT Mode is set 2991 * Either vlan_on 2992 * make sure the vlan is in VLVF 2993 * set the vind bit in the matching VLVFB 2994 * Or !vlan_on 2995 * clear the pool bit and possibly the vind 2996 */ 2997 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 2998 if (vt & IXGBE_VT_CTL_VT_ENABLE) { 2999 s32 vlvf_index; 3000 3001 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan); 3002 if (vlvf_index < 0) 3003 return vlvf_index; 3004 3005 if (vlan_on) { 3006 /* set the pool bit */ 3007 if (vind < 32) { 3008 bits = IXGBE_READ_REG(hw, 3009 IXGBE_VLVFB(vlvf_index*2)); 3010 bits |= (1 << vind); 3011 IXGBE_WRITE_REG(hw, 3012 IXGBE_VLVFB(vlvf_index*2), 3013 bits); 3014 } else { 3015 bits = IXGBE_READ_REG(hw, 3016 IXGBE_VLVFB((vlvf_index*2)+1)); 3017 bits |= (1 << (vind-32)); 3018 IXGBE_WRITE_REG(hw, 3019 IXGBE_VLVFB((vlvf_index*2)+1), 3020 bits); 3021 } 3022 } else { 3023 /* clear the pool bit */ 3024 if (vind < 32) { 3025 bits = IXGBE_READ_REG(hw, 3026 IXGBE_VLVFB(vlvf_index*2)); 3027 bits &= ~(1 << vind); 3028 IXGBE_WRITE_REG(hw, 3029 IXGBE_VLVFB(vlvf_index*2), 3030 bits); 3031 bits |= IXGBE_READ_REG(hw, 3032 IXGBE_VLVFB((vlvf_index*2)+1)); 3033 } else { 3034 bits = IXGBE_READ_REG(hw, 3035 IXGBE_VLVFB((vlvf_index*2)+1)); 3036 bits &= ~(1 << (vind-32)); 3037 IXGBE_WRITE_REG(hw, 3038 IXGBE_VLVFB((vlvf_index*2)+1), 3039 bits); 3040 bits |= IXGBE_READ_REG(hw, 3041 IXGBE_VLVFB(vlvf_index*2)); 3042 } 3043 } 3044 3045 /* 3046 * If there are still bits set in the VLVFB registers 3047 * for the VLAN ID indicated we need to see if the 3048 * caller is requesting that we clear the VFTA entry bit. 3049 * If the caller has requested that we clear the VFTA 3050 * entry bit but there are still pools/VFs using this VLAN 3051 * ID entry then ignore the request. We're not worried 3052 * about the case where we're turning the VFTA VLAN ID 3053 * entry bit on, only when requested to turn it off as 3054 * there may be multiple pools and/or VFs using the 3055 * VLAN ID entry. In that case we cannot clear the 3056 * VFTA bit until all pools/VFs using that VLAN ID have also 3057 * been cleared. This will be indicated by "bits" being 3058 * zero. 3059 */ 3060 if (bits) { 3061 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 3062 (IXGBE_VLVF_VIEN | vlan)); 3063 if (!vlan_on) { 3064 /* someone wants to clear the vfta entry 3065 * but some pools/VFs are still using it. 3066 * Ignore it. */ 3067 vfta_changed = false; 3068 } 3069 } 3070 else 3071 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 3072 } 3073 3074 if (vfta_changed) 3075 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta); 3076 3077 return 0; 3078 } 3079 3080 /** 3081 * ixgbe_clear_vfta_generic - Clear VLAN filter table 3082 * @hw: pointer to hardware structure 3083 * 3084 * Clears the VLAN filer table, and the VMDq index associated with the filter 3085 **/ 3086 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 3087 { 3088 u32 offset; 3089 3090 for (offset = 0; offset < hw->mac.vft_size; offset++) 3091 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 3092 3093 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 3094 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 3095 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0); 3096 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0); 3097 } 3098 3099 return 0; 3100 } 3101 3102 /** 3103 * ixgbe_check_mac_link_generic - Determine link and speed status 3104 * @hw: pointer to hardware structure 3105 * @speed: pointer to link speed 3106 * @link_up: true when link is up 3107 * @link_up_wait_to_complete: bool used to wait for link up or not 3108 * 3109 * Reads the links register to determine if link is up and the current speed 3110 **/ 3111 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3112 bool *link_up, bool link_up_wait_to_complete) 3113 { 3114 u32 links_reg, links_orig; 3115 u32 i; 3116 3117 /* clear the old state */ 3118 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 3119 3120 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3121 3122 if (links_orig != links_reg) { 3123 hw_dbg(hw, "LINKS changed from %08X to %08X\n", 3124 links_orig, links_reg); 3125 } 3126 3127 if (link_up_wait_to_complete) { 3128 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 3129 if (links_reg & IXGBE_LINKS_UP) { 3130 *link_up = true; 3131 break; 3132 } else { 3133 *link_up = false; 3134 } 3135 msleep(100); 3136 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3137 } 3138 } else { 3139 if (links_reg & IXGBE_LINKS_UP) 3140 *link_up = true; 3141 else 3142 *link_up = false; 3143 } 3144 3145 if ((links_reg & IXGBE_LINKS_SPEED_82599) == 3146 IXGBE_LINKS_SPEED_10G_82599) 3147 *speed = IXGBE_LINK_SPEED_10GB_FULL; 3148 else if ((links_reg & IXGBE_LINKS_SPEED_82599) == 3149 IXGBE_LINKS_SPEED_1G_82599) 3150 *speed = IXGBE_LINK_SPEED_1GB_FULL; 3151 else if ((links_reg & IXGBE_LINKS_SPEED_82599) == 3152 IXGBE_LINKS_SPEED_100_82599) 3153 *speed = IXGBE_LINK_SPEED_100_FULL; 3154 else 3155 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3156 3157 return 0; 3158 } 3159 3160 /** 3161 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 3162 * the EEPROM 3163 * @hw: pointer to hardware structure 3164 * @wwnn_prefix: the alternative WWNN prefix 3165 * @wwpn_prefix: the alternative WWPN prefix 3166 * 3167 * This function will read the EEPROM from the alternative SAN MAC address 3168 * block to check the support for the alternative WWNN/WWPN prefix support. 3169 **/ 3170 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 3171 u16 *wwpn_prefix) 3172 { 3173 u16 offset, caps; 3174 u16 alt_san_mac_blk_offset; 3175 3176 /* clear output first */ 3177 *wwnn_prefix = 0xFFFF; 3178 *wwpn_prefix = 0xFFFF; 3179 3180 /* check if alternative SAN MAC is supported */ 3181 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR, 3182 &alt_san_mac_blk_offset); 3183 3184 if ((alt_san_mac_blk_offset == 0) || 3185 (alt_san_mac_blk_offset == 0xFFFF)) 3186 goto wwn_prefix_out; 3187 3188 /* check capability in alternative san mac address block */ 3189 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 3190 hw->eeprom.ops.read(hw, offset, &caps); 3191 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 3192 goto wwn_prefix_out; 3193 3194 /* get the corresponding prefix for WWNN/WWPN */ 3195 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 3196 hw->eeprom.ops.read(hw, offset, wwnn_prefix); 3197 3198 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 3199 hw->eeprom.ops.read(hw, offset, wwpn_prefix); 3200 3201 wwn_prefix_out: 3202 return 0; 3203 } 3204 3205 /** 3206 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 3207 * @hw: pointer to hardware structure 3208 * @enable: enable or disable switch for anti-spoofing 3209 * @pf: Physical Function pool - do not enable anti-spoofing for the PF 3210 * 3211 **/ 3212 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf) 3213 { 3214 int j; 3215 int pf_target_reg = pf >> 3; 3216 int pf_target_shift = pf % 8; 3217 u32 pfvfspoof = 0; 3218 3219 if (hw->mac.type == ixgbe_mac_82598EB) 3220 return; 3221 3222 if (enable) 3223 pfvfspoof = IXGBE_SPOOF_MACAS_MASK; 3224 3225 /* 3226 * PFVFSPOOF register array is size 8 with 8 bits assigned to 3227 * MAC anti-spoof enables in each register array element. 3228 */ 3229 for (j = 0; j < pf_target_reg; j++) 3230 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof); 3231 3232 /* 3233 * The PF should be allowed to spoof so that it can support 3234 * emulation mode NICs. Do not set the bits assigned to the PF 3235 */ 3236 pfvfspoof &= (1 << pf_target_shift) - 1; 3237 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof); 3238 3239 /* 3240 * Remaining pools belong to the PF so they do not need to have 3241 * anti-spoofing enabled. 3242 */ 3243 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++) 3244 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0); 3245 } 3246 3247 /** 3248 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 3249 * @hw: pointer to hardware structure 3250 * @enable: enable or disable switch for VLAN anti-spoofing 3251 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 3252 * 3253 **/ 3254 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 3255 { 3256 int vf_target_reg = vf >> 3; 3257 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 3258 u32 pfvfspoof; 3259 3260 if (hw->mac.type == ixgbe_mac_82598EB) 3261 return; 3262 3263 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3264 if (enable) 3265 pfvfspoof |= (1 << vf_target_shift); 3266 else 3267 pfvfspoof &= ~(1 << vf_target_shift); 3268 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3269 } 3270 3271 /** 3272 * ixgbe_get_device_caps_generic - Get additional device capabilities 3273 * @hw: pointer to hardware structure 3274 * @device_caps: the EEPROM word with the extra device capabilities 3275 * 3276 * This function will read the EEPROM location for the device capabilities, 3277 * and return the word through device_caps. 3278 **/ 3279 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 3280 { 3281 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 3282 3283 return 0; 3284 } 3285 3286 /** 3287 * ixgbe_set_rxpba_generic - Initialize RX packet buffer 3288 * @hw: pointer to hardware structure 3289 * @num_pb: number of packet buffers to allocate 3290 * @headroom: reserve n KB of headroom 3291 * @strategy: packet buffer allocation strategy 3292 **/ 3293 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, 3294 int num_pb, 3295 u32 headroom, 3296 int strategy) 3297 { 3298 u32 pbsize = hw->mac.rx_pb_size; 3299 int i = 0; 3300 u32 rxpktsize, txpktsize, txpbthresh; 3301 3302 /* Reserve headroom */ 3303 pbsize -= headroom; 3304 3305 if (!num_pb) 3306 num_pb = 1; 3307 3308 /* Divide remaining packet buffer space amongst the number 3309 * of packet buffers requested using supplied strategy. 3310 */ 3311 switch (strategy) { 3312 case (PBA_STRATEGY_WEIGHTED): 3313 /* pba_80_48 strategy weight first half of packet buffer with 3314 * 5/8 of the packet buffer space. 3315 */ 3316 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8)); 3317 pbsize -= rxpktsize * (num_pb / 2); 3318 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 3319 for (; i < (num_pb / 2); i++) 3320 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3321 /* Fall through to configure remaining packet buffers */ 3322 case (PBA_STRATEGY_EQUAL): 3323 /* Divide the remaining Rx packet buffer evenly among the TCs */ 3324 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 3325 for (; i < num_pb; i++) 3326 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3327 break; 3328 default: 3329 break; 3330 } 3331 3332 /* 3333 * Setup Tx packet buffer and threshold equally for all TCs 3334 * TXPBTHRESH register is set in K so divide by 1024 and subtract 3335 * 10 since the largest packet we support is just over 9K. 3336 */ 3337 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 3338 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 3339 for (i = 0; i < num_pb; i++) { 3340 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 3341 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 3342 } 3343 3344 /* Clear unused TCs, if any, to zero buffer size*/ 3345 for (; i < IXGBE_MAX_PB; i++) { 3346 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 3347 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 3348 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 3349 } 3350 } 3351 3352 /** 3353 * ixgbe_calculate_checksum - Calculate checksum for buffer 3354 * @buffer: pointer to EEPROM 3355 * @length: size of EEPROM to calculate a checksum for 3356 * 3357 * Calculates the checksum for some buffer on a specified length. The 3358 * checksum calculated is returned. 3359 **/ 3360 static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 3361 { 3362 u32 i; 3363 u8 sum = 0; 3364 3365 if (!buffer) 3366 return 0; 3367 3368 for (i = 0; i < length; i++) 3369 sum += buffer[i]; 3370 3371 return (u8) (0 - sum); 3372 } 3373 3374 /** 3375 * ixgbe_host_interface_command - Issue command to manageability block 3376 * @hw: pointer to the HW structure 3377 * @buffer: contains the command to write and where the return status will 3378 * be placed 3379 * @length: length of buffer, must be multiple of 4 bytes 3380 * 3381 * Communicates with the manageability block. On success return 0 3382 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND. 3383 **/ 3384 static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 3385 u32 length) 3386 { 3387 u32 hicr, i, bi; 3388 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 3389 u8 buf_len, dword_len; 3390 3391 s32 ret_val = 0; 3392 3393 if (length == 0 || length & 0x3 || 3394 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 3395 hw_dbg(hw, "Buffer length failure.\n"); 3396 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3397 goto out; 3398 } 3399 3400 /* Check that the host interface is enabled. */ 3401 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3402 if ((hicr & IXGBE_HICR_EN) == 0) { 3403 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n"); 3404 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3405 goto out; 3406 } 3407 3408 /* Calculate length in DWORDs */ 3409 dword_len = length >> 2; 3410 3411 /* 3412 * The device driver writes the relevant command block 3413 * into the ram area. 3414 */ 3415 for (i = 0; i < dword_len; i++) 3416 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 3417 i, cpu_to_le32(buffer[i])); 3418 3419 /* Setting this bit tells the ARC that a new command is pending. */ 3420 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 3421 3422 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) { 3423 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3424 if (!(hicr & IXGBE_HICR_C)) 3425 break; 3426 usleep_range(1000, 2000); 3427 } 3428 3429 /* Check command successful completion. */ 3430 if (i == IXGBE_HI_COMMAND_TIMEOUT || 3431 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) { 3432 hw_dbg(hw, "Command has failed with no status valid.\n"); 3433 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3434 goto out; 3435 } 3436 3437 /* Calculate length in DWORDs */ 3438 dword_len = hdr_size >> 2; 3439 3440 /* first pull in the header so we know the buffer length */ 3441 for (bi = 0; bi < dword_len; bi++) { 3442 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3443 le32_to_cpus(&buffer[bi]); 3444 } 3445 3446 /* If there is any thing in data position pull it in */ 3447 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len; 3448 if (buf_len == 0) 3449 goto out; 3450 3451 if (length < (buf_len + hdr_size)) { 3452 hw_dbg(hw, "Buffer not large enough for reply message.\n"); 3453 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3454 goto out; 3455 } 3456 3457 /* Calculate length in DWORDs, add 3 for odd lengths */ 3458 dword_len = (buf_len + 3) >> 2; 3459 3460 /* Pull in the rest of the buffer (bi is where we left off)*/ 3461 for (; bi <= dword_len; bi++) { 3462 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3463 le32_to_cpus(&buffer[bi]); 3464 } 3465 3466 out: 3467 return ret_val; 3468 } 3469 3470 /** 3471 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 3472 * @hw: pointer to the HW structure 3473 * @maj: driver version major number 3474 * @min: driver version minor number 3475 * @build: driver version build number 3476 * @sub: driver version sub build number 3477 * 3478 * Sends driver version number to firmware through the manageability 3479 * block. On success return 0 3480 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 3481 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 3482 **/ 3483 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 3484 u8 build, u8 sub) 3485 { 3486 struct ixgbe_hic_drv_info fw_cmd; 3487 int i; 3488 s32 ret_val = 0; 3489 3490 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM) != 0) { 3491 ret_val = IXGBE_ERR_SWFW_SYNC; 3492 goto out; 3493 } 3494 3495 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 3496 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 3497 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 3498 fw_cmd.port_num = (u8)hw->bus.func; 3499 fw_cmd.ver_maj = maj; 3500 fw_cmd.ver_min = min; 3501 fw_cmd.ver_build = build; 3502 fw_cmd.ver_sub = sub; 3503 fw_cmd.hdr.checksum = 0; 3504 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 3505 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 3506 fw_cmd.pad = 0; 3507 fw_cmd.pad2 = 0; 3508 3509 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 3510 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 3511 sizeof(fw_cmd)); 3512 if (ret_val != 0) 3513 continue; 3514 3515 if (fw_cmd.hdr.cmd_or_resp.ret_status == 3516 FW_CEM_RESP_STATUS_SUCCESS) 3517 ret_val = 0; 3518 else 3519 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3520 3521 break; 3522 } 3523 3524 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 3525 out: 3526 return ret_val; 3527 } 3528 3529 /** 3530 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 3531 * @hw: pointer to the hardware structure 3532 * 3533 * The 82599 and x540 MACs can experience issues if TX work is still pending 3534 * when a reset occurs. This function prevents this by flushing the PCIe 3535 * buffers on the system. 3536 **/ 3537 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 3538 { 3539 u32 gcr_ext, hlreg0; 3540 3541 /* 3542 * If double reset is not requested then all transactions should 3543 * already be clear and as such there is no work to do 3544 */ 3545 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 3546 return; 3547 3548 /* 3549 * Set loopback enable to prevent any transmits from being sent 3550 * should the link come up. This assumes that the RXCTRL.RXEN bit 3551 * has already been cleared. 3552 */ 3553 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3554 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 3555 3556 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 3557 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 3558 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 3559 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 3560 3561 /* Flush all writes and allow 20usec for all transactions to clear */ 3562 IXGBE_WRITE_FLUSH(hw); 3563 udelay(20); 3564 3565 /* restore previous register values */ 3566 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 3567 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3568 } 3569 3570 static const u8 ixgbe_emc_temp_data[4] = { 3571 IXGBE_EMC_INTERNAL_DATA, 3572 IXGBE_EMC_DIODE1_DATA, 3573 IXGBE_EMC_DIODE2_DATA, 3574 IXGBE_EMC_DIODE3_DATA 3575 }; 3576 static const u8 ixgbe_emc_therm_limit[4] = { 3577 IXGBE_EMC_INTERNAL_THERM_LIMIT, 3578 IXGBE_EMC_DIODE1_THERM_LIMIT, 3579 IXGBE_EMC_DIODE2_THERM_LIMIT, 3580 IXGBE_EMC_DIODE3_THERM_LIMIT 3581 }; 3582 3583 /** 3584 * ixgbe_get_ets_data - Extracts the ETS bit data 3585 * @hw: pointer to hardware structure 3586 * @ets_cfg: extected ETS data 3587 * @ets_offset: offset of ETS data 3588 * 3589 * Returns error code. 3590 **/ 3591 static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg, 3592 u16 *ets_offset) 3593 { 3594 s32 status = 0; 3595 3596 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset); 3597 if (status) 3598 goto out; 3599 3600 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF)) { 3601 status = IXGBE_NOT_IMPLEMENTED; 3602 goto out; 3603 } 3604 3605 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg); 3606 if (status) 3607 goto out; 3608 3609 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED) { 3610 status = IXGBE_NOT_IMPLEMENTED; 3611 goto out; 3612 } 3613 3614 out: 3615 return status; 3616 } 3617 3618 /** 3619 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data 3620 * @hw: pointer to hardware structure 3621 * 3622 * Returns the thermal sensor data structure 3623 **/ 3624 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) 3625 { 3626 s32 status = 0; 3627 u16 ets_offset; 3628 u16 ets_cfg; 3629 u16 ets_sensor; 3630 u8 num_sensors; 3631 u8 i; 3632 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 3633 3634 /* Only support thermal sensors attached to physical port 0 */ 3635 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) { 3636 status = IXGBE_NOT_IMPLEMENTED; 3637 goto out; 3638 } 3639 3640 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); 3641 if (status) 3642 goto out; 3643 3644 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 3645 if (num_sensors > IXGBE_MAX_SENSORS) 3646 num_sensors = IXGBE_MAX_SENSORS; 3647 3648 for (i = 0; i < num_sensors; i++) { 3649 u8 sensor_index; 3650 u8 sensor_location; 3651 3652 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), 3653 &ets_sensor); 3654 if (status) 3655 goto out; 3656 3657 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 3658 IXGBE_ETS_DATA_INDEX_SHIFT); 3659 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 3660 IXGBE_ETS_DATA_LOC_SHIFT); 3661 3662 if (sensor_location != 0) { 3663 status = hw->phy.ops.read_i2c_byte(hw, 3664 ixgbe_emc_temp_data[sensor_index], 3665 IXGBE_I2C_THERMAL_SENSOR_ADDR, 3666 &data->sensor[i].temp); 3667 if (status) 3668 goto out; 3669 } 3670 } 3671 out: 3672 return status; 3673 } 3674 3675 /** 3676 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds 3677 * @hw: pointer to hardware structure 3678 * 3679 * Inits the thermal sensor thresholds according to the NVM map 3680 * and save off the threshold and location values into mac.thermal_sensor_data 3681 **/ 3682 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) 3683 { 3684 s32 status = 0; 3685 u16 ets_offset; 3686 u16 ets_cfg; 3687 u16 ets_sensor; 3688 u8 low_thresh_delta; 3689 u8 num_sensors; 3690 u8 therm_limit; 3691 u8 i; 3692 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 3693 3694 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data)); 3695 3696 /* Only support thermal sensors attached to physical port 0 */ 3697 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) { 3698 status = IXGBE_NOT_IMPLEMENTED; 3699 goto out; 3700 } 3701 3702 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); 3703 if (status) 3704 goto out; 3705 3706 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >> 3707 IXGBE_ETS_LTHRES_DELTA_SHIFT); 3708 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); 3709 if (num_sensors > IXGBE_MAX_SENSORS) 3710 num_sensors = IXGBE_MAX_SENSORS; 3711 3712 for (i = 0; i < num_sensors; i++) { 3713 u8 sensor_index; 3714 u8 sensor_location; 3715 3716 hw->eeprom.ops.read(hw, (ets_offset + 1 + i), &ets_sensor); 3717 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> 3718 IXGBE_ETS_DATA_INDEX_SHIFT); 3719 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> 3720 IXGBE_ETS_DATA_LOC_SHIFT); 3721 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK; 3722 3723 hw->phy.ops.write_i2c_byte(hw, 3724 ixgbe_emc_therm_limit[sensor_index], 3725 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit); 3726 3727 if (sensor_location == 0) 3728 continue; 3729 3730 data->sensor[i].location = sensor_location; 3731 data->sensor[i].caution_thresh = therm_limit; 3732 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta; 3733 } 3734 out: 3735 return status; 3736 } 3737 3738