1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/pci.h> 30 #include <linux/delay.h> 31 #include <linux/sched.h> 32 33 #include "ixgbe.h" 34 #include "ixgbe_phy.h" 35 #include "ixgbe_mbx.h" 36 37 #define IXGBE_82599_MAX_TX_QUEUES 128 38 #define IXGBE_82599_MAX_RX_QUEUES 128 39 #define IXGBE_82599_RAR_ENTRIES 128 40 #define IXGBE_82599_MC_TBL_SIZE 128 41 #define IXGBE_82599_VFT_TBL_SIZE 128 42 #define IXGBE_82599_RX_PB_SIZE 512 43 44 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 45 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 46 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 47 static void 48 ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *, ixgbe_link_speed); 49 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 50 ixgbe_link_speed speed, 51 bool autoneg_wait_to_complete); 52 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw); 53 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 54 bool autoneg_wait_to_complete); 55 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 56 ixgbe_link_speed speed, 57 bool autoneg_wait_to_complete); 58 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 59 ixgbe_link_speed speed, 60 bool autoneg_wait_to_complete); 61 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 62 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 63 u8 dev_addr, u8 *data); 64 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 65 u8 dev_addr, u8 data); 66 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw); 67 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw); 68 69 bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 70 { 71 u32 fwsm, manc, factps; 72 73 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 74 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) 75 return false; 76 77 manc = IXGBE_READ_REG(hw, IXGBE_MANC); 78 if (!(manc & IXGBE_MANC_RCV_TCO_EN)) 79 return false; 80 81 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); 82 if (factps & IXGBE_FACTPS_MNGCG) 83 return false; 84 85 return true; 86 } 87 88 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 89 { 90 struct ixgbe_mac_info *mac = &hw->mac; 91 92 /* enable the laser control functions for SFP+ fiber 93 * and MNG not enabled 94 */ 95 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && 96 !ixgbe_mng_enabled(hw)) { 97 mac->ops.disable_tx_laser = 98 &ixgbe_disable_tx_laser_multispeed_fiber; 99 mac->ops.enable_tx_laser = 100 &ixgbe_enable_tx_laser_multispeed_fiber; 101 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; 102 } else { 103 mac->ops.disable_tx_laser = NULL; 104 mac->ops.enable_tx_laser = NULL; 105 mac->ops.flap_tx_laser = NULL; 106 } 107 108 if (hw->phy.multispeed_fiber) { 109 /* Set up dual speed SFP+ support */ 110 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; 111 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599; 112 mac->ops.set_rate_select_speed = 113 ixgbe_set_hard_rate_select_speed; 114 } else { 115 if ((mac->ops.get_media_type(hw) == 116 ixgbe_media_type_backplane) && 117 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 118 hw->phy.smart_speed == ixgbe_smart_speed_on) && 119 !ixgbe_verify_lesm_fw_enabled_82599(hw)) 120 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; 121 else 122 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; 123 } 124 } 125 126 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 127 { 128 s32 ret_val; 129 u16 list_offset, data_offset, data_value; 130 131 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 132 ixgbe_init_mac_link_ops_82599(hw); 133 134 hw->phy.ops.reset = NULL; 135 136 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 137 &data_offset); 138 if (ret_val) 139 return ret_val; 140 141 /* PHY config will finish before releasing the semaphore */ 142 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 143 IXGBE_GSSR_MAC_CSR_SM); 144 if (ret_val) 145 return IXGBE_ERR_SWFW_SYNC; 146 147 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 148 goto setup_sfp_err; 149 while (data_value != 0xffff) { 150 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 151 IXGBE_WRITE_FLUSH(hw); 152 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 153 goto setup_sfp_err; 154 } 155 156 /* Release the semaphore */ 157 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 158 /* 159 * Delay obtaining semaphore again to allow FW access, 160 * semaphore_delay is in ms usleep_range needs us. 161 */ 162 usleep_range(hw->eeprom.semaphore_delay * 1000, 163 hw->eeprom.semaphore_delay * 2000); 164 165 /* Restart DSP and set SFI mode */ 166 ret_val = hw->mac.ops.prot_autoc_write(hw, 167 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL, 168 false); 169 170 if (ret_val) { 171 hw_dbg(hw, " sfp module setup not complete\n"); 172 return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 173 } 174 } 175 176 return 0; 177 178 setup_sfp_err: 179 /* Release the semaphore */ 180 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 181 /* Delay obtaining semaphore again to allow FW access, 182 * semaphore_delay is in ms usleep_range needs us. 183 */ 184 usleep_range(hw->eeprom.semaphore_delay * 1000, 185 hw->eeprom.semaphore_delay * 2000); 186 hw_err(hw, "eeprom read at offset %d failed\n", data_offset); 187 return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 188 } 189 190 /** 191 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read 192 * @hw: pointer to hardware structure 193 * @locked: Return the if we locked for this read. 194 * @reg_val: Value we read from AUTOC 195 * 196 * For this part (82599) we need to wrap read-modify-writes with a possible 197 * FW/SW lock. It is assumed this lock will be freed with the next 198 * prot_autoc_write_82599(). Note, that locked can only be true in cases 199 * where this function doesn't return an error. 200 **/ 201 static s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, 202 u32 *reg_val) 203 { 204 s32 ret_val; 205 206 *locked = false; 207 /* If LESM is on then we need to hold the SW/FW semaphore. */ 208 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 209 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 210 IXGBE_GSSR_MAC_CSR_SM); 211 if (ret_val) 212 return IXGBE_ERR_SWFW_SYNC; 213 214 *locked = true; 215 } 216 217 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 218 return 0; 219 } 220 221 /** 222 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write 223 * @hw: pointer to hardware structure 224 * @reg_val: value to write to AUTOC 225 * @locked: bool to indicate whether the SW/FW lock was already taken by 226 * previous proc_autoc_read_82599. 227 * 228 * This part (82599) may need to hold a the SW/FW lock around all writes to 229 * AUTOC. Likewise after a write we need to do a pipeline reset. 230 **/ 231 static s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked) 232 { 233 s32 ret_val = 0; 234 235 /* Blocked by MNG FW so bail */ 236 if (ixgbe_check_reset_blocked(hw)) 237 goto out; 238 239 /* We only need to get the lock if: 240 * - We didn't do it already (in the read part of a read-modify-write) 241 * - LESM is enabled. 242 */ 243 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) { 244 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 245 IXGBE_GSSR_MAC_CSR_SM); 246 if (ret_val) 247 return IXGBE_ERR_SWFW_SYNC; 248 249 locked = true; 250 } 251 252 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 253 ret_val = ixgbe_reset_pipeline_82599(hw); 254 255 out: 256 /* Free the SW/FW semaphore as we either grabbed it here or 257 * already had it when this function was called. 258 */ 259 if (locked) 260 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 261 262 return ret_val; 263 } 264 265 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw) 266 { 267 struct ixgbe_mac_info *mac = &hw->mac; 268 269 ixgbe_init_mac_link_ops_82599(hw); 270 271 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; 272 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; 273 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; 274 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE; 275 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; 276 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; 277 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 278 279 return 0; 280 } 281 282 /** 283 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 284 * @hw: pointer to hardware structure 285 * 286 * Initialize any function pointers that were not able to be 287 * set during get_invariants because the PHY/SFP type was 288 * not known. Perform the SFP init if necessary. 289 * 290 **/ 291 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 292 { 293 struct ixgbe_mac_info *mac = &hw->mac; 294 struct ixgbe_phy_info *phy = &hw->phy; 295 s32 ret_val; 296 u32 esdp; 297 298 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) { 299 /* Store flag indicating I2C bus access control unit. */ 300 hw->phy.qsfp_shared_i2c_bus = true; 301 302 /* Initialize access to QSFP+ I2C bus */ 303 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 304 esdp |= IXGBE_ESDP_SDP0_DIR; 305 esdp &= ~IXGBE_ESDP_SDP1_DIR; 306 esdp &= ~IXGBE_ESDP_SDP0; 307 esdp &= ~IXGBE_ESDP_SDP0_NATIVE; 308 esdp &= ~IXGBE_ESDP_SDP1_NATIVE; 309 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 310 IXGBE_WRITE_FLUSH(hw); 311 312 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599; 313 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599; 314 } 315 316 /* Identify the PHY or SFP module */ 317 ret_val = phy->ops.identify(hw); 318 319 /* Setup function pointers based on detected SFP module and speeds */ 320 ixgbe_init_mac_link_ops_82599(hw); 321 322 /* If copper media, overwrite with copper function pointers */ 323 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 324 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; 325 mac->ops.get_link_capabilities = 326 &ixgbe_get_copper_link_capabilities_generic; 327 } 328 329 /* Set necessary function pointers based on phy type */ 330 switch (hw->phy.type) { 331 case ixgbe_phy_tn: 332 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 333 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 334 break; 335 default: 336 break; 337 } 338 339 return ret_val; 340 } 341 342 /** 343 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 344 * @hw: pointer to hardware structure 345 * @speed: pointer to link speed 346 * @autoneg: true when autoneg or autotry is enabled 347 * 348 * Determines the link capabilities by reading the AUTOC register. 349 **/ 350 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 351 ixgbe_link_speed *speed, 352 bool *autoneg) 353 { 354 u32 autoc = 0; 355 356 /* Determine 1G link capabilities off of SFP+ type */ 357 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 358 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 359 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 360 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 361 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 362 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 363 *speed = IXGBE_LINK_SPEED_1GB_FULL; 364 *autoneg = true; 365 return 0; 366 } 367 368 /* 369 * Determine link capabilities based on the stored value of AUTOC, 370 * which represents EEPROM defaults. If AUTOC value has not been 371 * stored, use the current register value. 372 */ 373 if (hw->mac.orig_link_settings_stored) 374 autoc = hw->mac.orig_autoc; 375 else 376 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 377 378 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 379 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 380 *speed = IXGBE_LINK_SPEED_1GB_FULL; 381 *autoneg = false; 382 break; 383 384 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 385 *speed = IXGBE_LINK_SPEED_10GB_FULL; 386 *autoneg = false; 387 break; 388 389 case IXGBE_AUTOC_LMS_1G_AN: 390 *speed = IXGBE_LINK_SPEED_1GB_FULL; 391 *autoneg = true; 392 break; 393 394 case IXGBE_AUTOC_LMS_10G_SERIAL: 395 *speed = IXGBE_LINK_SPEED_10GB_FULL; 396 *autoneg = false; 397 break; 398 399 case IXGBE_AUTOC_LMS_KX4_KX_KR: 400 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 401 *speed = IXGBE_LINK_SPEED_UNKNOWN; 402 if (autoc & IXGBE_AUTOC_KR_SUPP) 403 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 404 if (autoc & IXGBE_AUTOC_KX4_SUPP) 405 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 406 if (autoc & IXGBE_AUTOC_KX_SUPP) 407 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 408 *autoneg = true; 409 break; 410 411 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 412 *speed = IXGBE_LINK_SPEED_100_FULL; 413 if (autoc & IXGBE_AUTOC_KR_SUPP) 414 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 415 if (autoc & IXGBE_AUTOC_KX4_SUPP) 416 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 417 if (autoc & IXGBE_AUTOC_KX_SUPP) 418 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 419 *autoneg = true; 420 break; 421 422 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 423 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 424 *autoneg = false; 425 break; 426 427 default: 428 return IXGBE_ERR_LINK_SETUP; 429 } 430 431 if (hw->phy.multispeed_fiber) { 432 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 433 IXGBE_LINK_SPEED_1GB_FULL; 434 435 /* QSFP must not enable auto-negotiation */ 436 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp) 437 *autoneg = false; 438 else 439 *autoneg = true; 440 } 441 442 return 0; 443 } 444 445 /** 446 * ixgbe_get_media_type_82599 - Get media type 447 * @hw: pointer to hardware structure 448 * 449 * Returns the media type (fiber, copper, backplane) 450 **/ 451 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 452 { 453 /* Detect if there is a copper PHY attached. */ 454 switch (hw->phy.type) { 455 case ixgbe_phy_cu_unknown: 456 case ixgbe_phy_tn: 457 return ixgbe_media_type_copper; 458 459 default: 460 break; 461 } 462 463 switch (hw->device_id) { 464 case IXGBE_DEV_ID_82599_KX4: 465 case IXGBE_DEV_ID_82599_KX4_MEZZ: 466 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 467 case IXGBE_DEV_ID_82599_KR: 468 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 469 case IXGBE_DEV_ID_82599_XAUI_LOM: 470 /* Default device ID is mezzanine card KX/KX4 */ 471 return ixgbe_media_type_backplane; 472 473 case IXGBE_DEV_ID_82599_SFP: 474 case IXGBE_DEV_ID_82599_SFP_FCOE: 475 case IXGBE_DEV_ID_82599_SFP_EM: 476 case IXGBE_DEV_ID_82599_SFP_SF2: 477 case IXGBE_DEV_ID_82599_SFP_SF_QP: 478 case IXGBE_DEV_ID_82599EN_SFP: 479 return ixgbe_media_type_fiber; 480 481 case IXGBE_DEV_ID_82599_CX4: 482 return ixgbe_media_type_cx4; 483 484 case IXGBE_DEV_ID_82599_T3_LOM: 485 return ixgbe_media_type_copper; 486 487 case IXGBE_DEV_ID_82599_LS: 488 return ixgbe_media_type_fiber_lco; 489 490 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 491 return ixgbe_media_type_fiber_qsfp; 492 493 default: 494 return ixgbe_media_type_unknown; 495 } 496 } 497 498 /** 499 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3 500 * @hw: pointer to hardware structure 501 * 502 * Disables link, should be called during D3 power down sequence. 503 * 504 **/ 505 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw) 506 { 507 u32 autoc2_reg; 508 u16 ee_ctrl_2 = 0; 509 510 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); 511 512 if (!ixgbe_mng_present(hw) && !hw->wol_enabled && 513 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) { 514 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 515 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK; 516 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 517 } 518 } 519 520 /** 521 * ixgbe_start_mac_link_82599 - Setup MAC link settings 522 * @hw: pointer to hardware structure 523 * @autoneg_wait_to_complete: true when waiting for completion is needed 524 * 525 * Configures link settings based on values in the ixgbe_hw struct. 526 * Restarts the link. Performs autonegotiation if needed. 527 **/ 528 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 529 bool autoneg_wait_to_complete) 530 { 531 u32 autoc_reg; 532 u32 links_reg; 533 u32 i; 534 s32 status = 0; 535 bool got_lock = false; 536 537 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 538 status = hw->mac.ops.acquire_swfw_sync(hw, 539 IXGBE_GSSR_MAC_CSR_SM); 540 if (status) 541 return status; 542 543 got_lock = true; 544 } 545 546 /* Restart link */ 547 ixgbe_reset_pipeline_82599(hw); 548 549 if (got_lock) 550 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 551 552 /* Only poll for autoneg to complete if specified to do so */ 553 if (autoneg_wait_to_complete) { 554 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 555 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 556 IXGBE_AUTOC_LMS_KX4_KX_KR || 557 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 558 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 559 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 560 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 561 links_reg = 0; /* Just in case Autoneg time = 0 */ 562 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 563 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 564 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 565 break; 566 msleep(100); 567 } 568 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 569 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 570 hw_dbg(hw, "Autoneg did not complete.\n"); 571 } 572 } 573 } 574 575 /* Add delay to filter out noises during initial link setup */ 576 msleep(50); 577 578 return status; 579 } 580 581 /** 582 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 583 * @hw: pointer to hardware structure 584 * 585 * The base drivers may require better control over SFP+ module 586 * PHY states. This includes selectively shutting down the Tx 587 * laser on the PHY, effectively halting physical link. 588 **/ 589 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 590 { 591 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 592 593 /* Blocked by MNG FW so bail */ 594 if (ixgbe_check_reset_blocked(hw)) 595 return; 596 597 /* Disable tx laser; allow 100us to go dark per spec */ 598 esdp_reg |= IXGBE_ESDP_SDP3; 599 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 600 IXGBE_WRITE_FLUSH(hw); 601 udelay(100); 602 } 603 604 /** 605 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 606 * @hw: pointer to hardware structure 607 * 608 * The base drivers may require better control over SFP+ module 609 * PHY states. This includes selectively turning on the Tx 610 * laser on the PHY, effectively starting physical link. 611 **/ 612 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 613 { 614 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 615 616 /* Enable tx laser; allow 100ms to light up */ 617 esdp_reg &= ~IXGBE_ESDP_SDP3; 618 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 619 IXGBE_WRITE_FLUSH(hw); 620 msleep(100); 621 } 622 623 /** 624 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 625 * @hw: pointer to hardware structure 626 * 627 * When the driver changes the link speeds that it can support, 628 * it sets autotry_restart to true to indicate that we need to 629 * initiate a new autotry session with the link partner. To do 630 * so, we set the speed then disable and re-enable the tx laser, to 631 * alert the link partner that it also needs to restart autotry on its 632 * end. This is consistent with true clause 37 autoneg, which also 633 * involves a loss of signal. 634 **/ 635 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 636 { 637 /* Blocked by MNG FW so bail */ 638 if (ixgbe_check_reset_blocked(hw)) 639 return; 640 641 if (hw->mac.autotry_restart) { 642 ixgbe_disable_tx_laser_multispeed_fiber(hw); 643 ixgbe_enable_tx_laser_multispeed_fiber(hw); 644 hw->mac.autotry_restart = false; 645 } 646 } 647 648 /** 649 * ixgbe_set_hard_rate_select_speed - Set module link speed 650 * @hw: pointer to hardware structure 651 * @speed: link speed to set 652 * 653 * Set module link speed via RS0/RS1 rate select pins. 654 */ 655 static void 656 ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 657 { 658 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 659 660 switch (speed) { 661 case IXGBE_LINK_SPEED_10GB_FULL: 662 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 663 break; 664 case IXGBE_LINK_SPEED_1GB_FULL: 665 esdp_reg &= ~IXGBE_ESDP_SDP5; 666 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 667 break; 668 default: 669 hw_dbg(hw, "Invalid fixed module speed\n"); 670 return; 671 } 672 673 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 674 IXGBE_WRITE_FLUSH(hw); 675 } 676 677 /** 678 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 679 * @hw: pointer to hardware structure 680 * @speed: new link speed 681 * @autoneg_wait_to_complete: true when waiting for completion is needed 682 * 683 * Implements the Intel SmartSpeed algorithm. 684 **/ 685 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 686 ixgbe_link_speed speed, 687 bool autoneg_wait_to_complete) 688 { 689 s32 status = 0; 690 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 691 s32 i, j; 692 bool link_up = false; 693 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 694 695 /* Set autoneg_advertised value based on input link speed */ 696 hw->phy.autoneg_advertised = 0; 697 698 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 699 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 700 701 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 702 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 703 704 if (speed & IXGBE_LINK_SPEED_100_FULL) 705 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 706 707 /* 708 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 709 * autoneg advertisement if link is unable to be established at the 710 * highest negotiated rate. This can sometimes happen due to integrity 711 * issues with the physical media connection. 712 */ 713 714 /* First, try to get link with full advertisement */ 715 hw->phy.smart_speed_active = false; 716 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 717 status = ixgbe_setup_mac_link_82599(hw, speed, 718 autoneg_wait_to_complete); 719 if (status != 0) 720 goto out; 721 722 /* 723 * Wait for the controller to acquire link. Per IEEE 802.3ap, 724 * Section 73.10.2, we may have to wait up to 500ms if KR is 725 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 726 * Table 9 in the AN MAS. 727 */ 728 for (i = 0; i < 5; i++) { 729 mdelay(100); 730 731 /* If we have link, just jump out */ 732 status = hw->mac.ops.check_link(hw, &link_speed, 733 &link_up, false); 734 if (status != 0) 735 goto out; 736 737 if (link_up) 738 goto out; 739 } 740 } 741 742 /* 743 * We didn't get link. If we advertised KR plus one of KX4/KX 744 * (or BX4/BX), then disable KR and try again. 745 */ 746 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 747 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 748 goto out; 749 750 /* Turn SmartSpeed on to disable KR support */ 751 hw->phy.smart_speed_active = true; 752 status = ixgbe_setup_mac_link_82599(hw, speed, 753 autoneg_wait_to_complete); 754 if (status != 0) 755 goto out; 756 757 /* 758 * Wait for the controller to acquire link. 600ms will allow for 759 * the AN link_fail_inhibit_timer as well for multiple cycles of 760 * parallel detect, both 10g and 1g. This allows for the maximum 761 * connect attempts as defined in the AN MAS table 73-7. 762 */ 763 for (i = 0; i < 6; i++) { 764 mdelay(100); 765 766 /* If we have link, just jump out */ 767 status = hw->mac.ops.check_link(hw, &link_speed, 768 &link_up, false); 769 if (status != 0) 770 goto out; 771 772 if (link_up) 773 goto out; 774 } 775 776 /* We didn't get link. Turn SmartSpeed back off. */ 777 hw->phy.smart_speed_active = false; 778 status = ixgbe_setup_mac_link_82599(hw, speed, 779 autoneg_wait_to_complete); 780 781 out: 782 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 783 hw_dbg(hw, "Smartspeed has downgraded the link speed from the maximum advertised\n"); 784 return status; 785 } 786 787 /** 788 * ixgbe_setup_mac_link_82599 - Set MAC link speed 789 * @hw: pointer to hardware structure 790 * @speed: new link speed 791 * @autoneg_wait_to_complete: true when waiting for completion is needed 792 * 793 * Set the link speed in the AUTOC register and restarts link. 794 **/ 795 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 796 ixgbe_link_speed speed, 797 bool autoneg_wait_to_complete) 798 { 799 bool autoneg = false; 800 s32 status; 801 u32 pma_pmd_1g, link_mode, links_reg, i; 802 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 803 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 804 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 805 806 /* holds the value of AUTOC register at this current point in time */ 807 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 808 /* holds the cached value of AUTOC register */ 809 u32 orig_autoc = 0; 810 /* temporary variable used for comparison purposes */ 811 u32 autoc = current_autoc; 812 813 /* Check to see if speed passed in is supported. */ 814 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities, 815 &autoneg); 816 if (status) 817 return status; 818 819 speed &= link_capabilities; 820 821 if (speed == IXGBE_LINK_SPEED_UNKNOWN) 822 return IXGBE_ERR_LINK_SETUP; 823 824 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 825 if (hw->mac.orig_link_settings_stored) 826 orig_autoc = hw->mac.orig_autoc; 827 else 828 orig_autoc = autoc; 829 830 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 831 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 832 833 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 834 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 835 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 836 /* Set KX4/KX/KR support according to speed requested */ 837 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 838 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 839 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 840 autoc |= IXGBE_AUTOC_KX4_SUPP; 841 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 842 (hw->phy.smart_speed_active == false)) 843 autoc |= IXGBE_AUTOC_KR_SUPP; 844 } 845 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 846 autoc |= IXGBE_AUTOC_KX_SUPP; 847 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 848 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 849 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 850 /* Switch from 1G SFI to 10G SFI if requested */ 851 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 852 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 853 autoc &= ~IXGBE_AUTOC_LMS_MASK; 854 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 855 } 856 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 857 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 858 /* Switch from 10G SFI to 1G SFI if requested */ 859 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 860 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 861 autoc &= ~IXGBE_AUTOC_LMS_MASK; 862 if (autoneg) 863 autoc |= IXGBE_AUTOC_LMS_1G_AN; 864 else 865 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 866 } 867 } 868 869 if (autoc != current_autoc) { 870 /* Restart link */ 871 status = hw->mac.ops.prot_autoc_write(hw, autoc, false); 872 if (status) 873 return status; 874 875 /* Only poll for autoneg to complete if specified to do so */ 876 if (autoneg_wait_to_complete) { 877 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 878 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 879 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 880 links_reg = 0; /*Just in case Autoneg time=0*/ 881 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 882 links_reg = 883 IXGBE_READ_REG(hw, IXGBE_LINKS); 884 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 885 break; 886 msleep(100); 887 } 888 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 889 status = 890 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 891 hw_dbg(hw, "Autoneg did not complete.\n"); 892 } 893 } 894 } 895 896 /* Add delay to filter out noises during initial link setup */ 897 msleep(50); 898 } 899 900 return status; 901 } 902 903 /** 904 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 905 * @hw: pointer to hardware structure 906 * @speed: new link speed 907 * @autoneg_wait_to_complete: true if waiting is needed to complete 908 * 909 * Restarts link on PHY and MAC based on settings passed in. 910 **/ 911 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 912 ixgbe_link_speed speed, 913 bool autoneg_wait_to_complete) 914 { 915 s32 status; 916 917 /* Setup the PHY according to input speed */ 918 status = hw->phy.ops.setup_link_speed(hw, speed, 919 autoneg_wait_to_complete); 920 /* Set up MAC */ 921 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 922 923 return status; 924 } 925 926 /** 927 * ixgbe_reset_hw_82599 - Perform hardware reset 928 * @hw: pointer to hardware structure 929 * 930 * Resets the hardware by resetting the transmit and receive units, masks 931 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 932 * reset. 933 **/ 934 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 935 { 936 ixgbe_link_speed link_speed; 937 s32 status; 938 u32 ctrl, i, autoc, autoc2; 939 u32 curr_lms; 940 bool link_up = false; 941 942 /* Call adapter stop to disable tx/rx and clear interrupts */ 943 status = hw->mac.ops.stop_adapter(hw); 944 if (status) 945 return status; 946 947 /* flush pending Tx transactions */ 948 ixgbe_clear_tx_pending(hw); 949 950 /* PHY ops must be identified and initialized prior to reset */ 951 952 /* Identify PHY and related function pointers */ 953 status = hw->phy.ops.init(hw); 954 955 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 956 return status; 957 958 /* Setup SFP module if there is one present. */ 959 if (hw->phy.sfp_setup_needed) { 960 status = hw->mac.ops.setup_sfp(hw); 961 hw->phy.sfp_setup_needed = false; 962 } 963 964 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 965 return status; 966 967 /* Reset PHY */ 968 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) 969 hw->phy.ops.reset(hw); 970 971 /* remember AUTOC from before we reset */ 972 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK; 973 974 mac_reset_top: 975 /* 976 * Issue global reset to the MAC. Needs to be SW reset if link is up. 977 * If link reset is used when link is up, it might reset the PHY when 978 * mng is using it. If link is down or the flag to force full link 979 * reset is set, then perform link reset. 980 */ 981 ctrl = IXGBE_CTRL_LNK_RST; 982 if (!hw->force_full_reset) { 983 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 984 if (link_up) 985 ctrl = IXGBE_CTRL_RST; 986 } 987 988 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 989 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 990 IXGBE_WRITE_FLUSH(hw); 991 usleep_range(1000, 1200); 992 993 /* Poll for reset bit to self-clear indicating reset is complete */ 994 for (i = 0; i < 10; i++) { 995 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 996 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 997 break; 998 udelay(1); 999 } 1000 1001 if (ctrl & IXGBE_CTRL_RST_MASK) { 1002 status = IXGBE_ERR_RESET_FAILED; 1003 hw_dbg(hw, "Reset polling failed to complete.\n"); 1004 } 1005 1006 msleep(50); 1007 1008 /* 1009 * Double resets are required for recovery from certain error 1010 * conditions. Between resets, it is necessary to stall to allow time 1011 * for any pending HW events to complete. 1012 */ 1013 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1014 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1015 goto mac_reset_top; 1016 } 1017 1018 /* 1019 * Store the original AUTOC/AUTOC2 values if they have not been 1020 * stored off yet. Otherwise restore the stored original 1021 * values since the reset operation sets back to defaults. 1022 */ 1023 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1024 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1025 1026 /* Enable link if disabled in NVM */ 1027 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 1028 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 1029 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1030 IXGBE_WRITE_FLUSH(hw); 1031 } 1032 1033 if (hw->mac.orig_link_settings_stored == false) { 1034 hw->mac.orig_autoc = autoc; 1035 hw->mac.orig_autoc2 = autoc2; 1036 hw->mac.orig_link_settings_stored = true; 1037 } else { 1038 1039 /* If MNG FW is running on a multi-speed device that 1040 * doesn't autoneg with out driver support we need to 1041 * leave LMS in the state it was before we MAC reset. 1042 * Likewise if we support WoL we don't want change the 1043 * LMS state either. 1044 */ 1045 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) || 1046 hw->wol_enabled) 1047 hw->mac.orig_autoc = 1048 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | 1049 curr_lms; 1050 1051 if (autoc != hw->mac.orig_autoc) { 1052 status = hw->mac.ops.prot_autoc_write(hw, 1053 hw->mac.orig_autoc, 1054 false); 1055 if (status) 1056 return status; 1057 } 1058 1059 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1060 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1061 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1062 autoc2 |= (hw->mac.orig_autoc2 & 1063 IXGBE_AUTOC2_UPPER_MASK); 1064 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1065 } 1066 } 1067 1068 /* Store the permanent mac address */ 1069 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1070 1071 /* 1072 * Store MAC address from RAR0, clear receive address registers, and 1073 * clear the multicast table. Also reset num_rar_entries to 128, 1074 * since we modify this value when programming the SAN MAC address. 1075 */ 1076 hw->mac.num_rar_entries = 128; 1077 hw->mac.ops.init_rx_addrs(hw); 1078 1079 /* Store the permanent SAN mac address */ 1080 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1081 1082 /* Add the SAN MAC address to the RAR only if it's a valid address */ 1083 if (is_valid_ether_addr(hw->mac.san_addr)) { 1084 /* Save the SAN MAC RAR index */ 1085 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 1086 1087 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, 1088 hw->mac.san_addr, 0, IXGBE_RAH_AV); 1089 1090 /* clear VMDq pool/queue selection for this RAR */ 1091 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, 1092 IXGBE_CLEAR_VMDQ_ALL); 1093 1094 /* Reserve the last RAR for the SAN MAC address */ 1095 hw->mac.num_rar_entries--; 1096 } 1097 1098 /* Store the alternative WWNN/WWPN prefix */ 1099 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 1100 &hw->mac.wwpn_prefix); 1101 1102 return status; 1103 } 1104 1105 /** 1106 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete 1107 * @hw: pointer to hardware structure 1108 * @fdircmd: current value of FDIRCMD register 1109 */ 1110 static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd) 1111 { 1112 int i; 1113 1114 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 1115 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); 1116 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK)) 1117 return 0; 1118 udelay(10); 1119 } 1120 1121 return IXGBE_ERR_FDIR_CMD_INCOMPLETE; 1122 } 1123 1124 /** 1125 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 1126 * @hw: pointer to hardware structure 1127 **/ 1128 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 1129 { 1130 int i; 1131 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1132 u32 fdircmd; 1133 s32 err; 1134 1135 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; 1136 1137 /* 1138 * Before starting reinitialization process, 1139 * FDIRCMD.CMD must be zero. 1140 */ 1141 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1142 if (err) { 1143 hw_dbg(hw, "Flow Director previous command did not complete, aborting table re-initialization.\n"); 1144 return err; 1145 } 1146 1147 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); 1148 IXGBE_WRITE_FLUSH(hw); 1149 /* 1150 * 82599 adapters flow director init flow cannot be restarted, 1151 * Workaround 82599 silicon errata by performing the following steps 1152 * before re-writing the FDIRCTRL control register with the same value. 1153 * - write 1 to bit 8 of FDIRCMD register & 1154 * - write 0 to bit 8 of FDIRCMD register 1155 */ 1156 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1157 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1158 IXGBE_FDIRCMD_CLEARHT)); 1159 IXGBE_WRITE_FLUSH(hw); 1160 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1161 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1162 ~IXGBE_FDIRCMD_CLEARHT)); 1163 IXGBE_WRITE_FLUSH(hw); 1164 /* 1165 * Clear FDIR Hash register to clear any leftover hashes 1166 * waiting to be programmed. 1167 */ 1168 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); 1169 IXGBE_WRITE_FLUSH(hw); 1170 1171 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1172 IXGBE_WRITE_FLUSH(hw); 1173 1174 /* Poll init-done after we write FDIRCTRL register */ 1175 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1176 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1177 IXGBE_FDIRCTRL_INIT_DONE) 1178 break; 1179 usleep_range(1000, 2000); 1180 } 1181 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1182 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); 1183 return IXGBE_ERR_FDIR_REINIT_FAILED; 1184 } 1185 1186 /* Clear FDIR statistics registers (read to clear) */ 1187 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1188 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); 1189 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 1190 IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 1191 IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1192 1193 return 0; 1194 } 1195 1196 /** 1197 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers 1198 * @hw: pointer to hardware structure 1199 * @fdirctrl: value to write to flow director control register 1200 **/ 1201 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1202 { 1203 int i; 1204 1205 /* Prime the keys for hashing */ 1206 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1207 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 1208 1209 /* 1210 * Poll init-done after we write the register. Estimated times: 1211 * 10G: PBALLOC = 11b, timing is 60us 1212 * 1G: PBALLOC = 11b, timing is 600us 1213 * 100M: PBALLOC = 11b, timing is 6ms 1214 * 1215 * Multiple these timings by 4 if under full Rx load 1216 * 1217 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1218 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1219 * this might not finish in our poll time, but we can live with that 1220 * for now. 1221 */ 1222 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1223 IXGBE_WRITE_FLUSH(hw); 1224 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1225 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1226 IXGBE_FDIRCTRL_INIT_DONE) 1227 break; 1228 usleep_range(1000, 2000); 1229 } 1230 1231 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1232 hw_dbg(hw, "Flow Director poll time exceeded!\n"); 1233 } 1234 1235 /** 1236 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1237 * @hw: pointer to hardware structure 1238 * @fdirctrl: value to write to flow director control register, initially 1239 * contains just the value of the Rx packet buffer allocation 1240 **/ 1241 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1242 { 1243 /* 1244 * Continue setup of fdirctrl register bits: 1245 * Move the flexible bytes to use the ethertype - shift 6 words 1246 * Set the maximum length per hash bucket to 0xA filters 1247 * Send interrupt when 64 filters are left 1248 */ 1249 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1250 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1251 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1252 1253 /* write hashes and fdirctrl register, poll for completion */ 1254 ixgbe_fdir_enable_82599(hw, fdirctrl); 1255 1256 return 0; 1257 } 1258 1259 /** 1260 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1261 * @hw: pointer to hardware structure 1262 * @fdirctrl: value to write to flow director control register, initially 1263 * contains just the value of the Rx packet buffer allocation 1264 **/ 1265 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1266 { 1267 /* 1268 * Continue setup of fdirctrl register bits: 1269 * Turn perfect match filtering on 1270 * Initialize the drop queue 1271 * Move the flexible bytes to use the ethertype - shift 6 words 1272 * Set the maximum length per hash bucket to 0xA filters 1273 * Send interrupt when 64 (0x4 * 16) filters are left 1274 */ 1275 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH | 1276 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) | 1277 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1278 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1279 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1280 1281 /* write hashes and fdirctrl register, poll for completion */ 1282 ixgbe_fdir_enable_82599(hw, fdirctrl); 1283 1284 return 0; 1285 } 1286 1287 /* 1288 * These defines allow us to quickly generate all of the necessary instructions 1289 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION 1290 * for values 0 through 15 1291 */ 1292 #define IXGBE_ATR_COMMON_HASH_KEY \ 1293 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) 1294 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ 1295 do { \ 1296 u32 n = (_n); \ 1297 if (IXGBE_ATR_COMMON_HASH_KEY & BIT(n)) \ 1298 common_hash ^= lo_hash_dword >> n; \ 1299 else if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n)) \ 1300 bucket_hash ^= lo_hash_dword >> n; \ 1301 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & BIT(n)) \ 1302 sig_hash ^= lo_hash_dword << (16 - n); \ 1303 if (IXGBE_ATR_COMMON_HASH_KEY & BIT(n + 16)) \ 1304 common_hash ^= hi_hash_dword >> n; \ 1305 else if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n + 16)) \ 1306 bucket_hash ^= hi_hash_dword >> n; \ 1307 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & BIT(n + 16)) \ 1308 sig_hash ^= hi_hash_dword << (16 - n); \ 1309 } while (0) 1310 1311 /** 1312 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash 1313 * @stream: input bitstream to compute the hash on 1314 * 1315 * This function is almost identical to the function above but contains 1316 * several optomizations such as unwinding all of the loops, letting the 1317 * compiler work out all of the conditional ifs since the keys are static 1318 * defines, and computing two keys at once since the hashed dword stream 1319 * will be the same for both keys. 1320 **/ 1321 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 1322 union ixgbe_atr_hash_dword common) 1323 { 1324 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1325 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0; 1326 1327 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1328 flow_vm_vlan = ntohl(input.dword); 1329 1330 /* generate common hash dword */ 1331 hi_hash_dword = ntohl(common.dword); 1332 1333 /* low dword is word swapped version of common */ 1334 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1335 1336 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1337 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1338 1339 /* Process bits 0 and 16 */ 1340 IXGBE_COMPUTE_SIG_HASH_ITERATION(0); 1341 1342 /* 1343 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1344 * delay this because bit 0 of the stream should not be processed 1345 * so we do not add the vlan until after bit 0 was processed 1346 */ 1347 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1348 1349 /* Process remaining 30 bit of the key */ 1350 IXGBE_COMPUTE_SIG_HASH_ITERATION(1); 1351 IXGBE_COMPUTE_SIG_HASH_ITERATION(2); 1352 IXGBE_COMPUTE_SIG_HASH_ITERATION(3); 1353 IXGBE_COMPUTE_SIG_HASH_ITERATION(4); 1354 IXGBE_COMPUTE_SIG_HASH_ITERATION(5); 1355 IXGBE_COMPUTE_SIG_HASH_ITERATION(6); 1356 IXGBE_COMPUTE_SIG_HASH_ITERATION(7); 1357 IXGBE_COMPUTE_SIG_HASH_ITERATION(8); 1358 IXGBE_COMPUTE_SIG_HASH_ITERATION(9); 1359 IXGBE_COMPUTE_SIG_HASH_ITERATION(10); 1360 IXGBE_COMPUTE_SIG_HASH_ITERATION(11); 1361 IXGBE_COMPUTE_SIG_HASH_ITERATION(12); 1362 IXGBE_COMPUTE_SIG_HASH_ITERATION(13); 1363 IXGBE_COMPUTE_SIG_HASH_ITERATION(14); 1364 IXGBE_COMPUTE_SIG_HASH_ITERATION(15); 1365 1366 /* combine common_hash result with signature and bucket hashes */ 1367 bucket_hash ^= common_hash; 1368 bucket_hash &= IXGBE_ATR_HASH_MASK; 1369 1370 sig_hash ^= common_hash << 16; 1371 sig_hash &= IXGBE_ATR_HASH_MASK << 16; 1372 1373 /* return completed signature hash */ 1374 return sig_hash ^ bucket_hash; 1375 } 1376 1377 /** 1378 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter 1379 * @hw: pointer to hardware structure 1380 * @input: unique input dword 1381 * @common: compressed common input dword 1382 * @queue: queue index to direct traffic to 1383 * 1384 * Note that the tunnel bit in input must not be set when the hardware 1385 * tunneling support does not exist. 1386 **/ 1387 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1388 union ixgbe_atr_hash_dword input, 1389 union ixgbe_atr_hash_dword common, 1390 u8 queue) 1391 { 1392 u64 fdirhashcmd; 1393 u8 flow_type; 1394 bool tunnel; 1395 u32 fdircmd; 1396 1397 /* 1398 * Get the flow_type in order to program FDIRCMD properly 1399 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 1400 */ 1401 tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK); 1402 flow_type = input.formatted.flow_type & 1403 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1); 1404 switch (flow_type) { 1405 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1406 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1407 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1408 case IXGBE_ATR_FLOW_TYPE_TCPV6: 1409 case IXGBE_ATR_FLOW_TYPE_UDPV6: 1410 case IXGBE_ATR_FLOW_TYPE_SCTPV6: 1411 break; 1412 default: 1413 hw_dbg(hw, " Error on flow type input\n"); 1414 return IXGBE_ERR_CONFIG; 1415 } 1416 1417 /* configure FDIRCMD register */ 1418 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1419 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1420 fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1421 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1422 if (tunnel) 1423 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER; 1424 1425 /* 1426 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 1427 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 1428 */ 1429 fdirhashcmd = (u64)fdircmd << 32; 1430 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common); 1431 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1432 1433 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); 1434 1435 return 0; 1436 } 1437 1438 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \ 1439 do { \ 1440 u32 n = (_n); \ 1441 if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n)) \ 1442 bucket_hash ^= lo_hash_dword >> n; \ 1443 if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n + 16)) \ 1444 bucket_hash ^= hi_hash_dword >> n; \ 1445 } while (0) 1446 1447 /** 1448 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash 1449 * @atr_input: input bitstream to compute the hash on 1450 * @input_mask: mask for the input bitstream 1451 * 1452 * This function serves two main purposes. First it applies the input_mask 1453 * to the atr_input resulting in a cleaned up atr_input data stream. 1454 * Secondly it computes the hash and stores it in the bkt_hash field at 1455 * the end of the input byte stream. This way it will be available for 1456 * future use without needing to recompute the hash. 1457 **/ 1458 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 1459 union ixgbe_atr_input *input_mask) 1460 { 1461 1462 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1463 u32 bucket_hash = 0, hi_dword = 0; 1464 int i; 1465 1466 /* Apply masks to input data */ 1467 for (i = 0; i <= 10; i++) 1468 input->dword_stream[i] &= input_mask->dword_stream[i]; 1469 1470 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1471 flow_vm_vlan = ntohl(input->dword_stream[0]); 1472 1473 /* generate common hash dword */ 1474 for (i = 1; i <= 10; i++) 1475 hi_dword ^= input->dword_stream[i]; 1476 hi_hash_dword = ntohl(hi_dword); 1477 1478 /* low dword is word swapped version of common */ 1479 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1480 1481 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1482 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1483 1484 /* Process bits 0 and 16 */ 1485 IXGBE_COMPUTE_BKT_HASH_ITERATION(0); 1486 1487 /* 1488 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1489 * delay this because bit 0 of the stream should not be processed 1490 * so we do not add the vlan until after bit 0 was processed 1491 */ 1492 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1493 1494 /* Process remaining 30 bit of the key */ 1495 for (i = 1; i <= 15; i++) 1496 IXGBE_COMPUTE_BKT_HASH_ITERATION(i); 1497 1498 /* 1499 * Limit hash to 13 bits since max bucket count is 8K. 1500 * Store result at the end of the input stream. 1501 */ 1502 input->formatted.bkt_hash = bucket_hash & 0x1FFF; 1503 } 1504 1505 /** 1506 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks 1507 * @input_mask: mask to be bit swapped 1508 * 1509 * The source and destination port masks for flow director are bit swapped 1510 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to 1511 * generate a correctly swapped value we need to bit swap the mask and that 1512 * is what is accomplished by this function. 1513 **/ 1514 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask) 1515 { 1516 u32 mask = ntohs(input_mask->formatted.dst_port); 1517 1518 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; 1519 mask |= ntohs(input_mask->formatted.src_port); 1520 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); 1521 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); 1522 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); 1523 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); 1524 } 1525 1526 /* 1527 * These two macros are meant to address the fact that we have registers 1528 * that are either all or in part big-endian. As a result on big-endian 1529 * systems we will end up byte swapping the value to little-endian before 1530 * it is byte swapped again and written to the hardware in the original 1531 * big-endian format. 1532 */ 1533 #define IXGBE_STORE_AS_BE32(_value) \ 1534 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \ 1535 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24)) 1536 1537 #define IXGBE_WRITE_REG_BE32(a, reg, value) \ 1538 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value))) 1539 1540 #define IXGBE_STORE_AS_BE16(_value) \ 1541 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8)) 1542 1543 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 1544 union ixgbe_atr_input *input_mask) 1545 { 1546 /* mask IPv6 since it is currently not supported */ 1547 u32 fdirm = IXGBE_FDIRM_DIPv6; 1548 u32 fdirtcpm; 1549 1550 /* 1551 * Program the relevant mask registers. If src/dst_port or src/dst_addr 1552 * are zero, then assume a full mask for that field. Also assume that 1553 * a VLAN of 0 is unspecified, so mask that out as well. L4type 1554 * cannot be masked out in this implementation. 1555 * 1556 * This also assumes IPv4 only. IPv6 masking isn't supported at this 1557 * point in time. 1558 */ 1559 1560 /* verify bucket hash is cleared on hash generation */ 1561 if (input_mask->formatted.bkt_hash) 1562 hw_dbg(hw, " bucket hash should always be 0 in mask\n"); 1563 1564 /* Program FDIRM and verify partial masks */ 1565 switch (input_mask->formatted.vm_pool & 0x7F) { 1566 case 0x0: 1567 fdirm |= IXGBE_FDIRM_POOL; 1568 case 0x7F: 1569 break; 1570 default: 1571 hw_dbg(hw, " Error on vm pool mask\n"); 1572 return IXGBE_ERR_CONFIG; 1573 } 1574 1575 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) { 1576 case 0x0: 1577 fdirm |= IXGBE_FDIRM_L4P; 1578 if (input_mask->formatted.dst_port || 1579 input_mask->formatted.src_port) { 1580 hw_dbg(hw, " Error on src/dst port mask\n"); 1581 return IXGBE_ERR_CONFIG; 1582 } 1583 case IXGBE_ATR_L4TYPE_MASK: 1584 break; 1585 default: 1586 hw_dbg(hw, " Error on flow type mask\n"); 1587 return IXGBE_ERR_CONFIG; 1588 } 1589 1590 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) { 1591 case 0x0000: 1592 /* mask VLAN ID */ 1593 fdirm |= IXGBE_FDIRM_VLANID; 1594 /* fall through */ 1595 case 0x0FFF: 1596 /* mask VLAN priority */ 1597 fdirm |= IXGBE_FDIRM_VLANP; 1598 break; 1599 case 0xE000: 1600 /* mask VLAN ID only */ 1601 fdirm |= IXGBE_FDIRM_VLANID; 1602 /* fall through */ 1603 case 0xEFFF: 1604 /* no VLAN fields masked */ 1605 break; 1606 default: 1607 hw_dbg(hw, " Error on VLAN mask\n"); 1608 return IXGBE_ERR_CONFIG; 1609 } 1610 1611 switch (input_mask->formatted.flex_bytes & 0xFFFF) { 1612 case 0x0000: 1613 /* Mask Flex Bytes */ 1614 fdirm |= IXGBE_FDIRM_FLEX; 1615 /* fall through */ 1616 case 0xFFFF: 1617 break; 1618 default: 1619 hw_dbg(hw, " Error on flexible byte mask\n"); 1620 return IXGBE_ERR_CONFIG; 1621 } 1622 1623 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ 1624 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 1625 1626 /* store the TCP/UDP port masks, bit reversed from port layout */ 1627 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask); 1628 1629 /* write both the same so that UDP and TCP use the same mask */ 1630 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); 1631 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); 1632 1633 /* also use it for SCTP */ 1634 switch (hw->mac.type) { 1635 case ixgbe_mac_X550: 1636 case ixgbe_mac_X550EM_x: 1637 case ixgbe_mac_x550em_a: 1638 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm); 1639 break; 1640 default: 1641 break; 1642 } 1643 1644 /* store source and destination IP masks (big-enian) */ 1645 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 1646 ~input_mask->formatted.src_ip[0]); 1647 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 1648 ~input_mask->formatted.dst_ip[0]); 1649 1650 return 0; 1651 } 1652 1653 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 1654 union ixgbe_atr_input *input, 1655 u16 soft_id, u8 queue) 1656 { 1657 u32 fdirport, fdirvlan, fdirhash, fdircmd; 1658 s32 err; 1659 1660 /* currently IPv6 is not supported, must be programmed with 0 */ 1661 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), 1662 input->formatted.src_ip[0]); 1663 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), 1664 input->formatted.src_ip[1]); 1665 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), 1666 input->formatted.src_ip[2]); 1667 1668 /* record the source address (big-endian) */ 1669 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); 1670 1671 /* record the first 32 bits of the destination address (big-endian) */ 1672 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); 1673 1674 /* record source and destination port (little-endian)*/ 1675 fdirport = ntohs(input->formatted.dst_port); 1676 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; 1677 fdirport |= ntohs(input->formatted.src_port); 1678 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); 1679 1680 /* record vlan (little-endian) and flex_bytes(big-endian) */ 1681 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); 1682 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; 1683 fdirvlan |= ntohs(input->formatted.vlan_id); 1684 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); 1685 1686 /* configure FDIRHASH register */ 1687 fdirhash = input->formatted.bkt_hash; 1688 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1689 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1690 1691 /* 1692 * flush all previous writes to make certain registers are 1693 * programmed prior to issuing the command 1694 */ 1695 IXGBE_WRITE_FLUSH(hw); 1696 1697 /* configure FDIRCMD register */ 1698 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1699 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1700 if (queue == IXGBE_FDIR_DROP_QUEUE) 1701 fdircmd |= IXGBE_FDIRCMD_DROP; 1702 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1703 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1704 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; 1705 1706 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1707 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1708 if (err) { 1709 hw_dbg(hw, "Flow Director command did not complete!\n"); 1710 return err; 1711 } 1712 1713 return 0; 1714 } 1715 1716 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 1717 union ixgbe_atr_input *input, 1718 u16 soft_id) 1719 { 1720 u32 fdirhash; 1721 u32 fdircmd; 1722 s32 err; 1723 1724 /* configure FDIRHASH register */ 1725 fdirhash = input->formatted.bkt_hash; 1726 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1727 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1728 1729 /* flush hash to HW */ 1730 IXGBE_WRITE_FLUSH(hw); 1731 1732 /* Query if filter is present */ 1733 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); 1734 1735 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1736 if (err) { 1737 hw_dbg(hw, "Flow Director command did not complete!\n"); 1738 return err; 1739 } 1740 1741 /* if filter exists in hardware then remove it */ 1742 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) { 1743 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1744 IXGBE_WRITE_FLUSH(hw); 1745 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1746 IXGBE_FDIRCMD_CMD_REMOVE_FLOW); 1747 } 1748 1749 return 0; 1750 } 1751 1752 /** 1753 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 1754 * @hw: pointer to hardware structure 1755 * @reg: analog register to read 1756 * @val: read value 1757 * 1758 * Performs read operation to Omer analog register specified. 1759 **/ 1760 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 1761 { 1762 u32 core_ctl; 1763 1764 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 1765 (reg << 8)); 1766 IXGBE_WRITE_FLUSH(hw); 1767 udelay(10); 1768 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 1769 *val = (u8)core_ctl; 1770 1771 return 0; 1772 } 1773 1774 /** 1775 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 1776 * @hw: pointer to hardware structure 1777 * @reg: atlas register to write 1778 * @val: value to write 1779 * 1780 * Performs write operation to Omer analog register specified. 1781 **/ 1782 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 1783 { 1784 u32 core_ctl; 1785 1786 core_ctl = (reg << 8) | val; 1787 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 1788 IXGBE_WRITE_FLUSH(hw); 1789 udelay(10); 1790 1791 return 0; 1792 } 1793 1794 /** 1795 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx 1796 * @hw: pointer to hardware structure 1797 * 1798 * Starts the hardware using the generic start_hw function 1799 * and the generation start_hw function. 1800 * Then performs revision-specific operations, if any. 1801 **/ 1802 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) 1803 { 1804 s32 ret_val = 0; 1805 1806 ret_val = ixgbe_start_hw_generic(hw); 1807 if (ret_val) 1808 return ret_val; 1809 1810 ret_val = ixgbe_start_hw_gen2(hw); 1811 if (ret_val) 1812 return ret_val; 1813 1814 /* We need to run link autotry after the driver loads */ 1815 hw->mac.autotry_restart = true; 1816 1817 return ixgbe_verify_fw_version_82599(hw); 1818 } 1819 1820 /** 1821 * ixgbe_identify_phy_82599 - Get physical layer module 1822 * @hw: pointer to hardware structure 1823 * 1824 * Determines the physical layer module found on the current adapter. 1825 * If PHY already detected, maintains current PHY type in hw struct, 1826 * otherwise executes the PHY detection routine. 1827 **/ 1828 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 1829 { 1830 s32 status; 1831 1832 /* Detect PHY if not unknown - returns success if already detected. */ 1833 status = ixgbe_identify_phy_generic(hw); 1834 if (status) { 1835 /* 82599 10GBASE-T requires an external PHY */ 1836 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 1837 return status; 1838 status = ixgbe_identify_module_generic(hw); 1839 } 1840 1841 /* Set PHY type none if no PHY detected */ 1842 if (hw->phy.type == ixgbe_phy_unknown) { 1843 hw->phy.type = ixgbe_phy_none; 1844 status = 0; 1845 } 1846 1847 /* Return error if SFP module has been detected but is not supported */ 1848 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1849 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1850 1851 return status; 1852 } 1853 1854 /** 1855 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 1856 * @hw: pointer to hardware structure 1857 * @regval: register value to write to RXCTRL 1858 * 1859 * Enables the Rx DMA unit for 82599 1860 **/ 1861 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 1862 { 1863 /* 1864 * Workaround for 82599 silicon errata when enabling the Rx datapath. 1865 * If traffic is incoming before we enable the Rx unit, it could hang 1866 * the Rx DMA unit. Therefore, make sure the security engine is 1867 * completely disabled prior to enabling the Rx unit. 1868 */ 1869 hw->mac.ops.disable_rx_buff(hw); 1870 1871 if (regval & IXGBE_RXCTRL_RXEN) 1872 hw->mac.ops.enable_rx(hw); 1873 else 1874 hw->mac.ops.disable_rx(hw); 1875 1876 hw->mac.ops.enable_rx_buff(hw); 1877 1878 return 0; 1879 } 1880 1881 /** 1882 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 1883 * @hw: pointer to hardware structure 1884 * 1885 * Verifies that installed the firmware version is 0.6 or higher 1886 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 1887 * 1888 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 1889 * if the FW version is not supported. 1890 **/ 1891 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 1892 { 1893 s32 status = IXGBE_ERR_EEPROM_VERSION; 1894 u16 fw_offset, fw_ptp_cfg_offset; 1895 u16 offset; 1896 u16 fw_version = 0; 1897 1898 /* firmware check is only necessary for SFI devices */ 1899 if (hw->phy.media_type != ixgbe_media_type_fiber) 1900 return 0; 1901 1902 /* get the offset to the Firmware Module block */ 1903 offset = IXGBE_FW_PTR; 1904 if (hw->eeprom.ops.read(hw, offset, &fw_offset)) 1905 goto fw_version_err; 1906 1907 if (fw_offset == 0 || fw_offset == 0xFFFF) 1908 return IXGBE_ERR_EEPROM_VERSION; 1909 1910 /* get the offset to the Pass Through Patch Configuration block */ 1911 offset = fw_offset + IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR; 1912 if (hw->eeprom.ops.read(hw, offset, &fw_ptp_cfg_offset)) 1913 goto fw_version_err; 1914 1915 if (fw_ptp_cfg_offset == 0 || fw_ptp_cfg_offset == 0xFFFF) 1916 return IXGBE_ERR_EEPROM_VERSION; 1917 1918 /* get the firmware version */ 1919 offset = fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4; 1920 if (hw->eeprom.ops.read(hw, offset, &fw_version)) 1921 goto fw_version_err; 1922 1923 if (fw_version > 0x5) 1924 status = 0; 1925 1926 return status; 1927 1928 fw_version_err: 1929 hw_err(hw, "eeprom read at offset %d failed\n", offset); 1930 return IXGBE_ERR_EEPROM_VERSION; 1931 } 1932 1933 /** 1934 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 1935 * @hw: pointer to hardware structure 1936 * 1937 * Returns true if the LESM FW module is present and enabled. Otherwise 1938 * returns false. Smart Speed must be disabled if LESM FW module is enabled. 1939 **/ 1940 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 1941 { 1942 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state; 1943 s32 status; 1944 1945 /* get the offset to the Firmware Module block */ 1946 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 1947 1948 if (status || fw_offset == 0 || fw_offset == 0xFFFF) 1949 return false; 1950 1951 /* get the offset to the LESM Parameters block */ 1952 status = hw->eeprom.ops.read(hw, (fw_offset + 1953 IXGBE_FW_LESM_PARAMETERS_PTR), 1954 &fw_lesm_param_offset); 1955 1956 if (status || 1957 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF) 1958 return false; 1959 1960 /* get the lesm state word */ 1961 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 1962 IXGBE_FW_LESM_STATE_1), 1963 &fw_lesm_state); 1964 1965 if (!status && (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 1966 return true; 1967 1968 return false; 1969 } 1970 1971 /** 1972 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using 1973 * fastest available method 1974 * 1975 * @hw: pointer to hardware structure 1976 * @offset: offset of word in EEPROM to read 1977 * @words: number of words 1978 * @data: word(s) read from the EEPROM 1979 * 1980 * Retrieves 16 bit word(s) read from EEPROM 1981 **/ 1982 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 1983 u16 words, u16 *data) 1984 { 1985 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1986 1987 /* If EEPROM is detected and can be addressed using 14 bits, 1988 * use EERD otherwise use bit bang 1989 */ 1990 if (eeprom->type == ixgbe_eeprom_spi && 1991 offset + (words - 1) <= IXGBE_EERD_MAX_ADDR) 1992 return ixgbe_read_eerd_buffer_generic(hw, offset, words, data); 1993 1994 return ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, words, 1995 data); 1996 } 1997 1998 /** 1999 * ixgbe_read_eeprom_82599 - Read EEPROM word using 2000 * fastest available method 2001 * 2002 * @hw: pointer to hardware structure 2003 * @offset: offset of word in the EEPROM to read 2004 * @data: word read from the EEPROM 2005 * 2006 * Reads a 16 bit word from the EEPROM 2007 **/ 2008 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 2009 u16 offset, u16 *data) 2010 { 2011 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2012 2013 /* 2014 * If EEPROM is detected and can be addressed using 14 bits, 2015 * use EERD otherwise use bit bang 2016 */ 2017 if (eeprom->type == ixgbe_eeprom_spi && offset <= IXGBE_EERD_MAX_ADDR) 2018 return ixgbe_read_eerd_generic(hw, offset, data); 2019 2020 return ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); 2021 } 2022 2023 /** 2024 * ixgbe_reset_pipeline_82599 - perform pipeline reset 2025 * 2026 * @hw: pointer to hardware structure 2027 * 2028 * Reset pipeline by asserting Restart_AN together with LMS change to ensure 2029 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing 2030 * to AUTOC, so this function assumes the semaphore is held. 2031 **/ 2032 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) 2033 { 2034 s32 ret_val; 2035 u32 anlp1_reg = 0; 2036 u32 i, autoc_reg, autoc2_reg; 2037 2038 /* Enable link if disabled in NVM */ 2039 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 2040 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 2041 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 2042 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 2043 IXGBE_WRITE_FLUSH(hw); 2044 } 2045 2046 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2047 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2048 2049 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */ 2050 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, 2051 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT)); 2052 2053 /* Wait for AN to leave state 0 */ 2054 for (i = 0; i < 10; i++) { 2055 usleep_range(4000, 8000); 2056 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2057 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK) 2058 break; 2059 } 2060 2061 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) { 2062 hw_dbg(hw, "auto negotiation not completed\n"); 2063 ret_val = IXGBE_ERR_RESET_FAILED; 2064 goto reset_pipeline_out; 2065 } 2066 2067 ret_val = 0; 2068 2069 reset_pipeline_out: 2070 /* Write AUTOC register with original LMS field and Restart_AN */ 2071 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2072 IXGBE_WRITE_FLUSH(hw); 2073 2074 return ret_val; 2075 } 2076 2077 /** 2078 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C 2079 * @hw: pointer to hardware structure 2080 * @byte_offset: byte offset to read 2081 * @data: value read 2082 * 2083 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2084 * a specified device address. 2085 **/ 2086 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2087 u8 dev_addr, u8 *data) 2088 { 2089 u32 esdp; 2090 s32 status; 2091 s32 timeout = 200; 2092 2093 if (hw->phy.qsfp_shared_i2c_bus == true) { 2094 /* Acquire I2C bus ownership. */ 2095 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2096 esdp |= IXGBE_ESDP_SDP0; 2097 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2098 IXGBE_WRITE_FLUSH(hw); 2099 2100 while (timeout) { 2101 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2102 if (esdp & IXGBE_ESDP_SDP1) 2103 break; 2104 2105 usleep_range(5000, 10000); 2106 timeout--; 2107 } 2108 2109 if (!timeout) { 2110 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n"); 2111 status = IXGBE_ERR_I2C; 2112 goto release_i2c_access; 2113 } 2114 } 2115 2116 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2117 2118 release_i2c_access: 2119 if (hw->phy.qsfp_shared_i2c_bus == true) { 2120 /* Release I2C bus ownership. */ 2121 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2122 esdp &= ~IXGBE_ESDP_SDP0; 2123 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2124 IXGBE_WRITE_FLUSH(hw); 2125 } 2126 2127 return status; 2128 } 2129 2130 /** 2131 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C 2132 * @hw: pointer to hardware structure 2133 * @byte_offset: byte offset to write 2134 * @data: value to write 2135 * 2136 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2137 * a specified device address. 2138 **/ 2139 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2140 u8 dev_addr, u8 data) 2141 { 2142 u32 esdp; 2143 s32 status; 2144 s32 timeout = 200; 2145 2146 if (hw->phy.qsfp_shared_i2c_bus == true) { 2147 /* Acquire I2C bus ownership. */ 2148 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2149 esdp |= IXGBE_ESDP_SDP0; 2150 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2151 IXGBE_WRITE_FLUSH(hw); 2152 2153 while (timeout) { 2154 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2155 if (esdp & IXGBE_ESDP_SDP1) 2156 break; 2157 2158 usleep_range(5000, 10000); 2159 timeout--; 2160 } 2161 2162 if (!timeout) { 2163 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n"); 2164 status = IXGBE_ERR_I2C; 2165 goto release_i2c_access; 2166 } 2167 } 2168 2169 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2170 2171 release_i2c_access: 2172 if (hw->phy.qsfp_shared_i2c_bus == true) { 2173 /* Release I2C bus ownership. */ 2174 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2175 esdp &= ~IXGBE_ESDP_SDP0; 2176 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2177 IXGBE_WRITE_FLUSH(hw); 2178 } 2179 2180 return status; 2181 } 2182 2183 static const struct ixgbe_mac_operations mac_ops_82599 = { 2184 .init_hw = &ixgbe_init_hw_generic, 2185 .reset_hw = &ixgbe_reset_hw_82599, 2186 .start_hw = &ixgbe_start_hw_82599, 2187 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 2188 .get_media_type = &ixgbe_get_media_type_82599, 2189 .enable_rx_dma = &ixgbe_enable_rx_dma_82599, 2190 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, 2191 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, 2192 .get_mac_addr = &ixgbe_get_mac_addr_generic, 2193 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 2194 .get_device_caps = &ixgbe_get_device_caps_generic, 2195 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 2196 .stop_adapter = &ixgbe_stop_adapter_generic, 2197 .get_bus_info = &ixgbe_get_bus_info_generic, 2198 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, 2199 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599, 2200 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599, 2201 .stop_link_on_d3 = &ixgbe_stop_mac_link_on_d3_82599, 2202 .setup_link = &ixgbe_setup_mac_link_82599, 2203 .set_rxpba = &ixgbe_set_rxpba_generic, 2204 .check_link = &ixgbe_check_mac_link_generic, 2205 .get_link_capabilities = &ixgbe_get_link_capabilities_82599, 2206 .led_on = &ixgbe_led_on_generic, 2207 .led_off = &ixgbe_led_off_generic, 2208 .init_led_link_act = ixgbe_init_led_link_act_generic, 2209 .blink_led_start = &ixgbe_blink_led_start_generic, 2210 .blink_led_stop = &ixgbe_blink_led_stop_generic, 2211 .set_rar = &ixgbe_set_rar_generic, 2212 .clear_rar = &ixgbe_clear_rar_generic, 2213 .set_vmdq = &ixgbe_set_vmdq_generic, 2214 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, 2215 .clear_vmdq = &ixgbe_clear_vmdq_generic, 2216 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 2217 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 2218 .enable_mc = &ixgbe_enable_mc_generic, 2219 .disable_mc = &ixgbe_disable_mc_generic, 2220 .clear_vfta = &ixgbe_clear_vfta_generic, 2221 .set_vfta = &ixgbe_set_vfta_generic, 2222 .fc_enable = &ixgbe_fc_enable_generic, 2223 .setup_fc = ixgbe_setup_fc_generic, 2224 .fc_autoneg = ixgbe_fc_autoneg, 2225 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, 2226 .init_uta_tables = &ixgbe_init_uta_tables_generic, 2227 .setup_sfp = &ixgbe_setup_sfp_modules_82599, 2228 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, 2229 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, 2230 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync, 2231 .release_swfw_sync = &ixgbe_release_swfw_sync, 2232 .init_swfw_sync = NULL, 2233 .get_thermal_sensor_data = &ixgbe_get_thermal_sensor_data_generic, 2234 .init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic, 2235 .prot_autoc_read = &prot_autoc_read_82599, 2236 .prot_autoc_write = &prot_autoc_write_82599, 2237 .enable_rx = &ixgbe_enable_rx_generic, 2238 .disable_rx = &ixgbe_disable_rx_generic, 2239 }; 2240 2241 static const struct ixgbe_eeprom_operations eeprom_ops_82599 = { 2242 .init_params = &ixgbe_init_eeprom_params_generic, 2243 .read = &ixgbe_read_eeprom_82599, 2244 .read_buffer = &ixgbe_read_eeprom_buffer_82599, 2245 .write = &ixgbe_write_eeprom_generic, 2246 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic, 2247 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, 2248 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 2249 .update_checksum = &ixgbe_update_eeprom_checksum_generic, 2250 }; 2251 2252 static const struct ixgbe_phy_operations phy_ops_82599 = { 2253 .identify = &ixgbe_identify_phy_82599, 2254 .identify_sfp = &ixgbe_identify_module_generic, 2255 .init = &ixgbe_init_phy_ops_82599, 2256 .reset = &ixgbe_reset_phy_generic, 2257 .read_reg = &ixgbe_read_phy_reg_generic, 2258 .write_reg = &ixgbe_write_phy_reg_generic, 2259 .setup_link = &ixgbe_setup_phy_link_generic, 2260 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 2261 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, 2262 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, 2263 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, 2264 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, 2265 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, 2266 .check_overtemp = &ixgbe_tn_check_overtemp, 2267 }; 2268 2269 const struct ixgbe_info ixgbe_82599_info = { 2270 .mac = ixgbe_mac_82599EB, 2271 .get_invariants = &ixgbe_get_invariants_82599, 2272 .mac_ops = &mac_ops_82599, 2273 .eeprom_ops = &eeprom_ops_82599, 2274 .phy_ops = &phy_ops_82599, 2275 .mbx_ops = &mbx_ops_generic, 2276 .mvals = ixgbe_mvals_8259X, 2277 }; 2278