1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #include <linux/pci.h> 5 #include <linux/delay.h> 6 #include <linux/sched.h> 7 8 #include "ixgbe.h" 9 #include "ixgbe_phy.h" 10 #include "ixgbe_mbx.h" 11 12 #define IXGBE_82599_MAX_TX_QUEUES 128 13 #define IXGBE_82599_MAX_RX_QUEUES 128 14 #define IXGBE_82599_RAR_ENTRIES 128 15 #define IXGBE_82599_MC_TBL_SIZE 128 16 #define IXGBE_82599_VFT_TBL_SIZE 128 17 #define IXGBE_82599_RX_PB_SIZE 512 18 19 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 20 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 21 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 22 static void 23 ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *, ixgbe_link_speed); 24 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 25 ixgbe_link_speed speed, 26 bool autoneg_wait_to_complete); 27 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw); 28 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 29 bool autoneg_wait_to_complete); 30 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 31 ixgbe_link_speed speed, 32 bool autoneg_wait_to_complete); 33 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 34 ixgbe_link_speed speed, 35 bool autoneg_wait_to_complete); 36 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 37 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 38 u8 dev_addr, u8 *data); 39 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 40 u8 dev_addr, u8 data); 41 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw); 42 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw); 43 44 bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 45 { 46 u32 fwsm, manc, factps; 47 48 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 49 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) 50 return false; 51 52 manc = IXGBE_READ_REG(hw, IXGBE_MANC); 53 if (!(manc & IXGBE_MANC_RCV_TCO_EN)) 54 return false; 55 56 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); 57 if (factps & IXGBE_FACTPS_MNGCG) 58 return false; 59 60 return true; 61 } 62 63 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 64 { 65 struct ixgbe_mac_info *mac = &hw->mac; 66 67 /* enable the laser control functions for SFP+ fiber 68 * and MNG not enabled 69 */ 70 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && 71 !ixgbe_mng_enabled(hw)) { 72 mac->ops.disable_tx_laser = 73 &ixgbe_disable_tx_laser_multispeed_fiber; 74 mac->ops.enable_tx_laser = 75 &ixgbe_enable_tx_laser_multispeed_fiber; 76 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; 77 } else { 78 mac->ops.disable_tx_laser = NULL; 79 mac->ops.enable_tx_laser = NULL; 80 mac->ops.flap_tx_laser = NULL; 81 } 82 83 if (hw->phy.multispeed_fiber) { 84 /* Set up dual speed SFP+ support */ 85 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; 86 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599; 87 mac->ops.set_rate_select_speed = 88 ixgbe_set_hard_rate_select_speed; 89 } else { 90 if ((mac->ops.get_media_type(hw) == 91 ixgbe_media_type_backplane) && 92 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 93 hw->phy.smart_speed == ixgbe_smart_speed_on) && 94 !ixgbe_verify_lesm_fw_enabled_82599(hw)) 95 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; 96 else 97 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; 98 } 99 } 100 101 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 102 { 103 s32 ret_val; 104 u16 list_offset, data_offset, data_value; 105 106 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 107 ixgbe_init_mac_link_ops_82599(hw); 108 109 hw->phy.ops.reset = NULL; 110 111 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 112 &data_offset); 113 if (ret_val) 114 return ret_val; 115 116 /* PHY config will finish before releasing the semaphore */ 117 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 118 IXGBE_GSSR_MAC_CSR_SM); 119 if (ret_val) 120 return IXGBE_ERR_SWFW_SYNC; 121 122 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 123 goto setup_sfp_err; 124 while (data_value != 0xffff) { 125 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 126 IXGBE_WRITE_FLUSH(hw); 127 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 128 goto setup_sfp_err; 129 } 130 131 /* Release the semaphore */ 132 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 133 /* 134 * Delay obtaining semaphore again to allow FW access, 135 * semaphore_delay is in ms usleep_range needs us. 136 */ 137 usleep_range(hw->eeprom.semaphore_delay * 1000, 138 hw->eeprom.semaphore_delay * 2000); 139 140 /* Restart DSP and set SFI mode */ 141 ret_val = hw->mac.ops.prot_autoc_write(hw, 142 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL, 143 false); 144 145 if (ret_val) { 146 hw_dbg(hw, " sfp module setup not complete\n"); 147 return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 148 } 149 } 150 151 return 0; 152 153 setup_sfp_err: 154 /* Release the semaphore */ 155 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 156 /* Delay obtaining semaphore again to allow FW access, 157 * semaphore_delay is in ms usleep_range needs us. 158 */ 159 usleep_range(hw->eeprom.semaphore_delay * 1000, 160 hw->eeprom.semaphore_delay * 2000); 161 hw_err(hw, "eeprom read at offset %d failed\n", data_offset); 162 return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 163 } 164 165 /** 166 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read 167 * @hw: pointer to hardware structure 168 * @locked: Return the if we locked for this read. 169 * @reg_val: Value we read from AUTOC 170 * 171 * For this part (82599) we need to wrap read-modify-writes with a possible 172 * FW/SW lock. It is assumed this lock will be freed with the next 173 * prot_autoc_write_82599(). Note, that locked can only be true in cases 174 * where this function doesn't return an error. 175 **/ 176 static s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, 177 u32 *reg_val) 178 { 179 s32 ret_val; 180 181 *locked = false; 182 /* If LESM is on then we need to hold the SW/FW semaphore. */ 183 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 184 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 185 IXGBE_GSSR_MAC_CSR_SM); 186 if (ret_val) 187 return IXGBE_ERR_SWFW_SYNC; 188 189 *locked = true; 190 } 191 192 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 193 return 0; 194 } 195 196 /** 197 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write 198 * @hw: pointer to hardware structure 199 * @autoc: value to write to AUTOC 200 * @locked: bool to indicate whether the SW/FW lock was already taken by 201 * previous proc_autoc_read_82599. 202 * 203 * This part (82599) may need to hold a the SW/FW lock around all writes to 204 * AUTOC. Likewise after a write we need to do a pipeline reset. 205 **/ 206 static s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked) 207 { 208 s32 ret_val = 0; 209 210 /* Blocked by MNG FW so bail */ 211 if (ixgbe_check_reset_blocked(hw)) 212 goto out; 213 214 /* We only need to get the lock if: 215 * - We didn't do it already (in the read part of a read-modify-write) 216 * - LESM is enabled. 217 */ 218 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) { 219 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 220 IXGBE_GSSR_MAC_CSR_SM); 221 if (ret_val) 222 return IXGBE_ERR_SWFW_SYNC; 223 224 locked = true; 225 } 226 227 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 228 ret_val = ixgbe_reset_pipeline_82599(hw); 229 230 out: 231 /* Free the SW/FW semaphore as we either grabbed it here or 232 * already had it when this function was called. 233 */ 234 if (locked) 235 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 236 237 return ret_val; 238 } 239 240 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw) 241 { 242 struct ixgbe_mac_info *mac = &hw->mac; 243 244 ixgbe_init_mac_link_ops_82599(hw); 245 246 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; 247 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; 248 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; 249 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE; 250 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; 251 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; 252 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 253 254 return 0; 255 } 256 257 /** 258 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 259 * @hw: pointer to hardware structure 260 * 261 * Initialize any function pointers that were not able to be 262 * set during get_invariants because the PHY/SFP type was 263 * not known. Perform the SFP init if necessary. 264 * 265 **/ 266 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 267 { 268 struct ixgbe_mac_info *mac = &hw->mac; 269 struct ixgbe_phy_info *phy = &hw->phy; 270 s32 ret_val; 271 u32 esdp; 272 273 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) { 274 /* Store flag indicating I2C bus access control unit. */ 275 hw->phy.qsfp_shared_i2c_bus = true; 276 277 /* Initialize access to QSFP+ I2C bus */ 278 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 279 esdp |= IXGBE_ESDP_SDP0_DIR; 280 esdp &= ~IXGBE_ESDP_SDP1_DIR; 281 esdp &= ~IXGBE_ESDP_SDP0; 282 esdp &= ~IXGBE_ESDP_SDP0_NATIVE; 283 esdp &= ~IXGBE_ESDP_SDP1_NATIVE; 284 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 285 IXGBE_WRITE_FLUSH(hw); 286 287 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599; 288 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599; 289 } 290 291 /* Identify the PHY or SFP module */ 292 ret_val = phy->ops.identify(hw); 293 294 /* Setup function pointers based on detected SFP module and speeds */ 295 ixgbe_init_mac_link_ops_82599(hw); 296 297 /* If copper media, overwrite with copper function pointers */ 298 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 299 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; 300 mac->ops.get_link_capabilities = 301 &ixgbe_get_copper_link_capabilities_generic; 302 } 303 304 /* Set necessary function pointers based on phy type */ 305 switch (hw->phy.type) { 306 case ixgbe_phy_tn: 307 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 308 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 309 break; 310 default: 311 break; 312 } 313 314 return ret_val; 315 } 316 317 /** 318 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 319 * @hw: pointer to hardware structure 320 * @speed: pointer to link speed 321 * @autoneg: true when autoneg or autotry is enabled 322 * 323 * Determines the link capabilities by reading the AUTOC register. 324 **/ 325 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 326 ixgbe_link_speed *speed, 327 bool *autoneg) 328 { 329 u32 autoc = 0; 330 331 /* Determine 1G link capabilities off of SFP+ type */ 332 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 333 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 334 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 335 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 336 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 337 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 338 *speed = IXGBE_LINK_SPEED_1GB_FULL; 339 *autoneg = true; 340 return 0; 341 } 342 343 /* 344 * Determine link capabilities based on the stored value of AUTOC, 345 * which represents EEPROM defaults. If AUTOC value has not been 346 * stored, use the current register value. 347 */ 348 if (hw->mac.orig_link_settings_stored) 349 autoc = hw->mac.orig_autoc; 350 else 351 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 352 353 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 354 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 355 *speed = IXGBE_LINK_SPEED_1GB_FULL; 356 *autoneg = false; 357 break; 358 359 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 360 *speed = IXGBE_LINK_SPEED_10GB_FULL; 361 *autoneg = false; 362 break; 363 364 case IXGBE_AUTOC_LMS_1G_AN: 365 *speed = IXGBE_LINK_SPEED_1GB_FULL; 366 *autoneg = true; 367 break; 368 369 case IXGBE_AUTOC_LMS_10G_SERIAL: 370 *speed = IXGBE_LINK_SPEED_10GB_FULL; 371 *autoneg = false; 372 break; 373 374 case IXGBE_AUTOC_LMS_KX4_KX_KR: 375 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 376 *speed = IXGBE_LINK_SPEED_UNKNOWN; 377 if (autoc & IXGBE_AUTOC_KR_SUPP) 378 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 379 if (autoc & IXGBE_AUTOC_KX4_SUPP) 380 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 381 if (autoc & IXGBE_AUTOC_KX_SUPP) 382 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 383 *autoneg = true; 384 break; 385 386 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 387 *speed = IXGBE_LINK_SPEED_100_FULL; 388 if (autoc & IXGBE_AUTOC_KR_SUPP) 389 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 390 if (autoc & IXGBE_AUTOC_KX4_SUPP) 391 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 392 if (autoc & IXGBE_AUTOC_KX_SUPP) 393 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 394 *autoneg = true; 395 break; 396 397 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 398 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 399 *autoneg = false; 400 break; 401 402 default: 403 return IXGBE_ERR_LINK_SETUP; 404 } 405 406 if (hw->phy.multispeed_fiber) { 407 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 408 IXGBE_LINK_SPEED_1GB_FULL; 409 410 /* QSFP must not enable auto-negotiation */ 411 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp) 412 *autoneg = false; 413 else 414 *autoneg = true; 415 } 416 417 return 0; 418 } 419 420 /** 421 * ixgbe_get_media_type_82599 - Get media type 422 * @hw: pointer to hardware structure 423 * 424 * Returns the media type (fiber, copper, backplane) 425 **/ 426 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 427 { 428 /* Detect if there is a copper PHY attached. */ 429 switch (hw->phy.type) { 430 case ixgbe_phy_cu_unknown: 431 case ixgbe_phy_tn: 432 return ixgbe_media_type_copper; 433 434 default: 435 break; 436 } 437 438 switch (hw->device_id) { 439 case IXGBE_DEV_ID_82599_KX4: 440 case IXGBE_DEV_ID_82599_KX4_MEZZ: 441 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 442 case IXGBE_DEV_ID_82599_KR: 443 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 444 case IXGBE_DEV_ID_82599_XAUI_LOM: 445 /* Default device ID is mezzanine card KX/KX4 */ 446 return ixgbe_media_type_backplane; 447 448 case IXGBE_DEV_ID_82599_SFP: 449 case IXGBE_DEV_ID_82599_SFP_FCOE: 450 case IXGBE_DEV_ID_82599_SFP_EM: 451 case IXGBE_DEV_ID_82599_SFP_SF2: 452 case IXGBE_DEV_ID_82599_SFP_SF_QP: 453 case IXGBE_DEV_ID_82599EN_SFP: 454 return ixgbe_media_type_fiber; 455 456 case IXGBE_DEV_ID_82599_CX4: 457 return ixgbe_media_type_cx4; 458 459 case IXGBE_DEV_ID_82599_T3_LOM: 460 return ixgbe_media_type_copper; 461 462 case IXGBE_DEV_ID_82599_LS: 463 return ixgbe_media_type_fiber_lco; 464 465 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 466 return ixgbe_media_type_fiber_qsfp; 467 468 default: 469 return ixgbe_media_type_unknown; 470 } 471 } 472 473 /** 474 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3 475 * @hw: pointer to hardware structure 476 * 477 * Disables link, should be called during D3 power down sequence. 478 * 479 **/ 480 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw) 481 { 482 u32 autoc2_reg; 483 u16 ee_ctrl_2 = 0; 484 485 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); 486 487 if (!ixgbe_mng_present(hw) && !hw->wol_enabled && 488 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) { 489 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 490 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK; 491 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 492 } 493 } 494 495 /** 496 * ixgbe_start_mac_link_82599 - Setup MAC link settings 497 * @hw: pointer to hardware structure 498 * @autoneg_wait_to_complete: true when waiting for completion is needed 499 * 500 * Configures link settings based on values in the ixgbe_hw struct. 501 * Restarts the link. Performs autonegotiation if needed. 502 **/ 503 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 504 bool autoneg_wait_to_complete) 505 { 506 u32 autoc_reg; 507 u32 links_reg; 508 u32 i; 509 s32 status = 0; 510 bool got_lock = false; 511 512 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 513 status = hw->mac.ops.acquire_swfw_sync(hw, 514 IXGBE_GSSR_MAC_CSR_SM); 515 if (status) 516 return status; 517 518 got_lock = true; 519 } 520 521 /* Restart link */ 522 ixgbe_reset_pipeline_82599(hw); 523 524 if (got_lock) 525 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 526 527 /* Only poll for autoneg to complete if specified to do so */ 528 if (autoneg_wait_to_complete) { 529 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 530 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 531 IXGBE_AUTOC_LMS_KX4_KX_KR || 532 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 533 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 534 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 535 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 536 links_reg = 0; /* Just in case Autoneg time = 0 */ 537 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 538 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 539 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 540 break; 541 msleep(100); 542 } 543 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 544 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 545 hw_dbg(hw, "Autoneg did not complete.\n"); 546 } 547 } 548 } 549 550 /* Add delay to filter out noises during initial link setup */ 551 msleep(50); 552 553 return status; 554 } 555 556 /** 557 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 558 * @hw: pointer to hardware structure 559 * 560 * The base drivers may require better control over SFP+ module 561 * PHY states. This includes selectively shutting down the Tx 562 * laser on the PHY, effectively halting physical link. 563 **/ 564 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 565 { 566 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 567 568 /* Blocked by MNG FW so bail */ 569 if (ixgbe_check_reset_blocked(hw)) 570 return; 571 572 /* Disable tx laser; allow 100us to go dark per spec */ 573 esdp_reg |= IXGBE_ESDP_SDP3; 574 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 575 IXGBE_WRITE_FLUSH(hw); 576 udelay(100); 577 } 578 579 /** 580 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 581 * @hw: pointer to hardware structure 582 * 583 * The base drivers may require better control over SFP+ module 584 * PHY states. This includes selectively turning on the Tx 585 * laser on the PHY, effectively starting physical link. 586 **/ 587 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 588 { 589 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 590 591 /* Enable tx laser; allow 100ms to light up */ 592 esdp_reg &= ~IXGBE_ESDP_SDP3; 593 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 594 IXGBE_WRITE_FLUSH(hw); 595 msleep(100); 596 } 597 598 /** 599 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 600 * @hw: pointer to hardware structure 601 * 602 * When the driver changes the link speeds that it can support, 603 * it sets autotry_restart to true to indicate that we need to 604 * initiate a new autotry session with the link partner. To do 605 * so, we set the speed then disable and re-enable the tx laser, to 606 * alert the link partner that it also needs to restart autotry on its 607 * end. This is consistent with true clause 37 autoneg, which also 608 * involves a loss of signal. 609 **/ 610 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 611 { 612 /* Blocked by MNG FW so bail */ 613 if (ixgbe_check_reset_blocked(hw)) 614 return; 615 616 if (hw->mac.autotry_restart) { 617 ixgbe_disable_tx_laser_multispeed_fiber(hw); 618 ixgbe_enable_tx_laser_multispeed_fiber(hw); 619 hw->mac.autotry_restart = false; 620 } 621 } 622 623 /** 624 * ixgbe_set_hard_rate_select_speed - Set module link speed 625 * @hw: pointer to hardware structure 626 * @speed: link speed to set 627 * 628 * Set module link speed via RS0/RS1 rate select pins. 629 */ 630 static void 631 ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 632 { 633 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 634 635 switch (speed) { 636 case IXGBE_LINK_SPEED_10GB_FULL: 637 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 638 break; 639 case IXGBE_LINK_SPEED_1GB_FULL: 640 esdp_reg &= ~IXGBE_ESDP_SDP5; 641 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 642 break; 643 default: 644 hw_dbg(hw, "Invalid fixed module speed\n"); 645 return; 646 } 647 648 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 649 IXGBE_WRITE_FLUSH(hw); 650 } 651 652 /** 653 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 654 * @hw: pointer to hardware structure 655 * @speed: new link speed 656 * @autoneg_wait_to_complete: true when waiting for completion is needed 657 * 658 * Implements the Intel SmartSpeed algorithm. 659 **/ 660 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 661 ixgbe_link_speed speed, 662 bool autoneg_wait_to_complete) 663 { 664 s32 status = 0; 665 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 666 s32 i, j; 667 bool link_up = false; 668 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 669 670 /* Set autoneg_advertised value based on input link speed */ 671 hw->phy.autoneg_advertised = 0; 672 673 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 674 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 675 676 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 677 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 678 679 if (speed & IXGBE_LINK_SPEED_100_FULL) 680 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 681 682 /* 683 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 684 * autoneg advertisement if link is unable to be established at the 685 * highest negotiated rate. This can sometimes happen due to integrity 686 * issues with the physical media connection. 687 */ 688 689 /* First, try to get link with full advertisement */ 690 hw->phy.smart_speed_active = false; 691 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 692 status = ixgbe_setup_mac_link_82599(hw, speed, 693 autoneg_wait_to_complete); 694 if (status != 0) 695 goto out; 696 697 /* 698 * Wait for the controller to acquire link. Per IEEE 802.3ap, 699 * Section 73.10.2, we may have to wait up to 500ms if KR is 700 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 701 * Table 9 in the AN MAS. 702 */ 703 for (i = 0; i < 5; i++) { 704 mdelay(100); 705 706 /* If we have link, just jump out */ 707 status = hw->mac.ops.check_link(hw, &link_speed, 708 &link_up, false); 709 if (status != 0) 710 goto out; 711 712 if (link_up) 713 goto out; 714 } 715 } 716 717 /* 718 * We didn't get link. If we advertised KR plus one of KX4/KX 719 * (or BX4/BX), then disable KR and try again. 720 */ 721 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 722 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 723 goto out; 724 725 /* Turn SmartSpeed on to disable KR support */ 726 hw->phy.smart_speed_active = true; 727 status = ixgbe_setup_mac_link_82599(hw, speed, 728 autoneg_wait_to_complete); 729 if (status != 0) 730 goto out; 731 732 /* 733 * Wait for the controller to acquire link. 600ms will allow for 734 * the AN link_fail_inhibit_timer as well for multiple cycles of 735 * parallel detect, both 10g and 1g. This allows for the maximum 736 * connect attempts as defined in the AN MAS table 73-7. 737 */ 738 for (i = 0; i < 6; i++) { 739 mdelay(100); 740 741 /* If we have link, just jump out */ 742 status = hw->mac.ops.check_link(hw, &link_speed, 743 &link_up, false); 744 if (status != 0) 745 goto out; 746 747 if (link_up) 748 goto out; 749 } 750 751 /* We didn't get link. Turn SmartSpeed back off. */ 752 hw->phy.smart_speed_active = false; 753 status = ixgbe_setup_mac_link_82599(hw, speed, 754 autoneg_wait_to_complete); 755 756 out: 757 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 758 hw_dbg(hw, "Smartspeed has downgraded the link speed from the maximum advertised\n"); 759 return status; 760 } 761 762 /** 763 * ixgbe_setup_mac_link_82599 - Set MAC link speed 764 * @hw: pointer to hardware structure 765 * @speed: new link speed 766 * @autoneg_wait_to_complete: true when waiting for completion is needed 767 * 768 * Set the link speed in the AUTOC register and restarts link. 769 **/ 770 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 771 ixgbe_link_speed speed, 772 bool autoneg_wait_to_complete) 773 { 774 bool autoneg = false; 775 s32 status; 776 u32 pma_pmd_1g, link_mode, links_reg, i; 777 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 778 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 779 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 780 781 /* holds the value of AUTOC register at this current point in time */ 782 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 783 /* holds the cached value of AUTOC register */ 784 u32 orig_autoc = 0; 785 /* temporary variable used for comparison purposes */ 786 u32 autoc = current_autoc; 787 788 /* Check to see if speed passed in is supported. */ 789 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities, 790 &autoneg); 791 if (status) 792 return status; 793 794 speed &= link_capabilities; 795 796 if (speed == IXGBE_LINK_SPEED_UNKNOWN) 797 return IXGBE_ERR_LINK_SETUP; 798 799 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 800 if (hw->mac.orig_link_settings_stored) 801 orig_autoc = hw->mac.orig_autoc; 802 else 803 orig_autoc = autoc; 804 805 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 806 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 807 808 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 809 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 810 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 811 /* Set KX4/KX/KR support according to speed requested */ 812 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 813 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 814 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 815 autoc |= IXGBE_AUTOC_KX4_SUPP; 816 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 817 (hw->phy.smart_speed_active == false)) 818 autoc |= IXGBE_AUTOC_KR_SUPP; 819 } 820 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 821 autoc |= IXGBE_AUTOC_KX_SUPP; 822 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 823 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 824 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 825 /* Switch from 1G SFI to 10G SFI if requested */ 826 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 827 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 828 autoc &= ~IXGBE_AUTOC_LMS_MASK; 829 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 830 } 831 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 832 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 833 /* Switch from 10G SFI to 1G SFI if requested */ 834 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 835 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 836 autoc &= ~IXGBE_AUTOC_LMS_MASK; 837 if (autoneg) 838 autoc |= IXGBE_AUTOC_LMS_1G_AN; 839 else 840 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 841 } 842 } 843 844 if (autoc != current_autoc) { 845 /* Restart link */ 846 status = hw->mac.ops.prot_autoc_write(hw, autoc, false); 847 if (status) 848 return status; 849 850 /* Only poll for autoneg to complete if specified to do so */ 851 if (autoneg_wait_to_complete) { 852 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 853 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 854 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 855 links_reg = 0; /*Just in case Autoneg time=0*/ 856 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 857 links_reg = 858 IXGBE_READ_REG(hw, IXGBE_LINKS); 859 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 860 break; 861 msleep(100); 862 } 863 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 864 status = 865 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 866 hw_dbg(hw, "Autoneg did not complete.\n"); 867 } 868 } 869 } 870 871 /* Add delay to filter out noises during initial link setup */ 872 msleep(50); 873 } 874 875 return status; 876 } 877 878 /** 879 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 880 * @hw: pointer to hardware structure 881 * @speed: new link speed 882 * @autoneg_wait_to_complete: true if waiting is needed to complete 883 * 884 * Restarts link on PHY and MAC based on settings passed in. 885 **/ 886 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 887 ixgbe_link_speed speed, 888 bool autoneg_wait_to_complete) 889 { 890 s32 status; 891 892 /* Setup the PHY according to input speed */ 893 status = hw->phy.ops.setup_link_speed(hw, speed, 894 autoneg_wait_to_complete); 895 /* Set up MAC */ 896 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 897 898 return status; 899 } 900 901 /** 902 * ixgbe_reset_hw_82599 - Perform hardware reset 903 * @hw: pointer to hardware structure 904 * 905 * Resets the hardware by resetting the transmit and receive units, masks 906 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 907 * reset. 908 **/ 909 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 910 { 911 ixgbe_link_speed link_speed; 912 s32 status; 913 u32 ctrl, i, autoc, autoc2; 914 u32 curr_lms; 915 bool link_up = false; 916 917 /* Call adapter stop to disable tx/rx and clear interrupts */ 918 status = hw->mac.ops.stop_adapter(hw); 919 if (status) 920 return status; 921 922 /* flush pending Tx transactions */ 923 ixgbe_clear_tx_pending(hw); 924 925 /* PHY ops must be identified and initialized prior to reset */ 926 927 /* Identify PHY and related function pointers */ 928 status = hw->phy.ops.init(hw); 929 930 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 931 return status; 932 933 /* Setup SFP module if there is one present. */ 934 if (hw->phy.sfp_setup_needed) { 935 status = hw->mac.ops.setup_sfp(hw); 936 hw->phy.sfp_setup_needed = false; 937 } 938 939 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 940 return status; 941 942 /* Reset PHY */ 943 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) 944 hw->phy.ops.reset(hw); 945 946 /* remember AUTOC from before we reset */ 947 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK; 948 949 mac_reset_top: 950 /* 951 * Issue global reset to the MAC. Needs to be SW reset if link is up. 952 * If link reset is used when link is up, it might reset the PHY when 953 * mng is using it. If link is down or the flag to force full link 954 * reset is set, then perform link reset. 955 */ 956 ctrl = IXGBE_CTRL_LNK_RST; 957 if (!hw->force_full_reset) { 958 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 959 if (link_up) 960 ctrl = IXGBE_CTRL_RST; 961 } 962 963 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 964 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 965 IXGBE_WRITE_FLUSH(hw); 966 usleep_range(1000, 1200); 967 968 /* Poll for reset bit to self-clear indicating reset is complete */ 969 for (i = 0; i < 10; i++) { 970 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 971 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 972 break; 973 udelay(1); 974 } 975 976 if (ctrl & IXGBE_CTRL_RST_MASK) { 977 status = IXGBE_ERR_RESET_FAILED; 978 hw_dbg(hw, "Reset polling failed to complete.\n"); 979 } 980 981 msleep(50); 982 983 /* 984 * Double resets are required for recovery from certain error 985 * conditions. Between resets, it is necessary to stall to allow time 986 * for any pending HW events to complete. 987 */ 988 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 989 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 990 goto mac_reset_top; 991 } 992 993 /* 994 * Store the original AUTOC/AUTOC2 values if they have not been 995 * stored off yet. Otherwise restore the stored original 996 * values since the reset operation sets back to defaults. 997 */ 998 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 999 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1000 1001 /* Enable link if disabled in NVM */ 1002 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 1003 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 1004 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1005 IXGBE_WRITE_FLUSH(hw); 1006 } 1007 1008 if (hw->mac.orig_link_settings_stored == false) { 1009 hw->mac.orig_autoc = autoc; 1010 hw->mac.orig_autoc2 = autoc2; 1011 hw->mac.orig_link_settings_stored = true; 1012 } else { 1013 1014 /* If MNG FW is running on a multi-speed device that 1015 * doesn't autoneg with out driver support we need to 1016 * leave LMS in the state it was before we MAC reset. 1017 * Likewise if we support WoL we don't want change the 1018 * LMS state either. 1019 */ 1020 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) || 1021 hw->wol_enabled) 1022 hw->mac.orig_autoc = 1023 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | 1024 curr_lms; 1025 1026 if (autoc != hw->mac.orig_autoc) { 1027 status = hw->mac.ops.prot_autoc_write(hw, 1028 hw->mac.orig_autoc, 1029 false); 1030 if (status) 1031 return status; 1032 } 1033 1034 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1035 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1036 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1037 autoc2 |= (hw->mac.orig_autoc2 & 1038 IXGBE_AUTOC2_UPPER_MASK); 1039 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1040 } 1041 } 1042 1043 /* Store the permanent mac address */ 1044 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1045 1046 /* 1047 * Store MAC address from RAR0, clear receive address registers, and 1048 * clear the multicast table. Also reset num_rar_entries to 128, 1049 * since we modify this value when programming the SAN MAC address. 1050 */ 1051 hw->mac.num_rar_entries = IXGBE_82599_RAR_ENTRIES; 1052 hw->mac.ops.init_rx_addrs(hw); 1053 1054 /* Store the permanent SAN mac address */ 1055 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1056 1057 /* Add the SAN MAC address to the RAR only if it's a valid address */ 1058 if (is_valid_ether_addr(hw->mac.san_addr)) { 1059 /* Save the SAN MAC RAR index */ 1060 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 1061 1062 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, 1063 hw->mac.san_addr, 0, IXGBE_RAH_AV); 1064 1065 /* clear VMDq pool/queue selection for this RAR */ 1066 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, 1067 IXGBE_CLEAR_VMDQ_ALL); 1068 1069 /* Reserve the last RAR for the SAN MAC address */ 1070 hw->mac.num_rar_entries--; 1071 } 1072 1073 /* Store the alternative WWNN/WWPN prefix */ 1074 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 1075 &hw->mac.wwpn_prefix); 1076 1077 return status; 1078 } 1079 1080 /** 1081 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete 1082 * @hw: pointer to hardware structure 1083 * @fdircmd: current value of FDIRCMD register 1084 */ 1085 static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd) 1086 { 1087 int i; 1088 1089 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 1090 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); 1091 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK)) 1092 return 0; 1093 udelay(10); 1094 } 1095 1096 return IXGBE_ERR_FDIR_CMD_INCOMPLETE; 1097 } 1098 1099 /** 1100 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 1101 * @hw: pointer to hardware structure 1102 **/ 1103 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 1104 { 1105 int i; 1106 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1107 u32 fdircmd; 1108 s32 err; 1109 1110 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; 1111 1112 /* 1113 * Before starting reinitialization process, 1114 * FDIRCMD.CMD must be zero. 1115 */ 1116 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1117 if (err) { 1118 hw_dbg(hw, "Flow Director previous command did not complete, aborting table re-initialization.\n"); 1119 return err; 1120 } 1121 1122 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); 1123 IXGBE_WRITE_FLUSH(hw); 1124 /* 1125 * 82599 adapters flow director init flow cannot be restarted, 1126 * Workaround 82599 silicon errata by performing the following steps 1127 * before re-writing the FDIRCTRL control register with the same value. 1128 * - write 1 to bit 8 of FDIRCMD register & 1129 * - write 0 to bit 8 of FDIRCMD register 1130 */ 1131 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1132 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1133 IXGBE_FDIRCMD_CLEARHT)); 1134 IXGBE_WRITE_FLUSH(hw); 1135 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1136 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1137 ~IXGBE_FDIRCMD_CLEARHT)); 1138 IXGBE_WRITE_FLUSH(hw); 1139 /* 1140 * Clear FDIR Hash register to clear any leftover hashes 1141 * waiting to be programmed. 1142 */ 1143 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); 1144 IXGBE_WRITE_FLUSH(hw); 1145 1146 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1147 IXGBE_WRITE_FLUSH(hw); 1148 1149 /* Poll init-done after we write FDIRCTRL register */ 1150 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1151 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1152 IXGBE_FDIRCTRL_INIT_DONE) 1153 break; 1154 usleep_range(1000, 2000); 1155 } 1156 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1157 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); 1158 return IXGBE_ERR_FDIR_REINIT_FAILED; 1159 } 1160 1161 /* Clear FDIR statistics registers (read to clear) */ 1162 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1163 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); 1164 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 1165 IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 1166 IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1167 1168 return 0; 1169 } 1170 1171 /** 1172 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers 1173 * @hw: pointer to hardware structure 1174 * @fdirctrl: value to write to flow director control register 1175 **/ 1176 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1177 { 1178 int i; 1179 1180 /* Prime the keys for hashing */ 1181 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1182 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 1183 1184 /* 1185 * Poll init-done after we write the register. Estimated times: 1186 * 10G: PBALLOC = 11b, timing is 60us 1187 * 1G: PBALLOC = 11b, timing is 600us 1188 * 100M: PBALLOC = 11b, timing is 6ms 1189 * 1190 * Multiple these timings by 4 if under full Rx load 1191 * 1192 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1193 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1194 * this might not finish in our poll time, but we can live with that 1195 * for now. 1196 */ 1197 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1198 IXGBE_WRITE_FLUSH(hw); 1199 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1200 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1201 IXGBE_FDIRCTRL_INIT_DONE) 1202 break; 1203 usleep_range(1000, 2000); 1204 } 1205 1206 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1207 hw_dbg(hw, "Flow Director poll time exceeded!\n"); 1208 } 1209 1210 /** 1211 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1212 * @hw: pointer to hardware structure 1213 * @fdirctrl: value to write to flow director control register, initially 1214 * contains just the value of the Rx packet buffer allocation 1215 **/ 1216 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1217 { 1218 /* 1219 * Continue setup of fdirctrl register bits: 1220 * Move the flexible bytes to use the ethertype - shift 6 words 1221 * Set the maximum length per hash bucket to 0xA filters 1222 * Send interrupt when 64 filters are left 1223 */ 1224 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1225 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1226 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1227 1228 /* write hashes and fdirctrl register, poll for completion */ 1229 ixgbe_fdir_enable_82599(hw, fdirctrl); 1230 1231 return 0; 1232 } 1233 1234 /** 1235 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1236 * @hw: pointer to hardware structure 1237 * @fdirctrl: value to write to flow director control register, initially 1238 * contains just the value of the Rx packet buffer allocation 1239 **/ 1240 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1241 { 1242 /* 1243 * Continue setup of fdirctrl register bits: 1244 * Turn perfect match filtering on 1245 * Initialize the drop queue 1246 * Move the flexible bytes to use the ethertype - shift 6 words 1247 * Set the maximum length per hash bucket to 0xA filters 1248 * Send interrupt when 64 (0x4 * 16) filters are left 1249 */ 1250 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH | 1251 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) | 1252 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1253 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1254 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1255 1256 /* write hashes and fdirctrl register, poll for completion */ 1257 ixgbe_fdir_enable_82599(hw, fdirctrl); 1258 1259 return 0; 1260 } 1261 1262 /* 1263 * These defines allow us to quickly generate all of the necessary instructions 1264 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION 1265 * for values 0 through 15 1266 */ 1267 #define IXGBE_ATR_COMMON_HASH_KEY \ 1268 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) 1269 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ 1270 do { \ 1271 u32 n = (_n); \ 1272 if (IXGBE_ATR_COMMON_HASH_KEY & BIT(n)) \ 1273 common_hash ^= lo_hash_dword >> n; \ 1274 else if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n)) \ 1275 bucket_hash ^= lo_hash_dword >> n; \ 1276 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & BIT(n)) \ 1277 sig_hash ^= lo_hash_dword << (16 - n); \ 1278 if (IXGBE_ATR_COMMON_HASH_KEY & BIT(n + 16)) \ 1279 common_hash ^= hi_hash_dword >> n; \ 1280 else if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n + 16)) \ 1281 bucket_hash ^= hi_hash_dword >> n; \ 1282 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & BIT(n + 16)) \ 1283 sig_hash ^= hi_hash_dword << (16 - n); \ 1284 } while (0) 1285 1286 /** 1287 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash 1288 * @input: input bitstream to compute the hash on 1289 * @common: compressed common input dword 1290 * 1291 * This function is almost identical to the function above but contains 1292 * several optimizations such as unwinding all of the loops, letting the 1293 * compiler work out all of the conditional ifs since the keys are static 1294 * defines, and computing two keys at once since the hashed dword stream 1295 * will be the same for both keys. 1296 **/ 1297 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 1298 union ixgbe_atr_hash_dword common) 1299 { 1300 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1301 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0; 1302 1303 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1304 flow_vm_vlan = ntohl(input.dword); 1305 1306 /* generate common hash dword */ 1307 hi_hash_dword = ntohl(common.dword); 1308 1309 /* low dword is word swapped version of common */ 1310 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1311 1312 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1313 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1314 1315 /* Process bits 0 and 16 */ 1316 IXGBE_COMPUTE_SIG_HASH_ITERATION(0); 1317 1318 /* 1319 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1320 * delay this because bit 0 of the stream should not be processed 1321 * so we do not add the vlan until after bit 0 was processed 1322 */ 1323 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1324 1325 /* Process remaining 30 bit of the key */ 1326 IXGBE_COMPUTE_SIG_HASH_ITERATION(1); 1327 IXGBE_COMPUTE_SIG_HASH_ITERATION(2); 1328 IXGBE_COMPUTE_SIG_HASH_ITERATION(3); 1329 IXGBE_COMPUTE_SIG_HASH_ITERATION(4); 1330 IXGBE_COMPUTE_SIG_HASH_ITERATION(5); 1331 IXGBE_COMPUTE_SIG_HASH_ITERATION(6); 1332 IXGBE_COMPUTE_SIG_HASH_ITERATION(7); 1333 IXGBE_COMPUTE_SIG_HASH_ITERATION(8); 1334 IXGBE_COMPUTE_SIG_HASH_ITERATION(9); 1335 IXGBE_COMPUTE_SIG_HASH_ITERATION(10); 1336 IXGBE_COMPUTE_SIG_HASH_ITERATION(11); 1337 IXGBE_COMPUTE_SIG_HASH_ITERATION(12); 1338 IXGBE_COMPUTE_SIG_HASH_ITERATION(13); 1339 IXGBE_COMPUTE_SIG_HASH_ITERATION(14); 1340 IXGBE_COMPUTE_SIG_HASH_ITERATION(15); 1341 1342 /* combine common_hash result with signature and bucket hashes */ 1343 bucket_hash ^= common_hash; 1344 bucket_hash &= IXGBE_ATR_HASH_MASK; 1345 1346 sig_hash ^= common_hash << 16; 1347 sig_hash &= IXGBE_ATR_HASH_MASK << 16; 1348 1349 /* return completed signature hash */ 1350 return sig_hash ^ bucket_hash; 1351 } 1352 1353 /** 1354 * ixgbe_fdir_add_signature_filter_82599 - Adds a signature hash filter 1355 * @hw: pointer to hardware structure 1356 * @input: unique input dword 1357 * @common: compressed common input dword 1358 * @queue: queue index to direct traffic to 1359 * 1360 * Note that the tunnel bit in input must not be set when the hardware 1361 * tunneling support does not exist. 1362 **/ 1363 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1364 union ixgbe_atr_hash_dword input, 1365 union ixgbe_atr_hash_dword common, 1366 u8 queue) 1367 { 1368 u64 fdirhashcmd; 1369 u8 flow_type; 1370 bool tunnel; 1371 u32 fdircmd; 1372 1373 /* 1374 * Get the flow_type in order to program FDIRCMD properly 1375 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 1376 */ 1377 tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK); 1378 flow_type = input.formatted.flow_type & 1379 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1); 1380 switch (flow_type) { 1381 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1382 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1383 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1384 case IXGBE_ATR_FLOW_TYPE_TCPV6: 1385 case IXGBE_ATR_FLOW_TYPE_UDPV6: 1386 case IXGBE_ATR_FLOW_TYPE_SCTPV6: 1387 break; 1388 default: 1389 hw_dbg(hw, " Error on flow type input\n"); 1390 return IXGBE_ERR_CONFIG; 1391 } 1392 1393 /* configure FDIRCMD register */ 1394 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1395 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1396 fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1397 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1398 if (tunnel) 1399 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER; 1400 1401 /* 1402 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 1403 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 1404 */ 1405 fdirhashcmd = (u64)fdircmd << 32; 1406 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common); 1407 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1408 1409 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); 1410 1411 return 0; 1412 } 1413 1414 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \ 1415 do { \ 1416 u32 n = (_n); \ 1417 if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n)) \ 1418 bucket_hash ^= lo_hash_dword >> n; \ 1419 if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n + 16)) \ 1420 bucket_hash ^= hi_hash_dword >> n; \ 1421 } while (0) 1422 1423 /** 1424 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash 1425 * @input: input bitstream to compute the hash on 1426 * @input_mask: mask for the input bitstream 1427 * 1428 * This function serves two main purposes. First it applies the input_mask 1429 * to the atr_input resulting in a cleaned up atr_input data stream. 1430 * Secondly it computes the hash and stores it in the bkt_hash field at 1431 * the end of the input byte stream. This way it will be available for 1432 * future use without needing to recompute the hash. 1433 **/ 1434 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 1435 union ixgbe_atr_input *input_mask) 1436 { 1437 1438 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1439 u32 bucket_hash = 0; 1440 __be32 hi_dword = 0; 1441 int i; 1442 1443 /* Apply masks to input data */ 1444 for (i = 0; i <= 10; i++) 1445 input->dword_stream[i] &= input_mask->dword_stream[i]; 1446 1447 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1448 flow_vm_vlan = ntohl(input->dword_stream[0]); 1449 1450 /* generate common hash dword */ 1451 for (i = 1; i <= 10; i++) 1452 hi_dword ^= input->dword_stream[i]; 1453 hi_hash_dword = ntohl(hi_dword); 1454 1455 /* low dword is word swapped version of common */ 1456 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1457 1458 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1459 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1460 1461 /* Process bits 0 and 16 */ 1462 IXGBE_COMPUTE_BKT_HASH_ITERATION(0); 1463 1464 /* 1465 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1466 * delay this because bit 0 of the stream should not be processed 1467 * so we do not add the vlan until after bit 0 was processed 1468 */ 1469 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1470 1471 /* Process remaining 30 bit of the key */ 1472 for (i = 1; i <= 15; i++) 1473 IXGBE_COMPUTE_BKT_HASH_ITERATION(i); 1474 1475 /* 1476 * Limit hash to 13 bits since max bucket count is 8K. 1477 * Store result at the end of the input stream. 1478 */ 1479 input->formatted.bkt_hash = (__force __be16)(bucket_hash & 0x1FFF); 1480 } 1481 1482 /** 1483 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks 1484 * @input_mask: mask to be bit swapped 1485 * 1486 * The source and destination port masks for flow director are bit swapped 1487 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to 1488 * generate a correctly swapped value we need to bit swap the mask and that 1489 * is what is accomplished by this function. 1490 **/ 1491 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask) 1492 { 1493 u32 mask = ntohs(input_mask->formatted.dst_port); 1494 1495 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; 1496 mask |= ntohs(input_mask->formatted.src_port); 1497 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); 1498 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); 1499 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); 1500 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); 1501 } 1502 1503 /* 1504 * These two macros are meant to address the fact that we have registers 1505 * that are either all or in part big-endian. As a result on big-endian 1506 * systems we will end up byte swapping the value to little-endian before 1507 * it is byte swapped again and written to the hardware in the original 1508 * big-endian format. 1509 */ 1510 #define IXGBE_STORE_AS_BE32(_value) \ 1511 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \ 1512 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24)) 1513 1514 #define IXGBE_WRITE_REG_BE32(a, reg, value) \ 1515 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value))) 1516 1517 #define IXGBE_STORE_AS_BE16(_value) __swab16(ntohs((_value))) 1518 1519 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 1520 union ixgbe_atr_input *input_mask) 1521 { 1522 /* mask IPv6 since it is currently not supported */ 1523 u32 fdirm = IXGBE_FDIRM_DIPv6; 1524 u32 fdirtcpm; 1525 1526 /* 1527 * Program the relevant mask registers. If src/dst_port or src/dst_addr 1528 * are zero, then assume a full mask for that field. Also assume that 1529 * a VLAN of 0 is unspecified, so mask that out as well. L4type 1530 * cannot be masked out in this implementation. 1531 * 1532 * This also assumes IPv4 only. IPv6 masking isn't supported at this 1533 * point in time. 1534 */ 1535 1536 /* verify bucket hash is cleared on hash generation */ 1537 if (input_mask->formatted.bkt_hash) 1538 hw_dbg(hw, " bucket hash should always be 0 in mask\n"); 1539 1540 /* Program FDIRM and verify partial masks */ 1541 switch (input_mask->formatted.vm_pool & 0x7F) { 1542 case 0x0: 1543 fdirm |= IXGBE_FDIRM_POOL; 1544 break; 1545 case 0x7F: 1546 break; 1547 default: 1548 hw_dbg(hw, " Error on vm pool mask\n"); 1549 return IXGBE_ERR_CONFIG; 1550 } 1551 1552 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) { 1553 case 0x0: 1554 fdirm |= IXGBE_FDIRM_L4P; 1555 if (input_mask->formatted.dst_port || 1556 input_mask->formatted.src_port) { 1557 hw_dbg(hw, " Error on src/dst port mask\n"); 1558 return IXGBE_ERR_CONFIG; 1559 } 1560 break; 1561 case IXGBE_ATR_L4TYPE_MASK: 1562 break; 1563 default: 1564 hw_dbg(hw, " Error on flow type mask\n"); 1565 return IXGBE_ERR_CONFIG; 1566 } 1567 1568 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) { 1569 case 0x0000: 1570 /* mask VLAN ID */ 1571 fdirm |= IXGBE_FDIRM_VLANID; 1572 fallthrough; 1573 case 0x0FFF: 1574 /* mask VLAN priority */ 1575 fdirm |= IXGBE_FDIRM_VLANP; 1576 break; 1577 case 0xE000: 1578 /* mask VLAN ID only */ 1579 fdirm |= IXGBE_FDIRM_VLANID; 1580 fallthrough; 1581 case 0xEFFF: 1582 /* no VLAN fields masked */ 1583 break; 1584 default: 1585 hw_dbg(hw, " Error on VLAN mask\n"); 1586 return IXGBE_ERR_CONFIG; 1587 } 1588 1589 switch ((__force u16)input_mask->formatted.flex_bytes & 0xFFFF) { 1590 case 0x0000: 1591 /* Mask Flex Bytes */ 1592 fdirm |= IXGBE_FDIRM_FLEX; 1593 fallthrough; 1594 case 0xFFFF: 1595 break; 1596 default: 1597 hw_dbg(hw, " Error on flexible byte mask\n"); 1598 return IXGBE_ERR_CONFIG; 1599 } 1600 1601 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ 1602 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 1603 1604 /* store the TCP/UDP port masks, bit reversed from port layout */ 1605 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask); 1606 1607 /* write both the same so that UDP and TCP use the same mask */ 1608 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); 1609 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); 1610 1611 /* also use it for SCTP */ 1612 switch (hw->mac.type) { 1613 case ixgbe_mac_X550: 1614 case ixgbe_mac_X550EM_x: 1615 case ixgbe_mac_x550em_a: 1616 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm); 1617 break; 1618 default: 1619 break; 1620 } 1621 1622 /* store source and destination IP masks (big-enian) */ 1623 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 1624 ~input_mask->formatted.src_ip[0]); 1625 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 1626 ~input_mask->formatted.dst_ip[0]); 1627 1628 return 0; 1629 } 1630 1631 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 1632 union ixgbe_atr_input *input, 1633 u16 soft_id, u8 queue) 1634 { 1635 u32 fdirport, fdirvlan, fdirhash, fdircmd; 1636 s32 err; 1637 1638 /* currently IPv6 is not supported, must be programmed with 0 */ 1639 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), 1640 input->formatted.src_ip[0]); 1641 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), 1642 input->formatted.src_ip[1]); 1643 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), 1644 input->formatted.src_ip[2]); 1645 1646 /* record the source address (big-endian) */ 1647 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); 1648 1649 /* record the first 32 bits of the destination address (big-endian) */ 1650 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); 1651 1652 /* record source and destination port (little-endian)*/ 1653 fdirport = be16_to_cpu(input->formatted.dst_port); 1654 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; 1655 fdirport |= be16_to_cpu(input->formatted.src_port); 1656 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); 1657 1658 /* record vlan (little-endian) and flex_bytes(big-endian) */ 1659 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); 1660 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; 1661 fdirvlan |= ntohs(input->formatted.vlan_id); 1662 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); 1663 1664 /* configure FDIRHASH register */ 1665 fdirhash = (__force u32)input->formatted.bkt_hash; 1666 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1667 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1668 1669 /* 1670 * flush all previous writes to make certain registers are 1671 * programmed prior to issuing the command 1672 */ 1673 IXGBE_WRITE_FLUSH(hw); 1674 1675 /* configure FDIRCMD register */ 1676 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1677 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1678 if (queue == IXGBE_FDIR_DROP_QUEUE) 1679 fdircmd |= IXGBE_FDIRCMD_DROP; 1680 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1681 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1682 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; 1683 1684 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1685 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1686 if (err) { 1687 hw_dbg(hw, "Flow Director command did not complete!\n"); 1688 return err; 1689 } 1690 1691 return 0; 1692 } 1693 1694 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 1695 union ixgbe_atr_input *input, 1696 u16 soft_id) 1697 { 1698 u32 fdirhash; 1699 u32 fdircmd; 1700 s32 err; 1701 1702 /* configure FDIRHASH register */ 1703 fdirhash = (__force u32)input->formatted.bkt_hash; 1704 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1705 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1706 1707 /* flush hash to HW */ 1708 IXGBE_WRITE_FLUSH(hw); 1709 1710 /* Query if filter is present */ 1711 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); 1712 1713 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1714 if (err) { 1715 hw_dbg(hw, "Flow Director command did not complete!\n"); 1716 return err; 1717 } 1718 1719 /* if filter exists in hardware then remove it */ 1720 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) { 1721 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1722 IXGBE_WRITE_FLUSH(hw); 1723 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1724 IXGBE_FDIRCMD_CMD_REMOVE_FLOW); 1725 } 1726 1727 return 0; 1728 } 1729 1730 /** 1731 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 1732 * @hw: pointer to hardware structure 1733 * @reg: analog register to read 1734 * @val: read value 1735 * 1736 * Performs read operation to Omer analog register specified. 1737 **/ 1738 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 1739 { 1740 u32 core_ctl; 1741 1742 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 1743 (reg << 8)); 1744 IXGBE_WRITE_FLUSH(hw); 1745 udelay(10); 1746 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 1747 *val = (u8)core_ctl; 1748 1749 return 0; 1750 } 1751 1752 /** 1753 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 1754 * @hw: pointer to hardware structure 1755 * @reg: atlas register to write 1756 * @val: value to write 1757 * 1758 * Performs write operation to Omer analog register specified. 1759 **/ 1760 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 1761 { 1762 u32 core_ctl; 1763 1764 core_ctl = (reg << 8) | val; 1765 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 1766 IXGBE_WRITE_FLUSH(hw); 1767 udelay(10); 1768 1769 return 0; 1770 } 1771 1772 /** 1773 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx 1774 * @hw: pointer to hardware structure 1775 * 1776 * Starts the hardware using the generic start_hw function 1777 * and the generation start_hw function. 1778 * Then performs revision-specific operations, if any. 1779 **/ 1780 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) 1781 { 1782 s32 ret_val = 0; 1783 1784 ret_val = ixgbe_start_hw_generic(hw); 1785 if (ret_val) 1786 return ret_val; 1787 1788 ret_val = ixgbe_start_hw_gen2(hw); 1789 if (ret_val) 1790 return ret_val; 1791 1792 /* We need to run link autotry after the driver loads */ 1793 hw->mac.autotry_restart = true; 1794 1795 return ixgbe_verify_fw_version_82599(hw); 1796 } 1797 1798 /** 1799 * ixgbe_identify_phy_82599 - Get physical layer module 1800 * @hw: pointer to hardware structure 1801 * 1802 * Determines the physical layer module found on the current adapter. 1803 * If PHY already detected, maintains current PHY type in hw struct, 1804 * otherwise executes the PHY detection routine. 1805 **/ 1806 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 1807 { 1808 s32 status; 1809 1810 /* Detect PHY if not unknown - returns success if already detected. */ 1811 status = ixgbe_identify_phy_generic(hw); 1812 if (status) { 1813 /* 82599 10GBASE-T requires an external PHY */ 1814 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 1815 return status; 1816 status = ixgbe_identify_module_generic(hw); 1817 } 1818 1819 /* Set PHY type none if no PHY detected */ 1820 if (hw->phy.type == ixgbe_phy_unknown) { 1821 hw->phy.type = ixgbe_phy_none; 1822 status = 0; 1823 } 1824 1825 /* Return error if SFP module has been detected but is not supported */ 1826 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1827 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1828 1829 return status; 1830 } 1831 1832 /** 1833 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 1834 * @hw: pointer to hardware structure 1835 * @regval: register value to write to RXCTRL 1836 * 1837 * Enables the Rx DMA unit for 82599 1838 **/ 1839 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 1840 { 1841 /* 1842 * Workaround for 82599 silicon errata when enabling the Rx datapath. 1843 * If traffic is incoming before we enable the Rx unit, it could hang 1844 * the Rx DMA unit. Therefore, make sure the security engine is 1845 * completely disabled prior to enabling the Rx unit. 1846 */ 1847 hw->mac.ops.disable_rx_buff(hw); 1848 1849 if (regval & IXGBE_RXCTRL_RXEN) 1850 hw->mac.ops.enable_rx(hw); 1851 else 1852 hw->mac.ops.disable_rx(hw); 1853 1854 hw->mac.ops.enable_rx_buff(hw); 1855 1856 return 0; 1857 } 1858 1859 /** 1860 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 1861 * @hw: pointer to hardware structure 1862 * 1863 * Verifies that installed the firmware version is 0.6 or higher 1864 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 1865 * 1866 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 1867 * if the FW version is not supported. 1868 **/ 1869 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 1870 { 1871 s32 status = IXGBE_ERR_EEPROM_VERSION; 1872 u16 fw_offset, fw_ptp_cfg_offset; 1873 u16 offset; 1874 u16 fw_version = 0; 1875 1876 /* firmware check is only necessary for SFI devices */ 1877 if (hw->phy.media_type != ixgbe_media_type_fiber) 1878 return 0; 1879 1880 /* get the offset to the Firmware Module block */ 1881 offset = IXGBE_FW_PTR; 1882 if (hw->eeprom.ops.read(hw, offset, &fw_offset)) 1883 goto fw_version_err; 1884 1885 if (fw_offset == 0 || fw_offset == 0xFFFF) 1886 return IXGBE_ERR_EEPROM_VERSION; 1887 1888 /* get the offset to the Pass Through Patch Configuration block */ 1889 offset = fw_offset + IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR; 1890 if (hw->eeprom.ops.read(hw, offset, &fw_ptp_cfg_offset)) 1891 goto fw_version_err; 1892 1893 if (fw_ptp_cfg_offset == 0 || fw_ptp_cfg_offset == 0xFFFF) 1894 return IXGBE_ERR_EEPROM_VERSION; 1895 1896 /* get the firmware version */ 1897 offset = fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4; 1898 if (hw->eeprom.ops.read(hw, offset, &fw_version)) 1899 goto fw_version_err; 1900 1901 if (fw_version > 0x5) 1902 status = 0; 1903 1904 return status; 1905 1906 fw_version_err: 1907 hw_err(hw, "eeprom read at offset %d failed\n", offset); 1908 return IXGBE_ERR_EEPROM_VERSION; 1909 } 1910 1911 /** 1912 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 1913 * @hw: pointer to hardware structure 1914 * 1915 * Returns true if the LESM FW module is present and enabled. Otherwise 1916 * returns false. Smart Speed must be disabled if LESM FW module is enabled. 1917 **/ 1918 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 1919 { 1920 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state; 1921 s32 status; 1922 1923 /* get the offset to the Firmware Module block */ 1924 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 1925 1926 if (status || fw_offset == 0 || fw_offset == 0xFFFF) 1927 return false; 1928 1929 /* get the offset to the LESM Parameters block */ 1930 status = hw->eeprom.ops.read(hw, (fw_offset + 1931 IXGBE_FW_LESM_PARAMETERS_PTR), 1932 &fw_lesm_param_offset); 1933 1934 if (status || 1935 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF) 1936 return false; 1937 1938 /* get the lesm state word */ 1939 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 1940 IXGBE_FW_LESM_STATE_1), 1941 &fw_lesm_state); 1942 1943 if (!status && (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 1944 return true; 1945 1946 return false; 1947 } 1948 1949 /** 1950 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using 1951 * fastest available method 1952 * 1953 * @hw: pointer to hardware structure 1954 * @offset: offset of word in EEPROM to read 1955 * @words: number of words 1956 * @data: word(s) read from the EEPROM 1957 * 1958 * Retrieves 16 bit word(s) read from EEPROM 1959 **/ 1960 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 1961 u16 words, u16 *data) 1962 { 1963 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1964 1965 /* If EEPROM is detected and can be addressed using 14 bits, 1966 * use EERD otherwise use bit bang 1967 */ 1968 if (eeprom->type == ixgbe_eeprom_spi && 1969 offset + (words - 1) <= IXGBE_EERD_MAX_ADDR) 1970 return ixgbe_read_eerd_buffer_generic(hw, offset, words, data); 1971 1972 return ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, words, 1973 data); 1974 } 1975 1976 /** 1977 * ixgbe_read_eeprom_82599 - Read EEPROM word using 1978 * fastest available method 1979 * 1980 * @hw: pointer to hardware structure 1981 * @offset: offset of word in the EEPROM to read 1982 * @data: word read from the EEPROM 1983 * 1984 * Reads a 16 bit word from the EEPROM 1985 **/ 1986 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 1987 u16 offset, u16 *data) 1988 { 1989 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1990 1991 /* 1992 * If EEPROM is detected and can be addressed using 14 bits, 1993 * use EERD otherwise use bit bang 1994 */ 1995 if (eeprom->type == ixgbe_eeprom_spi && offset <= IXGBE_EERD_MAX_ADDR) 1996 return ixgbe_read_eerd_generic(hw, offset, data); 1997 1998 return ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); 1999 } 2000 2001 /** 2002 * ixgbe_reset_pipeline_82599 - perform pipeline reset 2003 * 2004 * @hw: pointer to hardware structure 2005 * 2006 * Reset pipeline by asserting Restart_AN together with LMS change to ensure 2007 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing 2008 * to AUTOC, so this function assumes the semaphore is held. 2009 **/ 2010 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) 2011 { 2012 s32 ret_val; 2013 u32 anlp1_reg = 0; 2014 u32 i, autoc_reg, autoc2_reg; 2015 2016 /* Enable link if disabled in NVM */ 2017 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 2018 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 2019 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 2020 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 2021 IXGBE_WRITE_FLUSH(hw); 2022 } 2023 2024 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2025 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2026 2027 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */ 2028 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, 2029 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT)); 2030 2031 /* Wait for AN to leave state 0 */ 2032 for (i = 0; i < 10; i++) { 2033 usleep_range(4000, 8000); 2034 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2035 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK) 2036 break; 2037 } 2038 2039 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) { 2040 hw_dbg(hw, "auto negotiation not completed\n"); 2041 ret_val = IXGBE_ERR_RESET_FAILED; 2042 goto reset_pipeline_out; 2043 } 2044 2045 ret_val = 0; 2046 2047 reset_pipeline_out: 2048 /* Write AUTOC register with original LMS field and Restart_AN */ 2049 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2050 IXGBE_WRITE_FLUSH(hw); 2051 2052 return ret_val; 2053 } 2054 2055 /** 2056 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C 2057 * @hw: pointer to hardware structure 2058 * @byte_offset: byte offset to read 2059 * @dev_addr: address to read from 2060 * @data: value read 2061 * 2062 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2063 * a specified device address. 2064 **/ 2065 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2066 u8 dev_addr, u8 *data) 2067 { 2068 u32 esdp; 2069 s32 status; 2070 s32 timeout = 200; 2071 2072 if (hw->phy.qsfp_shared_i2c_bus == true) { 2073 /* Acquire I2C bus ownership. */ 2074 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2075 esdp |= IXGBE_ESDP_SDP0; 2076 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2077 IXGBE_WRITE_FLUSH(hw); 2078 2079 while (timeout) { 2080 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2081 if (esdp & IXGBE_ESDP_SDP1) 2082 break; 2083 2084 usleep_range(5000, 10000); 2085 timeout--; 2086 } 2087 2088 if (!timeout) { 2089 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n"); 2090 status = IXGBE_ERR_I2C; 2091 goto release_i2c_access; 2092 } 2093 } 2094 2095 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2096 2097 release_i2c_access: 2098 if (hw->phy.qsfp_shared_i2c_bus == true) { 2099 /* Release I2C bus ownership. */ 2100 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2101 esdp &= ~IXGBE_ESDP_SDP0; 2102 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2103 IXGBE_WRITE_FLUSH(hw); 2104 } 2105 2106 return status; 2107 } 2108 2109 /** 2110 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C 2111 * @hw: pointer to hardware structure 2112 * @byte_offset: byte offset to write 2113 * @dev_addr: address to write to 2114 * @data: value to write 2115 * 2116 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2117 * a specified device address. 2118 **/ 2119 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2120 u8 dev_addr, u8 data) 2121 { 2122 u32 esdp; 2123 s32 status; 2124 s32 timeout = 200; 2125 2126 if (hw->phy.qsfp_shared_i2c_bus == true) { 2127 /* Acquire I2C bus ownership. */ 2128 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2129 esdp |= IXGBE_ESDP_SDP0; 2130 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2131 IXGBE_WRITE_FLUSH(hw); 2132 2133 while (timeout) { 2134 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2135 if (esdp & IXGBE_ESDP_SDP1) 2136 break; 2137 2138 usleep_range(5000, 10000); 2139 timeout--; 2140 } 2141 2142 if (!timeout) { 2143 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n"); 2144 status = IXGBE_ERR_I2C; 2145 goto release_i2c_access; 2146 } 2147 } 2148 2149 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2150 2151 release_i2c_access: 2152 if (hw->phy.qsfp_shared_i2c_bus == true) { 2153 /* Release I2C bus ownership. */ 2154 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2155 esdp &= ~IXGBE_ESDP_SDP0; 2156 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2157 IXGBE_WRITE_FLUSH(hw); 2158 } 2159 2160 return status; 2161 } 2162 2163 static const struct ixgbe_mac_operations mac_ops_82599 = { 2164 .init_hw = &ixgbe_init_hw_generic, 2165 .reset_hw = &ixgbe_reset_hw_82599, 2166 .start_hw = &ixgbe_start_hw_82599, 2167 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 2168 .get_media_type = &ixgbe_get_media_type_82599, 2169 .enable_rx_dma = &ixgbe_enable_rx_dma_82599, 2170 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, 2171 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, 2172 .get_mac_addr = &ixgbe_get_mac_addr_generic, 2173 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 2174 .get_device_caps = &ixgbe_get_device_caps_generic, 2175 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 2176 .stop_adapter = &ixgbe_stop_adapter_generic, 2177 .get_bus_info = &ixgbe_get_bus_info_generic, 2178 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, 2179 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599, 2180 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599, 2181 .stop_link_on_d3 = &ixgbe_stop_mac_link_on_d3_82599, 2182 .setup_link = &ixgbe_setup_mac_link_82599, 2183 .set_rxpba = &ixgbe_set_rxpba_generic, 2184 .check_link = &ixgbe_check_mac_link_generic, 2185 .get_link_capabilities = &ixgbe_get_link_capabilities_82599, 2186 .led_on = &ixgbe_led_on_generic, 2187 .led_off = &ixgbe_led_off_generic, 2188 .init_led_link_act = ixgbe_init_led_link_act_generic, 2189 .blink_led_start = &ixgbe_blink_led_start_generic, 2190 .blink_led_stop = &ixgbe_blink_led_stop_generic, 2191 .set_rar = &ixgbe_set_rar_generic, 2192 .clear_rar = &ixgbe_clear_rar_generic, 2193 .set_vmdq = &ixgbe_set_vmdq_generic, 2194 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, 2195 .clear_vmdq = &ixgbe_clear_vmdq_generic, 2196 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 2197 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 2198 .enable_mc = &ixgbe_enable_mc_generic, 2199 .disable_mc = &ixgbe_disable_mc_generic, 2200 .clear_vfta = &ixgbe_clear_vfta_generic, 2201 .set_vfta = &ixgbe_set_vfta_generic, 2202 .fc_enable = &ixgbe_fc_enable_generic, 2203 .setup_fc = ixgbe_setup_fc_generic, 2204 .fc_autoneg = ixgbe_fc_autoneg, 2205 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, 2206 .init_uta_tables = &ixgbe_init_uta_tables_generic, 2207 .setup_sfp = &ixgbe_setup_sfp_modules_82599, 2208 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, 2209 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, 2210 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync, 2211 .release_swfw_sync = &ixgbe_release_swfw_sync, 2212 .init_swfw_sync = NULL, 2213 .get_thermal_sensor_data = &ixgbe_get_thermal_sensor_data_generic, 2214 .init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic, 2215 .prot_autoc_read = &prot_autoc_read_82599, 2216 .prot_autoc_write = &prot_autoc_write_82599, 2217 .enable_rx = &ixgbe_enable_rx_generic, 2218 .disable_rx = &ixgbe_disable_rx_generic, 2219 }; 2220 2221 static const struct ixgbe_eeprom_operations eeprom_ops_82599 = { 2222 .init_params = &ixgbe_init_eeprom_params_generic, 2223 .read = &ixgbe_read_eeprom_82599, 2224 .read_buffer = &ixgbe_read_eeprom_buffer_82599, 2225 .write = &ixgbe_write_eeprom_generic, 2226 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic, 2227 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, 2228 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 2229 .update_checksum = &ixgbe_update_eeprom_checksum_generic, 2230 }; 2231 2232 static const struct ixgbe_phy_operations phy_ops_82599 = { 2233 .identify = &ixgbe_identify_phy_82599, 2234 .identify_sfp = &ixgbe_identify_module_generic, 2235 .init = &ixgbe_init_phy_ops_82599, 2236 .reset = &ixgbe_reset_phy_generic, 2237 .read_reg = &ixgbe_read_phy_reg_generic, 2238 .write_reg = &ixgbe_write_phy_reg_generic, 2239 .setup_link = &ixgbe_setup_phy_link_generic, 2240 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 2241 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, 2242 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, 2243 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, 2244 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, 2245 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, 2246 .check_overtemp = &ixgbe_tn_check_overtemp, 2247 }; 2248 2249 const struct ixgbe_info ixgbe_82599_info = { 2250 .mac = ixgbe_mac_82599EB, 2251 .get_invariants = &ixgbe_get_invariants_82599, 2252 .mac_ops = &mac_ops_82599, 2253 .eeprom_ops = &eeprom_ops_82599, 2254 .phy_ops = &phy_ops_82599, 2255 .mbx_ops = &mbx_ops_generic, 2256 .mvals = ixgbe_mvals_8259X, 2257 }; 2258