1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include <linux/pci.h> 29 #include <linux/delay.h> 30 #include <linux/sched.h> 31 32 #include "ixgbe.h" 33 #include "ixgbe_phy.h" 34 #include "ixgbe_mbx.h" 35 36 #define IXGBE_82599_MAX_TX_QUEUES 128 37 #define IXGBE_82599_MAX_RX_QUEUES 128 38 #define IXGBE_82599_RAR_ENTRIES 128 39 #define IXGBE_82599_MC_TBL_SIZE 128 40 #define IXGBE_82599_VFT_TBL_SIZE 128 41 #define IXGBE_82599_RX_PB_SIZE 512 42 43 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 44 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 45 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 46 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 47 ixgbe_link_speed speed, 48 bool autoneg, 49 bool autoneg_wait_to_complete); 50 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 51 ixgbe_link_speed speed, 52 bool autoneg, 53 bool autoneg_wait_to_complete); 54 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 55 bool autoneg_wait_to_complete); 56 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 57 ixgbe_link_speed speed, 58 bool autoneg, 59 bool autoneg_wait_to_complete); 60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 61 ixgbe_link_speed speed, 62 bool autoneg, 63 bool autoneg_wait_to_complete); 64 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 65 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw); 66 67 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 68 { 69 struct ixgbe_mac_info *mac = &hw->mac; 70 71 /* enable the laser control functions for SFP+ fiber */ 72 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) { 73 mac->ops.disable_tx_laser = 74 &ixgbe_disable_tx_laser_multispeed_fiber; 75 mac->ops.enable_tx_laser = 76 &ixgbe_enable_tx_laser_multispeed_fiber; 77 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; 78 } else { 79 mac->ops.disable_tx_laser = NULL; 80 mac->ops.enable_tx_laser = NULL; 81 mac->ops.flap_tx_laser = NULL; 82 } 83 84 if (hw->phy.multispeed_fiber) { 85 /* Set up dual speed SFP+ support */ 86 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; 87 } else { 88 if ((mac->ops.get_media_type(hw) == 89 ixgbe_media_type_backplane) && 90 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 91 hw->phy.smart_speed == ixgbe_smart_speed_on) && 92 !ixgbe_verify_lesm_fw_enabled_82599(hw)) 93 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; 94 else 95 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; 96 } 97 } 98 99 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 100 { 101 s32 ret_val = 0; 102 u32 reg_anlp1 = 0; 103 u32 i = 0; 104 u16 list_offset, data_offset, data_value; 105 106 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 107 ixgbe_init_mac_link_ops_82599(hw); 108 109 hw->phy.ops.reset = NULL; 110 111 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 112 &data_offset); 113 if (ret_val != 0) 114 goto setup_sfp_out; 115 116 /* PHY config will finish before releasing the semaphore */ 117 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 118 IXGBE_GSSR_MAC_CSR_SM); 119 if (ret_val != 0) { 120 ret_val = IXGBE_ERR_SWFW_SYNC; 121 goto setup_sfp_out; 122 } 123 124 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 125 while (data_value != 0xffff) { 126 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 127 IXGBE_WRITE_FLUSH(hw); 128 hw->eeprom.ops.read(hw, ++data_offset, &data_value); 129 } 130 131 /* Release the semaphore */ 132 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 133 /* 134 * Delay obtaining semaphore again to allow FW access, 135 * semaphore_delay is in ms usleep_range needs us. 136 */ 137 usleep_range(hw->eeprom.semaphore_delay * 1000, 138 hw->eeprom.semaphore_delay * 2000); 139 140 /* Now restart DSP by setting Restart_AN and clearing LMS */ 141 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw, 142 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) | 143 IXGBE_AUTOC_AN_RESTART)); 144 145 /* Wait for AN to leave state 0 */ 146 for (i = 0; i < 10; i++) { 147 usleep_range(4000, 8000); 148 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1); 149 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK) 150 break; 151 } 152 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) { 153 hw_dbg(hw, "sfp module setup not complete\n"); 154 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 155 goto setup_sfp_out; 156 } 157 158 /* Restart DSP by setting Restart_AN and return to SFI mode */ 159 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw, 160 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL | 161 IXGBE_AUTOC_AN_RESTART)); 162 } 163 164 setup_sfp_out: 165 return ret_val; 166 } 167 168 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw) 169 { 170 struct ixgbe_mac_info *mac = &hw->mac; 171 172 ixgbe_init_mac_link_ops_82599(hw); 173 174 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; 175 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; 176 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; 177 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; 178 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; 179 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 180 181 return 0; 182 } 183 184 /** 185 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 186 * @hw: pointer to hardware structure 187 * 188 * Initialize any function pointers that were not able to be 189 * set during get_invariants because the PHY/SFP type was 190 * not known. Perform the SFP init if necessary. 191 * 192 **/ 193 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 194 { 195 struct ixgbe_mac_info *mac = &hw->mac; 196 struct ixgbe_phy_info *phy = &hw->phy; 197 s32 ret_val = 0; 198 199 /* Identify the PHY or SFP module */ 200 ret_val = phy->ops.identify(hw); 201 202 /* Setup function pointers based on detected SFP module and speeds */ 203 ixgbe_init_mac_link_ops_82599(hw); 204 205 /* If copper media, overwrite with copper function pointers */ 206 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 207 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; 208 mac->ops.get_link_capabilities = 209 &ixgbe_get_copper_link_capabilities_generic; 210 } 211 212 /* Set necessary function pointers based on phy type */ 213 switch (hw->phy.type) { 214 case ixgbe_phy_tn: 215 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 216 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 217 phy->ops.get_firmware_version = 218 &ixgbe_get_phy_firmware_version_tnx; 219 break; 220 default: 221 break; 222 } 223 224 return ret_val; 225 } 226 227 /** 228 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 229 * @hw: pointer to hardware structure 230 * @speed: pointer to link speed 231 * @negotiation: true when autoneg or autotry is enabled 232 * 233 * Determines the link capabilities by reading the AUTOC register. 234 **/ 235 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 236 ixgbe_link_speed *speed, 237 bool *negotiation) 238 { 239 s32 status = 0; 240 u32 autoc = 0; 241 242 /* Determine 1G link capabilities off of SFP+ type */ 243 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 244 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 245 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 246 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 247 *speed = IXGBE_LINK_SPEED_1GB_FULL; 248 *negotiation = true; 249 goto out; 250 } 251 252 /* 253 * Determine link capabilities based on the stored value of AUTOC, 254 * which represents EEPROM defaults. If AUTOC value has not been 255 * stored, use the current register value. 256 */ 257 if (hw->mac.orig_link_settings_stored) 258 autoc = hw->mac.orig_autoc; 259 else 260 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 261 262 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 263 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 264 *speed = IXGBE_LINK_SPEED_1GB_FULL; 265 *negotiation = false; 266 break; 267 268 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 269 *speed = IXGBE_LINK_SPEED_10GB_FULL; 270 *negotiation = false; 271 break; 272 273 case IXGBE_AUTOC_LMS_1G_AN: 274 *speed = IXGBE_LINK_SPEED_1GB_FULL; 275 *negotiation = true; 276 break; 277 278 case IXGBE_AUTOC_LMS_10G_SERIAL: 279 *speed = IXGBE_LINK_SPEED_10GB_FULL; 280 *negotiation = false; 281 break; 282 283 case IXGBE_AUTOC_LMS_KX4_KX_KR: 284 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 285 *speed = IXGBE_LINK_SPEED_UNKNOWN; 286 if (autoc & IXGBE_AUTOC_KR_SUPP) 287 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 288 if (autoc & IXGBE_AUTOC_KX4_SUPP) 289 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 290 if (autoc & IXGBE_AUTOC_KX_SUPP) 291 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 292 *negotiation = true; 293 break; 294 295 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 296 *speed = IXGBE_LINK_SPEED_100_FULL; 297 if (autoc & IXGBE_AUTOC_KR_SUPP) 298 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 299 if (autoc & IXGBE_AUTOC_KX4_SUPP) 300 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 301 if (autoc & IXGBE_AUTOC_KX_SUPP) 302 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 303 *negotiation = true; 304 break; 305 306 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 307 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 308 *negotiation = false; 309 break; 310 311 default: 312 status = IXGBE_ERR_LINK_SETUP; 313 goto out; 314 break; 315 } 316 317 if (hw->phy.multispeed_fiber) { 318 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 319 IXGBE_LINK_SPEED_1GB_FULL; 320 *negotiation = true; 321 } 322 323 out: 324 return status; 325 } 326 327 /** 328 * ixgbe_get_media_type_82599 - Get media type 329 * @hw: pointer to hardware structure 330 * 331 * Returns the media type (fiber, copper, backplane) 332 **/ 333 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 334 { 335 enum ixgbe_media_type media_type; 336 337 /* Detect if there is a copper PHY attached. */ 338 switch (hw->phy.type) { 339 case ixgbe_phy_cu_unknown: 340 case ixgbe_phy_tn: 341 media_type = ixgbe_media_type_copper; 342 goto out; 343 default: 344 break; 345 } 346 347 switch (hw->device_id) { 348 case IXGBE_DEV_ID_82599_KX4: 349 case IXGBE_DEV_ID_82599_KX4_MEZZ: 350 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 351 case IXGBE_DEV_ID_82599_KR: 352 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 353 case IXGBE_DEV_ID_82599_XAUI_LOM: 354 /* Default device ID is mezzanine card KX/KX4 */ 355 media_type = ixgbe_media_type_backplane; 356 break; 357 case IXGBE_DEV_ID_82599_SFP: 358 case IXGBE_DEV_ID_82599_SFP_FCOE: 359 case IXGBE_DEV_ID_82599_SFP_EM: 360 case IXGBE_DEV_ID_82599_SFP_SF2: 361 case IXGBE_DEV_ID_82599_SFP_SF_QP: 362 case IXGBE_DEV_ID_82599EN_SFP: 363 media_type = ixgbe_media_type_fiber; 364 break; 365 case IXGBE_DEV_ID_82599_CX4: 366 media_type = ixgbe_media_type_cx4; 367 break; 368 case IXGBE_DEV_ID_82599_T3_LOM: 369 media_type = ixgbe_media_type_copper; 370 break; 371 case IXGBE_DEV_ID_82599_LS: 372 media_type = ixgbe_media_type_fiber_lco; 373 break; 374 default: 375 media_type = ixgbe_media_type_unknown; 376 break; 377 } 378 out: 379 return media_type; 380 } 381 382 /** 383 * ixgbe_start_mac_link_82599 - Setup MAC link settings 384 * @hw: pointer to hardware structure 385 * @autoneg_wait_to_complete: true when waiting for completion is needed 386 * 387 * Configures link settings based on values in the ixgbe_hw struct. 388 * Restarts the link. Performs autonegotiation if needed. 389 **/ 390 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 391 bool autoneg_wait_to_complete) 392 { 393 u32 autoc_reg; 394 u32 links_reg; 395 u32 i; 396 s32 status = 0; 397 398 /* Restart link */ 399 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 400 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 401 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 402 403 /* Only poll for autoneg to complete if specified to do so */ 404 if (autoneg_wait_to_complete) { 405 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 406 IXGBE_AUTOC_LMS_KX4_KX_KR || 407 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 408 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 409 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 410 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 411 links_reg = 0; /* Just in case Autoneg time = 0 */ 412 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 413 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 414 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 415 break; 416 msleep(100); 417 } 418 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 419 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 420 hw_dbg(hw, "Autoneg did not complete.\n"); 421 } 422 } 423 } 424 425 /* Add delay to filter out noises during initial link setup */ 426 msleep(50); 427 428 return status; 429 } 430 431 /** 432 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 433 * @hw: pointer to hardware structure 434 * 435 * The base drivers may require better control over SFP+ module 436 * PHY states. This includes selectively shutting down the Tx 437 * laser on the PHY, effectively halting physical link. 438 **/ 439 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 440 { 441 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 442 443 /* Disable tx laser; allow 100us to go dark per spec */ 444 esdp_reg |= IXGBE_ESDP_SDP3; 445 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 446 IXGBE_WRITE_FLUSH(hw); 447 udelay(100); 448 } 449 450 /** 451 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 452 * @hw: pointer to hardware structure 453 * 454 * The base drivers may require better control over SFP+ module 455 * PHY states. This includes selectively turning on the Tx 456 * laser on the PHY, effectively starting physical link. 457 **/ 458 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 459 { 460 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 461 462 /* Enable tx laser; allow 100ms to light up */ 463 esdp_reg &= ~IXGBE_ESDP_SDP3; 464 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 465 IXGBE_WRITE_FLUSH(hw); 466 msleep(100); 467 } 468 469 /** 470 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 471 * @hw: pointer to hardware structure 472 * 473 * When the driver changes the link speeds that it can support, 474 * it sets autotry_restart to true to indicate that we need to 475 * initiate a new autotry session with the link partner. To do 476 * so, we set the speed then disable and re-enable the tx laser, to 477 * alert the link partner that it also needs to restart autotry on its 478 * end. This is consistent with true clause 37 autoneg, which also 479 * involves a loss of signal. 480 **/ 481 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 482 { 483 if (hw->mac.autotry_restart) { 484 ixgbe_disable_tx_laser_multispeed_fiber(hw); 485 ixgbe_enable_tx_laser_multispeed_fiber(hw); 486 hw->mac.autotry_restart = false; 487 } 488 } 489 490 /** 491 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 492 * @hw: pointer to hardware structure 493 * @speed: new link speed 494 * @autoneg: true if autonegotiation enabled 495 * @autoneg_wait_to_complete: true when waiting for completion is needed 496 * 497 * Set the link speed in the AUTOC register and restarts link. 498 **/ 499 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 500 ixgbe_link_speed speed, 501 bool autoneg, 502 bool autoneg_wait_to_complete) 503 { 504 s32 status = 0; 505 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 506 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 507 u32 speedcnt = 0; 508 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 509 u32 i = 0; 510 bool link_up = false; 511 bool negotiation; 512 513 /* Mask off requested but non-supported speeds */ 514 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, 515 &negotiation); 516 if (status != 0) 517 return status; 518 519 speed &= link_speed; 520 521 /* 522 * Try each speed one by one, highest priority first. We do this in 523 * software because 10gb fiber doesn't support speed autonegotiation. 524 */ 525 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 526 speedcnt++; 527 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 528 529 /* If we already have link at this speed, just jump out */ 530 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 531 false); 532 if (status != 0) 533 return status; 534 535 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) 536 goto out; 537 538 /* Set the module link speed */ 539 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 540 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 541 IXGBE_WRITE_FLUSH(hw); 542 543 /* Allow module to change analog characteristics (1G->10G) */ 544 msleep(40); 545 546 status = ixgbe_setup_mac_link_82599(hw, 547 IXGBE_LINK_SPEED_10GB_FULL, 548 autoneg, 549 autoneg_wait_to_complete); 550 if (status != 0) 551 return status; 552 553 /* Flap the tx laser if it has not already been done */ 554 hw->mac.ops.flap_tx_laser(hw); 555 556 /* 557 * Wait for the controller to acquire link. Per IEEE 802.3ap, 558 * Section 73.10.2, we may have to wait up to 500ms if KR is 559 * attempted. 82599 uses the same timing for 10g SFI. 560 */ 561 for (i = 0; i < 5; i++) { 562 /* Wait for the link partner to also set speed */ 563 msleep(100); 564 565 /* If we have link, just jump out */ 566 status = hw->mac.ops.check_link(hw, &link_speed, 567 &link_up, false); 568 if (status != 0) 569 return status; 570 571 if (link_up) 572 goto out; 573 } 574 } 575 576 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 577 speedcnt++; 578 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 579 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 580 581 /* If we already have link at this speed, just jump out */ 582 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 583 false); 584 if (status != 0) 585 return status; 586 587 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) 588 goto out; 589 590 /* Set the module link speed */ 591 esdp_reg &= ~IXGBE_ESDP_SDP5; 592 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 593 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 594 IXGBE_WRITE_FLUSH(hw); 595 596 /* Allow module to change analog characteristics (10G->1G) */ 597 msleep(40); 598 599 status = ixgbe_setup_mac_link_82599(hw, 600 IXGBE_LINK_SPEED_1GB_FULL, 601 autoneg, 602 autoneg_wait_to_complete); 603 if (status != 0) 604 return status; 605 606 /* Flap the tx laser if it has not already been done */ 607 hw->mac.ops.flap_tx_laser(hw); 608 609 /* Wait for the link partner to also set speed */ 610 msleep(100); 611 612 /* If we have link, just jump out */ 613 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, 614 false); 615 if (status != 0) 616 return status; 617 618 if (link_up) 619 goto out; 620 } 621 622 /* 623 * We didn't get link. Configure back to the highest speed we tried, 624 * (if there was more than one). We call ourselves back with just the 625 * single highest speed that the user requested. 626 */ 627 if (speedcnt > 1) 628 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 629 highest_link_speed, 630 autoneg, 631 autoneg_wait_to_complete); 632 633 out: 634 /* Set autoneg_advertised value based on input link speed */ 635 hw->phy.autoneg_advertised = 0; 636 637 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 638 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 639 640 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 641 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 642 643 return status; 644 } 645 646 /** 647 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 648 * @hw: pointer to hardware structure 649 * @speed: new link speed 650 * @autoneg: true if autonegotiation enabled 651 * @autoneg_wait_to_complete: true when waiting for completion is needed 652 * 653 * Implements the Intel SmartSpeed algorithm. 654 **/ 655 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 656 ixgbe_link_speed speed, bool autoneg, 657 bool autoneg_wait_to_complete) 658 { 659 s32 status = 0; 660 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 661 s32 i, j; 662 bool link_up = false; 663 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 664 665 /* Set autoneg_advertised value based on input link speed */ 666 hw->phy.autoneg_advertised = 0; 667 668 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 669 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 670 671 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 672 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 673 674 if (speed & IXGBE_LINK_SPEED_100_FULL) 675 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 676 677 /* 678 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 679 * autoneg advertisement if link is unable to be established at the 680 * highest negotiated rate. This can sometimes happen due to integrity 681 * issues with the physical media connection. 682 */ 683 684 /* First, try to get link with full advertisement */ 685 hw->phy.smart_speed_active = false; 686 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 687 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 688 autoneg_wait_to_complete); 689 if (status != 0) 690 goto out; 691 692 /* 693 * Wait for the controller to acquire link. Per IEEE 802.3ap, 694 * Section 73.10.2, we may have to wait up to 500ms if KR is 695 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 696 * Table 9 in the AN MAS. 697 */ 698 for (i = 0; i < 5; i++) { 699 mdelay(100); 700 701 /* If we have link, just jump out */ 702 status = hw->mac.ops.check_link(hw, &link_speed, 703 &link_up, false); 704 if (status != 0) 705 goto out; 706 707 if (link_up) 708 goto out; 709 } 710 } 711 712 /* 713 * We didn't get link. If we advertised KR plus one of KX4/KX 714 * (or BX4/BX), then disable KR and try again. 715 */ 716 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 717 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 718 goto out; 719 720 /* Turn SmartSpeed on to disable KR support */ 721 hw->phy.smart_speed_active = true; 722 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 723 autoneg_wait_to_complete); 724 if (status != 0) 725 goto out; 726 727 /* 728 * Wait for the controller to acquire link. 600ms will allow for 729 * the AN link_fail_inhibit_timer as well for multiple cycles of 730 * parallel detect, both 10g and 1g. This allows for the maximum 731 * connect attempts as defined in the AN MAS table 73-7. 732 */ 733 for (i = 0; i < 6; i++) { 734 mdelay(100); 735 736 /* If we have link, just jump out */ 737 status = hw->mac.ops.check_link(hw, &link_speed, 738 &link_up, false); 739 if (status != 0) 740 goto out; 741 742 if (link_up) 743 goto out; 744 } 745 746 /* We didn't get link. Turn SmartSpeed back off. */ 747 hw->phy.smart_speed_active = false; 748 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, 749 autoneg_wait_to_complete); 750 751 out: 752 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 753 hw_dbg(hw, "Smartspeed has downgraded the link speed from " 754 "the maximum advertised\n"); 755 return status; 756 } 757 758 /** 759 * ixgbe_setup_mac_link_82599 - Set MAC link speed 760 * @hw: pointer to hardware structure 761 * @speed: new link speed 762 * @autoneg: true if autonegotiation enabled 763 * @autoneg_wait_to_complete: true when waiting for completion is needed 764 * 765 * Set the link speed in the AUTOC register and restarts link. 766 **/ 767 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 768 ixgbe_link_speed speed, bool autoneg, 769 bool autoneg_wait_to_complete) 770 { 771 s32 status = 0; 772 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 773 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 774 u32 start_autoc = autoc; 775 u32 orig_autoc = 0; 776 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 777 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 778 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 779 u32 links_reg; 780 u32 i; 781 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 782 783 /* Check to see if speed passed in is supported. */ 784 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities, 785 &autoneg); 786 if (status != 0) 787 goto out; 788 789 speed &= link_capabilities; 790 791 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 792 status = IXGBE_ERR_LINK_SETUP; 793 goto out; 794 } 795 796 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 797 if (hw->mac.orig_link_settings_stored) 798 orig_autoc = hw->mac.orig_autoc; 799 else 800 orig_autoc = autoc; 801 802 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 803 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 804 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 805 /* Set KX4/KX/KR support according to speed requested */ 806 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 807 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 808 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 809 autoc |= IXGBE_AUTOC_KX4_SUPP; 810 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 811 (hw->phy.smart_speed_active == false)) 812 autoc |= IXGBE_AUTOC_KR_SUPP; 813 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 814 autoc |= IXGBE_AUTOC_KX_SUPP; 815 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 816 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 817 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 818 /* Switch from 1G SFI to 10G SFI if requested */ 819 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 820 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 821 autoc &= ~IXGBE_AUTOC_LMS_MASK; 822 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 823 } 824 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 825 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 826 /* Switch from 10G SFI to 1G SFI if requested */ 827 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 828 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 829 autoc &= ~IXGBE_AUTOC_LMS_MASK; 830 if (autoneg) 831 autoc |= IXGBE_AUTOC_LMS_1G_AN; 832 else 833 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 834 } 835 } 836 837 if (autoc != start_autoc) { 838 /* Restart link */ 839 autoc |= IXGBE_AUTOC_AN_RESTART; 840 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 841 842 /* Only poll for autoneg to complete if specified to do so */ 843 if (autoneg_wait_to_complete) { 844 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 845 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 846 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 847 links_reg = 0; /*Just in case Autoneg time=0*/ 848 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 849 links_reg = 850 IXGBE_READ_REG(hw, IXGBE_LINKS); 851 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 852 break; 853 msleep(100); 854 } 855 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 856 status = 857 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 858 hw_dbg(hw, "Autoneg did not " 859 "complete.\n"); 860 } 861 } 862 } 863 864 /* Add delay to filter out noises during initial link setup */ 865 msleep(50); 866 } 867 868 out: 869 return status; 870 } 871 872 /** 873 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 874 * @hw: pointer to hardware structure 875 * @speed: new link speed 876 * @autoneg: true if autonegotiation enabled 877 * @autoneg_wait_to_complete: true if waiting is needed to complete 878 * 879 * Restarts link on PHY and MAC based on settings passed in. 880 **/ 881 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 882 ixgbe_link_speed speed, 883 bool autoneg, 884 bool autoneg_wait_to_complete) 885 { 886 s32 status; 887 888 /* Setup the PHY according to input speed */ 889 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 890 autoneg_wait_to_complete); 891 /* Set up MAC */ 892 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 893 894 return status; 895 } 896 897 /** 898 * ixgbe_reset_hw_82599 - Perform hardware reset 899 * @hw: pointer to hardware structure 900 * 901 * Resets the hardware by resetting the transmit and receive units, masks 902 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 903 * reset. 904 **/ 905 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 906 { 907 ixgbe_link_speed link_speed; 908 s32 status; 909 u32 ctrl, i, autoc, autoc2; 910 bool link_up = false; 911 912 /* Call adapter stop to disable tx/rx and clear interrupts */ 913 status = hw->mac.ops.stop_adapter(hw); 914 if (status != 0) 915 goto reset_hw_out; 916 917 /* flush pending Tx transactions */ 918 ixgbe_clear_tx_pending(hw); 919 920 /* PHY ops must be identified and initialized prior to reset */ 921 922 /* Identify PHY and related function pointers */ 923 status = hw->phy.ops.init(hw); 924 925 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 926 goto reset_hw_out; 927 928 /* Setup SFP module if there is one present. */ 929 if (hw->phy.sfp_setup_needed) { 930 status = hw->mac.ops.setup_sfp(hw); 931 hw->phy.sfp_setup_needed = false; 932 } 933 934 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 935 goto reset_hw_out; 936 937 /* Reset PHY */ 938 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) 939 hw->phy.ops.reset(hw); 940 941 mac_reset_top: 942 /* 943 * Issue global reset to the MAC. Needs to be SW reset if link is up. 944 * If link reset is used when link is up, it might reset the PHY when 945 * mng is using it. If link is down or the flag to force full link 946 * reset is set, then perform link reset. 947 */ 948 ctrl = IXGBE_CTRL_LNK_RST; 949 if (!hw->force_full_reset) { 950 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 951 if (link_up) 952 ctrl = IXGBE_CTRL_RST; 953 } 954 955 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 956 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 957 IXGBE_WRITE_FLUSH(hw); 958 959 /* Poll for reset bit to self-clear indicating reset is complete */ 960 for (i = 0; i < 10; i++) { 961 udelay(1); 962 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 963 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 964 break; 965 } 966 967 if (ctrl & IXGBE_CTRL_RST_MASK) { 968 status = IXGBE_ERR_RESET_FAILED; 969 hw_dbg(hw, "Reset polling failed to complete.\n"); 970 } 971 972 msleep(50); 973 974 /* 975 * Double resets are required for recovery from certain error 976 * conditions. Between resets, it is necessary to stall to allow time 977 * for any pending HW events to complete. 978 */ 979 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 980 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 981 goto mac_reset_top; 982 } 983 984 /* 985 * Store the original AUTOC/AUTOC2 values if they have not been 986 * stored off yet. Otherwise restore the stored original 987 * values since the reset operation sets back to defaults. 988 */ 989 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 990 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 991 if (hw->mac.orig_link_settings_stored == false) { 992 hw->mac.orig_autoc = autoc; 993 hw->mac.orig_autoc2 = autoc2; 994 hw->mac.orig_link_settings_stored = true; 995 } else { 996 if (autoc != hw->mac.orig_autoc) 997 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc | 998 IXGBE_AUTOC_AN_RESTART)); 999 1000 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1001 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1002 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1003 autoc2 |= (hw->mac.orig_autoc2 & 1004 IXGBE_AUTOC2_UPPER_MASK); 1005 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1006 } 1007 } 1008 1009 /* Store the permanent mac address */ 1010 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1011 1012 /* 1013 * Store MAC address from RAR0, clear receive address registers, and 1014 * clear the multicast table. Also reset num_rar_entries to 128, 1015 * since we modify this value when programming the SAN MAC address. 1016 */ 1017 hw->mac.num_rar_entries = 128; 1018 hw->mac.ops.init_rx_addrs(hw); 1019 1020 /* Store the permanent SAN mac address */ 1021 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1022 1023 /* Add the SAN MAC address to the RAR only if it's a valid address */ 1024 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 1025 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 1026 hw->mac.san_addr, 0, IXGBE_RAH_AV); 1027 1028 /* Save the SAN MAC RAR index */ 1029 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 1030 1031 /* Reserve the last RAR for the SAN MAC address */ 1032 hw->mac.num_rar_entries--; 1033 } 1034 1035 /* Store the alternative WWNN/WWPN prefix */ 1036 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 1037 &hw->mac.wwpn_prefix); 1038 1039 reset_hw_out: 1040 return status; 1041 } 1042 1043 /** 1044 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 1045 * @hw: pointer to hardware structure 1046 **/ 1047 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 1048 { 1049 int i; 1050 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1051 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; 1052 1053 /* 1054 * Before starting reinitialization process, 1055 * FDIRCMD.CMD must be zero. 1056 */ 1057 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 1058 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1059 IXGBE_FDIRCMD_CMD_MASK)) 1060 break; 1061 udelay(10); 1062 } 1063 if (i >= IXGBE_FDIRCMD_CMD_POLL) { 1064 hw_dbg(hw, "Flow Director previous command isn't complete, " 1065 "aborting table re-initialization.\n"); 1066 return IXGBE_ERR_FDIR_REINIT_FAILED; 1067 } 1068 1069 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); 1070 IXGBE_WRITE_FLUSH(hw); 1071 /* 1072 * 82599 adapters flow director init flow cannot be restarted, 1073 * Workaround 82599 silicon errata by performing the following steps 1074 * before re-writing the FDIRCTRL control register with the same value. 1075 * - write 1 to bit 8 of FDIRCMD register & 1076 * - write 0 to bit 8 of FDIRCMD register 1077 */ 1078 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1079 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1080 IXGBE_FDIRCMD_CLEARHT)); 1081 IXGBE_WRITE_FLUSH(hw); 1082 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1083 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1084 ~IXGBE_FDIRCMD_CLEARHT)); 1085 IXGBE_WRITE_FLUSH(hw); 1086 /* 1087 * Clear FDIR Hash register to clear any leftover hashes 1088 * waiting to be programmed. 1089 */ 1090 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); 1091 IXGBE_WRITE_FLUSH(hw); 1092 1093 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1094 IXGBE_WRITE_FLUSH(hw); 1095 1096 /* Poll init-done after we write FDIRCTRL register */ 1097 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1098 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1099 IXGBE_FDIRCTRL_INIT_DONE) 1100 break; 1101 udelay(10); 1102 } 1103 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1104 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); 1105 return IXGBE_ERR_FDIR_REINIT_FAILED; 1106 } 1107 1108 /* Clear FDIR statistics registers (read to clear) */ 1109 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1110 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); 1111 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 1112 IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 1113 IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1114 1115 return 0; 1116 } 1117 1118 /** 1119 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers 1120 * @hw: pointer to hardware structure 1121 * @fdirctrl: value to write to flow director control register 1122 **/ 1123 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1124 { 1125 int i; 1126 1127 /* Prime the keys for hashing */ 1128 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1129 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 1130 1131 /* 1132 * Poll init-done after we write the register. Estimated times: 1133 * 10G: PBALLOC = 11b, timing is 60us 1134 * 1G: PBALLOC = 11b, timing is 600us 1135 * 100M: PBALLOC = 11b, timing is 6ms 1136 * 1137 * Multiple these timings by 4 if under full Rx load 1138 * 1139 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1140 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1141 * this might not finish in our poll time, but we can live with that 1142 * for now. 1143 */ 1144 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1145 IXGBE_WRITE_FLUSH(hw); 1146 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1147 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1148 IXGBE_FDIRCTRL_INIT_DONE) 1149 break; 1150 usleep_range(1000, 2000); 1151 } 1152 1153 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1154 hw_dbg(hw, "Flow Director poll time exceeded!\n"); 1155 } 1156 1157 /** 1158 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1159 * @hw: pointer to hardware structure 1160 * @fdirctrl: value to write to flow director control register, initially 1161 * contains just the value of the Rx packet buffer allocation 1162 **/ 1163 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1164 { 1165 /* 1166 * Continue setup of fdirctrl register bits: 1167 * Move the flexible bytes to use the ethertype - shift 6 words 1168 * Set the maximum length per hash bucket to 0xA filters 1169 * Send interrupt when 64 filters are left 1170 */ 1171 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1172 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1173 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1174 1175 /* write hashes and fdirctrl register, poll for completion */ 1176 ixgbe_fdir_enable_82599(hw, fdirctrl); 1177 1178 return 0; 1179 } 1180 1181 /** 1182 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1183 * @hw: pointer to hardware structure 1184 * @fdirctrl: value to write to flow director control register, initially 1185 * contains just the value of the Rx packet buffer allocation 1186 **/ 1187 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1188 { 1189 /* 1190 * Continue setup of fdirctrl register bits: 1191 * Turn perfect match filtering on 1192 * Report hash in RSS field of Rx wb descriptor 1193 * Initialize the drop queue 1194 * Move the flexible bytes to use the ethertype - shift 6 words 1195 * Set the maximum length per hash bucket to 0xA filters 1196 * Send interrupt when 64 (0x4 * 16) filters are left 1197 */ 1198 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH | 1199 IXGBE_FDIRCTRL_REPORT_STATUS | 1200 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) | 1201 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1202 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1203 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1204 1205 /* write hashes and fdirctrl register, poll for completion */ 1206 ixgbe_fdir_enable_82599(hw, fdirctrl); 1207 1208 return 0; 1209 } 1210 1211 /* 1212 * These defines allow us to quickly generate all of the necessary instructions 1213 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION 1214 * for values 0 through 15 1215 */ 1216 #define IXGBE_ATR_COMMON_HASH_KEY \ 1217 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) 1218 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ 1219 do { \ 1220 u32 n = (_n); \ 1221 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \ 1222 common_hash ^= lo_hash_dword >> n; \ 1223 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1224 bucket_hash ^= lo_hash_dword >> n; \ 1225 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \ 1226 sig_hash ^= lo_hash_dword << (16 - n); \ 1227 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \ 1228 common_hash ^= hi_hash_dword >> n; \ 1229 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1230 bucket_hash ^= hi_hash_dword >> n; \ 1231 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \ 1232 sig_hash ^= hi_hash_dword << (16 - n); \ 1233 } while (0); 1234 1235 /** 1236 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash 1237 * @stream: input bitstream to compute the hash on 1238 * 1239 * This function is almost identical to the function above but contains 1240 * several optomizations such as unwinding all of the loops, letting the 1241 * compiler work out all of the conditional ifs since the keys are static 1242 * defines, and computing two keys at once since the hashed dword stream 1243 * will be the same for both keys. 1244 **/ 1245 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 1246 union ixgbe_atr_hash_dword common) 1247 { 1248 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1249 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0; 1250 1251 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1252 flow_vm_vlan = ntohl(input.dword); 1253 1254 /* generate common hash dword */ 1255 hi_hash_dword = ntohl(common.dword); 1256 1257 /* low dword is word swapped version of common */ 1258 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1259 1260 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1261 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1262 1263 /* Process bits 0 and 16 */ 1264 IXGBE_COMPUTE_SIG_HASH_ITERATION(0); 1265 1266 /* 1267 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1268 * delay this because bit 0 of the stream should not be processed 1269 * so we do not add the vlan until after bit 0 was processed 1270 */ 1271 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1272 1273 /* Process remaining 30 bit of the key */ 1274 IXGBE_COMPUTE_SIG_HASH_ITERATION(1); 1275 IXGBE_COMPUTE_SIG_HASH_ITERATION(2); 1276 IXGBE_COMPUTE_SIG_HASH_ITERATION(3); 1277 IXGBE_COMPUTE_SIG_HASH_ITERATION(4); 1278 IXGBE_COMPUTE_SIG_HASH_ITERATION(5); 1279 IXGBE_COMPUTE_SIG_HASH_ITERATION(6); 1280 IXGBE_COMPUTE_SIG_HASH_ITERATION(7); 1281 IXGBE_COMPUTE_SIG_HASH_ITERATION(8); 1282 IXGBE_COMPUTE_SIG_HASH_ITERATION(9); 1283 IXGBE_COMPUTE_SIG_HASH_ITERATION(10); 1284 IXGBE_COMPUTE_SIG_HASH_ITERATION(11); 1285 IXGBE_COMPUTE_SIG_HASH_ITERATION(12); 1286 IXGBE_COMPUTE_SIG_HASH_ITERATION(13); 1287 IXGBE_COMPUTE_SIG_HASH_ITERATION(14); 1288 IXGBE_COMPUTE_SIG_HASH_ITERATION(15); 1289 1290 /* combine common_hash result with signature and bucket hashes */ 1291 bucket_hash ^= common_hash; 1292 bucket_hash &= IXGBE_ATR_HASH_MASK; 1293 1294 sig_hash ^= common_hash << 16; 1295 sig_hash &= IXGBE_ATR_HASH_MASK << 16; 1296 1297 /* return completed signature hash */ 1298 return sig_hash ^ bucket_hash; 1299 } 1300 1301 /** 1302 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter 1303 * @hw: pointer to hardware structure 1304 * @input: unique input dword 1305 * @common: compressed common input dword 1306 * @queue: queue index to direct traffic to 1307 **/ 1308 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1309 union ixgbe_atr_hash_dword input, 1310 union ixgbe_atr_hash_dword common, 1311 u8 queue) 1312 { 1313 u64 fdirhashcmd; 1314 u32 fdircmd; 1315 1316 /* 1317 * Get the flow_type in order to program FDIRCMD properly 1318 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 1319 */ 1320 switch (input.formatted.flow_type) { 1321 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1322 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1323 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1324 case IXGBE_ATR_FLOW_TYPE_TCPV6: 1325 case IXGBE_ATR_FLOW_TYPE_UDPV6: 1326 case IXGBE_ATR_FLOW_TYPE_SCTPV6: 1327 break; 1328 default: 1329 hw_dbg(hw, " Error on flow type input\n"); 1330 return IXGBE_ERR_CONFIG; 1331 } 1332 1333 /* configure FDIRCMD register */ 1334 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1335 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1336 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1337 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1338 1339 /* 1340 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 1341 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 1342 */ 1343 fdirhashcmd = (u64)fdircmd << 32; 1344 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common); 1345 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1346 1347 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); 1348 1349 return 0; 1350 } 1351 1352 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \ 1353 do { \ 1354 u32 n = (_n); \ 1355 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \ 1356 bucket_hash ^= lo_hash_dword >> n; \ 1357 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \ 1358 bucket_hash ^= hi_hash_dword >> n; \ 1359 } while (0); 1360 1361 /** 1362 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash 1363 * @atr_input: input bitstream to compute the hash on 1364 * @input_mask: mask for the input bitstream 1365 * 1366 * This function serves two main purposes. First it applys the input_mask 1367 * to the atr_input resulting in a cleaned up atr_input data stream. 1368 * Secondly it computes the hash and stores it in the bkt_hash field at 1369 * the end of the input byte stream. This way it will be available for 1370 * future use without needing to recompute the hash. 1371 **/ 1372 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 1373 union ixgbe_atr_input *input_mask) 1374 { 1375 1376 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1377 u32 bucket_hash = 0; 1378 1379 /* Apply masks to input data */ 1380 input->dword_stream[0] &= input_mask->dword_stream[0]; 1381 input->dword_stream[1] &= input_mask->dword_stream[1]; 1382 input->dword_stream[2] &= input_mask->dword_stream[2]; 1383 input->dword_stream[3] &= input_mask->dword_stream[3]; 1384 input->dword_stream[4] &= input_mask->dword_stream[4]; 1385 input->dword_stream[5] &= input_mask->dword_stream[5]; 1386 input->dword_stream[6] &= input_mask->dword_stream[6]; 1387 input->dword_stream[7] &= input_mask->dword_stream[7]; 1388 input->dword_stream[8] &= input_mask->dword_stream[8]; 1389 input->dword_stream[9] &= input_mask->dword_stream[9]; 1390 input->dword_stream[10] &= input_mask->dword_stream[10]; 1391 1392 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1393 flow_vm_vlan = ntohl(input->dword_stream[0]); 1394 1395 /* generate common hash dword */ 1396 hi_hash_dword = ntohl(input->dword_stream[1] ^ 1397 input->dword_stream[2] ^ 1398 input->dword_stream[3] ^ 1399 input->dword_stream[4] ^ 1400 input->dword_stream[5] ^ 1401 input->dword_stream[6] ^ 1402 input->dword_stream[7] ^ 1403 input->dword_stream[8] ^ 1404 input->dword_stream[9] ^ 1405 input->dword_stream[10]); 1406 1407 /* low dword is word swapped version of common */ 1408 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1409 1410 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1411 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1412 1413 /* Process bits 0 and 16 */ 1414 IXGBE_COMPUTE_BKT_HASH_ITERATION(0); 1415 1416 /* 1417 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1418 * delay this because bit 0 of the stream should not be processed 1419 * so we do not add the vlan until after bit 0 was processed 1420 */ 1421 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1422 1423 /* Process remaining 30 bit of the key */ 1424 IXGBE_COMPUTE_BKT_HASH_ITERATION(1); 1425 IXGBE_COMPUTE_BKT_HASH_ITERATION(2); 1426 IXGBE_COMPUTE_BKT_HASH_ITERATION(3); 1427 IXGBE_COMPUTE_BKT_HASH_ITERATION(4); 1428 IXGBE_COMPUTE_BKT_HASH_ITERATION(5); 1429 IXGBE_COMPUTE_BKT_HASH_ITERATION(6); 1430 IXGBE_COMPUTE_BKT_HASH_ITERATION(7); 1431 IXGBE_COMPUTE_BKT_HASH_ITERATION(8); 1432 IXGBE_COMPUTE_BKT_HASH_ITERATION(9); 1433 IXGBE_COMPUTE_BKT_HASH_ITERATION(10); 1434 IXGBE_COMPUTE_BKT_HASH_ITERATION(11); 1435 IXGBE_COMPUTE_BKT_HASH_ITERATION(12); 1436 IXGBE_COMPUTE_BKT_HASH_ITERATION(13); 1437 IXGBE_COMPUTE_BKT_HASH_ITERATION(14); 1438 IXGBE_COMPUTE_BKT_HASH_ITERATION(15); 1439 1440 /* 1441 * Limit hash to 13 bits since max bucket count is 8K. 1442 * Store result at the end of the input stream. 1443 */ 1444 input->formatted.bkt_hash = bucket_hash & 0x1FFF; 1445 } 1446 1447 /** 1448 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks 1449 * @input_mask: mask to be bit swapped 1450 * 1451 * The source and destination port masks for flow director are bit swapped 1452 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to 1453 * generate a correctly swapped value we need to bit swap the mask and that 1454 * is what is accomplished by this function. 1455 **/ 1456 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask) 1457 { 1458 u32 mask = ntohs(input_mask->formatted.dst_port); 1459 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; 1460 mask |= ntohs(input_mask->formatted.src_port); 1461 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); 1462 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); 1463 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); 1464 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); 1465 } 1466 1467 /* 1468 * These two macros are meant to address the fact that we have registers 1469 * that are either all or in part big-endian. As a result on big-endian 1470 * systems we will end up byte swapping the value to little-endian before 1471 * it is byte swapped again and written to the hardware in the original 1472 * big-endian format. 1473 */ 1474 #define IXGBE_STORE_AS_BE32(_value) \ 1475 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \ 1476 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24)) 1477 1478 #define IXGBE_WRITE_REG_BE32(a, reg, value) \ 1479 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value))) 1480 1481 #define IXGBE_STORE_AS_BE16(_value) \ 1482 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8)) 1483 1484 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 1485 union ixgbe_atr_input *input_mask) 1486 { 1487 /* mask IPv6 since it is currently not supported */ 1488 u32 fdirm = IXGBE_FDIRM_DIPv6; 1489 u32 fdirtcpm; 1490 1491 /* 1492 * Program the relevant mask registers. If src/dst_port or src/dst_addr 1493 * are zero, then assume a full mask for that field. Also assume that 1494 * a VLAN of 0 is unspecified, so mask that out as well. L4type 1495 * cannot be masked out in this implementation. 1496 * 1497 * This also assumes IPv4 only. IPv6 masking isn't supported at this 1498 * point in time. 1499 */ 1500 1501 /* verify bucket hash is cleared on hash generation */ 1502 if (input_mask->formatted.bkt_hash) 1503 hw_dbg(hw, " bucket hash should always be 0 in mask\n"); 1504 1505 /* Program FDIRM and verify partial masks */ 1506 switch (input_mask->formatted.vm_pool & 0x7F) { 1507 case 0x0: 1508 fdirm |= IXGBE_FDIRM_POOL; 1509 case 0x7F: 1510 break; 1511 default: 1512 hw_dbg(hw, " Error on vm pool mask\n"); 1513 return IXGBE_ERR_CONFIG; 1514 } 1515 1516 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) { 1517 case 0x0: 1518 fdirm |= IXGBE_FDIRM_L4P; 1519 if (input_mask->formatted.dst_port || 1520 input_mask->formatted.src_port) { 1521 hw_dbg(hw, " Error on src/dst port mask\n"); 1522 return IXGBE_ERR_CONFIG; 1523 } 1524 case IXGBE_ATR_L4TYPE_MASK: 1525 break; 1526 default: 1527 hw_dbg(hw, " Error on flow type mask\n"); 1528 return IXGBE_ERR_CONFIG; 1529 } 1530 1531 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) { 1532 case 0x0000: 1533 /* mask VLAN ID, fall through to mask VLAN priority */ 1534 fdirm |= IXGBE_FDIRM_VLANID; 1535 case 0x0FFF: 1536 /* mask VLAN priority */ 1537 fdirm |= IXGBE_FDIRM_VLANP; 1538 break; 1539 case 0xE000: 1540 /* mask VLAN ID only, fall through */ 1541 fdirm |= IXGBE_FDIRM_VLANID; 1542 case 0xEFFF: 1543 /* no VLAN fields masked */ 1544 break; 1545 default: 1546 hw_dbg(hw, " Error on VLAN mask\n"); 1547 return IXGBE_ERR_CONFIG; 1548 } 1549 1550 switch (input_mask->formatted.flex_bytes & 0xFFFF) { 1551 case 0x0000: 1552 /* Mask Flex Bytes, fall through */ 1553 fdirm |= IXGBE_FDIRM_FLEX; 1554 case 0xFFFF: 1555 break; 1556 default: 1557 hw_dbg(hw, " Error on flexible byte mask\n"); 1558 return IXGBE_ERR_CONFIG; 1559 } 1560 1561 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ 1562 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 1563 1564 /* store the TCP/UDP port masks, bit reversed from port layout */ 1565 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask); 1566 1567 /* write both the same so that UDP and TCP use the same mask */ 1568 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); 1569 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); 1570 1571 /* store source and destination IP masks (big-enian) */ 1572 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 1573 ~input_mask->formatted.src_ip[0]); 1574 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 1575 ~input_mask->formatted.dst_ip[0]); 1576 1577 return 0; 1578 } 1579 1580 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 1581 union ixgbe_atr_input *input, 1582 u16 soft_id, u8 queue) 1583 { 1584 u32 fdirport, fdirvlan, fdirhash, fdircmd; 1585 1586 /* currently IPv6 is not supported, must be programmed with 0 */ 1587 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), 1588 input->formatted.src_ip[0]); 1589 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), 1590 input->formatted.src_ip[1]); 1591 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), 1592 input->formatted.src_ip[2]); 1593 1594 /* record the source address (big-endian) */ 1595 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); 1596 1597 /* record the first 32 bits of the destination address (big-endian) */ 1598 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); 1599 1600 /* record source and destination port (little-endian)*/ 1601 fdirport = ntohs(input->formatted.dst_port); 1602 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; 1603 fdirport |= ntohs(input->formatted.src_port); 1604 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); 1605 1606 /* record vlan (little-endian) and flex_bytes(big-endian) */ 1607 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); 1608 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; 1609 fdirvlan |= ntohs(input->formatted.vlan_id); 1610 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); 1611 1612 /* configure FDIRHASH register */ 1613 fdirhash = input->formatted.bkt_hash; 1614 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1615 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1616 1617 /* 1618 * flush all previous writes to make certain registers are 1619 * programmed prior to issuing the command 1620 */ 1621 IXGBE_WRITE_FLUSH(hw); 1622 1623 /* configure FDIRCMD register */ 1624 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1625 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1626 if (queue == IXGBE_FDIR_DROP_QUEUE) 1627 fdircmd |= IXGBE_FDIRCMD_DROP; 1628 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1629 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1630 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; 1631 1632 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1633 1634 return 0; 1635 } 1636 1637 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 1638 union ixgbe_atr_input *input, 1639 u16 soft_id) 1640 { 1641 u32 fdirhash; 1642 u32 fdircmd = 0; 1643 u32 retry_count; 1644 s32 err = 0; 1645 1646 /* configure FDIRHASH register */ 1647 fdirhash = input->formatted.bkt_hash; 1648 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1649 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1650 1651 /* flush hash to HW */ 1652 IXGBE_WRITE_FLUSH(hw); 1653 1654 /* Query if filter is present */ 1655 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); 1656 1657 for (retry_count = 10; retry_count; retry_count--) { 1658 /* allow 10us for query to process */ 1659 udelay(10); 1660 /* verify query completed successfully */ 1661 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); 1662 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK)) 1663 break; 1664 } 1665 1666 if (!retry_count) 1667 err = IXGBE_ERR_FDIR_REINIT_FAILED; 1668 1669 /* if filter exists in hardware then remove it */ 1670 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) { 1671 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1672 IXGBE_WRITE_FLUSH(hw); 1673 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1674 IXGBE_FDIRCMD_CMD_REMOVE_FLOW); 1675 } 1676 1677 return err; 1678 } 1679 1680 /** 1681 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 1682 * @hw: pointer to hardware structure 1683 * @reg: analog register to read 1684 * @val: read value 1685 * 1686 * Performs read operation to Omer analog register specified. 1687 **/ 1688 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 1689 { 1690 u32 core_ctl; 1691 1692 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 1693 (reg << 8)); 1694 IXGBE_WRITE_FLUSH(hw); 1695 udelay(10); 1696 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 1697 *val = (u8)core_ctl; 1698 1699 return 0; 1700 } 1701 1702 /** 1703 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 1704 * @hw: pointer to hardware structure 1705 * @reg: atlas register to write 1706 * @val: value to write 1707 * 1708 * Performs write operation to Omer analog register specified. 1709 **/ 1710 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 1711 { 1712 u32 core_ctl; 1713 1714 core_ctl = (reg << 8) | val; 1715 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 1716 IXGBE_WRITE_FLUSH(hw); 1717 udelay(10); 1718 1719 return 0; 1720 } 1721 1722 /** 1723 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx 1724 * @hw: pointer to hardware structure 1725 * 1726 * Starts the hardware using the generic start_hw function 1727 * and the generation start_hw function. 1728 * Then performs revision-specific operations, if any. 1729 **/ 1730 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) 1731 { 1732 s32 ret_val = 0; 1733 1734 ret_val = ixgbe_start_hw_generic(hw); 1735 if (ret_val != 0) 1736 goto out; 1737 1738 ret_val = ixgbe_start_hw_gen2(hw); 1739 if (ret_val != 0) 1740 goto out; 1741 1742 /* We need to run link autotry after the driver loads */ 1743 hw->mac.autotry_restart = true; 1744 hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE; 1745 1746 if (ret_val == 0) 1747 ret_val = ixgbe_verify_fw_version_82599(hw); 1748 out: 1749 return ret_val; 1750 } 1751 1752 /** 1753 * ixgbe_identify_phy_82599 - Get physical layer module 1754 * @hw: pointer to hardware structure 1755 * 1756 * Determines the physical layer module found on the current adapter. 1757 * If PHY already detected, maintains current PHY type in hw struct, 1758 * otherwise executes the PHY detection routine. 1759 **/ 1760 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 1761 { 1762 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1763 1764 /* Detect PHY if not unknown - returns success if already detected. */ 1765 status = ixgbe_identify_phy_generic(hw); 1766 if (status != 0) { 1767 /* 82599 10GBASE-T requires an external PHY */ 1768 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 1769 goto out; 1770 else 1771 status = ixgbe_identify_sfp_module_generic(hw); 1772 } 1773 1774 /* Set PHY type none if no PHY detected */ 1775 if (hw->phy.type == ixgbe_phy_unknown) { 1776 hw->phy.type = ixgbe_phy_none; 1777 status = 0; 1778 } 1779 1780 /* Return error if SFP module has been detected but is not supported */ 1781 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1782 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1783 1784 out: 1785 return status; 1786 } 1787 1788 /** 1789 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type 1790 * @hw: pointer to hardware structure 1791 * 1792 * Determines physical layer capabilities of the current configuration. 1793 **/ 1794 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) 1795 { 1796 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1797 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1798 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1799 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 1800 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1801 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1802 u16 ext_ability = 0; 1803 u8 comp_codes_10g = 0; 1804 u8 comp_codes_1g = 0; 1805 1806 hw->phy.ops.identify(hw); 1807 1808 switch (hw->phy.type) { 1809 case ixgbe_phy_tn: 1810 case ixgbe_phy_cu_unknown: 1811 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, 1812 &ext_ability); 1813 if (ext_ability & MDIO_PMA_EXTABLE_10GBT) 1814 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1815 if (ext_ability & MDIO_PMA_EXTABLE_1000BT) 1816 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1817 if (ext_ability & MDIO_PMA_EXTABLE_100BTX) 1818 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1819 goto out; 1820 default: 1821 break; 1822 } 1823 1824 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1825 case IXGBE_AUTOC_LMS_1G_AN: 1826 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1827 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { 1828 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | 1829 IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1830 goto out; 1831 } else 1832 /* SFI mode so read SFP module */ 1833 goto sfp_check; 1834 break; 1835 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1836 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) 1837 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1838 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) 1839 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1840 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) 1841 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; 1842 goto out; 1843 break; 1844 case IXGBE_AUTOC_LMS_10G_SERIAL: 1845 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { 1846 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1847 goto out; 1848 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) 1849 goto sfp_check; 1850 break; 1851 case IXGBE_AUTOC_LMS_KX4_KX_KR: 1852 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 1853 if (autoc & IXGBE_AUTOC_KX_SUPP) 1854 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1855 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1856 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1857 if (autoc & IXGBE_AUTOC_KR_SUPP) 1858 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1859 goto out; 1860 break; 1861 default: 1862 goto out; 1863 break; 1864 } 1865 1866 sfp_check: 1867 /* SFP check must be done last since DA modules are sometimes used to 1868 * test KR mode - we need to id KR mode correctly before SFP module. 1869 * Call identify_sfp because the pluggable module may have changed */ 1870 hw->phy.ops.identify_sfp(hw); 1871 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1872 goto out; 1873 1874 switch (hw->phy.type) { 1875 case ixgbe_phy_sfp_passive_tyco: 1876 case ixgbe_phy_sfp_passive_unknown: 1877 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1878 break; 1879 case ixgbe_phy_sfp_ftl_active: 1880 case ixgbe_phy_sfp_active_unknown: 1881 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1882 break; 1883 case ixgbe_phy_sfp_avago: 1884 case ixgbe_phy_sfp_ftl: 1885 case ixgbe_phy_sfp_intel: 1886 case ixgbe_phy_sfp_unknown: 1887 hw->phy.ops.read_i2c_eeprom(hw, 1888 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1889 hw->phy.ops.read_i2c_eeprom(hw, 1890 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1891 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1892 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1893 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1894 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1895 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1896 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1897 break; 1898 default: 1899 break; 1900 } 1901 1902 out: 1903 return physical_layer; 1904 } 1905 1906 /** 1907 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 1908 * @hw: pointer to hardware structure 1909 * @regval: register value to write to RXCTRL 1910 * 1911 * Enables the Rx DMA unit for 82599 1912 **/ 1913 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 1914 { 1915 /* 1916 * Workaround for 82599 silicon errata when enabling the Rx datapath. 1917 * If traffic is incoming before we enable the Rx unit, it could hang 1918 * the Rx DMA unit. Therefore, make sure the security engine is 1919 * completely disabled prior to enabling the Rx unit. 1920 */ 1921 hw->mac.ops.disable_rx_buff(hw); 1922 1923 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 1924 1925 hw->mac.ops.enable_rx_buff(hw); 1926 1927 return 0; 1928 } 1929 1930 /** 1931 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 1932 * @hw: pointer to hardware structure 1933 * 1934 * Verifies that installed the firmware version is 0.6 or higher 1935 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 1936 * 1937 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 1938 * if the FW version is not supported. 1939 **/ 1940 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 1941 { 1942 s32 status = IXGBE_ERR_EEPROM_VERSION; 1943 u16 fw_offset, fw_ptp_cfg_offset; 1944 u16 fw_version = 0; 1945 1946 /* firmware check is only necessary for SFI devices */ 1947 if (hw->phy.media_type != ixgbe_media_type_fiber) { 1948 status = 0; 1949 goto fw_version_out; 1950 } 1951 1952 /* get the offset to the Firmware Module block */ 1953 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 1954 1955 if ((fw_offset == 0) || (fw_offset == 0xFFFF)) 1956 goto fw_version_out; 1957 1958 /* get the offset to the Pass Through Patch Configuration block */ 1959 hw->eeprom.ops.read(hw, (fw_offset + 1960 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), 1961 &fw_ptp_cfg_offset); 1962 1963 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) 1964 goto fw_version_out; 1965 1966 /* get the firmware version */ 1967 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + 1968 IXGBE_FW_PATCH_VERSION_4), 1969 &fw_version); 1970 1971 if (fw_version > 0x5) 1972 status = 0; 1973 1974 fw_version_out: 1975 return status; 1976 } 1977 1978 /** 1979 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 1980 * @hw: pointer to hardware structure 1981 * 1982 * Returns true if the LESM FW module is present and enabled. Otherwise 1983 * returns false. Smart Speed must be disabled if LESM FW module is enabled. 1984 **/ 1985 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 1986 { 1987 bool lesm_enabled = false; 1988 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state; 1989 s32 status; 1990 1991 /* get the offset to the Firmware Module block */ 1992 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 1993 1994 if ((status != 0) || 1995 (fw_offset == 0) || (fw_offset == 0xFFFF)) 1996 goto out; 1997 1998 /* get the offset to the LESM Parameters block */ 1999 status = hw->eeprom.ops.read(hw, (fw_offset + 2000 IXGBE_FW_LESM_PARAMETERS_PTR), 2001 &fw_lesm_param_offset); 2002 2003 if ((status != 0) || 2004 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF)) 2005 goto out; 2006 2007 /* get the lesm state word */ 2008 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 2009 IXGBE_FW_LESM_STATE_1), 2010 &fw_lesm_state); 2011 2012 if ((status == 0) && 2013 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 2014 lesm_enabled = true; 2015 2016 out: 2017 return lesm_enabled; 2018 } 2019 2020 /** 2021 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using 2022 * fastest available method 2023 * 2024 * @hw: pointer to hardware structure 2025 * @offset: offset of word in EEPROM to read 2026 * @words: number of words 2027 * @data: word(s) read from the EEPROM 2028 * 2029 * Retrieves 16 bit word(s) read from EEPROM 2030 **/ 2031 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 2032 u16 words, u16 *data) 2033 { 2034 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2035 s32 ret_val = IXGBE_ERR_CONFIG; 2036 2037 /* 2038 * If EEPROM is detected and can be addressed using 14 bits, 2039 * use EERD otherwise use bit bang 2040 */ 2041 if ((eeprom->type == ixgbe_eeprom_spi) && 2042 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR)) 2043 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words, 2044 data); 2045 else 2046 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, 2047 words, 2048 data); 2049 2050 return ret_val; 2051 } 2052 2053 /** 2054 * ixgbe_read_eeprom_82599 - Read EEPROM word using 2055 * fastest available method 2056 * 2057 * @hw: pointer to hardware structure 2058 * @offset: offset of word in the EEPROM to read 2059 * @data: word read from the EEPROM 2060 * 2061 * Reads a 16 bit word from the EEPROM 2062 **/ 2063 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 2064 u16 offset, u16 *data) 2065 { 2066 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2067 s32 ret_val = IXGBE_ERR_CONFIG; 2068 2069 /* 2070 * If EEPROM is detected and can be addressed using 14 bits, 2071 * use EERD otherwise use bit bang 2072 */ 2073 if ((eeprom->type == ixgbe_eeprom_spi) && 2074 (offset <= IXGBE_EERD_MAX_ADDR)) 2075 ret_val = ixgbe_read_eerd_generic(hw, offset, data); 2076 else 2077 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); 2078 2079 return ret_val; 2080 } 2081 2082 static struct ixgbe_mac_operations mac_ops_82599 = { 2083 .init_hw = &ixgbe_init_hw_generic, 2084 .reset_hw = &ixgbe_reset_hw_82599, 2085 .start_hw = &ixgbe_start_hw_82599, 2086 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 2087 .get_media_type = &ixgbe_get_media_type_82599, 2088 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599, 2089 .enable_rx_dma = &ixgbe_enable_rx_dma_82599, 2090 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, 2091 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, 2092 .get_mac_addr = &ixgbe_get_mac_addr_generic, 2093 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 2094 .get_device_caps = &ixgbe_get_device_caps_generic, 2095 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 2096 .stop_adapter = &ixgbe_stop_adapter_generic, 2097 .get_bus_info = &ixgbe_get_bus_info_generic, 2098 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, 2099 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599, 2100 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599, 2101 .setup_link = &ixgbe_setup_mac_link_82599, 2102 .set_rxpba = &ixgbe_set_rxpba_generic, 2103 .check_link = &ixgbe_check_mac_link_generic, 2104 .get_link_capabilities = &ixgbe_get_link_capabilities_82599, 2105 .led_on = &ixgbe_led_on_generic, 2106 .led_off = &ixgbe_led_off_generic, 2107 .blink_led_start = &ixgbe_blink_led_start_generic, 2108 .blink_led_stop = &ixgbe_blink_led_stop_generic, 2109 .set_rar = &ixgbe_set_rar_generic, 2110 .clear_rar = &ixgbe_clear_rar_generic, 2111 .set_vmdq = &ixgbe_set_vmdq_generic, 2112 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, 2113 .clear_vmdq = &ixgbe_clear_vmdq_generic, 2114 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 2115 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 2116 .enable_mc = &ixgbe_enable_mc_generic, 2117 .disable_mc = &ixgbe_disable_mc_generic, 2118 .clear_vfta = &ixgbe_clear_vfta_generic, 2119 .set_vfta = &ixgbe_set_vfta_generic, 2120 .fc_enable = &ixgbe_fc_enable_generic, 2121 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, 2122 .init_uta_tables = &ixgbe_init_uta_tables_generic, 2123 .setup_sfp = &ixgbe_setup_sfp_modules_82599, 2124 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, 2125 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, 2126 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync, 2127 .release_swfw_sync = &ixgbe_release_swfw_sync, 2128 .get_thermal_sensor_data = &ixgbe_get_thermal_sensor_data_generic, 2129 .init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic, 2130 2131 }; 2132 2133 static struct ixgbe_eeprom_operations eeprom_ops_82599 = { 2134 .init_params = &ixgbe_init_eeprom_params_generic, 2135 .read = &ixgbe_read_eeprom_82599, 2136 .read_buffer = &ixgbe_read_eeprom_buffer_82599, 2137 .write = &ixgbe_write_eeprom_generic, 2138 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic, 2139 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, 2140 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 2141 .update_checksum = &ixgbe_update_eeprom_checksum_generic, 2142 }; 2143 2144 static struct ixgbe_phy_operations phy_ops_82599 = { 2145 .identify = &ixgbe_identify_phy_82599, 2146 .identify_sfp = &ixgbe_identify_sfp_module_generic, 2147 .init = &ixgbe_init_phy_ops_82599, 2148 .reset = &ixgbe_reset_phy_generic, 2149 .read_reg = &ixgbe_read_phy_reg_generic, 2150 .write_reg = &ixgbe_write_phy_reg_generic, 2151 .setup_link = &ixgbe_setup_phy_link_generic, 2152 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 2153 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, 2154 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, 2155 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, 2156 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, 2157 .check_overtemp = &ixgbe_tn_check_overtemp, 2158 }; 2159 2160 struct ixgbe_info ixgbe_82599_info = { 2161 .mac = ixgbe_mac_82599EB, 2162 .get_invariants = &ixgbe_get_invariants_82599, 2163 .mac_ops = &mac_ops_82599, 2164 .eeprom_ops = &eeprom_ops_82599, 2165 .phy_ops = &phy_ops_82599, 2166 .mbx_ops = &mbx_ops_generic, 2167 }; 2168