1 // SPDX-License-Identifier: GPL-2.0 2 /******************************************************************************* 3 4 Intel 10 Gigabit PCI Express Linux driver 5 Copyright(c) 1999 - 2016 Intel Corporation. 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Contact Information: 24 Linux NICS <linux.nics@intel.com> 25 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 27 28 *******************************************************************************/ 29 30 #include <linux/pci.h> 31 #include <linux/delay.h> 32 #include <linux/sched.h> 33 34 #include "ixgbe.h" 35 #include "ixgbe_phy.h" 36 #include "ixgbe_mbx.h" 37 38 #define IXGBE_82599_MAX_TX_QUEUES 128 39 #define IXGBE_82599_MAX_RX_QUEUES 128 40 #define IXGBE_82599_RAR_ENTRIES 128 41 #define IXGBE_82599_MC_TBL_SIZE 128 42 #define IXGBE_82599_VFT_TBL_SIZE 128 43 #define IXGBE_82599_RX_PB_SIZE 512 44 45 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 46 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 47 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 48 static void 49 ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *, ixgbe_link_speed); 50 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 51 ixgbe_link_speed speed, 52 bool autoneg_wait_to_complete); 53 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw); 54 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 55 bool autoneg_wait_to_complete); 56 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 57 ixgbe_link_speed speed, 58 bool autoneg_wait_to_complete); 59 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 60 ixgbe_link_speed speed, 61 bool autoneg_wait_to_complete); 62 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 63 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 64 u8 dev_addr, u8 *data); 65 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 66 u8 dev_addr, u8 data); 67 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw); 68 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw); 69 70 bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 71 { 72 u32 fwsm, manc, factps; 73 74 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 75 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) 76 return false; 77 78 manc = IXGBE_READ_REG(hw, IXGBE_MANC); 79 if (!(manc & IXGBE_MANC_RCV_TCO_EN)) 80 return false; 81 82 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); 83 if (factps & IXGBE_FACTPS_MNGCG) 84 return false; 85 86 return true; 87 } 88 89 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 90 { 91 struct ixgbe_mac_info *mac = &hw->mac; 92 93 /* enable the laser control functions for SFP+ fiber 94 * and MNG not enabled 95 */ 96 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && 97 !ixgbe_mng_enabled(hw)) { 98 mac->ops.disable_tx_laser = 99 &ixgbe_disable_tx_laser_multispeed_fiber; 100 mac->ops.enable_tx_laser = 101 &ixgbe_enable_tx_laser_multispeed_fiber; 102 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; 103 } else { 104 mac->ops.disable_tx_laser = NULL; 105 mac->ops.enable_tx_laser = NULL; 106 mac->ops.flap_tx_laser = NULL; 107 } 108 109 if (hw->phy.multispeed_fiber) { 110 /* Set up dual speed SFP+ support */ 111 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; 112 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599; 113 mac->ops.set_rate_select_speed = 114 ixgbe_set_hard_rate_select_speed; 115 } else { 116 if ((mac->ops.get_media_type(hw) == 117 ixgbe_media_type_backplane) && 118 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 119 hw->phy.smart_speed == ixgbe_smart_speed_on) && 120 !ixgbe_verify_lesm_fw_enabled_82599(hw)) 121 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; 122 else 123 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; 124 } 125 } 126 127 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 128 { 129 s32 ret_val; 130 u16 list_offset, data_offset, data_value; 131 132 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 133 ixgbe_init_mac_link_ops_82599(hw); 134 135 hw->phy.ops.reset = NULL; 136 137 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 138 &data_offset); 139 if (ret_val) 140 return ret_val; 141 142 /* PHY config will finish before releasing the semaphore */ 143 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 144 IXGBE_GSSR_MAC_CSR_SM); 145 if (ret_val) 146 return IXGBE_ERR_SWFW_SYNC; 147 148 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 149 goto setup_sfp_err; 150 while (data_value != 0xffff) { 151 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 152 IXGBE_WRITE_FLUSH(hw); 153 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 154 goto setup_sfp_err; 155 } 156 157 /* Release the semaphore */ 158 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 159 /* 160 * Delay obtaining semaphore again to allow FW access, 161 * semaphore_delay is in ms usleep_range needs us. 162 */ 163 usleep_range(hw->eeprom.semaphore_delay * 1000, 164 hw->eeprom.semaphore_delay * 2000); 165 166 /* Restart DSP and set SFI mode */ 167 ret_val = hw->mac.ops.prot_autoc_write(hw, 168 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL, 169 false); 170 171 if (ret_val) { 172 hw_dbg(hw, " sfp module setup not complete\n"); 173 return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 174 } 175 } 176 177 return 0; 178 179 setup_sfp_err: 180 /* Release the semaphore */ 181 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 182 /* Delay obtaining semaphore again to allow FW access, 183 * semaphore_delay is in ms usleep_range needs us. 184 */ 185 usleep_range(hw->eeprom.semaphore_delay * 1000, 186 hw->eeprom.semaphore_delay * 2000); 187 hw_err(hw, "eeprom read at offset %d failed\n", data_offset); 188 return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 189 } 190 191 /** 192 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read 193 * @hw: pointer to hardware structure 194 * @locked: Return the if we locked for this read. 195 * @reg_val: Value we read from AUTOC 196 * 197 * For this part (82599) we need to wrap read-modify-writes with a possible 198 * FW/SW lock. It is assumed this lock will be freed with the next 199 * prot_autoc_write_82599(). Note, that locked can only be true in cases 200 * where this function doesn't return an error. 201 **/ 202 static s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, 203 u32 *reg_val) 204 { 205 s32 ret_val; 206 207 *locked = false; 208 /* If LESM is on then we need to hold the SW/FW semaphore. */ 209 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 210 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 211 IXGBE_GSSR_MAC_CSR_SM); 212 if (ret_val) 213 return IXGBE_ERR_SWFW_SYNC; 214 215 *locked = true; 216 } 217 218 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 219 return 0; 220 } 221 222 /** 223 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write 224 * @hw: pointer to hardware structure 225 * @autoc: value to write to AUTOC 226 * @locked: bool to indicate whether the SW/FW lock was already taken by 227 * previous proc_autoc_read_82599. 228 * 229 * This part (82599) may need to hold a the SW/FW lock around all writes to 230 * AUTOC. Likewise after a write we need to do a pipeline reset. 231 **/ 232 static s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked) 233 { 234 s32 ret_val = 0; 235 236 /* Blocked by MNG FW so bail */ 237 if (ixgbe_check_reset_blocked(hw)) 238 goto out; 239 240 /* We only need to get the lock if: 241 * - We didn't do it already (in the read part of a read-modify-write) 242 * - LESM is enabled. 243 */ 244 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) { 245 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 246 IXGBE_GSSR_MAC_CSR_SM); 247 if (ret_val) 248 return IXGBE_ERR_SWFW_SYNC; 249 250 locked = true; 251 } 252 253 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 254 ret_val = ixgbe_reset_pipeline_82599(hw); 255 256 out: 257 /* Free the SW/FW semaphore as we either grabbed it here or 258 * already had it when this function was called. 259 */ 260 if (locked) 261 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 262 263 return ret_val; 264 } 265 266 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw) 267 { 268 struct ixgbe_mac_info *mac = &hw->mac; 269 270 ixgbe_init_mac_link_ops_82599(hw); 271 272 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; 273 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; 274 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; 275 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE; 276 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; 277 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; 278 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 279 280 return 0; 281 } 282 283 /** 284 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 285 * @hw: pointer to hardware structure 286 * 287 * Initialize any function pointers that were not able to be 288 * set during get_invariants because the PHY/SFP type was 289 * not known. Perform the SFP init if necessary. 290 * 291 **/ 292 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 293 { 294 struct ixgbe_mac_info *mac = &hw->mac; 295 struct ixgbe_phy_info *phy = &hw->phy; 296 s32 ret_val; 297 u32 esdp; 298 299 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) { 300 /* Store flag indicating I2C bus access control unit. */ 301 hw->phy.qsfp_shared_i2c_bus = true; 302 303 /* Initialize access to QSFP+ I2C bus */ 304 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 305 esdp |= IXGBE_ESDP_SDP0_DIR; 306 esdp &= ~IXGBE_ESDP_SDP1_DIR; 307 esdp &= ~IXGBE_ESDP_SDP0; 308 esdp &= ~IXGBE_ESDP_SDP0_NATIVE; 309 esdp &= ~IXGBE_ESDP_SDP1_NATIVE; 310 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 311 IXGBE_WRITE_FLUSH(hw); 312 313 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599; 314 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599; 315 } 316 317 /* Identify the PHY or SFP module */ 318 ret_val = phy->ops.identify(hw); 319 320 /* Setup function pointers based on detected SFP module and speeds */ 321 ixgbe_init_mac_link_ops_82599(hw); 322 323 /* If copper media, overwrite with copper function pointers */ 324 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 325 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; 326 mac->ops.get_link_capabilities = 327 &ixgbe_get_copper_link_capabilities_generic; 328 } 329 330 /* Set necessary function pointers based on phy type */ 331 switch (hw->phy.type) { 332 case ixgbe_phy_tn: 333 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 334 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 335 break; 336 default: 337 break; 338 } 339 340 return ret_val; 341 } 342 343 /** 344 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 345 * @hw: pointer to hardware structure 346 * @speed: pointer to link speed 347 * @autoneg: true when autoneg or autotry is enabled 348 * 349 * Determines the link capabilities by reading the AUTOC register. 350 **/ 351 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 352 ixgbe_link_speed *speed, 353 bool *autoneg) 354 { 355 u32 autoc = 0; 356 357 /* Determine 1G link capabilities off of SFP+ type */ 358 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 359 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 360 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 361 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 362 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 363 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 364 *speed = IXGBE_LINK_SPEED_1GB_FULL; 365 *autoneg = true; 366 return 0; 367 } 368 369 /* 370 * Determine link capabilities based on the stored value of AUTOC, 371 * which represents EEPROM defaults. If AUTOC value has not been 372 * stored, use the current register value. 373 */ 374 if (hw->mac.orig_link_settings_stored) 375 autoc = hw->mac.orig_autoc; 376 else 377 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 378 379 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 380 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 381 *speed = IXGBE_LINK_SPEED_1GB_FULL; 382 *autoneg = false; 383 break; 384 385 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 386 *speed = IXGBE_LINK_SPEED_10GB_FULL; 387 *autoneg = false; 388 break; 389 390 case IXGBE_AUTOC_LMS_1G_AN: 391 *speed = IXGBE_LINK_SPEED_1GB_FULL; 392 *autoneg = true; 393 break; 394 395 case IXGBE_AUTOC_LMS_10G_SERIAL: 396 *speed = IXGBE_LINK_SPEED_10GB_FULL; 397 *autoneg = false; 398 break; 399 400 case IXGBE_AUTOC_LMS_KX4_KX_KR: 401 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 402 *speed = IXGBE_LINK_SPEED_UNKNOWN; 403 if (autoc & IXGBE_AUTOC_KR_SUPP) 404 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 405 if (autoc & IXGBE_AUTOC_KX4_SUPP) 406 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 407 if (autoc & IXGBE_AUTOC_KX_SUPP) 408 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 409 *autoneg = true; 410 break; 411 412 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 413 *speed = IXGBE_LINK_SPEED_100_FULL; 414 if (autoc & IXGBE_AUTOC_KR_SUPP) 415 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 416 if (autoc & IXGBE_AUTOC_KX4_SUPP) 417 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 418 if (autoc & IXGBE_AUTOC_KX_SUPP) 419 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 420 *autoneg = true; 421 break; 422 423 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 424 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 425 *autoneg = false; 426 break; 427 428 default: 429 return IXGBE_ERR_LINK_SETUP; 430 } 431 432 if (hw->phy.multispeed_fiber) { 433 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 434 IXGBE_LINK_SPEED_1GB_FULL; 435 436 /* QSFP must not enable auto-negotiation */ 437 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp) 438 *autoneg = false; 439 else 440 *autoneg = true; 441 } 442 443 return 0; 444 } 445 446 /** 447 * ixgbe_get_media_type_82599 - Get media type 448 * @hw: pointer to hardware structure 449 * 450 * Returns the media type (fiber, copper, backplane) 451 **/ 452 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 453 { 454 /* Detect if there is a copper PHY attached. */ 455 switch (hw->phy.type) { 456 case ixgbe_phy_cu_unknown: 457 case ixgbe_phy_tn: 458 return ixgbe_media_type_copper; 459 460 default: 461 break; 462 } 463 464 switch (hw->device_id) { 465 case IXGBE_DEV_ID_82599_KX4: 466 case IXGBE_DEV_ID_82599_KX4_MEZZ: 467 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 468 case IXGBE_DEV_ID_82599_KR: 469 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 470 case IXGBE_DEV_ID_82599_XAUI_LOM: 471 /* Default device ID is mezzanine card KX/KX4 */ 472 return ixgbe_media_type_backplane; 473 474 case IXGBE_DEV_ID_82599_SFP: 475 case IXGBE_DEV_ID_82599_SFP_FCOE: 476 case IXGBE_DEV_ID_82599_SFP_EM: 477 case IXGBE_DEV_ID_82599_SFP_SF2: 478 case IXGBE_DEV_ID_82599_SFP_SF_QP: 479 case IXGBE_DEV_ID_82599EN_SFP: 480 return ixgbe_media_type_fiber; 481 482 case IXGBE_DEV_ID_82599_CX4: 483 return ixgbe_media_type_cx4; 484 485 case IXGBE_DEV_ID_82599_T3_LOM: 486 return ixgbe_media_type_copper; 487 488 case IXGBE_DEV_ID_82599_LS: 489 return ixgbe_media_type_fiber_lco; 490 491 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 492 return ixgbe_media_type_fiber_qsfp; 493 494 default: 495 return ixgbe_media_type_unknown; 496 } 497 } 498 499 /** 500 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3 501 * @hw: pointer to hardware structure 502 * 503 * Disables link, should be called during D3 power down sequence. 504 * 505 **/ 506 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw) 507 { 508 u32 autoc2_reg; 509 u16 ee_ctrl_2 = 0; 510 511 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); 512 513 if (!ixgbe_mng_present(hw) && !hw->wol_enabled && 514 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) { 515 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 516 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK; 517 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 518 } 519 } 520 521 /** 522 * ixgbe_start_mac_link_82599 - Setup MAC link settings 523 * @hw: pointer to hardware structure 524 * @autoneg_wait_to_complete: true when waiting for completion is needed 525 * 526 * Configures link settings based on values in the ixgbe_hw struct. 527 * Restarts the link. Performs autonegotiation if needed. 528 **/ 529 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 530 bool autoneg_wait_to_complete) 531 { 532 u32 autoc_reg; 533 u32 links_reg; 534 u32 i; 535 s32 status = 0; 536 bool got_lock = false; 537 538 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 539 status = hw->mac.ops.acquire_swfw_sync(hw, 540 IXGBE_GSSR_MAC_CSR_SM); 541 if (status) 542 return status; 543 544 got_lock = true; 545 } 546 547 /* Restart link */ 548 ixgbe_reset_pipeline_82599(hw); 549 550 if (got_lock) 551 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 552 553 /* Only poll for autoneg to complete if specified to do so */ 554 if (autoneg_wait_to_complete) { 555 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 556 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 557 IXGBE_AUTOC_LMS_KX4_KX_KR || 558 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 559 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 560 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 561 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 562 links_reg = 0; /* Just in case Autoneg time = 0 */ 563 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 564 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 565 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 566 break; 567 msleep(100); 568 } 569 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 570 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 571 hw_dbg(hw, "Autoneg did not complete.\n"); 572 } 573 } 574 } 575 576 /* Add delay to filter out noises during initial link setup */ 577 msleep(50); 578 579 return status; 580 } 581 582 /** 583 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 584 * @hw: pointer to hardware structure 585 * 586 * The base drivers may require better control over SFP+ module 587 * PHY states. This includes selectively shutting down the Tx 588 * laser on the PHY, effectively halting physical link. 589 **/ 590 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 591 { 592 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 593 594 /* Blocked by MNG FW so bail */ 595 if (ixgbe_check_reset_blocked(hw)) 596 return; 597 598 /* Disable tx laser; allow 100us to go dark per spec */ 599 esdp_reg |= IXGBE_ESDP_SDP3; 600 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 601 IXGBE_WRITE_FLUSH(hw); 602 udelay(100); 603 } 604 605 /** 606 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 607 * @hw: pointer to hardware structure 608 * 609 * The base drivers may require better control over SFP+ module 610 * PHY states. This includes selectively turning on the Tx 611 * laser on the PHY, effectively starting physical link. 612 **/ 613 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 614 { 615 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 616 617 /* Enable tx laser; allow 100ms to light up */ 618 esdp_reg &= ~IXGBE_ESDP_SDP3; 619 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 620 IXGBE_WRITE_FLUSH(hw); 621 msleep(100); 622 } 623 624 /** 625 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 626 * @hw: pointer to hardware structure 627 * 628 * When the driver changes the link speeds that it can support, 629 * it sets autotry_restart to true to indicate that we need to 630 * initiate a new autotry session with the link partner. To do 631 * so, we set the speed then disable and re-enable the tx laser, to 632 * alert the link partner that it also needs to restart autotry on its 633 * end. This is consistent with true clause 37 autoneg, which also 634 * involves a loss of signal. 635 **/ 636 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 637 { 638 /* Blocked by MNG FW so bail */ 639 if (ixgbe_check_reset_blocked(hw)) 640 return; 641 642 if (hw->mac.autotry_restart) { 643 ixgbe_disable_tx_laser_multispeed_fiber(hw); 644 ixgbe_enable_tx_laser_multispeed_fiber(hw); 645 hw->mac.autotry_restart = false; 646 } 647 } 648 649 /** 650 * ixgbe_set_hard_rate_select_speed - Set module link speed 651 * @hw: pointer to hardware structure 652 * @speed: link speed to set 653 * 654 * Set module link speed via RS0/RS1 rate select pins. 655 */ 656 static void 657 ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 658 { 659 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 660 661 switch (speed) { 662 case IXGBE_LINK_SPEED_10GB_FULL: 663 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 664 break; 665 case IXGBE_LINK_SPEED_1GB_FULL: 666 esdp_reg &= ~IXGBE_ESDP_SDP5; 667 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 668 break; 669 default: 670 hw_dbg(hw, "Invalid fixed module speed\n"); 671 return; 672 } 673 674 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 675 IXGBE_WRITE_FLUSH(hw); 676 } 677 678 /** 679 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 680 * @hw: pointer to hardware structure 681 * @speed: new link speed 682 * @autoneg_wait_to_complete: true when waiting for completion is needed 683 * 684 * Implements the Intel SmartSpeed algorithm. 685 **/ 686 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 687 ixgbe_link_speed speed, 688 bool autoneg_wait_to_complete) 689 { 690 s32 status = 0; 691 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 692 s32 i, j; 693 bool link_up = false; 694 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 695 696 /* Set autoneg_advertised value based on input link speed */ 697 hw->phy.autoneg_advertised = 0; 698 699 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 700 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 701 702 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 703 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 704 705 if (speed & IXGBE_LINK_SPEED_100_FULL) 706 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 707 708 /* 709 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 710 * autoneg advertisement if link is unable to be established at the 711 * highest negotiated rate. This can sometimes happen due to integrity 712 * issues with the physical media connection. 713 */ 714 715 /* First, try to get link with full advertisement */ 716 hw->phy.smart_speed_active = false; 717 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 718 status = ixgbe_setup_mac_link_82599(hw, speed, 719 autoneg_wait_to_complete); 720 if (status != 0) 721 goto out; 722 723 /* 724 * Wait for the controller to acquire link. Per IEEE 802.3ap, 725 * Section 73.10.2, we may have to wait up to 500ms if KR is 726 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 727 * Table 9 in the AN MAS. 728 */ 729 for (i = 0; i < 5; i++) { 730 mdelay(100); 731 732 /* If we have link, just jump out */ 733 status = hw->mac.ops.check_link(hw, &link_speed, 734 &link_up, false); 735 if (status != 0) 736 goto out; 737 738 if (link_up) 739 goto out; 740 } 741 } 742 743 /* 744 * We didn't get link. If we advertised KR plus one of KX4/KX 745 * (or BX4/BX), then disable KR and try again. 746 */ 747 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 748 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 749 goto out; 750 751 /* Turn SmartSpeed on to disable KR support */ 752 hw->phy.smart_speed_active = true; 753 status = ixgbe_setup_mac_link_82599(hw, speed, 754 autoneg_wait_to_complete); 755 if (status != 0) 756 goto out; 757 758 /* 759 * Wait for the controller to acquire link. 600ms will allow for 760 * the AN link_fail_inhibit_timer as well for multiple cycles of 761 * parallel detect, both 10g and 1g. This allows for the maximum 762 * connect attempts as defined in the AN MAS table 73-7. 763 */ 764 for (i = 0; i < 6; i++) { 765 mdelay(100); 766 767 /* If we have link, just jump out */ 768 status = hw->mac.ops.check_link(hw, &link_speed, 769 &link_up, false); 770 if (status != 0) 771 goto out; 772 773 if (link_up) 774 goto out; 775 } 776 777 /* We didn't get link. Turn SmartSpeed back off. */ 778 hw->phy.smart_speed_active = false; 779 status = ixgbe_setup_mac_link_82599(hw, speed, 780 autoneg_wait_to_complete); 781 782 out: 783 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 784 hw_dbg(hw, "Smartspeed has downgraded the link speed from the maximum advertised\n"); 785 return status; 786 } 787 788 /** 789 * ixgbe_setup_mac_link_82599 - Set MAC link speed 790 * @hw: pointer to hardware structure 791 * @speed: new link speed 792 * @autoneg_wait_to_complete: true when waiting for completion is needed 793 * 794 * Set the link speed in the AUTOC register and restarts link. 795 **/ 796 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 797 ixgbe_link_speed speed, 798 bool autoneg_wait_to_complete) 799 { 800 bool autoneg = false; 801 s32 status; 802 u32 pma_pmd_1g, link_mode, links_reg, i; 803 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 804 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 805 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 806 807 /* holds the value of AUTOC register at this current point in time */ 808 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 809 /* holds the cached value of AUTOC register */ 810 u32 orig_autoc = 0; 811 /* temporary variable used for comparison purposes */ 812 u32 autoc = current_autoc; 813 814 /* Check to see if speed passed in is supported. */ 815 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities, 816 &autoneg); 817 if (status) 818 return status; 819 820 speed &= link_capabilities; 821 822 if (speed == IXGBE_LINK_SPEED_UNKNOWN) 823 return IXGBE_ERR_LINK_SETUP; 824 825 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 826 if (hw->mac.orig_link_settings_stored) 827 orig_autoc = hw->mac.orig_autoc; 828 else 829 orig_autoc = autoc; 830 831 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 832 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 833 834 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 835 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 836 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 837 /* Set KX4/KX/KR support according to speed requested */ 838 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 839 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 840 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 841 autoc |= IXGBE_AUTOC_KX4_SUPP; 842 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 843 (hw->phy.smart_speed_active == false)) 844 autoc |= IXGBE_AUTOC_KR_SUPP; 845 } 846 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 847 autoc |= IXGBE_AUTOC_KX_SUPP; 848 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 849 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 850 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 851 /* Switch from 1G SFI to 10G SFI if requested */ 852 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 853 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 854 autoc &= ~IXGBE_AUTOC_LMS_MASK; 855 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 856 } 857 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 858 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 859 /* Switch from 10G SFI to 1G SFI if requested */ 860 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 861 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 862 autoc &= ~IXGBE_AUTOC_LMS_MASK; 863 if (autoneg) 864 autoc |= IXGBE_AUTOC_LMS_1G_AN; 865 else 866 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 867 } 868 } 869 870 if (autoc != current_autoc) { 871 /* Restart link */ 872 status = hw->mac.ops.prot_autoc_write(hw, autoc, false); 873 if (status) 874 return status; 875 876 /* Only poll for autoneg to complete if specified to do so */ 877 if (autoneg_wait_to_complete) { 878 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 879 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 880 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 881 links_reg = 0; /*Just in case Autoneg time=0*/ 882 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 883 links_reg = 884 IXGBE_READ_REG(hw, IXGBE_LINKS); 885 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 886 break; 887 msleep(100); 888 } 889 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 890 status = 891 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 892 hw_dbg(hw, "Autoneg did not complete.\n"); 893 } 894 } 895 } 896 897 /* Add delay to filter out noises during initial link setup */ 898 msleep(50); 899 } 900 901 return status; 902 } 903 904 /** 905 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 906 * @hw: pointer to hardware structure 907 * @speed: new link speed 908 * @autoneg_wait_to_complete: true if waiting is needed to complete 909 * 910 * Restarts link on PHY and MAC based on settings passed in. 911 **/ 912 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 913 ixgbe_link_speed speed, 914 bool autoneg_wait_to_complete) 915 { 916 s32 status; 917 918 /* Setup the PHY according to input speed */ 919 status = hw->phy.ops.setup_link_speed(hw, speed, 920 autoneg_wait_to_complete); 921 /* Set up MAC */ 922 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 923 924 return status; 925 } 926 927 /** 928 * ixgbe_reset_hw_82599 - Perform hardware reset 929 * @hw: pointer to hardware structure 930 * 931 * Resets the hardware by resetting the transmit and receive units, masks 932 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 933 * reset. 934 **/ 935 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 936 { 937 ixgbe_link_speed link_speed; 938 s32 status; 939 u32 ctrl, i, autoc, autoc2; 940 u32 curr_lms; 941 bool link_up = false; 942 943 /* Call adapter stop to disable tx/rx and clear interrupts */ 944 status = hw->mac.ops.stop_adapter(hw); 945 if (status) 946 return status; 947 948 /* flush pending Tx transactions */ 949 ixgbe_clear_tx_pending(hw); 950 951 /* PHY ops must be identified and initialized prior to reset */ 952 953 /* Identify PHY and related function pointers */ 954 status = hw->phy.ops.init(hw); 955 956 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 957 return status; 958 959 /* Setup SFP module if there is one present. */ 960 if (hw->phy.sfp_setup_needed) { 961 status = hw->mac.ops.setup_sfp(hw); 962 hw->phy.sfp_setup_needed = false; 963 } 964 965 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 966 return status; 967 968 /* Reset PHY */ 969 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) 970 hw->phy.ops.reset(hw); 971 972 /* remember AUTOC from before we reset */ 973 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK; 974 975 mac_reset_top: 976 /* 977 * Issue global reset to the MAC. Needs to be SW reset if link is up. 978 * If link reset is used when link is up, it might reset the PHY when 979 * mng is using it. If link is down or the flag to force full link 980 * reset is set, then perform link reset. 981 */ 982 ctrl = IXGBE_CTRL_LNK_RST; 983 if (!hw->force_full_reset) { 984 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 985 if (link_up) 986 ctrl = IXGBE_CTRL_RST; 987 } 988 989 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 990 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 991 IXGBE_WRITE_FLUSH(hw); 992 usleep_range(1000, 1200); 993 994 /* Poll for reset bit to self-clear indicating reset is complete */ 995 for (i = 0; i < 10; i++) { 996 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 997 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 998 break; 999 udelay(1); 1000 } 1001 1002 if (ctrl & IXGBE_CTRL_RST_MASK) { 1003 status = IXGBE_ERR_RESET_FAILED; 1004 hw_dbg(hw, "Reset polling failed to complete.\n"); 1005 } 1006 1007 msleep(50); 1008 1009 /* 1010 * Double resets are required for recovery from certain error 1011 * conditions. Between resets, it is necessary to stall to allow time 1012 * for any pending HW events to complete. 1013 */ 1014 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1015 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1016 goto mac_reset_top; 1017 } 1018 1019 /* 1020 * Store the original AUTOC/AUTOC2 values if they have not been 1021 * stored off yet. Otherwise restore the stored original 1022 * values since the reset operation sets back to defaults. 1023 */ 1024 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1025 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1026 1027 /* Enable link if disabled in NVM */ 1028 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 1029 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 1030 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1031 IXGBE_WRITE_FLUSH(hw); 1032 } 1033 1034 if (hw->mac.orig_link_settings_stored == false) { 1035 hw->mac.orig_autoc = autoc; 1036 hw->mac.orig_autoc2 = autoc2; 1037 hw->mac.orig_link_settings_stored = true; 1038 } else { 1039 1040 /* If MNG FW is running on a multi-speed device that 1041 * doesn't autoneg with out driver support we need to 1042 * leave LMS in the state it was before we MAC reset. 1043 * Likewise if we support WoL we don't want change the 1044 * LMS state either. 1045 */ 1046 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) || 1047 hw->wol_enabled) 1048 hw->mac.orig_autoc = 1049 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | 1050 curr_lms; 1051 1052 if (autoc != hw->mac.orig_autoc) { 1053 status = hw->mac.ops.prot_autoc_write(hw, 1054 hw->mac.orig_autoc, 1055 false); 1056 if (status) 1057 return status; 1058 } 1059 1060 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1061 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1062 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1063 autoc2 |= (hw->mac.orig_autoc2 & 1064 IXGBE_AUTOC2_UPPER_MASK); 1065 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1066 } 1067 } 1068 1069 /* Store the permanent mac address */ 1070 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1071 1072 /* 1073 * Store MAC address from RAR0, clear receive address registers, and 1074 * clear the multicast table. Also reset num_rar_entries to 128, 1075 * since we modify this value when programming the SAN MAC address. 1076 */ 1077 hw->mac.num_rar_entries = 128; 1078 hw->mac.ops.init_rx_addrs(hw); 1079 1080 /* Store the permanent SAN mac address */ 1081 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 1082 1083 /* Add the SAN MAC address to the RAR only if it's a valid address */ 1084 if (is_valid_ether_addr(hw->mac.san_addr)) { 1085 /* Save the SAN MAC RAR index */ 1086 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 1087 1088 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, 1089 hw->mac.san_addr, 0, IXGBE_RAH_AV); 1090 1091 /* clear VMDq pool/queue selection for this RAR */ 1092 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, 1093 IXGBE_CLEAR_VMDQ_ALL); 1094 1095 /* Reserve the last RAR for the SAN MAC address */ 1096 hw->mac.num_rar_entries--; 1097 } 1098 1099 /* Store the alternative WWNN/WWPN prefix */ 1100 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 1101 &hw->mac.wwpn_prefix); 1102 1103 return status; 1104 } 1105 1106 /** 1107 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete 1108 * @hw: pointer to hardware structure 1109 * @fdircmd: current value of FDIRCMD register 1110 */ 1111 static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd) 1112 { 1113 int i; 1114 1115 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { 1116 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); 1117 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK)) 1118 return 0; 1119 udelay(10); 1120 } 1121 1122 return IXGBE_ERR_FDIR_CMD_INCOMPLETE; 1123 } 1124 1125 /** 1126 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. 1127 * @hw: pointer to hardware structure 1128 **/ 1129 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) 1130 { 1131 int i; 1132 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); 1133 u32 fdircmd; 1134 s32 err; 1135 1136 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; 1137 1138 /* 1139 * Before starting reinitialization process, 1140 * FDIRCMD.CMD must be zero. 1141 */ 1142 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1143 if (err) { 1144 hw_dbg(hw, "Flow Director previous command did not complete, aborting table re-initialization.\n"); 1145 return err; 1146 } 1147 1148 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); 1149 IXGBE_WRITE_FLUSH(hw); 1150 /* 1151 * 82599 adapters flow director init flow cannot be restarted, 1152 * Workaround 82599 silicon errata by performing the following steps 1153 * before re-writing the FDIRCTRL control register with the same value. 1154 * - write 1 to bit 8 of FDIRCMD register & 1155 * - write 0 to bit 8 of FDIRCMD register 1156 */ 1157 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1158 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | 1159 IXGBE_FDIRCMD_CLEARHT)); 1160 IXGBE_WRITE_FLUSH(hw); 1161 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1162 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & 1163 ~IXGBE_FDIRCMD_CLEARHT)); 1164 IXGBE_WRITE_FLUSH(hw); 1165 /* 1166 * Clear FDIR Hash register to clear any leftover hashes 1167 * waiting to be programmed. 1168 */ 1169 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); 1170 IXGBE_WRITE_FLUSH(hw); 1171 1172 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1173 IXGBE_WRITE_FLUSH(hw); 1174 1175 /* Poll init-done after we write FDIRCTRL register */ 1176 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1177 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1178 IXGBE_FDIRCTRL_INIT_DONE) 1179 break; 1180 usleep_range(1000, 2000); 1181 } 1182 if (i >= IXGBE_FDIR_INIT_DONE_POLL) { 1183 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); 1184 return IXGBE_ERR_FDIR_REINIT_FAILED; 1185 } 1186 1187 /* Clear FDIR statistics registers (read to clear) */ 1188 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); 1189 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); 1190 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 1191 IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 1192 IXGBE_READ_REG(hw, IXGBE_FDIRLEN); 1193 1194 return 0; 1195 } 1196 1197 /** 1198 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers 1199 * @hw: pointer to hardware structure 1200 * @fdirctrl: value to write to flow director control register 1201 **/ 1202 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1203 { 1204 int i; 1205 1206 /* Prime the keys for hashing */ 1207 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); 1208 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); 1209 1210 /* 1211 * Poll init-done after we write the register. Estimated times: 1212 * 10G: PBALLOC = 11b, timing is 60us 1213 * 1G: PBALLOC = 11b, timing is 600us 1214 * 100M: PBALLOC = 11b, timing is 6ms 1215 * 1216 * Multiple these timings by 4 if under full Rx load 1217 * 1218 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for 1219 * 1 msec per poll time. If we're at line rate and drop to 100M, then 1220 * this might not finish in our poll time, but we can live with that 1221 * for now. 1222 */ 1223 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); 1224 IXGBE_WRITE_FLUSH(hw); 1225 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { 1226 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & 1227 IXGBE_FDIRCTRL_INIT_DONE) 1228 break; 1229 usleep_range(1000, 2000); 1230 } 1231 1232 if (i >= IXGBE_FDIR_INIT_DONE_POLL) 1233 hw_dbg(hw, "Flow Director poll time exceeded!\n"); 1234 } 1235 1236 /** 1237 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters 1238 * @hw: pointer to hardware structure 1239 * @fdirctrl: value to write to flow director control register, initially 1240 * contains just the value of the Rx packet buffer allocation 1241 **/ 1242 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1243 { 1244 /* 1245 * Continue setup of fdirctrl register bits: 1246 * Move the flexible bytes to use the ethertype - shift 6 words 1247 * Set the maximum length per hash bucket to 0xA filters 1248 * Send interrupt when 64 filters are left 1249 */ 1250 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1251 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1252 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1253 1254 /* write hashes and fdirctrl register, poll for completion */ 1255 ixgbe_fdir_enable_82599(hw, fdirctrl); 1256 1257 return 0; 1258 } 1259 1260 /** 1261 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters 1262 * @hw: pointer to hardware structure 1263 * @fdirctrl: value to write to flow director control register, initially 1264 * contains just the value of the Rx packet buffer allocation 1265 **/ 1266 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl) 1267 { 1268 /* 1269 * Continue setup of fdirctrl register bits: 1270 * Turn perfect match filtering on 1271 * Initialize the drop queue 1272 * Move the flexible bytes to use the ethertype - shift 6 words 1273 * Set the maximum length per hash bucket to 0xA filters 1274 * Send interrupt when 64 (0x4 * 16) filters are left 1275 */ 1276 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH | 1277 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) | 1278 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) | 1279 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) | 1280 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT); 1281 1282 /* write hashes and fdirctrl register, poll for completion */ 1283 ixgbe_fdir_enable_82599(hw, fdirctrl); 1284 1285 return 0; 1286 } 1287 1288 /* 1289 * These defines allow us to quickly generate all of the necessary instructions 1290 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION 1291 * for values 0 through 15 1292 */ 1293 #define IXGBE_ATR_COMMON_HASH_KEY \ 1294 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY) 1295 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \ 1296 do { \ 1297 u32 n = (_n); \ 1298 if (IXGBE_ATR_COMMON_HASH_KEY & BIT(n)) \ 1299 common_hash ^= lo_hash_dword >> n; \ 1300 else if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n)) \ 1301 bucket_hash ^= lo_hash_dword >> n; \ 1302 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & BIT(n)) \ 1303 sig_hash ^= lo_hash_dword << (16 - n); \ 1304 if (IXGBE_ATR_COMMON_HASH_KEY & BIT(n + 16)) \ 1305 common_hash ^= hi_hash_dword >> n; \ 1306 else if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n + 16)) \ 1307 bucket_hash ^= hi_hash_dword >> n; \ 1308 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & BIT(n + 16)) \ 1309 sig_hash ^= hi_hash_dword << (16 - n); \ 1310 } while (0) 1311 1312 /** 1313 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash 1314 * @input: input bitstream to compute the hash on 1315 * @common: compressed common input dword 1316 * 1317 * This function is almost identical to the function above but contains 1318 * several optimizations such as unwinding all of the loops, letting the 1319 * compiler work out all of the conditional ifs since the keys are static 1320 * defines, and computing two keys at once since the hashed dword stream 1321 * will be the same for both keys. 1322 **/ 1323 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, 1324 union ixgbe_atr_hash_dword common) 1325 { 1326 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1327 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0; 1328 1329 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1330 flow_vm_vlan = ntohl(input.dword); 1331 1332 /* generate common hash dword */ 1333 hi_hash_dword = ntohl(common.dword); 1334 1335 /* low dword is word swapped version of common */ 1336 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1337 1338 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1339 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1340 1341 /* Process bits 0 and 16 */ 1342 IXGBE_COMPUTE_SIG_HASH_ITERATION(0); 1343 1344 /* 1345 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1346 * delay this because bit 0 of the stream should not be processed 1347 * so we do not add the vlan until after bit 0 was processed 1348 */ 1349 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1350 1351 /* Process remaining 30 bit of the key */ 1352 IXGBE_COMPUTE_SIG_HASH_ITERATION(1); 1353 IXGBE_COMPUTE_SIG_HASH_ITERATION(2); 1354 IXGBE_COMPUTE_SIG_HASH_ITERATION(3); 1355 IXGBE_COMPUTE_SIG_HASH_ITERATION(4); 1356 IXGBE_COMPUTE_SIG_HASH_ITERATION(5); 1357 IXGBE_COMPUTE_SIG_HASH_ITERATION(6); 1358 IXGBE_COMPUTE_SIG_HASH_ITERATION(7); 1359 IXGBE_COMPUTE_SIG_HASH_ITERATION(8); 1360 IXGBE_COMPUTE_SIG_HASH_ITERATION(9); 1361 IXGBE_COMPUTE_SIG_HASH_ITERATION(10); 1362 IXGBE_COMPUTE_SIG_HASH_ITERATION(11); 1363 IXGBE_COMPUTE_SIG_HASH_ITERATION(12); 1364 IXGBE_COMPUTE_SIG_HASH_ITERATION(13); 1365 IXGBE_COMPUTE_SIG_HASH_ITERATION(14); 1366 IXGBE_COMPUTE_SIG_HASH_ITERATION(15); 1367 1368 /* combine common_hash result with signature and bucket hashes */ 1369 bucket_hash ^= common_hash; 1370 bucket_hash &= IXGBE_ATR_HASH_MASK; 1371 1372 sig_hash ^= common_hash << 16; 1373 sig_hash &= IXGBE_ATR_HASH_MASK << 16; 1374 1375 /* return completed signature hash */ 1376 return sig_hash ^ bucket_hash; 1377 } 1378 1379 /** 1380 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter 1381 * @hw: pointer to hardware structure 1382 * @input: unique input dword 1383 * @common: compressed common input dword 1384 * @queue: queue index to direct traffic to 1385 * 1386 * Note that the tunnel bit in input must not be set when the hardware 1387 * tunneling support does not exist. 1388 **/ 1389 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 1390 union ixgbe_atr_hash_dword input, 1391 union ixgbe_atr_hash_dword common, 1392 u8 queue) 1393 { 1394 u64 fdirhashcmd; 1395 u8 flow_type; 1396 bool tunnel; 1397 u32 fdircmd; 1398 1399 /* 1400 * Get the flow_type in order to program FDIRCMD properly 1401 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 1402 */ 1403 tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK); 1404 flow_type = input.formatted.flow_type & 1405 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1); 1406 switch (flow_type) { 1407 case IXGBE_ATR_FLOW_TYPE_TCPV4: 1408 case IXGBE_ATR_FLOW_TYPE_UDPV4: 1409 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 1410 case IXGBE_ATR_FLOW_TYPE_TCPV6: 1411 case IXGBE_ATR_FLOW_TYPE_UDPV6: 1412 case IXGBE_ATR_FLOW_TYPE_SCTPV6: 1413 break; 1414 default: 1415 hw_dbg(hw, " Error on flow type input\n"); 1416 return IXGBE_ERR_CONFIG; 1417 } 1418 1419 /* configure FDIRCMD register */ 1420 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1421 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1422 fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1423 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1424 if (tunnel) 1425 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER; 1426 1427 /* 1428 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits 1429 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. 1430 */ 1431 fdirhashcmd = (u64)fdircmd << 32; 1432 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common); 1433 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); 1434 1435 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd); 1436 1437 return 0; 1438 } 1439 1440 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \ 1441 do { \ 1442 u32 n = (_n); \ 1443 if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n)) \ 1444 bucket_hash ^= lo_hash_dword >> n; \ 1445 if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n + 16)) \ 1446 bucket_hash ^= hi_hash_dword >> n; \ 1447 } while (0) 1448 1449 /** 1450 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash 1451 * @input: input bitstream to compute the hash on 1452 * @input_mask: mask for the input bitstream 1453 * 1454 * This function serves two main purposes. First it applies the input_mask 1455 * to the atr_input resulting in a cleaned up atr_input data stream. 1456 * Secondly it computes the hash and stores it in the bkt_hash field at 1457 * the end of the input byte stream. This way it will be available for 1458 * future use without needing to recompute the hash. 1459 **/ 1460 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 1461 union ixgbe_atr_input *input_mask) 1462 { 1463 1464 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan; 1465 u32 bucket_hash = 0, hi_dword = 0; 1466 int i; 1467 1468 /* Apply masks to input data */ 1469 for (i = 0; i <= 10; i++) 1470 input->dword_stream[i] &= input_mask->dword_stream[i]; 1471 1472 /* record the flow_vm_vlan bits as they are a key part to the hash */ 1473 flow_vm_vlan = ntohl(input->dword_stream[0]); 1474 1475 /* generate common hash dword */ 1476 for (i = 1; i <= 10; i++) 1477 hi_dword ^= input->dword_stream[i]; 1478 hi_hash_dword = ntohl(hi_dword); 1479 1480 /* low dword is word swapped version of common */ 1481 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16); 1482 1483 /* apply flow ID/VM pool/VLAN ID bits to hash words */ 1484 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16); 1485 1486 /* Process bits 0 and 16 */ 1487 IXGBE_COMPUTE_BKT_HASH_ITERATION(0); 1488 1489 /* 1490 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to 1491 * delay this because bit 0 of the stream should not be processed 1492 * so we do not add the vlan until after bit 0 was processed 1493 */ 1494 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16); 1495 1496 /* Process remaining 30 bit of the key */ 1497 for (i = 1; i <= 15; i++) 1498 IXGBE_COMPUTE_BKT_HASH_ITERATION(i); 1499 1500 /* 1501 * Limit hash to 13 bits since max bucket count is 8K. 1502 * Store result at the end of the input stream. 1503 */ 1504 input->formatted.bkt_hash = bucket_hash & 0x1FFF; 1505 } 1506 1507 /** 1508 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks 1509 * @input_mask: mask to be bit swapped 1510 * 1511 * The source and destination port masks for flow director are bit swapped 1512 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to 1513 * generate a correctly swapped value we need to bit swap the mask and that 1514 * is what is accomplished by this function. 1515 **/ 1516 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask) 1517 { 1518 u32 mask = ntohs(input_mask->formatted.dst_port); 1519 1520 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; 1521 mask |= ntohs(input_mask->formatted.src_port); 1522 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); 1523 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); 1524 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); 1525 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); 1526 } 1527 1528 /* 1529 * These two macros are meant to address the fact that we have registers 1530 * that are either all or in part big-endian. As a result on big-endian 1531 * systems we will end up byte swapping the value to little-endian before 1532 * it is byte swapped again and written to the hardware in the original 1533 * big-endian format. 1534 */ 1535 #define IXGBE_STORE_AS_BE32(_value) \ 1536 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \ 1537 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24)) 1538 1539 #define IXGBE_WRITE_REG_BE32(a, reg, value) \ 1540 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value))) 1541 1542 #define IXGBE_STORE_AS_BE16(_value) \ 1543 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8)) 1544 1545 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 1546 union ixgbe_atr_input *input_mask) 1547 { 1548 /* mask IPv6 since it is currently not supported */ 1549 u32 fdirm = IXGBE_FDIRM_DIPv6; 1550 u32 fdirtcpm; 1551 1552 /* 1553 * Program the relevant mask registers. If src/dst_port or src/dst_addr 1554 * are zero, then assume a full mask for that field. Also assume that 1555 * a VLAN of 0 is unspecified, so mask that out as well. L4type 1556 * cannot be masked out in this implementation. 1557 * 1558 * This also assumes IPv4 only. IPv6 masking isn't supported at this 1559 * point in time. 1560 */ 1561 1562 /* verify bucket hash is cleared on hash generation */ 1563 if (input_mask->formatted.bkt_hash) 1564 hw_dbg(hw, " bucket hash should always be 0 in mask\n"); 1565 1566 /* Program FDIRM and verify partial masks */ 1567 switch (input_mask->formatted.vm_pool & 0x7F) { 1568 case 0x0: 1569 fdirm |= IXGBE_FDIRM_POOL; 1570 case 0x7F: 1571 break; 1572 default: 1573 hw_dbg(hw, " Error on vm pool mask\n"); 1574 return IXGBE_ERR_CONFIG; 1575 } 1576 1577 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) { 1578 case 0x0: 1579 fdirm |= IXGBE_FDIRM_L4P; 1580 if (input_mask->formatted.dst_port || 1581 input_mask->formatted.src_port) { 1582 hw_dbg(hw, " Error on src/dst port mask\n"); 1583 return IXGBE_ERR_CONFIG; 1584 } 1585 case IXGBE_ATR_L4TYPE_MASK: 1586 break; 1587 default: 1588 hw_dbg(hw, " Error on flow type mask\n"); 1589 return IXGBE_ERR_CONFIG; 1590 } 1591 1592 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) { 1593 case 0x0000: 1594 /* mask VLAN ID */ 1595 fdirm |= IXGBE_FDIRM_VLANID; 1596 /* fall through */ 1597 case 0x0FFF: 1598 /* mask VLAN priority */ 1599 fdirm |= IXGBE_FDIRM_VLANP; 1600 break; 1601 case 0xE000: 1602 /* mask VLAN ID only */ 1603 fdirm |= IXGBE_FDIRM_VLANID; 1604 /* fall through */ 1605 case 0xEFFF: 1606 /* no VLAN fields masked */ 1607 break; 1608 default: 1609 hw_dbg(hw, " Error on VLAN mask\n"); 1610 return IXGBE_ERR_CONFIG; 1611 } 1612 1613 switch (input_mask->formatted.flex_bytes & 0xFFFF) { 1614 case 0x0000: 1615 /* Mask Flex Bytes */ 1616 fdirm |= IXGBE_FDIRM_FLEX; 1617 /* fall through */ 1618 case 0xFFFF: 1619 break; 1620 default: 1621 hw_dbg(hw, " Error on flexible byte mask\n"); 1622 return IXGBE_ERR_CONFIG; 1623 } 1624 1625 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ 1626 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); 1627 1628 /* store the TCP/UDP port masks, bit reversed from port layout */ 1629 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask); 1630 1631 /* write both the same so that UDP and TCP use the same mask */ 1632 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); 1633 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); 1634 1635 /* also use it for SCTP */ 1636 switch (hw->mac.type) { 1637 case ixgbe_mac_X550: 1638 case ixgbe_mac_X550EM_x: 1639 case ixgbe_mac_x550em_a: 1640 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm); 1641 break; 1642 default: 1643 break; 1644 } 1645 1646 /* store source and destination IP masks (big-enian) */ 1647 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 1648 ~input_mask->formatted.src_ip[0]); 1649 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 1650 ~input_mask->formatted.dst_ip[0]); 1651 1652 return 0; 1653 } 1654 1655 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 1656 union ixgbe_atr_input *input, 1657 u16 soft_id, u8 queue) 1658 { 1659 u32 fdirport, fdirvlan, fdirhash, fdircmd; 1660 s32 err; 1661 1662 /* currently IPv6 is not supported, must be programmed with 0 */ 1663 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), 1664 input->formatted.src_ip[0]); 1665 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), 1666 input->formatted.src_ip[1]); 1667 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), 1668 input->formatted.src_ip[2]); 1669 1670 /* record the source address (big-endian) */ 1671 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); 1672 1673 /* record the first 32 bits of the destination address (big-endian) */ 1674 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); 1675 1676 /* record source and destination port (little-endian)*/ 1677 fdirport = ntohs(input->formatted.dst_port); 1678 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT; 1679 fdirport |= ntohs(input->formatted.src_port); 1680 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); 1681 1682 /* record vlan (little-endian) and flex_bytes(big-endian) */ 1683 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); 1684 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT; 1685 fdirvlan |= ntohs(input->formatted.vlan_id); 1686 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); 1687 1688 /* configure FDIRHASH register */ 1689 fdirhash = input->formatted.bkt_hash; 1690 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1691 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1692 1693 /* 1694 * flush all previous writes to make certain registers are 1695 * programmed prior to issuing the command 1696 */ 1697 IXGBE_WRITE_FLUSH(hw); 1698 1699 /* configure FDIRCMD register */ 1700 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | 1701 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; 1702 if (queue == IXGBE_FDIR_DROP_QUEUE) 1703 fdircmd |= IXGBE_FDIRCMD_DROP; 1704 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; 1705 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; 1706 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; 1707 1708 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); 1709 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1710 if (err) { 1711 hw_dbg(hw, "Flow Director command did not complete!\n"); 1712 return err; 1713 } 1714 1715 return 0; 1716 } 1717 1718 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 1719 union ixgbe_atr_input *input, 1720 u16 soft_id) 1721 { 1722 u32 fdirhash; 1723 u32 fdircmd; 1724 s32 err; 1725 1726 /* configure FDIRHASH register */ 1727 fdirhash = input->formatted.bkt_hash; 1728 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT; 1729 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1730 1731 /* flush hash to HW */ 1732 IXGBE_WRITE_FLUSH(hw); 1733 1734 /* Query if filter is present */ 1735 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); 1736 1737 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); 1738 if (err) { 1739 hw_dbg(hw, "Flow Director command did not complete!\n"); 1740 return err; 1741 } 1742 1743 /* if filter exists in hardware then remove it */ 1744 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) { 1745 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); 1746 IXGBE_WRITE_FLUSH(hw); 1747 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, 1748 IXGBE_FDIRCMD_CMD_REMOVE_FLOW); 1749 } 1750 1751 return 0; 1752 } 1753 1754 /** 1755 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 1756 * @hw: pointer to hardware structure 1757 * @reg: analog register to read 1758 * @val: read value 1759 * 1760 * Performs read operation to Omer analog register specified. 1761 **/ 1762 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) 1763 { 1764 u32 core_ctl; 1765 1766 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 1767 (reg << 8)); 1768 IXGBE_WRITE_FLUSH(hw); 1769 udelay(10); 1770 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 1771 *val = (u8)core_ctl; 1772 1773 return 0; 1774 } 1775 1776 /** 1777 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 1778 * @hw: pointer to hardware structure 1779 * @reg: atlas register to write 1780 * @val: value to write 1781 * 1782 * Performs write operation to Omer analog register specified. 1783 **/ 1784 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) 1785 { 1786 u32 core_ctl; 1787 1788 core_ctl = (reg << 8) | val; 1789 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 1790 IXGBE_WRITE_FLUSH(hw); 1791 udelay(10); 1792 1793 return 0; 1794 } 1795 1796 /** 1797 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx 1798 * @hw: pointer to hardware structure 1799 * 1800 * Starts the hardware using the generic start_hw function 1801 * and the generation start_hw function. 1802 * Then performs revision-specific operations, if any. 1803 **/ 1804 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) 1805 { 1806 s32 ret_val = 0; 1807 1808 ret_val = ixgbe_start_hw_generic(hw); 1809 if (ret_val) 1810 return ret_val; 1811 1812 ret_val = ixgbe_start_hw_gen2(hw); 1813 if (ret_val) 1814 return ret_val; 1815 1816 /* We need to run link autotry after the driver loads */ 1817 hw->mac.autotry_restart = true; 1818 1819 return ixgbe_verify_fw_version_82599(hw); 1820 } 1821 1822 /** 1823 * ixgbe_identify_phy_82599 - Get physical layer module 1824 * @hw: pointer to hardware structure 1825 * 1826 * Determines the physical layer module found on the current adapter. 1827 * If PHY already detected, maintains current PHY type in hw struct, 1828 * otherwise executes the PHY detection routine. 1829 **/ 1830 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 1831 { 1832 s32 status; 1833 1834 /* Detect PHY if not unknown - returns success if already detected. */ 1835 status = ixgbe_identify_phy_generic(hw); 1836 if (status) { 1837 /* 82599 10GBASE-T requires an external PHY */ 1838 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 1839 return status; 1840 status = ixgbe_identify_module_generic(hw); 1841 } 1842 1843 /* Set PHY type none if no PHY detected */ 1844 if (hw->phy.type == ixgbe_phy_unknown) { 1845 hw->phy.type = ixgbe_phy_none; 1846 status = 0; 1847 } 1848 1849 /* Return error if SFP module has been detected but is not supported */ 1850 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1851 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1852 1853 return status; 1854 } 1855 1856 /** 1857 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 1858 * @hw: pointer to hardware structure 1859 * @regval: register value to write to RXCTRL 1860 * 1861 * Enables the Rx DMA unit for 82599 1862 **/ 1863 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 1864 { 1865 /* 1866 * Workaround for 82599 silicon errata when enabling the Rx datapath. 1867 * If traffic is incoming before we enable the Rx unit, it could hang 1868 * the Rx DMA unit. Therefore, make sure the security engine is 1869 * completely disabled prior to enabling the Rx unit. 1870 */ 1871 hw->mac.ops.disable_rx_buff(hw); 1872 1873 if (regval & IXGBE_RXCTRL_RXEN) 1874 hw->mac.ops.enable_rx(hw); 1875 else 1876 hw->mac.ops.disable_rx(hw); 1877 1878 hw->mac.ops.enable_rx_buff(hw); 1879 1880 return 0; 1881 } 1882 1883 /** 1884 * ixgbe_verify_fw_version_82599 - verify fw version for 82599 1885 * @hw: pointer to hardware structure 1886 * 1887 * Verifies that installed the firmware version is 0.6 or higher 1888 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 1889 * 1890 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 1891 * if the FW version is not supported. 1892 **/ 1893 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 1894 { 1895 s32 status = IXGBE_ERR_EEPROM_VERSION; 1896 u16 fw_offset, fw_ptp_cfg_offset; 1897 u16 offset; 1898 u16 fw_version = 0; 1899 1900 /* firmware check is only necessary for SFI devices */ 1901 if (hw->phy.media_type != ixgbe_media_type_fiber) 1902 return 0; 1903 1904 /* get the offset to the Firmware Module block */ 1905 offset = IXGBE_FW_PTR; 1906 if (hw->eeprom.ops.read(hw, offset, &fw_offset)) 1907 goto fw_version_err; 1908 1909 if (fw_offset == 0 || fw_offset == 0xFFFF) 1910 return IXGBE_ERR_EEPROM_VERSION; 1911 1912 /* get the offset to the Pass Through Patch Configuration block */ 1913 offset = fw_offset + IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR; 1914 if (hw->eeprom.ops.read(hw, offset, &fw_ptp_cfg_offset)) 1915 goto fw_version_err; 1916 1917 if (fw_ptp_cfg_offset == 0 || fw_ptp_cfg_offset == 0xFFFF) 1918 return IXGBE_ERR_EEPROM_VERSION; 1919 1920 /* get the firmware version */ 1921 offset = fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4; 1922 if (hw->eeprom.ops.read(hw, offset, &fw_version)) 1923 goto fw_version_err; 1924 1925 if (fw_version > 0x5) 1926 status = 0; 1927 1928 return status; 1929 1930 fw_version_err: 1931 hw_err(hw, "eeprom read at offset %d failed\n", offset); 1932 return IXGBE_ERR_EEPROM_VERSION; 1933 } 1934 1935 /** 1936 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 1937 * @hw: pointer to hardware structure 1938 * 1939 * Returns true if the LESM FW module is present and enabled. Otherwise 1940 * returns false. Smart Speed must be disabled if LESM FW module is enabled. 1941 **/ 1942 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 1943 { 1944 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state; 1945 s32 status; 1946 1947 /* get the offset to the Firmware Module block */ 1948 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 1949 1950 if (status || fw_offset == 0 || fw_offset == 0xFFFF) 1951 return false; 1952 1953 /* get the offset to the LESM Parameters block */ 1954 status = hw->eeprom.ops.read(hw, (fw_offset + 1955 IXGBE_FW_LESM_PARAMETERS_PTR), 1956 &fw_lesm_param_offset); 1957 1958 if (status || 1959 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF) 1960 return false; 1961 1962 /* get the lesm state word */ 1963 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 1964 IXGBE_FW_LESM_STATE_1), 1965 &fw_lesm_state); 1966 1967 if (!status && (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 1968 return true; 1969 1970 return false; 1971 } 1972 1973 /** 1974 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using 1975 * fastest available method 1976 * 1977 * @hw: pointer to hardware structure 1978 * @offset: offset of word in EEPROM to read 1979 * @words: number of words 1980 * @data: word(s) read from the EEPROM 1981 * 1982 * Retrieves 16 bit word(s) read from EEPROM 1983 **/ 1984 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, 1985 u16 words, u16 *data) 1986 { 1987 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1988 1989 /* If EEPROM is detected and can be addressed using 14 bits, 1990 * use EERD otherwise use bit bang 1991 */ 1992 if (eeprom->type == ixgbe_eeprom_spi && 1993 offset + (words - 1) <= IXGBE_EERD_MAX_ADDR) 1994 return ixgbe_read_eerd_buffer_generic(hw, offset, words, data); 1995 1996 return ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, words, 1997 data); 1998 } 1999 2000 /** 2001 * ixgbe_read_eeprom_82599 - Read EEPROM word using 2002 * fastest available method 2003 * 2004 * @hw: pointer to hardware structure 2005 * @offset: offset of word in the EEPROM to read 2006 * @data: word read from the EEPROM 2007 * 2008 * Reads a 16 bit word from the EEPROM 2009 **/ 2010 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 2011 u16 offset, u16 *data) 2012 { 2013 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 2014 2015 /* 2016 * If EEPROM is detected and can be addressed using 14 bits, 2017 * use EERD otherwise use bit bang 2018 */ 2019 if (eeprom->type == ixgbe_eeprom_spi && offset <= IXGBE_EERD_MAX_ADDR) 2020 return ixgbe_read_eerd_generic(hw, offset, data); 2021 2022 return ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); 2023 } 2024 2025 /** 2026 * ixgbe_reset_pipeline_82599 - perform pipeline reset 2027 * 2028 * @hw: pointer to hardware structure 2029 * 2030 * Reset pipeline by asserting Restart_AN together with LMS change to ensure 2031 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing 2032 * to AUTOC, so this function assumes the semaphore is held. 2033 **/ 2034 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) 2035 { 2036 s32 ret_val; 2037 u32 anlp1_reg = 0; 2038 u32 i, autoc_reg, autoc2_reg; 2039 2040 /* Enable link if disabled in NVM */ 2041 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 2042 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 2043 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 2044 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 2045 IXGBE_WRITE_FLUSH(hw); 2046 } 2047 2048 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2049 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2050 2051 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */ 2052 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, 2053 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT)); 2054 2055 /* Wait for AN to leave state 0 */ 2056 for (i = 0; i < 10; i++) { 2057 usleep_range(4000, 8000); 2058 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2059 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK) 2060 break; 2061 } 2062 2063 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) { 2064 hw_dbg(hw, "auto negotiation not completed\n"); 2065 ret_val = IXGBE_ERR_RESET_FAILED; 2066 goto reset_pipeline_out; 2067 } 2068 2069 ret_val = 0; 2070 2071 reset_pipeline_out: 2072 /* Write AUTOC register with original LMS field and Restart_AN */ 2073 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2074 IXGBE_WRITE_FLUSH(hw); 2075 2076 return ret_val; 2077 } 2078 2079 /** 2080 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C 2081 * @hw: pointer to hardware structure 2082 * @byte_offset: byte offset to read 2083 * @dev_addr: address to read from 2084 * @data: value read 2085 * 2086 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2087 * a specified device address. 2088 **/ 2089 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2090 u8 dev_addr, u8 *data) 2091 { 2092 u32 esdp; 2093 s32 status; 2094 s32 timeout = 200; 2095 2096 if (hw->phy.qsfp_shared_i2c_bus == true) { 2097 /* Acquire I2C bus ownership. */ 2098 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2099 esdp |= IXGBE_ESDP_SDP0; 2100 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2101 IXGBE_WRITE_FLUSH(hw); 2102 2103 while (timeout) { 2104 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2105 if (esdp & IXGBE_ESDP_SDP1) 2106 break; 2107 2108 usleep_range(5000, 10000); 2109 timeout--; 2110 } 2111 2112 if (!timeout) { 2113 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n"); 2114 status = IXGBE_ERR_I2C; 2115 goto release_i2c_access; 2116 } 2117 } 2118 2119 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2120 2121 release_i2c_access: 2122 if (hw->phy.qsfp_shared_i2c_bus == true) { 2123 /* Release I2C bus ownership. */ 2124 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2125 esdp &= ~IXGBE_ESDP_SDP0; 2126 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2127 IXGBE_WRITE_FLUSH(hw); 2128 } 2129 2130 return status; 2131 } 2132 2133 /** 2134 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C 2135 * @hw: pointer to hardware structure 2136 * @byte_offset: byte offset to write 2137 * @dev_addr: address to write to 2138 * @data: value to write 2139 * 2140 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2141 * a specified device address. 2142 **/ 2143 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, 2144 u8 dev_addr, u8 data) 2145 { 2146 u32 esdp; 2147 s32 status; 2148 s32 timeout = 200; 2149 2150 if (hw->phy.qsfp_shared_i2c_bus == true) { 2151 /* Acquire I2C bus ownership. */ 2152 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2153 esdp |= IXGBE_ESDP_SDP0; 2154 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2155 IXGBE_WRITE_FLUSH(hw); 2156 2157 while (timeout) { 2158 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2159 if (esdp & IXGBE_ESDP_SDP1) 2160 break; 2161 2162 usleep_range(5000, 10000); 2163 timeout--; 2164 } 2165 2166 if (!timeout) { 2167 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n"); 2168 status = IXGBE_ERR_I2C; 2169 goto release_i2c_access; 2170 } 2171 } 2172 2173 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data); 2174 2175 release_i2c_access: 2176 if (hw->phy.qsfp_shared_i2c_bus == true) { 2177 /* Release I2C bus ownership. */ 2178 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2179 esdp &= ~IXGBE_ESDP_SDP0; 2180 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2181 IXGBE_WRITE_FLUSH(hw); 2182 } 2183 2184 return status; 2185 } 2186 2187 static const struct ixgbe_mac_operations mac_ops_82599 = { 2188 .init_hw = &ixgbe_init_hw_generic, 2189 .reset_hw = &ixgbe_reset_hw_82599, 2190 .start_hw = &ixgbe_start_hw_82599, 2191 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 2192 .get_media_type = &ixgbe_get_media_type_82599, 2193 .enable_rx_dma = &ixgbe_enable_rx_dma_82599, 2194 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, 2195 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, 2196 .get_mac_addr = &ixgbe_get_mac_addr_generic, 2197 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 2198 .get_device_caps = &ixgbe_get_device_caps_generic, 2199 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 2200 .stop_adapter = &ixgbe_stop_adapter_generic, 2201 .get_bus_info = &ixgbe_get_bus_info_generic, 2202 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, 2203 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599, 2204 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599, 2205 .stop_link_on_d3 = &ixgbe_stop_mac_link_on_d3_82599, 2206 .setup_link = &ixgbe_setup_mac_link_82599, 2207 .set_rxpba = &ixgbe_set_rxpba_generic, 2208 .check_link = &ixgbe_check_mac_link_generic, 2209 .get_link_capabilities = &ixgbe_get_link_capabilities_82599, 2210 .led_on = &ixgbe_led_on_generic, 2211 .led_off = &ixgbe_led_off_generic, 2212 .init_led_link_act = ixgbe_init_led_link_act_generic, 2213 .blink_led_start = &ixgbe_blink_led_start_generic, 2214 .blink_led_stop = &ixgbe_blink_led_stop_generic, 2215 .set_rar = &ixgbe_set_rar_generic, 2216 .clear_rar = &ixgbe_clear_rar_generic, 2217 .set_vmdq = &ixgbe_set_vmdq_generic, 2218 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, 2219 .clear_vmdq = &ixgbe_clear_vmdq_generic, 2220 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 2221 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 2222 .enable_mc = &ixgbe_enable_mc_generic, 2223 .disable_mc = &ixgbe_disable_mc_generic, 2224 .clear_vfta = &ixgbe_clear_vfta_generic, 2225 .set_vfta = &ixgbe_set_vfta_generic, 2226 .fc_enable = &ixgbe_fc_enable_generic, 2227 .setup_fc = ixgbe_setup_fc_generic, 2228 .fc_autoneg = ixgbe_fc_autoneg, 2229 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, 2230 .init_uta_tables = &ixgbe_init_uta_tables_generic, 2231 .setup_sfp = &ixgbe_setup_sfp_modules_82599, 2232 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, 2233 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, 2234 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync, 2235 .release_swfw_sync = &ixgbe_release_swfw_sync, 2236 .init_swfw_sync = NULL, 2237 .get_thermal_sensor_data = &ixgbe_get_thermal_sensor_data_generic, 2238 .init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic, 2239 .prot_autoc_read = &prot_autoc_read_82599, 2240 .prot_autoc_write = &prot_autoc_write_82599, 2241 .enable_rx = &ixgbe_enable_rx_generic, 2242 .disable_rx = &ixgbe_disable_rx_generic, 2243 }; 2244 2245 static const struct ixgbe_eeprom_operations eeprom_ops_82599 = { 2246 .init_params = &ixgbe_init_eeprom_params_generic, 2247 .read = &ixgbe_read_eeprom_82599, 2248 .read_buffer = &ixgbe_read_eeprom_buffer_82599, 2249 .write = &ixgbe_write_eeprom_generic, 2250 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic, 2251 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, 2252 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 2253 .update_checksum = &ixgbe_update_eeprom_checksum_generic, 2254 }; 2255 2256 static const struct ixgbe_phy_operations phy_ops_82599 = { 2257 .identify = &ixgbe_identify_phy_82599, 2258 .identify_sfp = &ixgbe_identify_module_generic, 2259 .init = &ixgbe_init_phy_ops_82599, 2260 .reset = &ixgbe_reset_phy_generic, 2261 .read_reg = &ixgbe_read_phy_reg_generic, 2262 .write_reg = &ixgbe_write_phy_reg_generic, 2263 .setup_link = &ixgbe_setup_phy_link_generic, 2264 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 2265 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, 2266 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, 2267 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, 2268 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, 2269 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, 2270 .check_overtemp = &ixgbe_tn_check_overtemp, 2271 }; 2272 2273 const struct ixgbe_info ixgbe_82599_info = { 2274 .mac = ixgbe_mac_82599EB, 2275 .get_invariants = &ixgbe_get_invariants_82599, 2276 .mac_ops = &mac_ops_82599, 2277 .eeprom_ops = &eeprom_ops_82599, 2278 .phy_ops = &phy_ops_82599, 2279 .mbx_ops = &mbx_ops_generic, 2280 .mvals = ixgbe_mvals_8259X, 2281 }; 2282