1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include <linux/pci.h> 29 #include <linux/delay.h> 30 #include <linux/sched.h> 31 32 #include "ixgbe.h" 33 #include "ixgbe_phy.h" 34 35 #define IXGBE_82598_MAX_TX_QUEUES 32 36 #define IXGBE_82598_MAX_RX_QUEUES 64 37 #define IXGBE_82598_RAR_ENTRIES 16 38 #define IXGBE_82598_MC_TBL_SIZE 128 39 #define IXGBE_82598_VFT_TBL_SIZE 128 40 #define IXGBE_82598_RX_PB_SIZE 512 41 42 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 43 ixgbe_link_speed speed, 44 bool autoneg, 45 bool autoneg_wait_to_complete); 46 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 47 u8 *eeprom_data); 48 49 /** 50 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout 51 * @hw: pointer to the HW structure 52 * 53 * The defaults for 82598 should be in the range of 50us to 50ms, 54 * however the hardware default for these parts is 500us to 1ms which is less 55 * than the 10ms recommended by the pci-e spec. To address this we need to 56 * increase the value to either 10ms to 250ms for capability version 1 config, 57 * or 16ms to 55ms for version 2. 58 **/ 59 static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) 60 { 61 struct ixgbe_adapter *adapter = hw->back; 62 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); 63 u16 pcie_devctl2; 64 65 /* only take action if timeout value is defaulted to 0 */ 66 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) 67 goto out; 68 69 /* 70 * if capababilities version is type 1 we can write the 71 * timeout of 10ms to 250ms through the GCR register 72 */ 73 if (!(gcr & IXGBE_GCR_CAP_VER2)) { 74 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; 75 goto out; 76 } 77 78 /* 79 * for version 2 capabilities we need to write the config space 80 * directly in order to set the completion timeout value for 81 * 16ms to 55ms 82 */ 83 pci_read_config_word(adapter->pdev, 84 IXGBE_PCI_DEVICE_CONTROL2, &pcie_devctl2); 85 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; 86 pci_write_config_word(adapter->pdev, 87 IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); 88 out: 89 /* disable completion timeout resend */ 90 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; 91 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); 92 } 93 94 /** 95 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count 96 * @hw: pointer to hardware structure 97 * 98 * Read PCIe configuration space, and get the MSI-X vector count from 99 * the capabilities table. 100 **/ 101 static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw) 102 { 103 struct ixgbe_adapter *adapter = hw->back; 104 u16 msix_count; 105 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS, 106 &msix_count); 107 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 108 109 /* MSI-X count is zero-based in HW, so increment to give proper value */ 110 msix_count++; 111 112 return msix_count; 113 } 114 115 /** 116 */ 117 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) 118 { 119 struct ixgbe_mac_info *mac = &hw->mac; 120 121 /* Call PHY identify routine to get the phy type */ 122 ixgbe_identify_phy_generic(hw); 123 124 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; 125 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; 126 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; 127 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; 128 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; 129 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw); 130 131 return 0; 132 } 133 134 /** 135 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init 136 * @hw: pointer to hardware structure 137 * 138 * Initialize any function pointers that were not able to be 139 * set during get_invariants because the PHY/SFP type was 140 * not known. Perform the SFP init if necessary. 141 * 142 **/ 143 static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) 144 { 145 struct ixgbe_mac_info *mac = &hw->mac; 146 struct ixgbe_phy_info *phy = &hw->phy; 147 s32 ret_val = 0; 148 u16 list_offset, data_offset; 149 150 /* Identify the PHY */ 151 phy->ops.identify(hw); 152 153 /* Overwrite the link function pointers if copper PHY */ 154 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 155 mac->ops.setup_link = &ixgbe_setup_copper_link_82598; 156 mac->ops.get_link_capabilities = 157 &ixgbe_get_copper_link_capabilities_generic; 158 } 159 160 switch (hw->phy.type) { 161 case ixgbe_phy_tn: 162 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 163 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 164 phy->ops.get_firmware_version = 165 &ixgbe_get_phy_firmware_version_tnx; 166 break; 167 case ixgbe_phy_nl: 168 phy->ops.reset = &ixgbe_reset_phy_nl; 169 170 /* Call SFP+ identify routine to get the SFP+ module type */ 171 ret_val = phy->ops.identify_sfp(hw); 172 if (ret_val != 0) 173 goto out; 174 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { 175 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 176 goto out; 177 } 178 179 /* Check to see if SFP+ module is supported */ 180 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, 181 &list_offset, 182 &data_offset); 183 if (ret_val != 0) { 184 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 185 goto out; 186 } 187 break; 188 default: 189 break; 190 } 191 192 out: 193 return ret_val; 194 } 195 196 /** 197 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx 198 * @hw: pointer to hardware structure 199 * 200 * Starts the hardware using the generic start_hw function. 201 * Disables relaxed ordering Then set pcie completion timeout 202 * 203 **/ 204 static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) 205 { 206 u32 regval; 207 u32 i; 208 s32 ret_val = 0; 209 210 ret_val = ixgbe_start_hw_generic(hw); 211 212 /* Disable relaxed ordering */ 213 for (i = 0; ((i < hw->mac.max_tx_queues) && 214 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 215 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 216 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 217 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); 218 } 219 220 for (i = 0; ((i < hw->mac.max_rx_queues) && 221 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 222 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 223 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 224 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 225 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 226 } 227 228 hw->mac.rx_pb_size = IXGBE_82598_RX_PB_SIZE; 229 230 /* set the completion timeout for interface */ 231 if (ret_val == 0) 232 ixgbe_set_pcie_completion_timeout(hw); 233 234 return ret_val; 235 } 236 237 /** 238 * ixgbe_get_link_capabilities_82598 - Determines link capabilities 239 * @hw: pointer to hardware structure 240 * @speed: pointer to link speed 241 * @autoneg: boolean auto-negotiation value 242 * 243 * Determines the link capabilities by reading the AUTOC register. 244 **/ 245 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 246 ixgbe_link_speed *speed, 247 bool *autoneg) 248 { 249 s32 status = 0; 250 u32 autoc = 0; 251 252 /* 253 * Determine link capabilities based on the stored value of AUTOC, 254 * which represents EEPROM defaults. If AUTOC value has not been 255 * stored, use the current register value. 256 */ 257 if (hw->mac.orig_link_settings_stored) 258 autoc = hw->mac.orig_autoc; 259 else 260 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 261 262 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 263 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 264 *speed = IXGBE_LINK_SPEED_1GB_FULL; 265 *autoneg = false; 266 break; 267 268 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 269 *speed = IXGBE_LINK_SPEED_10GB_FULL; 270 *autoneg = false; 271 break; 272 273 case IXGBE_AUTOC_LMS_1G_AN: 274 *speed = IXGBE_LINK_SPEED_1GB_FULL; 275 *autoneg = true; 276 break; 277 278 case IXGBE_AUTOC_LMS_KX4_AN: 279 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 280 *speed = IXGBE_LINK_SPEED_UNKNOWN; 281 if (autoc & IXGBE_AUTOC_KX4_SUPP) 282 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 283 if (autoc & IXGBE_AUTOC_KX_SUPP) 284 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 285 *autoneg = true; 286 break; 287 288 default: 289 status = IXGBE_ERR_LINK_SETUP; 290 break; 291 } 292 293 return status; 294 } 295 296 /** 297 * ixgbe_get_media_type_82598 - Determines media type 298 * @hw: pointer to hardware structure 299 * 300 * Returns the media type (fiber, copper, backplane) 301 **/ 302 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 303 { 304 enum ixgbe_media_type media_type; 305 306 /* Detect if there is a copper PHY attached. */ 307 switch (hw->phy.type) { 308 case ixgbe_phy_cu_unknown: 309 case ixgbe_phy_tn: 310 media_type = ixgbe_media_type_copper; 311 goto out; 312 default: 313 break; 314 } 315 316 /* Media type for I82598 is based on device ID */ 317 switch (hw->device_id) { 318 case IXGBE_DEV_ID_82598: 319 case IXGBE_DEV_ID_82598_BX: 320 /* Default device ID is mezzanine card KX/KX4 */ 321 media_type = ixgbe_media_type_backplane; 322 break; 323 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 324 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 325 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 326 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 327 case IXGBE_DEV_ID_82598EB_XF_LR: 328 case IXGBE_DEV_ID_82598EB_SFP_LOM: 329 media_type = ixgbe_media_type_fiber; 330 break; 331 case IXGBE_DEV_ID_82598EB_CX4: 332 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 333 media_type = ixgbe_media_type_cx4; 334 break; 335 case IXGBE_DEV_ID_82598AT: 336 case IXGBE_DEV_ID_82598AT2: 337 media_type = ixgbe_media_type_copper; 338 break; 339 default: 340 media_type = ixgbe_media_type_unknown; 341 break; 342 } 343 out: 344 return media_type; 345 } 346 347 /** 348 * ixgbe_fc_enable_82598 - Enable flow control 349 * @hw: pointer to hardware structure 350 * @packetbuf_num: packet buffer number (0-7) 351 * 352 * Enable flow control according to the current settings. 353 **/ 354 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) 355 { 356 s32 ret_val = 0; 357 u32 fctrl_reg; 358 u32 rmcs_reg; 359 u32 reg; 360 u32 link_speed = 0; 361 bool link_up; 362 363 #ifdef CONFIG_DCB 364 if (hw->fc.requested_mode == ixgbe_fc_pfc) 365 goto out; 366 367 #endif /* CONFIG_DCB */ 368 /* 369 * On 82598 having Rx FC on causes resets while doing 1G 370 * so if it's on turn it off once we know link_speed. For 371 * more details see 82598 Specification update. 372 */ 373 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 374 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) { 375 switch (hw->fc.requested_mode) { 376 case ixgbe_fc_full: 377 hw->fc.requested_mode = ixgbe_fc_tx_pause; 378 break; 379 case ixgbe_fc_rx_pause: 380 hw->fc.requested_mode = ixgbe_fc_none; 381 break; 382 default: 383 /* no change */ 384 break; 385 } 386 } 387 388 /* Negotiate the fc mode to use */ 389 ret_val = ixgbe_fc_autoneg(hw); 390 if (ret_val == IXGBE_ERR_FLOW_CONTROL) 391 goto out; 392 393 /* Disable any previous flow control settings */ 394 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 395 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 396 397 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 398 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 399 400 /* 401 * The possible values of fc.current_mode are: 402 * 0: Flow control is completely disabled 403 * 1: Rx flow control is enabled (we can receive pause frames, 404 * but not send pause frames). 405 * 2: Tx flow control is enabled (we can send pause frames but 406 * we do not support receiving pause frames). 407 * 3: Both Rx and Tx flow control (symmetric) are enabled. 408 #ifdef CONFIG_DCB 409 * 4: Priority Flow Control is enabled. 410 #endif 411 * other: Invalid. 412 */ 413 switch (hw->fc.current_mode) { 414 case ixgbe_fc_none: 415 /* 416 * Flow control is disabled by software override or autoneg. 417 * The code below will actually disable it in the HW. 418 */ 419 break; 420 case ixgbe_fc_rx_pause: 421 /* 422 * Rx Flow control is enabled and Tx Flow control is 423 * disabled by software override. Since there really 424 * isn't a way to advertise that we are capable of RX 425 * Pause ONLY, we will advertise that we support both 426 * symmetric and asymmetric Rx PAUSE. Later, we will 427 * disable the adapter's ability to send PAUSE frames. 428 */ 429 fctrl_reg |= IXGBE_FCTRL_RFCE; 430 break; 431 case ixgbe_fc_tx_pause: 432 /* 433 * Tx Flow control is enabled, and Rx Flow control is 434 * disabled by software override. 435 */ 436 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 437 break; 438 case ixgbe_fc_full: 439 /* Flow control (both Rx and Tx) is enabled by SW override. */ 440 fctrl_reg |= IXGBE_FCTRL_RFCE; 441 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 442 break; 443 #ifdef CONFIG_DCB 444 case ixgbe_fc_pfc: 445 goto out; 446 break; 447 #endif /* CONFIG_DCB */ 448 default: 449 hw_dbg(hw, "Flow control param set incorrectly\n"); 450 ret_val = IXGBE_ERR_CONFIG; 451 goto out; 452 break; 453 } 454 455 /* Set 802.3x based flow control settings. */ 456 fctrl_reg |= IXGBE_FCTRL_DPF; 457 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); 458 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 459 460 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 461 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 462 reg = hw->fc.low_water << 6; 463 if (hw->fc.send_xon) 464 reg |= IXGBE_FCRTL_XONE; 465 466 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg); 467 468 reg = hw->fc.high_water[packetbuf_num] << 6; 469 reg |= IXGBE_FCRTH_FCEN; 470 471 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg); 472 } 473 474 /* Configure pause time (2 TCs per register) */ 475 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); 476 if ((packetbuf_num & 1) == 0) 477 reg = (reg & 0xFFFF0000) | hw->fc.pause_time; 478 else 479 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); 480 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); 481 482 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 483 484 out: 485 return ret_val; 486 } 487 488 /** 489 * ixgbe_start_mac_link_82598 - Configures MAC link settings 490 * @hw: pointer to hardware structure 491 * 492 * Configures link settings based on values in the ixgbe_hw struct. 493 * Restarts the link. Performs autonegotiation if needed. 494 **/ 495 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, 496 bool autoneg_wait_to_complete) 497 { 498 u32 autoc_reg; 499 u32 links_reg; 500 u32 i; 501 s32 status = 0; 502 503 /* Restart link */ 504 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 505 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 506 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 507 508 /* Only poll for autoneg to complete if specified to do so */ 509 if (autoneg_wait_to_complete) { 510 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 511 IXGBE_AUTOC_LMS_KX4_AN || 512 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 513 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 514 links_reg = 0; /* Just in case Autoneg time = 0 */ 515 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 516 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 517 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 518 break; 519 msleep(100); 520 } 521 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 522 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 523 hw_dbg(hw, "Autonegotiation did not complete.\n"); 524 } 525 } 526 } 527 528 /* Add delay to filter out noises during initial link setup */ 529 msleep(50); 530 531 return status; 532 } 533 534 /** 535 * ixgbe_validate_link_ready - Function looks for phy link 536 * @hw: pointer to hardware structure 537 * 538 * Function indicates success when phy link is available. If phy is not ready 539 * within 5 seconds of MAC indicating link, the function returns error. 540 **/ 541 static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) 542 { 543 u32 timeout; 544 u16 an_reg; 545 546 if (hw->device_id != IXGBE_DEV_ID_82598AT2) 547 return 0; 548 549 for (timeout = 0; 550 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) { 551 hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg); 552 553 if ((an_reg & MDIO_AN_STAT1_COMPLETE) && 554 (an_reg & MDIO_STAT1_LSTATUS)) 555 break; 556 557 msleep(100); 558 } 559 560 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) { 561 hw_dbg(hw, "Link was indicated but link is down\n"); 562 return IXGBE_ERR_LINK_SETUP; 563 } 564 565 return 0; 566 } 567 568 /** 569 * ixgbe_check_mac_link_82598 - Get link/speed status 570 * @hw: pointer to hardware structure 571 * @speed: pointer to link speed 572 * @link_up: true is link is up, false otherwise 573 * @link_up_wait_to_complete: bool used to wait for link up or not 574 * 575 * Reads the links register to determine if link is up and the current speed 576 **/ 577 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 578 ixgbe_link_speed *speed, bool *link_up, 579 bool link_up_wait_to_complete) 580 { 581 u32 links_reg; 582 u32 i; 583 u16 link_reg, adapt_comp_reg; 584 585 /* 586 * SERDES PHY requires us to read link status from register 0xC79F. 587 * Bit 0 set indicates link is up/ready; clear indicates link down. 588 * 0xC00C is read to check that the XAUI lanes are active. Bit 0 589 * clear indicates active; set indicates inactive. 590 */ 591 if (hw->phy.type == ixgbe_phy_nl) { 592 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); 593 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); 594 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD, 595 &adapt_comp_reg); 596 if (link_up_wait_to_complete) { 597 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 598 if ((link_reg & 1) && 599 ((adapt_comp_reg & 1) == 0)) { 600 *link_up = true; 601 break; 602 } else { 603 *link_up = false; 604 } 605 msleep(100); 606 hw->phy.ops.read_reg(hw, 0xC79F, 607 MDIO_MMD_PMAPMD, 608 &link_reg); 609 hw->phy.ops.read_reg(hw, 0xC00C, 610 MDIO_MMD_PMAPMD, 611 &adapt_comp_reg); 612 } 613 } else { 614 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) 615 *link_up = true; 616 else 617 *link_up = false; 618 } 619 620 if (!*link_up) 621 goto out; 622 } 623 624 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 625 if (link_up_wait_to_complete) { 626 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 627 if (links_reg & IXGBE_LINKS_UP) { 628 *link_up = true; 629 break; 630 } else { 631 *link_up = false; 632 } 633 msleep(100); 634 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 635 } 636 } else { 637 if (links_reg & IXGBE_LINKS_UP) 638 *link_up = true; 639 else 640 *link_up = false; 641 } 642 643 if (links_reg & IXGBE_LINKS_SPEED) 644 *speed = IXGBE_LINK_SPEED_10GB_FULL; 645 else 646 *speed = IXGBE_LINK_SPEED_1GB_FULL; 647 648 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && *link_up && 649 (ixgbe_validate_link_ready(hw) != 0)) 650 *link_up = false; 651 652 out: 653 return 0; 654 } 655 656 /** 657 * ixgbe_setup_mac_link_82598 - Set MAC link speed 658 * @hw: pointer to hardware structure 659 * @speed: new link speed 660 * @autoneg: true if auto-negotiation enabled 661 * @autoneg_wait_to_complete: true when waiting for completion is needed 662 * 663 * Set the link speed in the AUTOC register and restarts link. 664 **/ 665 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, 666 ixgbe_link_speed speed, bool autoneg, 667 bool autoneg_wait_to_complete) 668 { 669 s32 status = 0; 670 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 671 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 672 u32 autoc = curr_autoc; 673 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 674 675 /* Check to see if speed passed in is supported. */ 676 ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg); 677 speed &= link_capabilities; 678 679 if (speed == IXGBE_LINK_SPEED_UNKNOWN) 680 status = IXGBE_ERR_LINK_SETUP; 681 682 /* Set KX4/KX support according to speed requested */ 683 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || 684 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 685 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; 686 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 687 autoc |= IXGBE_AUTOC_KX4_SUPP; 688 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 689 autoc |= IXGBE_AUTOC_KX_SUPP; 690 if (autoc != curr_autoc) 691 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 692 } 693 694 if (status == 0) { 695 /* 696 * Setup and restart the link based on the new values in 697 * ixgbe_hw This will write the AUTOC register based on the new 698 * stored values 699 */ 700 status = ixgbe_start_mac_link_82598(hw, 701 autoneg_wait_to_complete); 702 } 703 704 return status; 705 } 706 707 708 /** 709 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field 710 * @hw: pointer to hardware structure 711 * @speed: new link speed 712 * @autoneg: true if autonegotiation enabled 713 * @autoneg_wait_to_complete: true if waiting is needed to complete 714 * 715 * Sets the link speed in the AUTOC register in the MAC and restarts link. 716 **/ 717 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 718 ixgbe_link_speed speed, 719 bool autoneg, 720 bool autoneg_wait_to_complete) 721 { 722 s32 status; 723 724 /* Setup the PHY according to input speed */ 725 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 726 autoneg_wait_to_complete); 727 /* Set up MAC */ 728 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); 729 730 return status; 731 } 732 733 /** 734 * ixgbe_reset_hw_82598 - Performs hardware reset 735 * @hw: pointer to hardware structure 736 * 737 * Resets the hardware by resetting the transmit and receive units, masks and 738 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 739 * reset. 740 **/ 741 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 742 { 743 s32 status = 0; 744 s32 phy_status = 0; 745 u32 ctrl; 746 u32 gheccr; 747 u32 i; 748 u32 autoc; 749 u8 analog_val; 750 751 /* Call adapter stop to disable tx/rx and clear interrupts */ 752 status = hw->mac.ops.stop_adapter(hw); 753 if (status != 0) 754 goto reset_hw_out; 755 756 /* 757 * Power up the Atlas Tx lanes if they are currently powered down. 758 * Atlas Tx lanes are powered down for MAC loopback tests, but 759 * they are not automatically restored on reset. 760 */ 761 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 762 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 763 /* Enable Tx Atlas so packets can be transmitted again */ 764 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 765 &analog_val); 766 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 767 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 768 analog_val); 769 770 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 771 &analog_val); 772 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 773 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 774 analog_val); 775 776 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 777 &analog_val); 778 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 779 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 780 analog_val); 781 782 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 783 &analog_val); 784 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 785 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 786 analog_val); 787 } 788 789 /* Reset PHY */ 790 if (hw->phy.reset_disable == false) { 791 /* PHY ops must be identified and initialized prior to reset */ 792 793 /* Init PHY and function pointers, perform SFP setup */ 794 phy_status = hw->phy.ops.init(hw); 795 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) 796 goto reset_hw_out; 797 if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) 798 goto mac_reset_top; 799 800 hw->phy.ops.reset(hw); 801 } 802 803 mac_reset_top: 804 /* 805 * Issue global reset to the MAC. This needs to be a SW reset. 806 * If link reset is used, it might reset the MAC when mng is using it 807 */ 808 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST; 809 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 810 IXGBE_WRITE_FLUSH(hw); 811 812 /* Poll for reset bit to self-clear indicating reset is complete */ 813 for (i = 0; i < 10; i++) { 814 udelay(1); 815 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 816 if (!(ctrl & IXGBE_CTRL_RST)) 817 break; 818 } 819 if (ctrl & IXGBE_CTRL_RST) { 820 status = IXGBE_ERR_RESET_FAILED; 821 hw_dbg(hw, "Reset polling failed to complete.\n"); 822 } 823 824 msleep(50); 825 826 /* 827 * Double resets are required for recovery from certain error 828 * conditions. Between resets, it is necessary to stall to allow time 829 * for any pending HW events to complete. 830 */ 831 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 832 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 833 goto mac_reset_top; 834 } 835 836 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 837 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 838 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 839 840 /* 841 * Store the original AUTOC value if it has not been 842 * stored off yet. Otherwise restore the stored original 843 * AUTOC value since the reset operation sets back to deaults. 844 */ 845 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 846 if (hw->mac.orig_link_settings_stored == false) { 847 hw->mac.orig_autoc = autoc; 848 hw->mac.orig_link_settings_stored = true; 849 } else if (autoc != hw->mac.orig_autoc) { 850 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); 851 } 852 853 /* Store the permanent mac address */ 854 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 855 856 /* 857 * Store MAC address from RAR0, clear receive address registers, and 858 * clear the multicast table 859 */ 860 hw->mac.ops.init_rx_addrs(hw); 861 862 reset_hw_out: 863 if (phy_status) 864 status = phy_status; 865 866 return status; 867 } 868 869 /** 870 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 871 * @hw: pointer to hardware struct 872 * @rar: receive address register index to associate with a VMDq index 873 * @vmdq: VMDq set index 874 **/ 875 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 876 { 877 u32 rar_high; 878 u32 rar_entries = hw->mac.num_rar_entries; 879 880 /* Make sure we are using a valid rar index range */ 881 if (rar >= rar_entries) { 882 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 883 return IXGBE_ERR_INVALID_ARGUMENT; 884 } 885 886 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 887 rar_high &= ~IXGBE_RAH_VIND_MASK; 888 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 889 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 890 return 0; 891 } 892 893 /** 894 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address 895 * @hw: pointer to hardware struct 896 * @rar: receive address register index to associate with a VMDq index 897 * @vmdq: VMDq clear index (not used in 82598, but elsewhere) 898 **/ 899 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 900 { 901 u32 rar_high; 902 u32 rar_entries = hw->mac.num_rar_entries; 903 904 905 /* Make sure we are using a valid rar index range */ 906 if (rar >= rar_entries) { 907 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 908 return IXGBE_ERR_INVALID_ARGUMENT; 909 } 910 911 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 912 if (rar_high & IXGBE_RAH_VIND_MASK) { 913 rar_high &= ~IXGBE_RAH_VIND_MASK; 914 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 915 } 916 917 return 0; 918 } 919 920 /** 921 * ixgbe_set_vfta_82598 - Set VLAN filter table 922 * @hw: pointer to hardware structure 923 * @vlan: VLAN id to write to VLAN filter 924 * @vind: VMDq output index that maps queue to VLAN id in VFTA 925 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 926 * 927 * Turn on/off specified VLAN in the VLAN filter table. 928 **/ 929 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, 930 bool vlan_on) 931 { 932 u32 regindex; 933 u32 bitindex; 934 u32 bits; 935 u32 vftabyte; 936 937 if (vlan > 4095) 938 return IXGBE_ERR_PARAM; 939 940 /* Determine 32-bit word position in array */ 941 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ 942 943 /* Determine the location of the (VMD) queue index */ 944 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 945 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 946 947 /* Set the nibble for VMD queue index */ 948 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); 949 bits &= (~(0x0F << bitindex)); 950 bits |= (vind << bitindex); 951 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); 952 953 /* Determine the location of the bit for this VLAN id */ 954 bitindex = vlan & 0x1F; /* lower five bits */ 955 956 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 957 if (vlan_on) 958 /* Turn on this VLAN id */ 959 bits |= (1 << bitindex); 960 else 961 /* Turn off this VLAN id */ 962 bits &= ~(1 << bitindex); 963 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 964 965 return 0; 966 } 967 968 /** 969 * ixgbe_clear_vfta_82598 - Clear VLAN filter table 970 * @hw: pointer to hardware structure 971 * 972 * Clears the VLAN filer table, and the VMDq index associated with the filter 973 **/ 974 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) 975 { 976 u32 offset; 977 u32 vlanbyte; 978 979 for (offset = 0; offset < hw->mac.vft_size; offset++) 980 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 981 982 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 983 for (offset = 0; offset < hw->mac.vft_size; offset++) 984 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), 985 0); 986 987 return 0; 988 } 989 990 /** 991 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register 992 * @hw: pointer to hardware structure 993 * @reg: analog register to read 994 * @val: read value 995 * 996 * Performs read operation to Atlas analog register specified. 997 **/ 998 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) 999 { 1000 u32 atlas_ctl; 1001 1002 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, 1003 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 1004 IXGBE_WRITE_FLUSH(hw); 1005 udelay(10); 1006 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 1007 *val = (u8)atlas_ctl; 1008 1009 return 0; 1010 } 1011 1012 /** 1013 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register 1014 * @hw: pointer to hardware structure 1015 * @reg: atlas register to write 1016 * @val: value to write 1017 * 1018 * Performs write operation to Atlas analog register specified. 1019 **/ 1020 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) 1021 { 1022 u32 atlas_ctl; 1023 1024 atlas_ctl = (reg << 8) | val; 1025 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 1026 IXGBE_WRITE_FLUSH(hw); 1027 udelay(10); 1028 1029 return 0; 1030 } 1031 1032 /** 1033 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. 1034 * @hw: pointer to hardware structure 1035 * @byte_offset: EEPROM byte offset to read 1036 * @eeprom_data: value read 1037 * 1038 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 1039 **/ 1040 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 1041 u8 *eeprom_data) 1042 { 1043 s32 status = 0; 1044 u16 sfp_addr = 0; 1045 u16 sfp_data = 0; 1046 u16 sfp_stat = 0; 1047 u32 i; 1048 1049 if (hw->phy.type == ixgbe_phy_nl) { 1050 /* 1051 * phy SDA/SCL registers are at addresses 0xC30A to 1052 * 0xC30D. These registers are used to talk to the SFP+ 1053 * module's EEPROM through the SDA/SCL (I2C) interface. 1054 */ 1055 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset; 1056 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); 1057 hw->phy.ops.write_reg(hw, 1058 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, 1059 MDIO_MMD_PMAPMD, 1060 sfp_addr); 1061 1062 /* Poll status */ 1063 for (i = 0; i < 100; i++) { 1064 hw->phy.ops.read_reg(hw, 1065 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, 1066 MDIO_MMD_PMAPMD, 1067 &sfp_stat); 1068 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; 1069 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) 1070 break; 1071 usleep_range(10000, 20000); 1072 } 1073 1074 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { 1075 hw_dbg(hw, "EEPROM read did not pass.\n"); 1076 status = IXGBE_ERR_SFP_NOT_PRESENT; 1077 goto out; 1078 } 1079 1080 /* Read data */ 1081 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, 1082 MDIO_MMD_PMAPMD, &sfp_data); 1083 1084 *eeprom_data = (u8)(sfp_data >> 8); 1085 } else { 1086 status = IXGBE_ERR_PHY; 1087 goto out; 1088 } 1089 1090 out: 1091 return status; 1092 } 1093 1094 /** 1095 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type 1096 * @hw: pointer to hardware structure 1097 * 1098 * Determines physical layer capabilities of the current configuration. 1099 **/ 1100 static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) 1101 { 1102 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1103 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1104 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1105 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1106 u16 ext_ability = 0; 1107 1108 hw->phy.ops.identify(hw); 1109 1110 /* Copper PHY must be checked before AUTOC LMS to determine correct 1111 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */ 1112 switch (hw->phy.type) { 1113 case ixgbe_phy_tn: 1114 case ixgbe_phy_cu_unknown: 1115 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, 1116 MDIO_MMD_PMAPMD, &ext_ability); 1117 if (ext_ability & MDIO_PMA_EXTABLE_10GBT) 1118 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1119 if (ext_ability & MDIO_PMA_EXTABLE_1000BT) 1120 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1121 if (ext_ability & MDIO_PMA_EXTABLE_100BTX) 1122 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1123 goto out; 1124 default: 1125 break; 1126 } 1127 1128 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1129 case IXGBE_AUTOC_LMS_1G_AN: 1130 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1131 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX) 1132 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1133 else 1134 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1135 break; 1136 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1137 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4) 1138 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1139 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4) 1140 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1141 else /* XAUI */ 1142 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1143 break; 1144 case IXGBE_AUTOC_LMS_KX4_AN: 1145 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 1146 if (autoc & IXGBE_AUTOC_KX_SUPP) 1147 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1148 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1149 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1150 break; 1151 default: 1152 break; 1153 } 1154 1155 if (hw->phy.type == ixgbe_phy_nl) { 1156 hw->phy.ops.identify_sfp(hw); 1157 1158 switch (hw->phy.sfp_type) { 1159 case ixgbe_sfp_type_da_cu: 1160 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1161 break; 1162 case ixgbe_sfp_type_sr: 1163 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1164 break; 1165 case ixgbe_sfp_type_lr: 1166 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1167 break; 1168 default: 1169 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1170 break; 1171 } 1172 } 1173 1174 switch (hw->device_id) { 1175 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 1176 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1177 break; 1178 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 1179 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 1180 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 1181 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1182 break; 1183 case IXGBE_DEV_ID_82598EB_XF_LR: 1184 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1185 break; 1186 default: 1187 break; 1188 } 1189 1190 out: 1191 return physical_layer; 1192 } 1193 1194 /** 1195 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple 1196 * port devices. 1197 * @hw: pointer to the HW structure 1198 * 1199 * Calls common function and corrects issue with some single port devices 1200 * that enable LAN1 but not LAN0. 1201 **/ 1202 static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw) 1203 { 1204 struct ixgbe_bus_info *bus = &hw->bus; 1205 u16 pci_gen = 0; 1206 u16 pci_ctrl2 = 0; 1207 1208 ixgbe_set_lan_id_multi_port_pcie(hw); 1209 1210 /* check if LAN0 is disabled */ 1211 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen); 1212 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) { 1213 1214 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2); 1215 1216 /* if LAN0 is completely disabled force function to 0 */ 1217 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) && 1218 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) && 1219 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) { 1220 1221 bus->func = 0; 1222 } 1223 } 1224 } 1225 1226 /** 1227 * ixgbe_set_rxpba_82598 - Configure packet buffers 1228 * @hw: pointer to hardware structure 1229 * @dcb_config: pointer to ixgbe_dcb_config structure 1230 * 1231 * Configure packet buffers. 1232 */ 1233 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, u32 headroom, 1234 int strategy) 1235 { 1236 u32 rxpktsize = IXGBE_RXPBSIZE_64KB; 1237 u8 i = 0; 1238 1239 if (!num_pb) 1240 return; 1241 1242 /* Setup Rx packet buffer sizes */ 1243 switch (strategy) { 1244 case PBA_STRATEGY_WEIGHTED: 1245 /* Setup the first four at 80KB */ 1246 rxpktsize = IXGBE_RXPBSIZE_80KB; 1247 for (; i < 4; i++) 1248 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 1249 /* Setup the last four at 48KB...don't re-init i */ 1250 rxpktsize = IXGBE_RXPBSIZE_48KB; 1251 /* Fall Through */ 1252 case PBA_STRATEGY_EQUAL: 1253 default: 1254 /* Divide the remaining Rx packet buffer evenly among the TCs */ 1255 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++) 1256 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 1257 break; 1258 } 1259 1260 /* Setup Tx packet buffer sizes */ 1261 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) 1262 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB); 1263 1264 return; 1265 } 1266 1267 static struct ixgbe_mac_operations mac_ops_82598 = { 1268 .init_hw = &ixgbe_init_hw_generic, 1269 .reset_hw = &ixgbe_reset_hw_82598, 1270 .start_hw = &ixgbe_start_hw_82598, 1271 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 1272 .get_media_type = &ixgbe_get_media_type_82598, 1273 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598, 1274 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, 1275 .get_mac_addr = &ixgbe_get_mac_addr_generic, 1276 .stop_adapter = &ixgbe_stop_adapter_generic, 1277 .get_bus_info = &ixgbe_get_bus_info_generic, 1278 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598, 1279 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598, 1280 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598, 1281 .setup_link = &ixgbe_setup_mac_link_82598, 1282 .set_rxpba = &ixgbe_set_rxpba_82598, 1283 .check_link = &ixgbe_check_mac_link_82598, 1284 .get_link_capabilities = &ixgbe_get_link_capabilities_82598, 1285 .led_on = &ixgbe_led_on_generic, 1286 .led_off = &ixgbe_led_off_generic, 1287 .blink_led_start = &ixgbe_blink_led_start_generic, 1288 .blink_led_stop = &ixgbe_blink_led_stop_generic, 1289 .set_rar = &ixgbe_set_rar_generic, 1290 .clear_rar = &ixgbe_clear_rar_generic, 1291 .set_vmdq = &ixgbe_set_vmdq_82598, 1292 .clear_vmdq = &ixgbe_clear_vmdq_82598, 1293 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 1294 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 1295 .enable_mc = &ixgbe_enable_mc_generic, 1296 .disable_mc = &ixgbe_disable_mc_generic, 1297 .clear_vfta = &ixgbe_clear_vfta_82598, 1298 .set_vfta = &ixgbe_set_vfta_82598, 1299 .fc_enable = &ixgbe_fc_enable_82598, 1300 .set_fw_drv_ver = NULL, 1301 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync, 1302 .release_swfw_sync = &ixgbe_release_swfw_sync, 1303 }; 1304 1305 static struct ixgbe_eeprom_operations eeprom_ops_82598 = { 1306 .init_params = &ixgbe_init_eeprom_params_generic, 1307 .read = &ixgbe_read_eerd_generic, 1308 .write = &ixgbe_write_eeprom_generic, 1309 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic, 1310 .read_buffer = &ixgbe_read_eerd_buffer_generic, 1311 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, 1312 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 1313 .update_checksum = &ixgbe_update_eeprom_checksum_generic, 1314 }; 1315 1316 static struct ixgbe_phy_operations phy_ops_82598 = { 1317 .identify = &ixgbe_identify_phy_generic, 1318 .identify_sfp = &ixgbe_identify_sfp_module_generic, 1319 .init = &ixgbe_init_phy_ops_82598, 1320 .reset = &ixgbe_reset_phy_generic, 1321 .read_reg = &ixgbe_read_phy_reg_generic, 1322 .write_reg = &ixgbe_write_phy_reg_generic, 1323 .setup_link = &ixgbe_setup_phy_link_generic, 1324 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 1325 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598, 1326 .check_overtemp = &ixgbe_tn_check_overtemp, 1327 }; 1328 1329 struct ixgbe_info ixgbe_82598_info = { 1330 .mac = ixgbe_mac_82598EB, 1331 .get_invariants = &ixgbe_get_invariants_82598, 1332 .mac_ops = &mac_ops_82598, 1333 .eeprom_ops = &eeprom_ops_82598, 1334 .phy_ops = &phy_ops_82598, 1335 }; 1336 1337