1 // SPDX-License-Identifier: GPL-2.0 2 /******************************************************************************* 3 4 Intel 10 Gigabit PCI Express Linux driver 5 Copyright(c) 1999 - 2016 Intel Corporation. 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Contact Information: 24 Linux NICS <linux.nics@intel.com> 25 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 27 28 *******************************************************************************/ 29 30 #include <linux/pci.h> 31 #include <linux/delay.h> 32 #include <linux/sched.h> 33 34 #include "ixgbe.h" 35 #include "ixgbe_phy.h" 36 37 #define IXGBE_82598_MAX_TX_QUEUES 32 38 #define IXGBE_82598_MAX_RX_QUEUES 64 39 #define IXGBE_82598_RAR_ENTRIES 16 40 #define IXGBE_82598_MC_TBL_SIZE 128 41 #define IXGBE_82598_VFT_TBL_SIZE 128 42 #define IXGBE_82598_RX_PB_SIZE 512 43 44 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 45 ixgbe_link_speed speed, 46 bool autoneg_wait_to_complete); 47 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 48 u8 *eeprom_data); 49 50 /** 51 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout 52 * @hw: pointer to the HW structure 53 * 54 * The defaults for 82598 should be in the range of 50us to 50ms, 55 * however the hardware default for these parts is 500us to 1ms which is less 56 * than the 10ms recommended by the pci-e spec. To address this we need to 57 * increase the value to either 10ms to 250ms for capability version 1 config, 58 * or 16ms to 55ms for version 2. 59 **/ 60 static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) 61 { 62 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); 63 u16 pcie_devctl2; 64 65 if (ixgbe_removed(hw->hw_addr)) 66 return; 67 68 /* only take action if timeout value is defaulted to 0 */ 69 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) 70 goto out; 71 72 /* 73 * if capababilities version is type 1 we can write the 74 * timeout of 10ms to 250ms through the GCR register 75 */ 76 if (!(gcr & IXGBE_GCR_CAP_VER2)) { 77 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; 78 goto out; 79 } 80 81 /* 82 * for version 2 capabilities we need to write the config space 83 * directly in order to set the completion timeout value for 84 * 16ms to 55ms 85 */ 86 pcie_devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); 87 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; 88 ixgbe_write_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); 89 out: 90 /* disable completion timeout resend */ 91 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; 92 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); 93 } 94 95 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) 96 { 97 struct ixgbe_mac_info *mac = &hw->mac; 98 99 /* Call PHY identify routine to get the phy type */ 100 ixgbe_identify_phy_generic(hw); 101 102 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; 103 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; 104 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; 105 mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE; 106 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; 107 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; 108 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 109 110 return 0; 111 } 112 113 /** 114 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init 115 * @hw: pointer to hardware structure 116 * 117 * Initialize any function pointers that were not able to be 118 * set during get_invariants because the PHY/SFP type was 119 * not known. Perform the SFP init if necessary. 120 * 121 **/ 122 static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) 123 { 124 struct ixgbe_mac_info *mac = &hw->mac; 125 struct ixgbe_phy_info *phy = &hw->phy; 126 s32 ret_val; 127 u16 list_offset, data_offset; 128 129 /* Identify the PHY */ 130 phy->ops.identify(hw); 131 132 /* Overwrite the link function pointers if copper PHY */ 133 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 134 mac->ops.setup_link = &ixgbe_setup_copper_link_82598; 135 mac->ops.get_link_capabilities = 136 &ixgbe_get_copper_link_capabilities_generic; 137 } 138 139 switch (hw->phy.type) { 140 case ixgbe_phy_tn: 141 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 142 phy->ops.check_link = &ixgbe_check_phy_link_tnx; 143 break; 144 case ixgbe_phy_nl: 145 phy->ops.reset = &ixgbe_reset_phy_nl; 146 147 /* Call SFP+ identify routine to get the SFP+ module type */ 148 ret_val = phy->ops.identify_sfp(hw); 149 if (ret_val) 150 return ret_val; 151 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 152 return IXGBE_ERR_SFP_NOT_SUPPORTED; 153 154 /* Check to see if SFP+ module is supported */ 155 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, 156 &list_offset, 157 &data_offset); 158 if (ret_val) 159 return IXGBE_ERR_SFP_NOT_SUPPORTED; 160 break; 161 default: 162 break; 163 } 164 165 return 0; 166 } 167 168 /** 169 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx 170 * @hw: pointer to hardware structure 171 * 172 * Starts the hardware using the generic start_hw function. 173 * Disables relaxed ordering for archs other than SPARC 174 * Then set pcie completion timeout 175 * 176 **/ 177 static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) 178 { 179 s32 ret_val; 180 181 ret_val = ixgbe_start_hw_generic(hw); 182 if (ret_val) 183 return ret_val; 184 185 /* set the completion timeout for interface */ 186 ixgbe_set_pcie_completion_timeout(hw); 187 188 return 0; 189 } 190 191 /** 192 * ixgbe_get_link_capabilities_82598 - Determines link capabilities 193 * @hw: pointer to hardware structure 194 * @speed: pointer to link speed 195 * @autoneg: boolean auto-negotiation value 196 * 197 * Determines the link capabilities by reading the AUTOC register. 198 **/ 199 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 200 ixgbe_link_speed *speed, 201 bool *autoneg) 202 { 203 u32 autoc = 0; 204 205 /* 206 * Determine link capabilities based on the stored value of AUTOC, 207 * which represents EEPROM defaults. If AUTOC value has not been 208 * stored, use the current register value. 209 */ 210 if (hw->mac.orig_link_settings_stored) 211 autoc = hw->mac.orig_autoc; 212 else 213 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 214 215 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 216 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 217 *speed = IXGBE_LINK_SPEED_1GB_FULL; 218 *autoneg = false; 219 break; 220 221 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 222 *speed = IXGBE_LINK_SPEED_10GB_FULL; 223 *autoneg = false; 224 break; 225 226 case IXGBE_AUTOC_LMS_1G_AN: 227 *speed = IXGBE_LINK_SPEED_1GB_FULL; 228 *autoneg = true; 229 break; 230 231 case IXGBE_AUTOC_LMS_KX4_AN: 232 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 233 *speed = IXGBE_LINK_SPEED_UNKNOWN; 234 if (autoc & IXGBE_AUTOC_KX4_SUPP) 235 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 236 if (autoc & IXGBE_AUTOC_KX_SUPP) 237 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 238 *autoneg = true; 239 break; 240 241 default: 242 return IXGBE_ERR_LINK_SETUP; 243 } 244 245 return 0; 246 } 247 248 /** 249 * ixgbe_get_media_type_82598 - Determines media type 250 * @hw: pointer to hardware structure 251 * 252 * Returns the media type (fiber, copper, backplane) 253 **/ 254 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 255 { 256 /* Detect if there is a copper PHY attached. */ 257 switch (hw->phy.type) { 258 case ixgbe_phy_cu_unknown: 259 case ixgbe_phy_tn: 260 return ixgbe_media_type_copper; 261 262 default: 263 break; 264 } 265 266 /* Media type for I82598 is based on device ID */ 267 switch (hw->device_id) { 268 case IXGBE_DEV_ID_82598: 269 case IXGBE_DEV_ID_82598_BX: 270 /* Default device ID is mezzanine card KX/KX4 */ 271 return ixgbe_media_type_backplane; 272 273 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 274 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 275 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 276 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 277 case IXGBE_DEV_ID_82598EB_XF_LR: 278 case IXGBE_DEV_ID_82598EB_SFP_LOM: 279 return ixgbe_media_type_fiber; 280 281 case IXGBE_DEV_ID_82598EB_CX4: 282 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 283 return ixgbe_media_type_cx4; 284 285 case IXGBE_DEV_ID_82598AT: 286 case IXGBE_DEV_ID_82598AT2: 287 return ixgbe_media_type_copper; 288 289 default: 290 return ixgbe_media_type_unknown; 291 } 292 } 293 294 /** 295 * ixgbe_fc_enable_82598 - Enable flow control 296 * @hw: pointer to hardware structure 297 * 298 * Enable flow control according to the current settings. 299 **/ 300 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw) 301 { 302 u32 fctrl_reg; 303 u32 rmcs_reg; 304 u32 reg; 305 u32 fcrtl, fcrth; 306 u32 link_speed = 0; 307 int i; 308 bool link_up; 309 310 /* Validate the water mark configuration */ 311 if (!hw->fc.pause_time) 312 return IXGBE_ERR_INVALID_LINK_SETTINGS; 313 314 /* Low water mark of zero causes XOFF floods */ 315 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 316 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 317 hw->fc.high_water[i]) { 318 if (!hw->fc.low_water[i] || 319 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 320 hw_dbg(hw, "Invalid water mark configuration\n"); 321 return IXGBE_ERR_INVALID_LINK_SETTINGS; 322 } 323 } 324 } 325 326 /* 327 * On 82598 having Rx FC on causes resets while doing 1G 328 * so if it's on turn it off once we know link_speed. For 329 * more details see 82598 Specification update. 330 */ 331 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 332 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) { 333 switch (hw->fc.requested_mode) { 334 case ixgbe_fc_full: 335 hw->fc.requested_mode = ixgbe_fc_tx_pause; 336 break; 337 case ixgbe_fc_rx_pause: 338 hw->fc.requested_mode = ixgbe_fc_none; 339 break; 340 default: 341 /* no change */ 342 break; 343 } 344 } 345 346 /* Negotiate the fc mode to use */ 347 hw->mac.ops.fc_autoneg(hw); 348 349 /* Disable any previous flow control settings */ 350 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 351 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 352 353 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 354 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 355 356 /* 357 * The possible values of fc.current_mode are: 358 * 0: Flow control is completely disabled 359 * 1: Rx flow control is enabled (we can receive pause frames, 360 * but not send pause frames). 361 * 2: Tx flow control is enabled (we can send pause frames but 362 * we do not support receiving pause frames). 363 * 3: Both Rx and Tx flow control (symmetric) are enabled. 364 * other: Invalid. 365 */ 366 switch (hw->fc.current_mode) { 367 case ixgbe_fc_none: 368 /* 369 * Flow control is disabled by software override or autoneg. 370 * The code below will actually disable it in the HW. 371 */ 372 break; 373 case ixgbe_fc_rx_pause: 374 /* 375 * Rx Flow control is enabled and Tx Flow control is 376 * disabled by software override. Since there really 377 * isn't a way to advertise that we are capable of RX 378 * Pause ONLY, we will advertise that we support both 379 * symmetric and asymmetric Rx PAUSE. Later, we will 380 * disable the adapter's ability to send PAUSE frames. 381 */ 382 fctrl_reg |= IXGBE_FCTRL_RFCE; 383 break; 384 case ixgbe_fc_tx_pause: 385 /* 386 * Tx Flow control is enabled, and Rx Flow control is 387 * disabled by software override. 388 */ 389 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 390 break; 391 case ixgbe_fc_full: 392 /* Flow control (both Rx and Tx) is enabled by SW override. */ 393 fctrl_reg |= IXGBE_FCTRL_RFCE; 394 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 395 break; 396 default: 397 hw_dbg(hw, "Flow control param set incorrectly\n"); 398 return IXGBE_ERR_CONFIG; 399 } 400 401 /* Set 802.3x based flow control settings. */ 402 fctrl_reg |= IXGBE_FCTRL_DPF; 403 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); 404 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 405 406 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 407 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 408 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 409 hw->fc.high_water[i]) { 410 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 411 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 412 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl); 413 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth); 414 } else { 415 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); 416 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); 417 } 418 419 } 420 421 /* Configure pause time (2 TCs per register) */ 422 reg = hw->fc.pause_time * 0x00010001; 423 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 424 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 425 426 /* Configure flow control refresh threshold value */ 427 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 428 429 return 0; 430 } 431 432 /** 433 * ixgbe_start_mac_link_82598 - Configures MAC link settings 434 * @hw: pointer to hardware structure 435 * @autoneg_wait_to_complete: true when waiting for completion is needed 436 * 437 * Configures link settings based on values in the ixgbe_hw struct. 438 * Restarts the link. Performs autonegotiation if needed. 439 **/ 440 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, 441 bool autoneg_wait_to_complete) 442 { 443 u32 autoc_reg; 444 u32 links_reg; 445 u32 i; 446 s32 status = 0; 447 448 /* Restart link */ 449 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 450 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 451 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 452 453 /* Only poll for autoneg to complete if specified to do so */ 454 if (autoneg_wait_to_complete) { 455 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 456 IXGBE_AUTOC_LMS_KX4_AN || 457 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 458 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 459 links_reg = 0; /* Just in case Autoneg time = 0 */ 460 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 461 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 462 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 463 break; 464 msleep(100); 465 } 466 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 467 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 468 hw_dbg(hw, "Autonegotiation did not complete.\n"); 469 } 470 } 471 } 472 473 /* Add delay to filter out noises during initial link setup */ 474 msleep(50); 475 476 return status; 477 } 478 479 /** 480 * ixgbe_validate_link_ready - Function looks for phy link 481 * @hw: pointer to hardware structure 482 * 483 * Function indicates success when phy link is available. If phy is not ready 484 * within 5 seconds of MAC indicating link, the function returns error. 485 **/ 486 static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) 487 { 488 u32 timeout; 489 u16 an_reg; 490 491 if (hw->device_id != IXGBE_DEV_ID_82598AT2) 492 return 0; 493 494 for (timeout = 0; 495 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) { 496 hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg); 497 498 if ((an_reg & MDIO_AN_STAT1_COMPLETE) && 499 (an_reg & MDIO_STAT1_LSTATUS)) 500 break; 501 502 msleep(100); 503 } 504 505 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) { 506 hw_dbg(hw, "Link was indicated but link is down\n"); 507 return IXGBE_ERR_LINK_SETUP; 508 } 509 510 return 0; 511 } 512 513 /** 514 * ixgbe_check_mac_link_82598 - Get link/speed status 515 * @hw: pointer to hardware structure 516 * @speed: pointer to link speed 517 * @link_up: true is link is up, false otherwise 518 * @link_up_wait_to_complete: bool used to wait for link up or not 519 * 520 * Reads the links register to determine if link is up and the current speed 521 **/ 522 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 523 ixgbe_link_speed *speed, bool *link_up, 524 bool link_up_wait_to_complete) 525 { 526 u32 links_reg; 527 u32 i; 528 u16 link_reg, adapt_comp_reg; 529 530 /* 531 * SERDES PHY requires us to read link status from register 0xC79F. 532 * Bit 0 set indicates link is up/ready; clear indicates link down. 533 * 0xC00C is read to check that the XAUI lanes are active. Bit 0 534 * clear indicates active; set indicates inactive. 535 */ 536 if (hw->phy.type == ixgbe_phy_nl) { 537 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); 538 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); 539 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD, 540 &adapt_comp_reg); 541 if (link_up_wait_to_complete) { 542 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 543 if ((link_reg & 1) && 544 ((adapt_comp_reg & 1) == 0)) { 545 *link_up = true; 546 break; 547 } else { 548 *link_up = false; 549 } 550 msleep(100); 551 hw->phy.ops.read_reg(hw, 0xC79F, 552 MDIO_MMD_PMAPMD, 553 &link_reg); 554 hw->phy.ops.read_reg(hw, 0xC00C, 555 MDIO_MMD_PMAPMD, 556 &adapt_comp_reg); 557 } 558 } else { 559 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) 560 *link_up = true; 561 else 562 *link_up = false; 563 } 564 565 if (!*link_up) 566 return 0; 567 } 568 569 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 570 if (link_up_wait_to_complete) { 571 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 572 if (links_reg & IXGBE_LINKS_UP) { 573 *link_up = true; 574 break; 575 } else { 576 *link_up = false; 577 } 578 msleep(100); 579 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 580 } 581 } else { 582 if (links_reg & IXGBE_LINKS_UP) 583 *link_up = true; 584 else 585 *link_up = false; 586 } 587 588 if (links_reg & IXGBE_LINKS_SPEED) 589 *speed = IXGBE_LINK_SPEED_10GB_FULL; 590 else 591 *speed = IXGBE_LINK_SPEED_1GB_FULL; 592 593 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && *link_up && 594 (ixgbe_validate_link_ready(hw) != 0)) 595 *link_up = false; 596 597 return 0; 598 } 599 600 /** 601 * ixgbe_setup_mac_link_82598 - Set MAC link speed 602 * @hw: pointer to hardware structure 603 * @speed: new link speed 604 * @autoneg_wait_to_complete: true when waiting for completion is needed 605 * 606 * Set the link speed in the AUTOC register and restarts link. 607 **/ 608 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, 609 ixgbe_link_speed speed, 610 bool autoneg_wait_to_complete) 611 { 612 bool autoneg = false; 613 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 614 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 615 u32 autoc = curr_autoc; 616 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 617 618 /* Check to see if speed passed in is supported. */ 619 ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg); 620 speed &= link_capabilities; 621 622 if (speed == IXGBE_LINK_SPEED_UNKNOWN) 623 return IXGBE_ERR_LINK_SETUP; 624 625 /* Set KX4/KX support according to speed requested */ 626 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || 627 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 628 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; 629 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 630 autoc |= IXGBE_AUTOC_KX4_SUPP; 631 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 632 autoc |= IXGBE_AUTOC_KX_SUPP; 633 if (autoc != curr_autoc) 634 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 635 } 636 637 /* Setup and restart the link based on the new values in 638 * ixgbe_hw This will write the AUTOC register based on the new 639 * stored values 640 */ 641 return ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); 642 } 643 644 645 /** 646 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field 647 * @hw: pointer to hardware structure 648 * @speed: new link speed 649 * @autoneg_wait_to_complete: true if waiting is needed to complete 650 * 651 * Sets the link speed in the AUTOC register in the MAC and restarts link. 652 **/ 653 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 654 ixgbe_link_speed speed, 655 bool autoneg_wait_to_complete) 656 { 657 s32 status; 658 659 /* Setup the PHY according to input speed */ 660 status = hw->phy.ops.setup_link_speed(hw, speed, 661 autoneg_wait_to_complete); 662 /* Set up MAC */ 663 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); 664 665 return status; 666 } 667 668 /** 669 * ixgbe_reset_hw_82598 - Performs hardware reset 670 * @hw: pointer to hardware structure 671 * 672 * Resets the hardware by resetting the transmit and receive units, masks and 673 * clears all interrupts, performing a PHY reset, and performing a link (MAC) 674 * reset. 675 **/ 676 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 677 { 678 s32 status; 679 s32 phy_status = 0; 680 u32 ctrl; 681 u32 gheccr; 682 u32 i; 683 u32 autoc; 684 u8 analog_val; 685 686 /* Call adapter stop to disable tx/rx and clear interrupts */ 687 status = hw->mac.ops.stop_adapter(hw); 688 if (status) 689 return status; 690 691 /* 692 * Power up the Atlas Tx lanes if they are currently powered down. 693 * Atlas Tx lanes are powered down for MAC loopback tests, but 694 * they are not automatically restored on reset. 695 */ 696 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 697 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 698 /* Enable Tx Atlas so packets can be transmitted again */ 699 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 700 &analog_val); 701 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 702 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 703 analog_val); 704 705 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 706 &analog_val); 707 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 708 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 709 analog_val); 710 711 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 712 &analog_val); 713 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 714 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 715 analog_val); 716 717 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 718 &analog_val); 719 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 720 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 721 analog_val); 722 } 723 724 /* Reset PHY */ 725 if (hw->phy.reset_disable == false) { 726 /* PHY ops must be identified and initialized prior to reset */ 727 728 /* Init PHY and function pointers, perform SFP setup */ 729 phy_status = hw->phy.ops.init(hw); 730 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) 731 return phy_status; 732 if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) 733 goto mac_reset_top; 734 735 hw->phy.ops.reset(hw); 736 } 737 738 mac_reset_top: 739 /* 740 * Issue global reset to the MAC. This needs to be a SW reset. 741 * If link reset is used, it might reset the MAC when mng is using it 742 */ 743 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST; 744 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 745 IXGBE_WRITE_FLUSH(hw); 746 usleep_range(1000, 1200); 747 748 /* Poll for reset bit to self-clear indicating reset is complete */ 749 for (i = 0; i < 10; i++) { 750 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 751 if (!(ctrl & IXGBE_CTRL_RST)) 752 break; 753 udelay(1); 754 } 755 if (ctrl & IXGBE_CTRL_RST) { 756 status = IXGBE_ERR_RESET_FAILED; 757 hw_dbg(hw, "Reset polling failed to complete.\n"); 758 } 759 760 msleep(50); 761 762 /* 763 * Double resets are required for recovery from certain error 764 * conditions. Between resets, it is necessary to stall to allow time 765 * for any pending HW events to complete. 766 */ 767 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 768 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 769 goto mac_reset_top; 770 } 771 772 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 773 gheccr &= ~(BIT(21) | BIT(18) | BIT(9) | BIT(6)); 774 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 775 776 /* 777 * Store the original AUTOC value if it has not been 778 * stored off yet. Otherwise restore the stored original 779 * AUTOC value since the reset operation sets back to deaults. 780 */ 781 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 782 if (hw->mac.orig_link_settings_stored == false) { 783 hw->mac.orig_autoc = autoc; 784 hw->mac.orig_link_settings_stored = true; 785 } else if (autoc != hw->mac.orig_autoc) { 786 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); 787 } 788 789 /* Store the permanent mac address */ 790 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 791 792 /* 793 * Store MAC address from RAR0, clear receive address registers, and 794 * clear the multicast table 795 */ 796 hw->mac.ops.init_rx_addrs(hw); 797 798 if (phy_status) 799 status = phy_status; 800 801 return status; 802 } 803 804 /** 805 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 806 * @hw: pointer to hardware struct 807 * @rar: receive address register index to associate with a VMDq index 808 * @vmdq: VMDq set index 809 **/ 810 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 811 { 812 u32 rar_high; 813 u32 rar_entries = hw->mac.num_rar_entries; 814 815 /* Make sure we are using a valid rar index range */ 816 if (rar >= rar_entries) { 817 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 818 return IXGBE_ERR_INVALID_ARGUMENT; 819 } 820 821 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 822 rar_high &= ~IXGBE_RAH_VIND_MASK; 823 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 824 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 825 return 0; 826 } 827 828 /** 829 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address 830 * @hw: pointer to hardware struct 831 * @rar: receive address register index to associate with a VMDq index 832 * @vmdq: VMDq clear index (not used in 82598, but elsewhere) 833 **/ 834 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 835 { 836 u32 rar_high; 837 u32 rar_entries = hw->mac.num_rar_entries; 838 839 840 /* Make sure we are using a valid rar index range */ 841 if (rar >= rar_entries) { 842 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 843 return IXGBE_ERR_INVALID_ARGUMENT; 844 } 845 846 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 847 if (rar_high & IXGBE_RAH_VIND_MASK) { 848 rar_high &= ~IXGBE_RAH_VIND_MASK; 849 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 850 } 851 852 return 0; 853 } 854 855 /** 856 * ixgbe_set_vfta_82598 - Set VLAN filter table 857 * @hw: pointer to hardware structure 858 * @vlan: VLAN id to write to VLAN filter 859 * @vind: VMDq output index that maps queue to VLAN id in VFTA 860 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 861 * @vlvf_bypass: boolean flag - unused 862 * 863 * Turn on/off specified VLAN in the VLAN filter table. 864 **/ 865 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, 866 bool vlan_on, bool vlvf_bypass) 867 { 868 u32 regindex; 869 u32 bitindex; 870 u32 bits; 871 u32 vftabyte; 872 873 if (vlan > 4095) 874 return IXGBE_ERR_PARAM; 875 876 /* Determine 32-bit word position in array */ 877 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ 878 879 /* Determine the location of the (VMD) queue index */ 880 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 881 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 882 883 /* Set the nibble for VMD queue index */ 884 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); 885 bits &= (~(0x0F << bitindex)); 886 bits |= (vind << bitindex); 887 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); 888 889 /* Determine the location of the bit for this VLAN id */ 890 bitindex = vlan & 0x1F; /* lower five bits */ 891 892 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 893 if (vlan_on) 894 /* Turn on this VLAN id */ 895 bits |= BIT(bitindex); 896 else 897 /* Turn off this VLAN id */ 898 bits &= ~BIT(bitindex); 899 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 900 901 return 0; 902 } 903 904 /** 905 * ixgbe_clear_vfta_82598 - Clear VLAN filter table 906 * @hw: pointer to hardware structure 907 * 908 * Clears the VLAN filer table, and the VMDq index associated with the filter 909 **/ 910 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) 911 { 912 u32 offset; 913 u32 vlanbyte; 914 915 for (offset = 0; offset < hw->mac.vft_size; offset++) 916 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 917 918 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 919 for (offset = 0; offset < hw->mac.vft_size; offset++) 920 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), 921 0); 922 923 return 0; 924 } 925 926 /** 927 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register 928 * @hw: pointer to hardware structure 929 * @reg: analog register to read 930 * @val: read value 931 * 932 * Performs read operation to Atlas analog register specified. 933 **/ 934 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) 935 { 936 u32 atlas_ctl; 937 938 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, 939 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 940 IXGBE_WRITE_FLUSH(hw); 941 udelay(10); 942 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 943 *val = (u8)atlas_ctl; 944 945 return 0; 946 } 947 948 /** 949 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register 950 * @hw: pointer to hardware structure 951 * @reg: atlas register to write 952 * @val: value to write 953 * 954 * Performs write operation to Atlas analog register specified. 955 **/ 956 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) 957 { 958 u32 atlas_ctl; 959 960 atlas_ctl = (reg << 8) | val; 961 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 962 IXGBE_WRITE_FLUSH(hw); 963 udelay(10); 964 965 return 0; 966 } 967 968 /** 969 * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface. 970 * @hw: pointer to hardware structure 971 * @dev_addr: address to read from 972 * @byte_offset: byte offset to read from dev_addr 973 * @eeprom_data: value read 974 * 975 * Performs 8 byte read operation to SFP module's data over I2C interface. 976 **/ 977 static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr, 978 u8 byte_offset, u8 *eeprom_data) 979 { 980 s32 status = 0; 981 u16 sfp_addr = 0; 982 u16 sfp_data = 0; 983 u16 sfp_stat = 0; 984 u16 gssr; 985 u32 i; 986 987 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 988 gssr = IXGBE_GSSR_PHY1_SM; 989 else 990 gssr = IXGBE_GSSR_PHY0_SM; 991 992 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0) 993 return IXGBE_ERR_SWFW_SYNC; 994 995 if (hw->phy.type == ixgbe_phy_nl) { 996 /* 997 * phy SDA/SCL registers are at addresses 0xC30A to 998 * 0xC30D. These registers are used to talk to the SFP+ 999 * module's EEPROM through the SDA/SCL (I2C) interface. 1000 */ 1001 sfp_addr = (dev_addr << 8) + byte_offset; 1002 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); 1003 hw->phy.ops.write_reg_mdi(hw, 1004 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, 1005 MDIO_MMD_PMAPMD, 1006 sfp_addr); 1007 1008 /* Poll status */ 1009 for (i = 0; i < 100; i++) { 1010 hw->phy.ops.read_reg_mdi(hw, 1011 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, 1012 MDIO_MMD_PMAPMD, 1013 &sfp_stat); 1014 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; 1015 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) 1016 break; 1017 usleep_range(10000, 20000); 1018 } 1019 1020 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { 1021 hw_dbg(hw, "EEPROM read did not pass.\n"); 1022 status = IXGBE_ERR_SFP_NOT_PRESENT; 1023 goto out; 1024 } 1025 1026 /* Read data */ 1027 hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, 1028 MDIO_MMD_PMAPMD, &sfp_data); 1029 1030 *eeprom_data = (u8)(sfp_data >> 8); 1031 } else { 1032 status = IXGBE_ERR_PHY; 1033 } 1034 1035 out: 1036 hw->mac.ops.release_swfw_sync(hw, gssr); 1037 return status; 1038 } 1039 1040 /** 1041 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. 1042 * @hw: pointer to hardware structure 1043 * @byte_offset: EEPROM byte offset to read 1044 * @eeprom_data: value read 1045 * 1046 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 1047 **/ 1048 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 1049 u8 *eeprom_data) 1050 { 1051 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR, 1052 byte_offset, eeprom_data); 1053 } 1054 1055 /** 1056 * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface. 1057 * @hw: pointer to hardware structure 1058 * @byte_offset: byte offset at address 0xA2 1059 * @sff8472_data: value read 1060 * 1061 * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C 1062 **/ 1063 static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset, 1064 u8 *sff8472_data) 1065 { 1066 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2, 1067 byte_offset, sff8472_data); 1068 } 1069 1070 /** 1071 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple 1072 * port devices. 1073 * @hw: pointer to the HW structure 1074 * 1075 * Calls common function and corrects issue with some single port devices 1076 * that enable LAN1 but not LAN0. 1077 **/ 1078 static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw) 1079 { 1080 struct ixgbe_bus_info *bus = &hw->bus; 1081 u16 pci_gen = 0; 1082 u16 pci_ctrl2 = 0; 1083 1084 ixgbe_set_lan_id_multi_port_pcie(hw); 1085 1086 /* check if LAN0 is disabled */ 1087 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen); 1088 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) { 1089 1090 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2); 1091 1092 /* if LAN0 is completely disabled force function to 0 */ 1093 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) && 1094 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) && 1095 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) { 1096 1097 bus->func = 0; 1098 } 1099 } 1100 } 1101 1102 /** 1103 * ixgbe_set_rxpba_82598 - Initialize RX packet buffer 1104 * @hw: pointer to hardware structure 1105 * @num_pb: number of packet buffers to allocate 1106 * @headroom: reserve n KB of headroom 1107 * @strategy: packet buffer allocation strategy 1108 **/ 1109 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, 1110 u32 headroom, int strategy) 1111 { 1112 u32 rxpktsize = IXGBE_RXPBSIZE_64KB; 1113 u8 i = 0; 1114 1115 if (!num_pb) 1116 return; 1117 1118 /* Setup Rx packet buffer sizes */ 1119 switch (strategy) { 1120 case PBA_STRATEGY_WEIGHTED: 1121 /* Setup the first four at 80KB */ 1122 rxpktsize = IXGBE_RXPBSIZE_80KB; 1123 for (; i < 4; i++) 1124 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 1125 /* Setup the last four at 48KB...don't re-init i */ 1126 rxpktsize = IXGBE_RXPBSIZE_48KB; 1127 /* Fall Through */ 1128 case PBA_STRATEGY_EQUAL: 1129 default: 1130 /* Divide the remaining Rx packet buffer evenly among the TCs */ 1131 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++) 1132 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 1133 break; 1134 } 1135 1136 /* Setup Tx packet buffer sizes */ 1137 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) 1138 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB); 1139 } 1140 1141 static const struct ixgbe_mac_operations mac_ops_82598 = { 1142 .init_hw = &ixgbe_init_hw_generic, 1143 .reset_hw = &ixgbe_reset_hw_82598, 1144 .start_hw = &ixgbe_start_hw_82598, 1145 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 1146 .get_media_type = &ixgbe_get_media_type_82598, 1147 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, 1148 .get_mac_addr = &ixgbe_get_mac_addr_generic, 1149 .stop_adapter = &ixgbe_stop_adapter_generic, 1150 .get_bus_info = &ixgbe_get_bus_info_generic, 1151 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598, 1152 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598, 1153 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598, 1154 .setup_link = &ixgbe_setup_mac_link_82598, 1155 .set_rxpba = &ixgbe_set_rxpba_82598, 1156 .check_link = &ixgbe_check_mac_link_82598, 1157 .get_link_capabilities = &ixgbe_get_link_capabilities_82598, 1158 .led_on = &ixgbe_led_on_generic, 1159 .led_off = &ixgbe_led_off_generic, 1160 .init_led_link_act = ixgbe_init_led_link_act_generic, 1161 .blink_led_start = &ixgbe_blink_led_start_generic, 1162 .blink_led_stop = &ixgbe_blink_led_stop_generic, 1163 .set_rar = &ixgbe_set_rar_generic, 1164 .clear_rar = &ixgbe_clear_rar_generic, 1165 .set_vmdq = &ixgbe_set_vmdq_82598, 1166 .clear_vmdq = &ixgbe_clear_vmdq_82598, 1167 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 1168 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 1169 .enable_mc = &ixgbe_enable_mc_generic, 1170 .disable_mc = &ixgbe_disable_mc_generic, 1171 .clear_vfta = &ixgbe_clear_vfta_82598, 1172 .set_vfta = &ixgbe_set_vfta_82598, 1173 .fc_enable = &ixgbe_fc_enable_82598, 1174 .setup_fc = ixgbe_setup_fc_generic, 1175 .fc_autoneg = ixgbe_fc_autoneg, 1176 .set_fw_drv_ver = NULL, 1177 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync, 1178 .release_swfw_sync = &ixgbe_release_swfw_sync, 1179 .init_swfw_sync = NULL, 1180 .get_thermal_sensor_data = NULL, 1181 .init_thermal_sensor_thresh = NULL, 1182 .prot_autoc_read = &prot_autoc_read_generic, 1183 .prot_autoc_write = &prot_autoc_write_generic, 1184 .enable_rx = &ixgbe_enable_rx_generic, 1185 .disable_rx = &ixgbe_disable_rx_generic, 1186 }; 1187 1188 static const struct ixgbe_eeprom_operations eeprom_ops_82598 = { 1189 .init_params = &ixgbe_init_eeprom_params_generic, 1190 .read = &ixgbe_read_eerd_generic, 1191 .write = &ixgbe_write_eeprom_generic, 1192 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic, 1193 .read_buffer = &ixgbe_read_eerd_buffer_generic, 1194 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, 1195 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 1196 .update_checksum = &ixgbe_update_eeprom_checksum_generic, 1197 }; 1198 1199 static const struct ixgbe_phy_operations phy_ops_82598 = { 1200 .identify = &ixgbe_identify_phy_generic, 1201 .identify_sfp = &ixgbe_identify_module_generic, 1202 .init = &ixgbe_init_phy_ops_82598, 1203 .reset = &ixgbe_reset_phy_generic, 1204 .read_reg = &ixgbe_read_phy_reg_generic, 1205 .write_reg = &ixgbe_write_phy_reg_generic, 1206 .read_reg_mdi = &ixgbe_read_phy_reg_mdi, 1207 .write_reg_mdi = &ixgbe_write_phy_reg_mdi, 1208 .setup_link = &ixgbe_setup_phy_link_generic, 1209 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 1210 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_82598, 1211 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598, 1212 .check_overtemp = &ixgbe_tn_check_overtemp, 1213 }; 1214 1215 const struct ixgbe_info ixgbe_82598_info = { 1216 .mac = ixgbe_mac_82598EB, 1217 .get_invariants = &ixgbe_get_invariants_82598, 1218 .mac_ops = &mac_ops_82598, 1219 .eeprom_ops = &eeprom_ops_82598, 1220 .phy_ops = &phy_ops_82598, 1221 .mvals = ixgbe_mvals_8259X, 1222 }; 1223