1dee1ad47SJeff Kirsher /******************************************************************************* 2dee1ad47SJeff Kirsher 3dee1ad47SJeff Kirsher Intel 10 Gigabit PCI Express Linux driver 437689010SMark Rustad Copyright(c) 1999 - 2016 Intel Corporation. 5dee1ad47SJeff Kirsher 6dee1ad47SJeff Kirsher This program is free software; you can redistribute it and/or modify it 7dee1ad47SJeff Kirsher under the terms and conditions of the GNU General Public License, 8dee1ad47SJeff Kirsher version 2, as published by the Free Software Foundation. 9dee1ad47SJeff Kirsher 10dee1ad47SJeff Kirsher This program is distributed in the hope it will be useful, but WITHOUT 11dee1ad47SJeff Kirsher ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12dee1ad47SJeff Kirsher FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13dee1ad47SJeff Kirsher more details. 14dee1ad47SJeff Kirsher 15dee1ad47SJeff Kirsher You should have received a copy of the GNU General Public License along with 16dee1ad47SJeff Kirsher this program; if not, write to the Free Software Foundation, Inc., 17dee1ad47SJeff Kirsher 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18dee1ad47SJeff Kirsher 19dee1ad47SJeff Kirsher The full GNU General Public License is included in this distribution in 20dee1ad47SJeff Kirsher the file called "COPYING". 21dee1ad47SJeff Kirsher 22dee1ad47SJeff Kirsher Contact Information: 23b89aae71SJacob Keller Linux NICS <linux.nics@intel.com> 24dee1ad47SJeff Kirsher e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25dee1ad47SJeff Kirsher Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26dee1ad47SJeff Kirsher 27dee1ad47SJeff Kirsher *******************************************************************************/ 28dee1ad47SJeff Kirsher 29dee1ad47SJeff Kirsher #include <linux/pci.h> 30dee1ad47SJeff Kirsher #include <linux/delay.h> 31dee1ad47SJeff Kirsher #include <linux/sched.h> 32dee1ad47SJeff Kirsher 33dee1ad47SJeff Kirsher #include "ixgbe.h" 34dee1ad47SJeff Kirsher #include "ixgbe_phy.h" 35dee1ad47SJeff Kirsher 36dee1ad47SJeff Kirsher #define IXGBE_82598_MAX_TX_QUEUES 32 37dee1ad47SJeff Kirsher #define IXGBE_82598_MAX_RX_QUEUES 64 38dee1ad47SJeff Kirsher #define IXGBE_82598_RAR_ENTRIES 16 39dee1ad47SJeff Kirsher #define IXGBE_82598_MC_TBL_SIZE 128 40dee1ad47SJeff Kirsher #define IXGBE_82598_VFT_TBL_SIZE 128 41dee1ad47SJeff Kirsher #define IXGBE_82598_RX_PB_SIZE 512 42dee1ad47SJeff Kirsher 43dee1ad47SJeff Kirsher static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 44dee1ad47SJeff Kirsher ixgbe_link_speed speed, 45dee1ad47SJeff Kirsher bool autoneg_wait_to_complete); 46dee1ad47SJeff Kirsher static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 47dee1ad47SJeff Kirsher u8 *eeprom_data); 48dee1ad47SJeff Kirsher 49dee1ad47SJeff Kirsher /** 50dee1ad47SJeff Kirsher * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout 51dee1ad47SJeff Kirsher * @hw: pointer to the HW structure 52dee1ad47SJeff Kirsher * 53dee1ad47SJeff Kirsher * The defaults for 82598 should be in the range of 50us to 50ms, 54dee1ad47SJeff Kirsher * however the hardware default for these parts is 500us to 1ms which is less 55dee1ad47SJeff Kirsher * than the 10ms recommended by the pci-e spec. To address this we need to 56dee1ad47SJeff Kirsher * increase the value to either 10ms to 250ms for capability version 1 config, 57dee1ad47SJeff Kirsher * or 16ms to 55ms for version 2. 58dee1ad47SJeff Kirsher **/ 59dee1ad47SJeff Kirsher static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) 60dee1ad47SJeff Kirsher { 61dee1ad47SJeff Kirsher u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); 62dee1ad47SJeff Kirsher u16 pcie_devctl2; 63dee1ad47SJeff Kirsher 6414438464SMark Rustad if (ixgbe_removed(hw->hw_addr)) 6514438464SMark Rustad return; 6614438464SMark Rustad 67dee1ad47SJeff Kirsher /* only take action if timeout value is defaulted to 0 */ 68dee1ad47SJeff Kirsher if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) 69dee1ad47SJeff Kirsher goto out; 70dee1ad47SJeff Kirsher 71dee1ad47SJeff Kirsher /* 72dee1ad47SJeff Kirsher * if capababilities version is type 1 we can write the 73dee1ad47SJeff Kirsher * timeout of 10ms to 250ms through the GCR register 74dee1ad47SJeff Kirsher */ 75dee1ad47SJeff Kirsher if (!(gcr & IXGBE_GCR_CAP_VER2)) { 76dee1ad47SJeff Kirsher gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; 77dee1ad47SJeff Kirsher goto out; 78dee1ad47SJeff Kirsher } 79dee1ad47SJeff Kirsher 80dee1ad47SJeff Kirsher /* 81dee1ad47SJeff Kirsher * for version 2 capabilities we need to write the config space 82dee1ad47SJeff Kirsher * directly in order to set the completion timeout value for 83dee1ad47SJeff Kirsher * 16ms to 55ms 84dee1ad47SJeff Kirsher */ 8514438464SMark Rustad pcie_devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); 86dee1ad47SJeff Kirsher pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; 87ed19231cSJacob Keller ixgbe_write_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); 88dee1ad47SJeff Kirsher out: 89dee1ad47SJeff Kirsher /* disable completion timeout resend */ 90dee1ad47SJeff Kirsher gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; 91dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); 92dee1ad47SJeff Kirsher } 93dee1ad47SJeff Kirsher 94dee1ad47SJeff Kirsher static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) 95dee1ad47SJeff Kirsher { 96dee1ad47SJeff Kirsher struct ixgbe_mac_info *mac = &hw->mac; 97dee1ad47SJeff Kirsher 98dee1ad47SJeff Kirsher /* Call PHY identify routine to get the phy type */ 99dee1ad47SJeff Kirsher ixgbe_identify_phy_generic(hw); 100dee1ad47SJeff Kirsher 101dee1ad47SJeff Kirsher mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; 102dee1ad47SJeff Kirsher mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; 103dee1ad47SJeff Kirsher mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; 1046997d4d1SJacob Keller mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE; 105dee1ad47SJeff Kirsher mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; 106dee1ad47SJeff Kirsher mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; 10771161302SEmil Tantilov mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 108dee1ad47SJeff Kirsher 109dee1ad47SJeff Kirsher return 0; 110dee1ad47SJeff Kirsher } 111dee1ad47SJeff Kirsher 112dee1ad47SJeff Kirsher /** 113dee1ad47SJeff Kirsher * ixgbe_init_phy_ops_82598 - PHY/SFP specific init 114dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 115dee1ad47SJeff Kirsher * 116dee1ad47SJeff Kirsher * Initialize any function pointers that were not able to be 117dee1ad47SJeff Kirsher * set during get_invariants because the PHY/SFP type was 118dee1ad47SJeff Kirsher * not known. Perform the SFP init if necessary. 119dee1ad47SJeff Kirsher * 120dee1ad47SJeff Kirsher **/ 121dee1ad47SJeff Kirsher static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) 122dee1ad47SJeff Kirsher { 123dee1ad47SJeff Kirsher struct ixgbe_mac_info *mac = &hw->mac; 124dee1ad47SJeff Kirsher struct ixgbe_phy_info *phy = &hw->phy; 125e90dd264SMark Rustad s32 ret_val; 126dee1ad47SJeff Kirsher u16 list_offset, data_offset; 127dee1ad47SJeff Kirsher 128dee1ad47SJeff Kirsher /* Identify the PHY */ 129dee1ad47SJeff Kirsher phy->ops.identify(hw); 130dee1ad47SJeff Kirsher 131dee1ad47SJeff Kirsher /* Overwrite the link function pointers if copper PHY */ 132dee1ad47SJeff Kirsher if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 133dee1ad47SJeff Kirsher mac->ops.setup_link = &ixgbe_setup_copper_link_82598; 134dee1ad47SJeff Kirsher mac->ops.get_link_capabilities = 135dee1ad47SJeff Kirsher &ixgbe_get_copper_link_capabilities_generic; 136dee1ad47SJeff Kirsher } 137dee1ad47SJeff Kirsher 138dee1ad47SJeff Kirsher switch (hw->phy.type) { 139dee1ad47SJeff Kirsher case ixgbe_phy_tn: 140dee1ad47SJeff Kirsher phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 141dee1ad47SJeff Kirsher phy->ops.check_link = &ixgbe_check_phy_link_tnx; 142dee1ad47SJeff Kirsher phy->ops.get_firmware_version = 143dee1ad47SJeff Kirsher &ixgbe_get_phy_firmware_version_tnx; 144dee1ad47SJeff Kirsher break; 145dee1ad47SJeff Kirsher case ixgbe_phy_nl: 146dee1ad47SJeff Kirsher phy->ops.reset = &ixgbe_reset_phy_nl; 147dee1ad47SJeff Kirsher 148dee1ad47SJeff Kirsher /* Call SFP+ identify routine to get the SFP+ module type */ 149dee1ad47SJeff Kirsher ret_val = phy->ops.identify_sfp(hw); 150e90dd264SMark Rustad if (ret_val) 151e90dd264SMark Rustad return ret_val; 152e90dd264SMark Rustad if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 153e90dd264SMark Rustad return IXGBE_ERR_SFP_NOT_SUPPORTED; 154dee1ad47SJeff Kirsher 155dee1ad47SJeff Kirsher /* Check to see if SFP+ module is supported */ 156dee1ad47SJeff Kirsher ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, 157dee1ad47SJeff Kirsher &list_offset, 158dee1ad47SJeff Kirsher &data_offset); 159e90dd264SMark Rustad if (ret_val) 160e90dd264SMark Rustad return IXGBE_ERR_SFP_NOT_SUPPORTED; 161dee1ad47SJeff Kirsher break; 162dee1ad47SJeff Kirsher default: 163dee1ad47SJeff Kirsher break; 164dee1ad47SJeff Kirsher } 165dee1ad47SJeff Kirsher 166e90dd264SMark Rustad return 0; 167dee1ad47SJeff Kirsher } 168dee1ad47SJeff Kirsher 169dee1ad47SJeff Kirsher /** 170dee1ad47SJeff Kirsher * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx 171dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 172dee1ad47SJeff Kirsher * 173dee1ad47SJeff Kirsher * Starts the hardware using the generic start_hw function. 174887012e8SJeff Kirsher * Disables relaxed ordering for archs other than SPARC 175887012e8SJeff Kirsher * Then set pcie completion timeout 176dee1ad47SJeff Kirsher * 177dee1ad47SJeff Kirsher **/ 178dee1ad47SJeff Kirsher static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) 179dee1ad47SJeff Kirsher { 180887012e8SJeff Kirsher #ifndef CONFIG_SPARC 181dee1ad47SJeff Kirsher u32 regval; 182dee1ad47SJeff Kirsher u32 i; 183887012e8SJeff Kirsher #endif 184e90dd264SMark Rustad s32 ret_val; 185dee1ad47SJeff Kirsher 186dee1ad47SJeff Kirsher ret_val = ixgbe_start_hw_generic(hw); 187dee1ad47SJeff Kirsher 188887012e8SJeff Kirsher #ifndef CONFIG_SPARC 189dee1ad47SJeff Kirsher /* Disable relaxed ordering */ 190dee1ad47SJeff Kirsher for (i = 0; ((i < hw->mac.max_tx_queues) && 191dee1ad47SJeff Kirsher (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 192dee1ad47SJeff Kirsher regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 193bdda1a61SAlexander Duyck regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 194dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); 195dee1ad47SJeff Kirsher } 196dee1ad47SJeff Kirsher 197dee1ad47SJeff Kirsher for (i = 0; ((i < hw->mac.max_rx_queues) && 198dee1ad47SJeff Kirsher (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 199dee1ad47SJeff Kirsher regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 200bdda1a61SAlexander Duyck regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 201bdda1a61SAlexander Duyck IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 202dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 203dee1ad47SJeff Kirsher } 204887012e8SJeff Kirsher #endif 205e90dd264SMark Rustad if (ret_val) 206e90dd264SMark Rustad return ret_val; 207e90dd264SMark Rustad 208dee1ad47SJeff Kirsher /* set the completion timeout for interface */ 209dee1ad47SJeff Kirsher ixgbe_set_pcie_completion_timeout(hw); 210dee1ad47SJeff Kirsher 211e90dd264SMark Rustad return 0; 212dee1ad47SJeff Kirsher } 213dee1ad47SJeff Kirsher 214dee1ad47SJeff Kirsher /** 215dee1ad47SJeff Kirsher * ixgbe_get_link_capabilities_82598 - Determines link capabilities 216dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 217dee1ad47SJeff Kirsher * @speed: pointer to link speed 218dee1ad47SJeff Kirsher * @autoneg: boolean auto-negotiation value 219dee1ad47SJeff Kirsher * 220dee1ad47SJeff Kirsher * Determines the link capabilities by reading the AUTOC register. 221dee1ad47SJeff Kirsher **/ 222dee1ad47SJeff Kirsher static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 223dee1ad47SJeff Kirsher ixgbe_link_speed *speed, 224dee1ad47SJeff Kirsher bool *autoneg) 225dee1ad47SJeff Kirsher { 226dee1ad47SJeff Kirsher u32 autoc = 0; 227dee1ad47SJeff Kirsher 228dee1ad47SJeff Kirsher /* 229dee1ad47SJeff Kirsher * Determine link capabilities based on the stored value of AUTOC, 230dee1ad47SJeff Kirsher * which represents EEPROM defaults. If AUTOC value has not been 231dee1ad47SJeff Kirsher * stored, use the current register value. 232dee1ad47SJeff Kirsher */ 233dee1ad47SJeff Kirsher if (hw->mac.orig_link_settings_stored) 234dee1ad47SJeff Kirsher autoc = hw->mac.orig_autoc; 235dee1ad47SJeff Kirsher else 236dee1ad47SJeff Kirsher autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 237dee1ad47SJeff Kirsher 238dee1ad47SJeff Kirsher switch (autoc & IXGBE_AUTOC_LMS_MASK) { 239dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 240dee1ad47SJeff Kirsher *speed = IXGBE_LINK_SPEED_1GB_FULL; 241dee1ad47SJeff Kirsher *autoneg = false; 242dee1ad47SJeff Kirsher break; 243dee1ad47SJeff Kirsher 244dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 245dee1ad47SJeff Kirsher *speed = IXGBE_LINK_SPEED_10GB_FULL; 246dee1ad47SJeff Kirsher *autoneg = false; 247dee1ad47SJeff Kirsher break; 248dee1ad47SJeff Kirsher 249dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_1G_AN: 250dee1ad47SJeff Kirsher *speed = IXGBE_LINK_SPEED_1GB_FULL; 251dee1ad47SJeff Kirsher *autoneg = true; 252dee1ad47SJeff Kirsher break; 253dee1ad47SJeff Kirsher 254dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_KX4_AN: 255dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 256dee1ad47SJeff Kirsher *speed = IXGBE_LINK_SPEED_UNKNOWN; 257dee1ad47SJeff Kirsher if (autoc & IXGBE_AUTOC_KX4_SUPP) 258dee1ad47SJeff Kirsher *speed |= IXGBE_LINK_SPEED_10GB_FULL; 259dee1ad47SJeff Kirsher if (autoc & IXGBE_AUTOC_KX_SUPP) 260dee1ad47SJeff Kirsher *speed |= IXGBE_LINK_SPEED_1GB_FULL; 261dee1ad47SJeff Kirsher *autoneg = true; 262dee1ad47SJeff Kirsher break; 263dee1ad47SJeff Kirsher 264dee1ad47SJeff Kirsher default: 265e90dd264SMark Rustad return IXGBE_ERR_LINK_SETUP; 266dee1ad47SJeff Kirsher } 267dee1ad47SJeff Kirsher 268e90dd264SMark Rustad return 0; 269dee1ad47SJeff Kirsher } 270dee1ad47SJeff Kirsher 271dee1ad47SJeff Kirsher /** 272dee1ad47SJeff Kirsher * ixgbe_get_media_type_82598 - Determines media type 273dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 274dee1ad47SJeff Kirsher * 275dee1ad47SJeff Kirsher * Returns the media type (fiber, copper, backplane) 276dee1ad47SJeff Kirsher **/ 277dee1ad47SJeff Kirsher static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 278dee1ad47SJeff Kirsher { 279dee1ad47SJeff Kirsher /* Detect if there is a copper PHY attached. */ 280dee1ad47SJeff Kirsher switch (hw->phy.type) { 281dee1ad47SJeff Kirsher case ixgbe_phy_cu_unknown: 282dee1ad47SJeff Kirsher case ixgbe_phy_tn: 283e90dd264SMark Rustad return ixgbe_media_type_copper; 284e90dd264SMark Rustad 285dee1ad47SJeff Kirsher default: 286dee1ad47SJeff Kirsher break; 287dee1ad47SJeff Kirsher } 288dee1ad47SJeff Kirsher 289dee1ad47SJeff Kirsher /* Media type for I82598 is based on device ID */ 290dee1ad47SJeff Kirsher switch (hw->device_id) { 291dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598: 292dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598_BX: 293dee1ad47SJeff Kirsher /* Default device ID is mezzanine card KX/KX4 */ 294e90dd264SMark Rustad return ixgbe_media_type_backplane; 295e90dd264SMark Rustad 296dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598AF_DUAL_PORT: 297dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 298dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 299dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 300dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598EB_XF_LR: 301dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598EB_SFP_LOM: 302e90dd264SMark Rustad return ixgbe_media_type_fiber; 303e90dd264SMark Rustad 304dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598EB_CX4: 305dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 306e90dd264SMark Rustad return ixgbe_media_type_cx4; 307e90dd264SMark Rustad 308dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598AT: 309dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598AT2: 310e90dd264SMark Rustad return ixgbe_media_type_copper; 311e90dd264SMark Rustad 312dee1ad47SJeff Kirsher default: 313e90dd264SMark Rustad return ixgbe_media_type_unknown; 314dee1ad47SJeff Kirsher } 315dee1ad47SJeff Kirsher } 316dee1ad47SJeff Kirsher 317dee1ad47SJeff Kirsher /** 318dee1ad47SJeff Kirsher * ixgbe_fc_enable_82598 - Enable flow control 319dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 320dee1ad47SJeff Kirsher * 321dee1ad47SJeff Kirsher * Enable flow control according to the current settings. 322dee1ad47SJeff Kirsher **/ 323041441d0SAlexander Duyck static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw) 324dee1ad47SJeff Kirsher { 325dee1ad47SJeff Kirsher u32 fctrl_reg; 326dee1ad47SJeff Kirsher u32 rmcs_reg; 327dee1ad47SJeff Kirsher u32 reg; 328041441d0SAlexander Duyck u32 fcrtl, fcrth; 329dee1ad47SJeff Kirsher u32 link_speed = 0; 330041441d0SAlexander Duyck int i; 331dee1ad47SJeff Kirsher bool link_up; 332dee1ad47SJeff Kirsher 333e5776620SJacob Keller /* Validate the water mark configuration */ 334e90dd264SMark Rustad if (!hw->fc.pause_time) 335e90dd264SMark Rustad return IXGBE_ERR_INVALID_LINK_SETTINGS; 336e5776620SJacob Keller 337e5776620SJacob Keller /* Low water mark of zero causes XOFF floods */ 338e5776620SJacob Keller for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 339e5776620SJacob Keller if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 340e5776620SJacob Keller hw->fc.high_water[i]) { 341e5776620SJacob Keller if (!hw->fc.low_water[i] || 342e5776620SJacob Keller hw->fc.low_water[i] >= hw->fc.high_water[i]) { 343041441d0SAlexander Duyck hw_dbg(hw, "Invalid water mark configuration\n"); 344e90dd264SMark Rustad return IXGBE_ERR_INVALID_LINK_SETTINGS; 345041441d0SAlexander Duyck } 346e5776620SJacob Keller } 347e5776620SJacob Keller } 348dee1ad47SJeff Kirsher 349dee1ad47SJeff Kirsher /* 350dee1ad47SJeff Kirsher * On 82598 having Rx FC on causes resets while doing 1G 351dee1ad47SJeff Kirsher * so if it's on turn it off once we know link_speed. For 352dee1ad47SJeff Kirsher * more details see 82598 Specification update. 353dee1ad47SJeff Kirsher */ 354dee1ad47SJeff Kirsher hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 355dee1ad47SJeff Kirsher if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) { 356dee1ad47SJeff Kirsher switch (hw->fc.requested_mode) { 357dee1ad47SJeff Kirsher case ixgbe_fc_full: 358dee1ad47SJeff Kirsher hw->fc.requested_mode = ixgbe_fc_tx_pause; 359dee1ad47SJeff Kirsher break; 360dee1ad47SJeff Kirsher case ixgbe_fc_rx_pause: 361dee1ad47SJeff Kirsher hw->fc.requested_mode = ixgbe_fc_none; 362dee1ad47SJeff Kirsher break; 363dee1ad47SJeff Kirsher default: 364dee1ad47SJeff Kirsher /* no change */ 365dee1ad47SJeff Kirsher break; 366dee1ad47SJeff Kirsher } 367dee1ad47SJeff Kirsher } 368dee1ad47SJeff Kirsher 369dee1ad47SJeff Kirsher /* Negotiate the fc mode to use */ 370786e9a5fSAlexander Duyck ixgbe_fc_autoneg(hw); 371dee1ad47SJeff Kirsher 372dee1ad47SJeff Kirsher /* Disable any previous flow control settings */ 373dee1ad47SJeff Kirsher fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 374dee1ad47SJeff Kirsher fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 375dee1ad47SJeff Kirsher 376dee1ad47SJeff Kirsher rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 377dee1ad47SJeff Kirsher rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 378dee1ad47SJeff Kirsher 379dee1ad47SJeff Kirsher /* 380dee1ad47SJeff Kirsher * The possible values of fc.current_mode are: 381dee1ad47SJeff Kirsher * 0: Flow control is completely disabled 382dee1ad47SJeff Kirsher * 1: Rx flow control is enabled (we can receive pause frames, 383dee1ad47SJeff Kirsher * but not send pause frames). 384dee1ad47SJeff Kirsher * 2: Tx flow control is enabled (we can send pause frames but 385dee1ad47SJeff Kirsher * we do not support receiving pause frames). 386dee1ad47SJeff Kirsher * 3: Both Rx and Tx flow control (symmetric) are enabled. 387dee1ad47SJeff Kirsher * other: Invalid. 388dee1ad47SJeff Kirsher */ 389dee1ad47SJeff Kirsher switch (hw->fc.current_mode) { 390dee1ad47SJeff Kirsher case ixgbe_fc_none: 391dee1ad47SJeff Kirsher /* 392dee1ad47SJeff Kirsher * Flow control is disabled by software override or autoneg. 393dee1ad47SJeff Kirsher * The code below will actually disable it in the HW. 394dee1ad47SJeff Kirsher */ 395dee1ad47SJeff Kirsher break; 396dee1ad47SJeff Kirsher case ixgbe_fc_rx_pause: 397dee1ad47SJeff Kirsher /* 398dee1ad47SJeff Kirsher * Rx Flow control is enabled and Tx Flow control is 399dee1ad47SJeff Kirsher * disabled by software override. Since there really 400dee1ad47SJeff Kirsher * isn't a way to advertise that we are capable of RX 401dee1ad47SJeff Kirsher * Pause ONLY, we will advertise that we support both 402dee1ad47SJeff Kirsher * symmetric and asymmetric Rx PAUSE. Later, we will 403dee1ad47SJeff Kirsher * disable the adapter's ability to send PAUSE frames. 404dee1ad47SJeff Kirsher */ 405dee1ad47SJeff Kirsher fctrl_reg |= IXGBE_FCTRL_RFCE; 406dee1ad47SJeff Kirsher break; 407dee1ad47SJeff Kirsher case ixgbe_fc_tx_pause: 408dee1ad47SJeff Kirsher /* 409dee1ad47SJeff Kirsher * Tx Flow control is enabled, and Rx Flow control is 410dee1ad47SJeff Kirsher * disabled by software override. 411dee1ad47SJeff Kirsher */ 412dee1ad47SJeff Kirsher rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 413dee1ad47SJeff Kirsher break; 414dee1ad47SJeff Kirsher case ixgbe_fc_full: 415dee1ad47SJeff Kirsher /* Flow control (both Rx and Tx) is enabled by SW override. */ 416dee1ad47SJeff Kirsher fctrl_reg |= IXGBE_FCTRL_RFCE; 417dee1ad47SJeff Kirsher rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 418dee1ad47SJeff Kirsher break; 419dee1ad47SJeff Kirsher default: 420dee1ad47SJeff Kirsher hw_dbg(hw, "Flow control param set incorrectly\n"); 421e90dd264SMark Rustad return IXGBE_ERR_CONFIG; 422dee1ad47SJeff Kirsher } 423dee1ad47SJeff Kirsher 424dee1ad47SJeff Kirsher /* Set 802.3x based flow control settings. */ 425dee1ad47SJeff Kirsher fctrl_reg |= IXGBE_FCTRL_DPF; 426dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); 427dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 428dee1ad47SJeff Kirsher 429dee1ad47SJeff Kirsher /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 430041441d0SAlexander Duyck for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 431041441d0SAlexander Duyck if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 432041441d0SAlexander Duyck hw->fc.high_water[i]) { 433e5776620SJacob Keller fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 434041441d0SAlexander Duyck fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 435041441d0SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl); 436041441d0SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth); 437041441d0SAlexander Duyck } else { 438041441d0SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); 439041441d0SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); 440041441d0SAlexander Duyck } 441dee1ad47SJeff Kirsher 442dee1ad47SJeff Kirsher } 443dee1ad47SJeff Kirsher 444dee1ad47SJeff Kirsher /* Configure pause time (2 TCs per register) */ 445041441d0SAlexander Duyck reg = hw->fc.pause_time * 0x00010001; 446041441d0SAlexander Duyck for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) 447041441d0SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 448dee1ad47SJeff Kirsher 449041441d0SAlexander Duyck /* Configure flow control refresh threshold value */ 450041441d0SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 451dee1ad47SJeff Kirsher 452e90dd264SMark Rustad return 0; 453dee1ad47SJeff Kirsher } 454dee1ad47SJeff Kirsher 455dee1ad47SJeff Kirsher /** 456dee1ad47SJeff Kirsher * ixgbe_start_mac_link_82598 - Configures MAC link settings 457dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 458dee1ad47SJeff Kirsher * 459dee1ad47SJeff Kirsher * Configures link settings based on values in the ixgbe_hw struct. 460dee1ad47SJeff Kirsher * Restarts the link. Performs autonegotiation if needed. 461dee1ad47SJeff Kirsher **/ 462dee1ad47SJeff Kirsher static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, 463dee1ad47SJeff Kirsher bool autoneg_wait_to_complete) 464dee1ad47SJeff Kirsher { 465dee1ad47SJeff Kirsher u32 autoc_reg; 466dee1ad47SJeff Kirsher u32 links_reg; 467dee1ad47SJeff Kirsher u32 i; 468dee1ad47SJeff Kirsher s32 status = 0; 469dee1ad47SJeff Kirsher 470dee1ad47SJeff Kirsher /* Restart link */ 471dee1ad47SJeff Kirsher autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 472dee1ad47SJeff Kirsher autoc_reg |= IXGBE_AUTOC_AN_RESTART; 473dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 474dee1ad47SJeff Kirsher 475dee1ad47SJeff Kirsher /* Only poll for autoneg to complete if specified to do so */ 476dee1ad47SJeff Kirsher if (autoneg_wait_to_complete) { 477dee1ad47SJeff Kirsher if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 478dee1ad47SJeff Kirsher IXGBE_AUTOC_LMS_KX4_AN || 479dee1ad47SJeff Kirsher (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 480dee1ad47SJeff Kirsher IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 481dee1ad47SJeff Kirsher links_reg = 0; /* Just in case Autoneg time = 0 */ 482dee1ad47SJeff Kirsher for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 483dee1ad47SJeff Kirsher links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 484dee1ad47SJeff Kirsher if (links_reg & IXGBE_LINKS_KX_AN_COMP) 485dee1ad47SJeff Kirsher break; 486dee1ad47SJeff Kirsher msleep(100); 487dee1ad47SJeff Kirsher } 488dee1ad47SJeff Kirsher if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 489dee1ad47SJeff Kirsher status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 490dee1ad47SJeff Kirsher hw_dbg(hw, "Autonegotiation did not complete.\n"); 491dee1ad47SJeff Kirsher } 492dee1ad47SJeff Kirsher } 493dee1ad47SJeff Kirsher } 494dee1ad47SJeff Kirsher 495dee1ad47SJeff Kirsher /* Add delay to filter out noises during initial link setup */ 496dee1ad47SJeff Kirsher msleep(50); 497dee1ad47SJeff Kirsher 498dee1ad47SJeff Kirsher return status; 499dee1ad47SJeff Kirsher } 500dee1ad47SJeff Kirsher 501dee1ad47SJeff Kirsher /** 502dee1ad47SJeff Kirsher * ixgbe_validate_link_ready - Function looks for phy link 503dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 504dee1ad47SJeff Kirsher * 505dee1ad47SJeff Kirsher * Function indicates success when phy link is available. If phy is not ready 506dee1ad47SJeff Kirsher * within 5 seconds of MAC indicating link, the function returns error. 507dee1ad47SJeff Kirsher **/ 508dee1ad47SJeff Kirsher static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) 509dee1ad47SJeff Kirsher { 510dee1ad47SJeff Kirsher u32 timeout; 511dee1ad47SJeff Kirsher u16 an_reg; 512dee1ad47SJeff Kirsher 513dee1ad47SJeff Kirsher if (hw->device_id != IXGBE_DEV_ID_82598AT2) 514dee1ad47SJeff Kirsher return 0; 515dee1ad47SJeff Kirsher 516dee1ad47SJeff Kirsher for (timeout = 0; 517dee1ad47SJeff Kirsher timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) { 518dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg); 519dee1ad47SJeff Kirsher 520dee1ad47SJeff Kirsher if ((an_reg & MDIO_AN_STAT1_COMPLETE) && 521dee1ad47SJeff Kirsher (an_reg & MDIO_STAT1_LSTATUS)) 522dee1ad47SJeff Kirsher break; 523dee1ad47SJeff Kirsher 524dee1ad47SJeff Kirsher msleep(100); 525dee1ad47SJeff Kirsher } 526dee1ad47SJeff Kirsher 527dee1ad47SJeff Kirsher if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) { 528dee1ad47SJeff Kirsher hw_dbg(hw, "Link was indicated but link is down\n"); 529dee1ad47SJeff Kirsher return IXGBE_ERR_LINK_SETUP; 530dee1ad47SJeff Kirsher } 531dee1ad47SJeff Kirsher 532dee1ad47SJeff Kirsher return 0; 533dee1ad47SJeff Kirsher } 534dee1ad47SJeff Kirsher 535dee1ad47SJeff Kirsher /** 536dee1ad47SJeff Kirsher * ixgbe_check_mac_link_82598 - Get link/speed status 537dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 538dee1ad47SJeff Kirsher * @speed: pointer to link speed 539dee1ad47SJeff Kirsher * @link_up: true is link is up, false otherwise 540dee1ad47SJeff Kirsher * @link_up_wait_to_complete: bool used to wait for link up or not 541dee1ad47SJeff Kirsher * 542dee1ad47SJeff Kirsher * Reads the links register to determine if link is up and the current speed 543dee1ad47SJeff Kirsher **/ 544dee1ad47SJeff Kirsher static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 545dee1ad47SJeff Kirsher ixgbe_link_speed *speed, bool *link_up, 546dee1ad47SJeff Kirsher bool link_up_wait_to_complete) 547dee1ad47SJeff Kirsher { 548dee1ad47SJeff Kirsher u32 links_reg; 549dee1ad47SJeff Kirsher u32 i; 550dee1ad47SJeff Kirsher u16 link_reg, adapt_comp_reg; 551dee1ad47SJeff Kirsher 552dee1ad47SJeff Kirsher /* 553dee1ad47SJeff Kirsher * SERDES PHY requires us to read link status from register 0xC79F. 554dee1ad47SJeff Kirsher * Bit 0 set indicates link is up/ready; clear indicates link down. 555dee1ad47SJeff Kirsher * 0xC00C is read to check that the XAUI lanes are active. Bit 0 556dee1ad47SJeff Kirsher * clear indicates active; set indicates inactive. 557dee1ad47SJeff Kirsher */ 558dee1ad47SJeff Kirsher if (hw->phy.type == ixgbe_phy_nl) { 559dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); 560dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); 561dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD, 562dee1ad47SJeff Kirsher &adapt_comp_reg); 563dee1ad47SJeff Kirsher if (link_up_wait_to_complete) { 564dee1ad47SJeff Kirsher for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 565dee1ad47SJeff Kirsher if ((link_reg & 1) && 566dee1ad47SJeff Kirsher ((adapt_comp_reg & 1) == 0)) { 567dee1ad47SJeff Kirsher *link_up = true; 568dee1ad47SJeff Kirsher break; 569dee1ad47SJeff Kirsher } else { 570dee1ad47SJeff Kirsher *link_up = false; 571dee1ad47SJeff Kirsher } 572dee1ad47SJeff Kirsher msleep(100); 573dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, 0xC79F, 574dee1ad47SJeff Kirsher MDIO_MMD_PMAPMD, 575dee1ad47SJeff Kirsher &link_reg); 576dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, 0xC00C, 577dee1ad47SJeff Kirsher MDIO_MMD_PMAPMD, 578dee1ad47SJeff Kirsher &adapt_comp_reg); 579dee1ad47SJeff Kirsher } 580dee1ad47SJeff Kirsher } else { 581dee1ad47SJeff Kirsher if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) 582dee1ad47SJeff Kirsher *link_up = true; 583dee1ad47SJeff Kirsher else 584dee1ad47SJeff Kirsher *link_up = false; 585dee1ad47SJeff Kirsher } 586dee1ad47SJeff Kirsher 58723677ce3SJoe Perches if (!*link_up) 588e90dd264SMark Rustad return 0; 589dee1ad47SJeff Kirsher } 590dee1ad47SJeff Kirsher 591dee1ad47SJeff Kirsher links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 592dee1ad47SJeff Kirsher if (link_up_wait_to_complete) { 593dee1ad47SJeff Kirsher for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 594dee1ad47SJeff Kirsher if (links_reg & IXGBE_LINKS_UP) { 595dee1ad47SJeff Kirsher *link_up = true; 596dee1ad47SJeff Kirsher break; 597dee1ad47SJeff Kirsher } else { 598dee1ad47SJeff Kirsher *link_up = false; 599dee1ad47SJeff Kirsher } 600dee1ad47SJeff Kirsher msleep(100); 601dee1ad47SJeff Kirsher links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 602dee1ad47SJeff Kirsher } 603dee1ad47SJeff Kirsher } else { 604dee1ad47SJeff Kirsher if (links_reg & IXGBE_LINKS_UP) 605dee1ad47SJeff Kirsher *link_up = true; 606dee1ad47SJeff Kirsher else 607dee1ad47SJeff Kirsher *link_up = false; 608dee1ad47SJeff Kirsher } 609dee1ad47SJeff Kirsher 610dee1ad47SJeff Kirsher if (links_reg & IXGBE_LINKS_SPEED) 611dee1ad47SJeff Kirsher *speed = IXGBE_LINK_SPEED_10GB_FULL; 612dee1ad47SJeff Kirsher else 613dee1ad47SJeff Kirsher *speed = IXGBE_LINK_SPEED_1GB_FULL; 614dee1ad47SJeff Kirsher 61523677ce3SJoe Perches if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && *link_up && 616dee1ad47SJeff Kirsher (ixgbe_validate_link_ready(hw) != 0)) 617dee1ad47SJeff Kirsher *link_up = false; 618dee1ad47SJeff Kirsher 619dee1ad47SJeff Kirsher return 0; 620dee1ad47SJeff Kirsher } 621dee1ad47SJeff Kirsher 622dee1ad47SJeff Kirsher /** 623dee1ad47SJeff Kirsher * ixgbe_setup_mac_link_82598 - Set MAC link speed 624dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 625dee1ad47SJeff Kirsher * @speed: new link speed 626dee1ad47SJeff Kirsher * @autoneg_wait_to_complete: true when waiting for completion is needed 627dee1ad47SJeff Kirsher * 628dee1ad47SJeff Kirsher * Set the link speed in the AUTOC register and restarts link. 629dee1ad47SJeff Kirsher **/ 630dee1ad47SJeff Kirsher static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, 631fd0326f2SJosh Hay ixgbe_link_speed speed, 632dee1ad47SJeff Kirsher bool autoneg_wait_to_complete) 633dee1ad47SJeff Kirsher { 634fd0326f2SJosh Hay bool autoneg = false; 635dee1ad47SJeff Kirsher ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 636dee1ad47SJeff Kirsher u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 637dee1ad47SJeff Kirsher u32 autoc = curr_autoc; 638dee1ad47SJeff Kirsher u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 639dee1ad47SJeff Kirsher 640dee1ad47SJeff Kirsher /* Check to see if speed passed in is supported. */ 641dee1ad47SJeff Kirsher ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg); 642dee1ad47SJeff Kirsher speed &= link_capabilities; 643dee1ad47SJeff Kirsher 644dee1ad47SJeff Kirsher if (speed == IXGBE_LINK_SPEED_UNKNOWN) 645e90dd264SMark Rustad return IXGBE_ERR_LINK_SETUP; 646dee1ad47SJeff Kirsher 647dee1ad47SJeff Kirsher /* Set KX4/KX support according to speed requested */ 648dee1ad47SJeff Kirsher else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || 649dee1ad47SJeff Kirsher link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 650dee1ad47SJeff Kirsher autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; 651dee1ad47SJeff Kirsher if (speed & IXGBE_LINK_SPEED_10GB_FULL) 652dee1ad47SJeff Kirsher autoc |= IXGBE_AUTOC_KX4_SUPP; 653dee1ad47SJeff Kirsher if (speed & IXGBE_LINK_SPEED_1GB_FULL) 654dee1ad47SJeff Kirsher autoc |= IXGBE_AUTOC_KX_SUPP; 655dee1ad47SJeff Kirsher if (autoc != curr_autoc) 656dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 657dee1ad47SJeff Kirsher } 658dee1ad47SJeff Kirsher 659e90dd264SMark Rustad /* Setup and restart the link based on the new values in 660dee1ad47SJeff Kirsher * ixgbe_hw This will write the AUTOC register based on the new 661dee1ad47SJeff Kirsher * stored values 662dee1ad47SJeff Kirsher */ 663e90dd264SMark Rustad return ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); 664dee1ad47SJeff Kirsher } 665dee1ad47SJeff Kirsher 666dee1ad47SJeff Kirsher 667dee1ad47SJeff Kirsher /** 668dee1ad47SJeff Kirsher * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field 669dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 670dee1ad47SJeff Kirsher * @speed: new link speed 671dee1ad47SJeff Kirsher * @autoneg_wait_to_complete: true if waiting is needed to complete 672dee1ad47SJeff Kirsher * 673dee1ad47SJeff Kirsher * Sets the link speed in the AUTOC register in the MAC and restarts link. 674dee1ad47SJeff Kirsher **/ 675dee1ad47SJeff Kirsher static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 676dee1ad47SJeff Kirsher ixgbe_link_speed speed, 677dee1ad47SJeff Kirsher bool autoneg_wait_to_complete) 678dee1ad47SJeff Kirsher { 679dee1ad47SJeff Kirsher s32 status; 680dee1ad47SJeff Kirsher 681dee1ad47SJeff Kirsher /* Setup the PHY according to input speed */ 68299b76642SJosh Hay status = hw->phy.ops.setup_link_speed(hw, speed, 683dee1ad47SJeff Kirsher autoneg_wait_to_complete); 684dee1ad47SJeff Kirsher /* Set up MAC */ 685dee1ad47SJeff Kirsher ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); 686dee1ad47SJeff Kirsher 687dee1ad47SJeff Kirsher return status; 688dee1ad47SJeff Kirsher } 689dee1ad47SJeff Kirsher 690dee1ad47SJeff Kirsher /** 691dee1ad47SJeff Kirsher * ixgbe_reset_hw_82598 - Performs hardware reset 692dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 693dee1ad47SJeff Kirsher * 694dee1ad47SJeff Kirsher * Resets the hardware by resetting the transmit and receive units, masks and 695dee1ad47SJeff Kirsher * clears all interrupts, performing a PHY reset, and performing a link (MAC) 696dee1ad47SJeff Kirsher * reset. 697dee1ad47SJeff Kirsher **/ 698dee1ad47SJeff Kirsher static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 699dee1ad47SJeff Kirsher { 700e90dd264SMark Rustad s32 status; 701dee1ad47SJeff Kirsher s32 phy_status = 0; 702dee1ad47SJeff Kirsher u32 ctrl; 703dee1ad47SJeff Kirsher u32 gheccr; 704dee1ad47SJeff Kirsher u32 i; 705dee1ad47SJeff Kirsher u32 autoc; 706dee1ad47SJeff Kirsher u8 analog_val; 707dee1ad47SJeff Kirsher 708dee1ad47SJeff Kirsher /* Call adapter stop to disable tx/rx and clear interrupts */ 709ff9d1a5aSEmil Tantilov status = hw->mac.ops.stop_adapter(hw); 710e90dd264SMark Rustad if (status) 711e90dd264SMark Rustad return status; 712dee1ad47SJeff Kirsher 713dee1ad47SJeff Kirsher /* 714dee1ad47SJeff Kirsher * Power up the Atlas Tx lanes if they are currently powered down. 715dee1ad47SJeff Kirsher * Atlas Tx lanes are powered down for MAC loopback tests, but 716dee1ad47SJeff Kirsher * they are not automatically restored on reset. 717dee1ad47SJeff Kirsher */ 718dee1ad47SJeff Kirsher hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 719dee1ad47SJeff Kirsher if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 720dee1ad47SJeff Kirsher /* Enable Tx Atlas so packets can be transmitted again */ 721dee1ad47SJeff Kirsher hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 722dee1ad47SJeff Kirsher &analog_val); 723dee1ad47SJeff Kirsher analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 724dee1ad47SJeff Kirsher hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 725dee1ad47SJeff Kirsher analog_val); 726dee1ad47SJeff Kirsher 727dee1ad47SJeff Kirsher hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 728dee1ad47SJeff Kirsher &analog_val); 729dee1ad47SJeff Kirsher analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 730dee1ad47SJeff Kirsher hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 731dee1ad47SJeff Kirsher analog_val); 732dee1ad47SJeff Kirsher 733dee1ad47SJeff Kirsher hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 734dee1ad47SJeff Kirsher &analog_val); 735dee1ad47SJeff Kirsher analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 736dee1ad47SJeff Kirsher hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 737dee1ad47SJeff Kirsher analog_val); 738dee1ad47SJeff Kirsher 739dee1ad47SJeff Kirsher hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 740dee1ad47SJeff Kirsher &analog_val); 741dee1ad47SJeff Kirsher analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 742dee1ad47SJeff Kirsher hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 743dee1ad47SJeff Kirsher analog_val); 744dee1ad47SJeff Kirsher } 745dee1ad47SJeff Kirsher 746dee1ad47SJeff Kirsher /* Reset PHY */ 747dee1ad47SJeff Kirsher if (hw->phy.reset_disable == false) { 748dee1ad47SJeff Kirsher /* PHY ops must be identified and initialized prior to reset */ 749dee1ad47SJeff Kirsher 750dee1ad47SJeff Kirsher /* Init PHY and function pointers, perform SFP setup */ 751dee1ad47SJeff Kirsher phy_status = hw->phy.ops.init(hw); 752dee1ad47SJeff Kirsher if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) 753e90dd264SMark Rustad return phy_status; 754ff9d1a5aSEmil Tantilov if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) 755ff9d1a5aSEmil Tantilov goto mac_reset_top; 756dee1ad47SJeff Kirsher 757dee1ad47SJeff Kirsher hw->phy.ops.reset(hw); 758dee1ad47SJeff Kirsher } 759dee1ad47SJeff Kirsher 760dee1ad47SJeff Kirsher mac_reset_top: 761dee1ad47SJeff Kirsher /* 762dee1ad47SJeff Kirsher * Issue global reset to the MAC. This needs to be a SW reset. 763dee1ad47SJeff Kirsher * If link reset is used, it might reset the MAC when mng is using it 764dee1ad47SJeff Kirsher */ 7658132b54eSAlexander Duyck ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST; 7668132b54eSAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 767dee1ad47SJeff Kirsher IXGBE_WRITE_FLUSH(hw); 768efff2e02SMark Rustad usleep_range(1000, 1200); 769dee1ad47SJeff Kirsher 770dee1ad47SJeff Kirsher /* Poll for reset bit to self-clear indicating reset is complete */ 771dee1ad47SJeff Kirsher for (i = 0; i < 10; i++) { 772dee1ad47SJeff Kirsher ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 773dee1ad47SJeff Kirsher if (!(ctrl & IXGBE_CTRL_RST)) 774dee1ad47SJeff Kirsher break; 775efff2e02SMark Rustad udelay(1); 776dee1ad47SJeff Kirsher } 777dee1ad47SJeff Kirsher if (ctrl & IXGBE_CTRL_RST) { 778dee1ad47SJeff Kirsher status = IXGBE_ERR_RESET_FAILED; 779dee1ad47SJeff Kirsher hw_dbg(hw, "Reset polling failed to complete.\n"); 780dee1ad47SJeff Kirsher } 781dee1ad47SJeff Kirsher 7828132b54eSAlexander Duyck msleep(50); 7838132b54eSAlexander Duyck 784dee1ad47SJeff Kirsher /* 785dee1ad47SJeff Kirsher * Double resets are required for recovery from certain error 786dee1ad47SJeff Kirsher * conditions. Between resets, it is necessary to stall to allow time 7878132b54eSAlexander Duyck * for any pending HW events to complete. 788dee1ad47SJeff Kirsher */ 789dee1ad47SJeff Kirsher if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 790dee1ad47SJeff Kirsher hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 791dee1ad47SJeff Kirsher goto mac_reset_top; 792dee1ad47SJeff Kirsher } 793dee1ad47SJeff Kirsher 794dee1ad47SJeff Kirsher gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 795b4f47a48SJacob Keller gheccr &= ~(BIT(21) | BIT(18) | BIT(9) | BIT(6)); 796dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 797dee1ad47SJeff Kirsher 798dee1ad47SJeff Kirsher /* 799dee1ad47SJeff Kirsher * Store the original AUTOC value if it has not been 800dee1ad47SJeff Kirsher * stored off yet. Otherwise restore the stored original 801dee1ad47SJeff Kirsher * AUTOC value since the reset operation sets back to deaults. 802dee1ad47SJeff Kirsher */ 803dee1ad47SJeff Kirsher autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 804dee1ad47SJeff Kirsher if (hw->mac.orig_link_settings_stored == false) { 805dee1ad47SJeff Kirsher hw->mac.orig_autoc = autoc; 806dee1ad47SJeff Kirsher hw->mac.orig_link_settings_stored = true; 807dee1ad47SJeff Kirsher } else if (autoc != hw->mac.orig_autoc) { 808dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); 809dee1ad47SJeff Kirsher } 810dee1ad47SJeff Kirsher 811dee1ad47SJeff Kirsher /* Store the permanent mac address */ 812dee1ad47SJeff Kirsher hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 813dee1ad47SJeff Kirsher 814dee1ad47SJeff Kirsher /* 815dee1ad47SJeff Kirsher * Store MAC address from RAR0, clear receive address registers, and 816dee1ad47SJeff Kirsher * clear the multicast table 817dee1ad47SJeff Kirsher */ 818dee1ad47SJeff Kirsher hw->mac.ops.init_rx_addrs(hw); 819dee1ad47SJeff Kirsher 820dee1ad47SJeff Kirsher if (phy_status) 821dee1ad47SJeff Kirsher status = phy_status; 822dee1ad47SJeff Kirsher 823dee1ad47SJeff Kirsher return status; 824dee1ad47SJeff Kirsher } 825dee1ad47SJeff Kirsher 826dee1ad47SJeff Kirsher /** 827dee1ad47SJeff Kirsher * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 828dee1ad47SJeff Kirsher * @hw: pointer to hardware struct 829dee1ad47SJeff Kirsher * @rar: receive address register index to associate with a VMDq index 830dee1ad47SJeff Kirsher * @vmdq: VMDq set index 831dee1ad47SJeff Kirsher **/ 832dee1ad47SJeff Kirsher static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 833dee1ad47SJeff Kirsher { 834dee1ad47SJeff Kirsher u32 rar_high; 835dee1ad47SJeff Kirsher u32 rar_entries = hw->mac.num_rar_entries; 836dee1ad47SJeff Kirsher 837dee1ad47SJeff Kirsher /* Make sure we are using a valid rar index range */ 838dee1ad47SJeff Kirsher if (rar >= rar_entries) { 839dee1ad47SJeff Kirsher hw_dbg(hw, "RAR index %d is out of range.\n", rar); 840dee1ad47SJeff Kirsher return IXGBE_ERR_INVALID_ARGUMENT; 841dee1ad47SJeff Kirsher } 842dee1ad47SJeff Kirsher 843dee1ad47SJeff Kirsher rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 844dee1ad47SJeff Kirsher rar_high &= ~IXGBE_RAH_VIND_MASK; 845dee1ad47SJeff Kirsher rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 846dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 847dee1ad47SJeff Kirsher return 0; 848dee1ad47SJeff Kirsher } 849dee1ad47SJeff Kirsher 850dee1ad47SJeff Kirsher /** 851dee1ad47SJeff Kirsher * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address 852dee1ad47SJeff Kirsher * @hw: pointer to hardware struct 853dee1ad47SJeff Kirsher * @rar: receive address register index to associate with a VMDq index 854dee1ad47SJeff Kirsher * @vmdq: VMDq clear index (not used in 82598, but elsewhere) 855dee1ad47SJeff Kirsher **/ 856dee1ad47SJeff Kirsher static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 857dee1ad47SJeff Kirsher { 858dee1ad47SJeff Kirsher u32 rar_high; 859dee1ad47SJeff Kirsher u32 rar_entries = hw->mac.num_rar_entries; 860dee1ad47SJeff Kirsher 861dee1ad47SJeff Kirsher 862dee1ad47SJeff Kirsher /* Make sure we are using a valid rar index range */ 863dee1ad47SJeff Kirsher if (rar >= rar_entries) { 864dee1ad47SJeff Kirsher hw_dbg(hw, "RAR index %d is out of range.\n", rar); 865dee1ad47SJeff Kirsher return IXGBE_ERR_INVALID_ARGUMENT; 866dee1ad47SJeff Kirsher } 867dee1ad47SJeff Kirsher 868dee1ad47SJeff Kirsher rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 869dee1ad47SJeff Kirsher if (rar_high & IXGBE_RAH_VIND_MASK) { 870dee1ad47SJeff Kirsher rar_high &= ~IXGBE_RAH_VIND_MASK; 871dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 872dee1ad47SJeff Kirsher } 873dee1ad47SJeff Kirsher 874dee1ad47SJeff Kirsher return 0; 875dee1ad47SJeff Kirsher } 876dee1ad47SJeff Kirsher 877dee1ad47SJeff Kirsher /** 878dee1ad47SJeff Kirsher * ixgbe_set_vfta_82598 - Set VLAN filter table 879dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 880dee1ad47SJeff Kirsher * @vlan: VLAN id to write to VLAN filter 881dee1ad47SJeff Kirsher * @vind: VMDq output index that maps queue to VLAN id in VFTA 882dee1ad47SJeff Kirsher * @vlan_on: boolean flag to turn on/off VLAN in VFTA 883b6488b66SAlexander Duyck * @vlvf_bypass: boolean flag - unused 884dee1ad47SJeff Kirsher * 885dee1ad47SJeff Kirsher * Turn on/off specified VLAN in the VLAN filter table. 886dee1ad47SJeff Kirsher **/ 887dee1ad47SJeff Kirsher static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, 888b6488b66SAlexander Duyck bool vlan_on, bool vlvf_bypass) 889dee1ad47SJeff Kirsher { 890dee1ad47SJeff Kirsher u32 regindex; 891dee1ad47SJeff Kirsher u32 bitindex; 892dee1ad47SJeff Kirsher u32 bits; 893dee1ad47SJeff Kirsher u32 vftabyte; 894dee1ad47SJeff Kirsher 895dee1ad47SJeff Kirsher if (vlan > 4095) 896dee1ad47SJeff Kirsher return IXGBE_ERR_PARAM; 897dee1ad47SJeff Kirsher 898dee1ad47SJeff Kirsher /* Determine 32-bit word position in array */ 899dee1ad47SJeff Kirsher regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ 900dee1ad47SJeff Kirsher 901dee1ad47SJeff Kirsher /* Determine the location of the (VMD) queue index */ 902dee1ad47SJeff Kirsher vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 903dee1ad47SJeff Kirsher bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 904dee1ad47SJeff Kirsher 905dee1ad47SJeff Kirsher /* Set the nibble for VMD queue index */ 906dee1ad47SJeff Kirsher bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); 907dee1ad47SJeff Kirsher bits &= (~(0x0F << bitindex)); 908dee1ad47SJeff Kirsher bits |= (vind << bitindex); 909dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); 910dee1ad47SJeff Kirsher 911dee1ad47SJeff Kirsher /* Determine the location of the bit for this VLAN id */ 912dee1ad47SJeff Kirsher bitindex = vlan & 0x1F; /* lower five bits */ 913dee1ad47SJeff Kirsher 914dee1ad47SJeff Kirsher bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 915dee1ad47SJeff Kirsher if (vlan_on) 916dee1ad47SJeff Kirsher /* Turn on this VLAN id */ 917b4f47a48SJacob Keller bits |= BIT(bitindex); 918dee1ad47SJeff Kirsher else 919dee1ad47SJeff Kirsher /* Turn off this VLAN id */ 920b4f47a48SJacob Keller bits &= ~BIT(bitindex); 921dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 922dee1ad47SJeff Kirsher 923dee1ad47SJeff Kirsher return 0; 924dee1ad47SJeff Kirsher } 925dee1ad47SJeff Kirsher 926dee1ad47SJeff Kirsher /** 927dee1ad47SJeff Kirsher * ixgbe_clear_vfta_82598 - Clear VLAN filter table 928dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 929dee1ad47SJeff Kirsher * 930dee1ad47SJeff Kirsher * Clears the VLAN filer table, and the VMDq index associated with the filter 931dee1ad47SJeff Kirsher **/ 932dee1ad47SJeff Kirsher static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) 933dee1ad47SJeff Kirsher { 934dee1ad47SJeff Kirsher u32 offset; 935dee1ad47SJeff Kirsher u32 vlanbyte; 936dee1ad47SJeff Kirsher 937dee1ad47SJeff Kirsher for (offset = 0; offset < hw->mac.vft_size; offset++) 938dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 939dee1ad47SJeff Kirsher 940dee1ad47SJeff Kirsher for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 941dee1ad47SJeff Kirsher for (offset = 0; offset < hw->mac.vft_size; offset++) 942dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), 943dee1ad47SJeff Kirsher 0); 944dee1ad47SJeff Kirsher 945dee1ad47SJeff Kirsher return 0; 946dee1ad47SJeff Kirsher } 947dee1ad47SJeff Kirsher 948dee1ad47SJeff Kirsher /** 949dee1ad47SJeff Kirsher * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register 950dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 951dee1ad47SJeff Kirsher * @reg: analog register to read 952dee1ad47SJeff Kirsher * @val: read value 953dee1ad47SJeff Kirsher * 954dee1ad47SJeff Kirsher * Performs read operation to Atlas analog register specified. 955dee1ad47SJeff Kirsher **/ 956dee1ad47SJeff Kirsher static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) 957dee1ad47SJeff Kirsher { 958dee1ad47SJeff Kirsher u32 atlas_ctl; 959dee1ad47SJeff Kirsher 960dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, 961dee1ad47SJeff Kirsher IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 962dee1ad47SJeff Kirsher IXGBE_WRITE_FLUSH(hw); 963dee1ad47SJeff Kirsher udelay(10); 964dee1ad47SJeff Kirsher atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 965dee1ad47SJeff Kirsher *val = (u8)atlas_ctl; 966dee1ad47SJeff Kirsher 967dee1ad47SJeff Kirsher return 0; 968dee1ad47SJeff Kirsher } 969dee1ad47SJeff Kirsher 970dee1ad47SJeff Kirsher /** 971dee1ad47SJeff Kirsher * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register 972dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 973dee1ad47SJeff Kirsher * @reg: atlas register to write 974dee1ad47SJeff Kirsher * @val: value to write 975dee1ad47SJeff Kirsher * 976dee1ad47SJeff Kirsher * Performs write operation to Atlas analog register specified. 977dee1ad47SJeff Kirsher **/ 978dee1ad47SJeff Kirsher static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) 979dee1ad47SJeff Kirsher { 980dee1ad47SJeff Kirsher u32 atlas_ctl; 981dee1ad47SJeff Kirsher 982dee1ad47SJeff Kirsher atlas_ctl = (reg << 8) | val; 983dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 984dee1ad47SJeff Kirsher IXGBE_WRITE_FLUSH(hw); 985dee1ad47SJeff Kirsher udelay(10); 986dee1ad47SJeff Kirsher 987dee1ad47SJeff Kirsher return 0; 988dee1ad47SJeff Kirsher } 989dee1ad47SJeff Kirsher 990dee1ad47SJeff Kirsher /** 99107ce870bSEmil Tantilov * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface. 992dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 99307ce870bSEmil Tantilov * @dev_addr: address to read from 99407ce870bSEmil Tantilov * @byte_offset: byte offset to read from dev_addr 995dee1ad47SJeff Kirsher * @eeprom_data: value read 996dee1ad47SJeff Kirsher * 99707ce870bSEmil Tantilov * Performs 8 byte read operation to SFP module's data over I2C interface. 998dee1ad47SJeff Kirsher **/ 99907ce870bSEmil Tantilov static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr, 100007ce870bSEmil Tantilov u8 byte_offset, u8 *eeprom_data) 1001dee1ad47SJeff Kirsher { 1002dee1ad47SJeff Kirsher s32 status = 0; 1003dee1ad47SJeff Kirsher u16 sfp_addr = 0; 1004dee1ad47SJeff Kirsher u16 sfp_data = 0; 1005dee1ad47SJeff Kirsher u16 sfp_stat = 0; 10063dcc2f41SEmil Tantilov u16 gssr; 1007dee1ad47SJeff Kirsher u32 i; 1008dee1ad47SJeff Kirsher 10093dcc2f41SEmil Tantilov if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 10103dcc2f41SEmil Tantilov gssr = IXGBE_GSSR_PHY1_SM; 10113dcc2f41SEmil Tantilov else 10123dcc2f41SEmil Tantilov gssr = IXGBE_GSSR_PHY0_SM; 10133dcc2f41SEmil Tantilov 10143dcc2f41SEmil Tantilov if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0) 10153dcc2f41SEmil Tantilov return IXGBE_ERR_SWFW_SYNC; 10163dcc2f41SEmil Tantilov 1017dee1ad47SJeff Kirsher if (hw->phy.type == ixgbe_phy_nl) { 1018dee1ad47SJeff Kirsher /* 1019dee1ad47SJeff Kirsher * phy SDA/SCL registers are at addresses 0xC30A to 1020dee1ad47SJeff Kirsher * 0xC30D. These registers are used to talk to the SFP+ 1021dee1ad47SJeff Kirsher * module's EEPROM through the SDA/SCL (I2C) interface. 1022dee1ad47SJeff Kirsher */ 102307ce870bSEmil Tantilov sfp_addr = (dev_addr << 8) + byte_offset; 1024dee1ad47SJeff Kirsher sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); 10253dcc2f41SEmil Tantilov hw->phy.ops.write_reg_mdi(hw, 1026dee1ad47SJeff Kirsher IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, 1027dee1ad47SJeff Kirsher MDIO_MMD_PMAPMD, 1028dee1ad47SJeff Kirsher sfp_addr); 1029dee1ad47SJeff Kirsher 1030dee1ad47SJeff Kirsher /* Poll status */ 1031dee1ad47SJeff Kirsher for (i = 0; i < 100; i++) { 10323dcc2f41SEmil Tantilov hw->phy.ops.read_reg_mdi(hw, 1033dee1ad47SJeff Kirsher IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, 1034dee1ad47SJeff Kirsher MDIO_MMD_PMAPMD, 1035dee1ad47SJeff Kirsher &sfp_stat); 1036dee1ad47SJeff Kirsher sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; 1037dee1ad47SJeff Kirsher if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) 1038dee1ad47SJeff Kirsher break; 1039dee1ad47SJeff Kirsher usleep_range(10000, 20000); 1040dee1ad47SJeff Kirsher } 1041dee1ad47SJeff Kirsher 1042dee1ad47SJeff Kirsher if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { 1043dee1ad47SJeff Kirsher hw_dbg(hw, "EEPROM read did not pass.\n"); 1044dee1ad47SJeff Kirsher status = IXGBE_ERR_SFP_NOT_PRESENT; 1045dee1ad47SJeff Kirsher goto out; 1046dee1ad47SJeff Kirsher } 1047dee1ad47SJeff Kirsher 1048dee1ad47SJeff Kirsher /* Read data */ 10493dcc2f41SEmil Tantilov hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, 1050dee1ad47SJeff Kirsher MDIO_MMD_PMAPMD, &sfp_data); 1051dee1ad47SJeff Kirsher 1052dee1ad47SJeff Kirsher *eeprom_data = (u8)(sfp_data >> 8); 1053dee1ad47SJeff Kirsher } else { 1054dee1ad47SJeff Kirsher status = IXGBE_ERR_PHY; 1055dee1ad47SJeff Kirsher } 1056dee1ad47SJeff Kirsher 1057dee1ad47SJeff Kirsher out: 10583dcc2f41SEmil Tantilov hw->mac.ops.release_swfw_sync(hw, gssr); 1059dee1ad47SJeff Kirsher return status; 1060dee1ad47SJeff Kirsher } 1061dee1ad47SJeff Kirsher 1062dee1ad47SJeff Kirsher /** 106307ce870bSEmil Tantilov * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. 106407ce870bSEmil Tantilov * @hw: pointer to hardware structure 106507ce870bSEmil Tantilov * @byte_offset: EEPROM byte offset to read 106607ce870bSEmil Tantilov * @eeprom_data: value read 106707ce870bSEmil Tantilov * 106807ce870bSEmil Tantilov * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 106907ce870bSEmil Tantilov **/ 107007ce870bSEmil Tantilov static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 107107ce870bSEmil Tantilov u8 *eeprom_data) 107207ce870bSEmil Tantilov { 107307ce870bSEmil Tantilov return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR, 107407ce870bSEmil Tantilov byte_offset, eeprom_data); 107507ce870bSEmil Tantilov } 107607ce870bSEmil Tantilov 107707ce870bSEmil Tantilov /** 107807ce870bSEmil Tantilov * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface. 107907ce870bSEmil Tantilov * @hw: pointer to hardware structure 108007ce870bSEmil Tantilov * @byte_offset: byte offset at address 0xA2 108107ce870bSEmil Tantilov * @eeprom_data: value read 108207ce870bSEmil Tantilov * 108307ce870bSEmil Tantilov * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C 108407ce870bSEmil Tantilov **/ 108507ce870bSEmil Tantilov static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset, 108607ce870bSEmil Tantilov u8 *sff8472_data) 108707ce870bSEmil Tantilov { 108807ce870bSEmil Tantilov return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2, 108907ce870bSEmil Tantilov byte_offset, sff8472_data); 109007ce870bSEmil Tantilov } 109107ce870bSEmil Tantilov 109207ce870bSEmil Tantilov /** 1093dee1ad47SJeff Kirsher * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple 1094dee1ad47SJeff Kirsher * port devices. 1095dee1ad47SJeff Kirsher * @hw: pointer to the HW structure 1096dee1ad47SJeff Kirsher * 1097dee1ad47SJeff Kirsher * Calls common function and corrects issue with some single port devices 1098dee1ad47SJeff Kirsher * that enable LAN1 but not LAN0. 1099dee1ad47SJeff Kirsher **/ 1100dee1ad47SJeff Kirsher static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw) 1101dee1ad47SJeff Kirsher { 1102dee1ad47SJeff Kirsher struct ixgbe_bus_info *bus = &hw->bus; 1103dee1ad47SJeff Kirsher u16 pci_gen = 0; 1104dee1ad47SJeff Kirsher u16 pci_ctrl2 = 0; 1105dee1ad47SJeff Kirsher 1106dee1ad47SJeff Kirsher ixgbe_set_lan_id_multi_port_pcie(hw); 1107dee1ad47SJeff Kirsher 1108dee1ad47SJeff Kirsher /* check if LAN0 is disabled */ 1109dee1ad47SJeff Kirsher hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen); 1110dee1ad47SJeff Kirsher if ((pci_gen != 0) && (pci_gen != 0xFFFF)) { 1111dee1ad47SJeff Kirsher 1112dee1ad47SJeff Kirsher hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2); 1113dee1ad47SJeff Kirsher 1114dee1ad47SJeff Kirsher /* if LAN0 is completely disabled force function to 0 */ 1115dee1ad47SJeff Kirsher if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) && 1116dee1ad47SJeff Kirsher !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) && 1117dee1ad47SJeff Kirsher !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) { 1118dee1ad47SJeff Kirsher 1119dee1ad47SJeff Kirsher bus->func = 0; 1120dee1ad47SJeff Kirsher } 1121dee1ad47SJeff Kirsher } 1122dee1ad47SJeff Kirsher } 1123dee1ad47SJeff Kirsher 1124dee1ad47SJeff Kirsher /** 112544834700SJacob Keller * ixgbe_set_rxpba_82598 - Initialize RX packet buffer 1126dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 112744834700SJacob Keller * @num_pb: number of packet buffers to allocate 112844834700SJacob Keller * @headroom: reserve n KB of headroom 112944834700SJacob Keller * @strategy: packet buffer allocation strategy 113044834700SJacob Keller **/ 113144834700SJacob Keller static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, 113244834700SJacob Keller u32 headroom, int strategy) 1133dee1ad47SJeff Kirsher { 1134dee1ad47SJeff Kirsher u32 rxpktsize = IXGBE_RXPBSIZE_64KB; 1135dee1ad47SJeff Kirsher u8 i = 0; 1136dee1ad47SJeff Kirsher 1137dee1ad47SJeff Kirsher if (!num_pb) 1138dee1ad47SJeff Kirsher return; 1139dee1ad47SJeff Kirsher 1140dee1ad47SJeff Kirsher /* Setup Rx packet buffer sizes */ 1141dee1ad47SJeff Kirsher switch (strategy) { 1142dee1ad47SJeff Kirsher case PBA_STRATEGY_WEIGHTED: 1143dee1ad47SJeff Kirsher /* Setup the first four at 80KB */ 1144dee1ad47SJeff Kirsher rxpktsize = IXGBE_RXPBSIZE_80KB; 1145dee1ad47SJeff Kirsher for (; i < 4; i++) 1146dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 1147dee1ad47SJeff Kirsher /* Setup the last four at 48KB...don't re-init i */ 1148dee1ad47SJeff Kirsher rxpktsize = IXGBE_RXPBSIZE_48KB; 1149dee1ad47SJeff Kirsher /* Fall Through */ 1150dee1ad47SJeff Kirsher case PBA_STRATEGY_EQUAL: 1151dee1ad47SJeff Kirsher default: 1152dee1ad47SJeff Kirsher /* Divide the remaining Rx packet buffer evenly among the TCs */ 1153dee1ad47SJeff Kirsher for (; i < IXGBE_MAX_PACKET_BUFFERS; i++) 1154dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 1155dee1ad47SJeff Kirsher break; 1156dee1ad47SJeff Kirsher } 1157dee1ad47SJeff Kirsher 1158dee1ad47SJeff Kirsher /* Setup Tx packet buffer sizes */ 1159dee1ad47SJeff Kirsher for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) 1160dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB); 1161dee1ad47SJeff Kirsher } 1162dee1ad47SJeff Kirsher 116337689010SMark Rustad static const struct ixgbe_mac_operations mac_ops_82598 = { 1164dee1ad47SJeff Kirsher .init_hw = &ixgbe_init_hw_generic, 1165dee1ad47SJeff Kirsher .reset_hw = &ixgbe_reset_hw_82598, 1166dee1ad47SJeff Kirsher .start_hw = &ixgbe_start_hw_82598, 1167dee1ad47SJeff Kirsher .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 1168dee1ad47SJeff Kirsher .get_media_type = &ixgbe_get_media_type_82598, 1169dee1ad47SJeff Kirsher .enable_rx_dma = &ixgbe_enable_rx_dma_generic, 1170dee1ad47SJeff Kirsher .get_mac_addr = &ixgbe_get_mac_addr_generic, 1171dee1ad47SJeff Kirsher .stop_adapter = &ixgbe_stop_adapter_generic, 1172dee1ad47SJeff Kirsher .get_bus_info = &ixgbe_get_bus_info_generic, 1173dee1ad47SJeff Kirsher .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598, 1174dee1ad47SJeff Kirsher .read_analog_reg8 = &ixgbe_read_analog_reg8_82598, 1175dee1ad47SJeff Kirsher .write_analog_reg8 = &ixgbe_write_analog_reg8_82598, 1176dee1ad47SJeff Kirsher .setup_link = &ixgbe_setup_mac_link_82598, 1177dee1ad47SJeff Kirsher .set_rxpba = &ixgbe_set_rxpba_82598, 1178dee1ad47SJeff Kirsher .check_link = &ixgbe_check_mac_link_82598, 1179dee1ad47SJeff Kirsher .get_link_capabilities = &ixgbe_get_link_capabilities_82598, 1180dee1ad47SJeff Kirsher .led_on = &ixgbe_led_on_generic, 1181dee1ad47SJeff Kirsher .led_off = &ixgbe_led_off_generic, 1182dee1ad47SJeff Kirsher .blink_led_start = &ixgbe_blink_led_start_generic, 1183dee1ad47SJeff Kirsher .blink_led_stop = &ixgbe_blink_led_stop_generic, 1184dee1ad47SJeff Kirsher .set_rar = &ixgbe_set_rar_generic, 1185dee1ad47SJeff Kirsher .clear_rar = &ixgbe_clear_rar_generic, 1186dee1ad47SJeff Kirsher .set_vmdq = &ixgbe_set_vmdq_82598, 1187dee1ad47SJeff Kirsher .clear_vmdq = &ixgbe_clear_vmdq_82598, 1188dee1ad47SJeff Kirsher .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 1189dee1ad47SJeff Kirsher .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 1190dee1ad47SJeff Kirsher .enable_mc = &ixgbe_enable_mc_generic, 1191dee1ad47SJeff Kirsher .disable_mc = &ixgbe_disable_mc_generic, 1192dee1ad47SJeff Kirsher .clear_vfta = &ixgbe_clear_vfta_82598, 1193dee1ad47SJeff Kirsher .set_vfta = &ixgbe_set_vfta_82598, 1194dee1ad47SJeff Kirsher .fc_enable = &ixgbe_fc_enable_82598, 1195afdc71e4SMark Rustad .setup_fc = ixgbe_setup_fc_generic, 1196dee1ad47SJeff Kirsher .set_fw_drv_ver = NULL, 1197dee1ad47SJeff Kirsher .acquire_swfw_sync = &ixgbe_acquire_swfw_sync, 1198dee1ad47SJeff Kirsher .release_swfw_sync = &ixgbe_release_swfw_sync, 1199dbd15b8fSDon Skidmore .init_swfw_sync = NULL, 12003ca8bc6dSDon Skidmore .get_thermal_sensor_data = NULL, 12013ca8bc6dSDon Skidmore .init_thermal_sensor_thresh = NULL, 1202429d6a3bSDon Skidmore .prot_autoc_read = &prot_autoc_read_generic, 1203429d6a3bSDon Skidmore .prot_autoc_write = &prot_autoc_write_generic, 12041f9ac57cSDon Skidmore .enable_rx = &ixgbe_enable_rx_generic, 12051f9ac57cSDon Skidmore .disable_rx = &ixgbe_disable_rx_generic, 1206dee1ad47SJeff Kirsher }; 1207dee1ad47SJeff Kirsher 120837689010SMark Rustad static const struct ixgbe_eeprom_operations eeprom_ops_82598 = { 1209dee1ad47SJeff Kirsher .init_params = &ixgbe_init_eeprom_params_generic, 1210dee1ad47SJeff Kirsher .read = &ixgbe_read_eerd_generic, 12112fa5eef4SEmil Tantilov .write = &ixgbe_write_eeprom_generic, 12122fa5eef4SEmil Tantilov .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic, 1213dee1ad47SJeff Kirsher .read_buffer = &ixgbe_read_eerd_buffer_generic, 1214dee1ad47SJeff Kirsher .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, 1215dee1ad47SJeff Kirsher .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 1216dee1ad47SJeff Kirsher .update_checksum = &ixgbe_update_eeprom_checksum_generic, 1217dee1ad47SJeff Kirsher }; 1218dee1ad47SJeff Kirsher 121937689010SMark Rustad static const struct ixgbe_phy_operations phy_ops_82598 = { 1220dee1ad47SJeff Kirsher .identify = &ixgbe_identify_phy_generic, 12218f58332bSDon Skidmore .identify_sfp = &ixgbe_identify_module_generic, 1222dee1ad47SJeff Kirsher .init = &ixgbe_init_phy_ops_82598, 1223dee1ad47SJeff Kirsher .reset = &ixgbe_reset_phy_generic, 1224dee1ad47SJeff Kirsher .read_reg = &ixgbe_read_phy_reg_generic, 1225dee1ad47SJeff Kirsher .write_reg = &ixgbe_write_phy_reg_generic, 12263dcc2f41SEmil Tantilov .read_reg_mdi = &ixgbe_read_phy_reg_mdi, 12273dcc2f41SEmil Tantilov .write_reg_mdi = &ixgbe_write_phy_reg_mdi, 1228dee1ad47SJeff Kirsher .setup_link = &ixgbe_setup_phy_link_generic, 1229dee1ad47SJeff Kirsher .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 123007ce870bSEmil Tantilov .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_82598, 1231dee1ad47SJeff Kirsher .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598, 1232dee1ad47SJeff Kirsher .check_overtemp = &ixgbe_tn_check_overtemp, 1233dee1ad47SJeff Kirsher }; 1234dee1ad47SJeff Kirsher 123537689010SMark Rustad const struct ixgbe_info ixgbe_82598_info = { 1236dee1ad47SJeff Kirsher .mac = ixgbe_mac_82598EB, 1237dee1ad47SJeff Kirsher .get_invariants = &ixgbe_get_invariants_82598, 1238dee1ad47SJeff Kirsher .mac_ops = &mac_ops_82598, 1239dee1ad47SJeff Kirsher .eeprom_ops = &eeprom_ops_82598, 1240dee1ad47SJeff Kirsher .phy_ops = &phy_ops_82598, 12419a900ecaSDon Skidmore .mvals = ixgbe_mvals_8259X, 1242dee1ad47SJeff Kirsher }; 1243