1dee1ad47SJeff Kirsher /******************************************************************************* 2dee1ad47SJeff Kirsher 3dee1ad47SJeff Kirsher Intel 10 Gigabit PCI Express Linux driver 494971820SDon Skidmore Copyright(c) 1999 - 2012 Intel Corporation. 5dee1ad47SJeff Kirsher 6dee1ad47SJeff Kirsher This program is free software; you can redistribute it and/or modify it 7dee1ad47SJeff Kirsher under the terms and conditions of the GNU General Public License, 8dee1ad47SJeff Kirsher version 2, as published by the Free Software Foundation. 9dee1ad47SJeff Kirsher 10dee1ad47SJeff Kirsher This program is distributed in the hope it will be useful, but WITHOUT 11dee1ad47SJeff Kirsher ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12dee1ad47SJeff Kirsher FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13dee1ad47SJeff Kirsher more details. 14dee1ad47SJeff Kirsher 15dee1ad47SJeff Kirsher You should have received a copy of the GNU General Public License along with 16dee1ad47SJeff Kirsher this program; if not, write to the Free Software Foundation, Inc., 17dee1ad47SJeff Kirsher 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18dee1ad47SJeff Kirsher 19dee1ad47SJeff Kirsher The full GNU General Public License is included in this distribution in 20dee1ad47SJeff Kirsher the file called "COPYING". 21dee1ad47SJeff Kirsher 22dee1ad47SJeff Kirsher Contact Information: 23dee1ad47SJeff Kirsher e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24dee1ad47SJeff Kirsher Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25dee1ad47SJeff Kirsher 26dee1ad47SJeff Kirsher *******************************************************************************/ 27dee1ad47SJeff Kirsher 28dee1ad47SJeff Kirsher #include <linux/pci.h> 29dee1ad47SJeff Kirsher #include <linux/delay.h> 30dee1ad47SJeff Kirsher #include <linux/sched.h> 31dee1ad47SJeff Kirsher 32dee1ad47SJeff Kirsher #include "ixgbe.h" 33dee1ad47SJeff Kirsher #include "ixgbe_phy.h" 34dee1ad47SJeff Kirsher 35dee1ad47SJeff Kirsher #define IXGBE_82598_MAX_TX_QUEUES 32 36dee1ad47SJeff Kirsher #define IXGBE_82598_MAX_RX_QUEUES 64 37dee1ad47SJeff Kirsher #define IXGBE_82598_RAR_ENTRIES 16 38dee1ad47SJeff Kirsher #define IXGBE_82598_MC_TBL_SIZE 128 39dee1ad47SJeff Kirsher #define IXGBE_82598_VFT_TBL_SIZE 128 40dee1ad47SJeff Kirsher #define IXGBE_82598_RX_PB_SIZE 512 41dee1ad47SJeff Kirsher 42dee1ad47SJeff Kirsher static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 43dee1ad47SJeff Kirsher ixgbe_link_speed speed, 44dee1ad47SJeff Kirsher bool autoneg, 45dee1ad47SJeff Kirsher bool autoneg_wait_to_complete); 46dee1ad47SJeff Kirsher static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 47dee1ad47SJeff Kirsher u8 *eeprom_data); 48dee1ad47SJeff Kirsher 49dee1ad47SJeff Kirsher /** 50dee1ad47SJeff Kirsher * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout 51dee1ad47SJeff Kirsher * @hw: pointer to the HW structure 52dee1ad47SJeff Kirsher * 53dee1ad47SJeff Kirsher * The defaults for 82598 should be in the range of 50us to 50ms, 54dee1ad47SJeff Kirsher * however the hardware default for these parts is 500us to 1ms which is less 55dee1ad47SJeff Kirsher * than the 10ms recommended by the pci-e spec. To address this we need to 56dee1ad47SJeff Kirsher * increase the value to either 10ms to 250ms for capability version 1 config, 57dee1ad47SJeff Kirsher * or 16ms to 55ms for version 2. 58dee1ad47SJeff Kirsher **/ 59dee1ad47SJeff Kirsher static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) 60dee1ad47SJeff Kirsher { 61dee1ad47SJeff Kirsher struct ixgbe_adapter *adapter = hw->back; 62dee1ad47SJeff Kirsher u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); 63dee1ad47SJeff Kirsher u16 pcie_devctl2; 64dee1ad47SJeff Kirsher 65dee1ad47SJeff Kirsher /* only take action if timeout value is defaulted to 0 */ 66dee1ad47SJeff Kirsher if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) 67dee1ad47SJeff Kirsher goto out; 68dee1ad47SJeff Kirsher 69dee1ad47SJeff Kirsher /* 70dee1ad47SJeff Kirsher * if capababilities version is type 1 we can write the 71dee1ad47SJeff Kirsher * timeout of 10ms to 250ms through the GCR register 72dee1ad47SJeff Kirsher */ 73dee1ad47SJeff Kirsher if (!(gcr & IXGBE_GCR_CAP_VER2)) { 74dee1ad47SJeff Kirsher gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; 75dee1ad47SJeff Kirsher goto out; 76dee1ad47SJeff Kirsher } 77dee1ad47SJeff Kirsher 78dee1ad47SJeff Kirsher /* 79dee1ad47SJeff Kirsher * for version 2 capabilities we need to write the config space 80dee1ad47SJeff Kirsher * directly in order to set the completion timeout value for 81dee1ad47SJeff Kirsher * 16ms to 55ms 82dee1ad47SJeff Kirsher */ 83dee1ad47SJeff Kirsher pci_read_config_word(adapter->pdev, 84dee1ad47SJeff Kirsher IXGBE_PCI_DEVICE_CONTROL2, &pcie_devctl2); 85dee1ad47SJeff Kirsher pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; 86dee1ad47SJeff Kirsher pci_write_config_word(adapter->pdev, 87dee1ad47SJeff Kirsher IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); 88dee1ad47SJeff Kirsher out: 89dee1ad47SJeff Kirsher /* disable completion timeout resend */ 90dee1ad47SJeff Kirsher gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; 91dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); 92dee1ad47SJeff Kirsher } 93dee1ad47SJeff Kirsher 94dee1ad47SJeff Kirsher static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) 95dee1ad47SJeff Kirsher { 96dee1ad47SJeff Kirsher struct ixgbe_mac_info *mac = &hw->mac; 97dee1ad47SJeff Kirsher 98dee1ad47SJeff Kirsher /* Call PHY identify routine to get the phy type */ 99dee1ad47SJeff Kirsher ixgbe_identify_phy_generic(hw); 100dee1ad47SJeff Kirsher 101dee1ad47SJeff Kirsher mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; 102dee1ad47SJeff Kirsher mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; 103dee1ad47SJeff Kirsher mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; 104dee1ad47SJeff Kirsher mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; 105dee1ad47SJeff Kirsher mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; 10671161302SEmil Tantilov mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 107dee1ad47SJeff Kirsher 108dee1ad47SJeff Kirsher return 0; 109dee1ad47SJeff Kirsher } 110dee1ad47SJeff Kirsher 111dee1ad47SJeff Kirsher /** 112dee1ad47SJeff Kirsher * ixgbe_init_phy_ops_82598 - PHY/SFP specific init 113dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 114dee1ad47SJeff Kirsher * 115dee1ad47SJeff Kirsher * Initialize any function pointers that were not able to be 116dee1ad47SJeff Kirsher * set during get_invariants because the PHY/SFP type was 117dee1ad47SJeff Kirsher * not known. Perform the SFP init if necessary. 118dee1ad47SJeff Kirsher * 119dee1ad47SJeff Kirsher **/ 120dee1ad47SJeff Kirsher static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) 121dee1ad47SJeff Kirsher { 122dee1ad47SJeff Kirsher struct ixgbe_mac_info *mac = &hw->mac; 123dee1ad47SJeff Kirsher struct ixgbe_phy_info *phy = &hw->phy; 124dee1ad47SJeff Kirsher s32 ret_val = 0; 125dee1ad47SJeff Kirsher u16 list_offset, data_offset; 126dee1ad47SJeff Kirsher 127dee1ad47SJeff Kirsher /* Identify the PHY */ 128dee1ad47SJeff Kirsher phy->ops.identify(hw); 129dee1ad47SJeff Kirsher 130dee1ad47SJeff Kirsher /* Overwrite the link function pointers if copper PHY */ 131dee1ad47SJeff Kirsher if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 132dee1ad47SJeff Kirsher mac->ops.setup_link = &ixgbe_setup_copper_link_82598; 133dee1ad47SJeff Kirsher mac->ops.get_link_capabilities = 134dee1ad47SJeff Kirsher &ixgbe_get_copper_link_capabilities_generic; 135dee1ad47SJeff Kirsher } 136dee1ad47SJeff Kirsher 137dee1ad47SJeff Kirsher switch (hw->phy.type) { 138dee1ad47SJeff Kirsher case ixgbe_phy_tn: 139dee1ad47SJeff Kirsher phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; 140dee1ad47SJeff Kirsher phy->ops.check_link = &ixgbe_check_phy_link_tnx; 141dee1ad47SJeff Kirsher phy->ops.get_firmware_version = 142dee1ad47SJeff Kirsher &ixgbe_get_phy_firmware_version_tnx; 143dee1ad47SJeff Kirsher break; 144dee1ad47SJeff Kirsher case ixgbe_phy_nl: 145dee1ad47SJeff Kirsher phy->ops.reset = &ixgbe_reset_phy_nl; 146dee1ad47SJeff Kirsher 147dee1ad47SJeff Kirsher /* Call SFP+ identify routine to get the SFP+ module type */ 148dee1ad47SJeff Kirsher ret_val = phy->ops.identify_sfp(hw); 149dee1ad47SJeff Kirsher if (ret_val != 0) 150dee1ad47SJeff Kirsher goto out; 151dee1ad47SJeff Kirsher else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { 152dee1ad47SJeff Kirsher ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 153dee1ad47SJeff Kirsher goto out; 154dee1ad47SJeff Kirsher } 155dee1ad47SJeff Kirsher 156dee1ad47SJeff Kirsher /* Check to see if SFP+ module is supported */ 157dee1ad47SJeff Kirsher ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, 158dee1ad47SJeff Kirsher &list_offset, 159dee1ad47SJeff Kirsher &data_offset); 160dee1ad47SJeff Kirsher if (ret_val != 0) { 161dee1ad47SJeff Kirsher ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 162dee1ad47SJeff Kirsher goto out; 163dee1ad47SJeff Kirsher } 164dee1ad47SJeff Kirsher break; 165dee1ad47SJeff Kirsher default: 166dee1ad47SJeff Kirsher break; 167dee1ad47SJeff Kirsher } 168dee1ad47SJeff Kirsher 169dee1ad47SJeff Kirsher out: 170dee1ad47SJeff Kirsher return ret_val; 171dee1ad47SJeff Kirsher } 172dee1ad47SJeff Kirsher 173dee1ad47SJeff Kirsher /** 174dee1ad47SJeff Kirsher * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx 175dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 176dee1ad47SJeff Kirsher * 177dee1ad47SJeff Kirsher * Starts the hardware using the generic start_hw function. 178dee1ad47SJeff Kirsher * Disables relaxed ordering Then set pcie completion timeout 179dee1ad47SJeff Kirsher * 180dee1ad47SJeff Kirsher **/ 181dee1ad47SJeff Kirsher static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) 182dee1ad47SJeff Kirsher { 183dee1ad47SJeff Kirsher u32 regval; 184dee1ad47SJeff Kirsher u32 i; 185dee1ad47SJeff Kirsher s32 ret_val = 0; 186dee1ad47SJeff Kirsher 187dee1ad47SJeff Kirsher ret_val = ixgbe_start_hw_generic(hw); 188dee1ad47SJeff Kirsher 189dee1ad47SJeff Kirsher /* Disable relaxed ordering */ 190dee1ad47SJeff Kirsher for (i = 0; ((i < hw->mac.max_tx_queues) && 191dee1ad47SJeff Kirsher (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 192dee1ad47SJeff Kirsher regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 193bdda1a61SAlexander Duyck regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 194dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); 195dee1ad47SJeff Kirsher } 196dee1ad47SJeff Kirsher 197dee1ad47SJeff Kirsher for (i = 0; ((i < hw->mac.max_rx_queues) && 198dee1ad47SJeff Kirsher (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 199dee1ad47SJeff Kirsher regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 200bdda1a61SAlexander Duyck regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 201bdda1a61SAlexander Duyck IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 202dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 203dee1ad47SJeff Kirsher } 204dee1ad47SJeff Kirsher 205dee1ad47SJeff Kirsher hw->mac.rx_pb_size = IXGBE_82598_RX_PB_SIZE; 206dee1ad47SJeff Kirsher 207dee1ad47SJeff Kirsher /* set the completion timeout for interface */ 208dee1ad47SJeff Kirsher if (ret_val == 0) 209dee1ad47SJeff Kirsher ixgbe_set_pcie_completion_timeout(hw); 210dee1ad47SJeff Kirsher 211dee1ad47SJeff Kirsher return ret_val; 212dee1ad47SJeff Kirsher } 213dee1ad47SJeff Kirsher 214dee1ad47SJeff Kirsher /** 215dee1ad47SJeff Kirsher * ixgbe_get_link_capabilities_82598 - Determines link capabilities 216dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 217dee1ad47SJeff Kirsher * @speed: pointer to link speed 218dee1ad47SJeff Kirsher * @autoneg: boolean auto-negotiation value 219dee1ad47SJeff Kirsher * 220dee1ad47SJeff Kirsher * Determines the link capabilities by reading the AUTOC register. 221dee1ad47SJeff Kirsher **/ 222dee1ad47SJeff Kirsher static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 223dee1ad47SJeff Kirsher ixgbe_link_speed *speed, 224dee1ad47SJeff Kirsher bool *autoneg) 225dee1ad47SJeff Kirsher { 226dee1ad47SJeff Kirsher s32 status = 0; 227dee1ad47SJeff Kirsher u32 autoc = 0; 228dee1ad47SJeff Kirsher 229dee1ad47SJeff Kirsher /* 230dee1ad47SJeff Kirsher * Determine link capabilities based on the stored value of AUTOC, 231dee1ad47SJeff Kirsher * which represents EEPROM defaults. If AUTOC value has not been 232dee1ad47SJeff Kirsher * stored, use the current register value. 233dee1ad47SJeff Kirsher */ 234dee1ad47SJeff Kirsher if (hw->mac.orig_link_settings_stored) 235dee1ad47SJeff Kirsher autoc = hw->mac.orig_autoc; 236dee1ad47SJeff Kirsher else 237dee1ad47SJeff Kirsher autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 238dee1ad47SJeff Kirsher 239dee1ad47SJeff Kirsher switch (autoc & IXGBE_AUTOC_LMS_MASK) { 240dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 241dee1ad47SJeff Kirsher *speed = IXGBE_LINK_SPEED_1GB_FULL; 242dee1ad47SJeff Kirsher *autoneg = false; 243dee1ad47SJeff Kirsher break; 244dee1ad47SJeff Kirsher 245dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 246dee1ad47SJeff Kirsher *speed = IXGBE_LINK_SPEED_10GB_FULL; 247dee1ad47SJeff Kirsher *autoneg = false; 248dee1ad47SJeff Kirsher break; 249dee1ad47SJeff Kirsher 250dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_1G_AN: 251dee1ad47SJeff Kirsher *speed = IXGBE_LINK_SPEED_1GB_FULL; 252dee1ad47SJeff Kirsher *autoneg = true; 253dee1ad47SJeff Kirsher break; 254dee1ad47SJeff Kirsher 255dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_KX4_AN: 256dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 257dee1ad47SJeff Kirsher *speed = IXGBE_LINK_SPEED_UNKNOWN; 258dee1ad47SJeff Kirsher if (autoc & IXGBE_AUTOC_KX4_SUPP) 259dee1ad47SJeff Kirsher *speed |= IXGBE_LINK_SPEED_10GB_FULL; 260dee1ad47SJeff Kirsher if (autoc & IXGBE_AUTOC_KX_SUPP) 261dee1ad47SJeff Kirsher *speed |= IXGBE_LINK_SPEED_1GB_FULL; 262dee1ad47SJeff Kirsher *autoneg = true; 263dee1ad47SJeff Kirsher break; 264dee1ad47SJeff Kirsher 265dee1ad47SJeff Kirsher default: 266dee1ad47SJeff Kirsher status = IXGBE_ERR_LINK_SETUP; 267dee1ad47SJeff Kirsher break; 268dee1ad47SJeff Kirsher } 269dee1ad47SJeff Kirsher 270dee1ad47SJeff Kirsher return status; 271dee1ad47SJeff Kirsher } 272dee1ad47SJeff Kirsher 273dee1ad47SJeff Kirsher /** 274dee1ad47SJeff Kirsher * ixgbe_get_media_type_82598 - Determines media type 275dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 276dee1ad47SJeff Kirsher * 277dee1ad47SJeff Kirsher * Returns the media type (fiber, copper, backplane) 278dee1ad47SJeff Kirsher **/ 279dee1ad47SJeff Kirsher static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 280dee1ad47SJeff Kirsher { 281dee1ad47SJeff Kirsher enum ixgbe_media_type media_type; 282dee1ad47SJeff Kirsher 283dee1ad47SJeff Kirsher /* Detect if there is a copper PHY attached. */ 284dee1ad47SJeff Kirsher switch (hw->phy.type) { 285dee1ad47SJeff Kirsher case ixgbe_phy_cu_unknown: 286dee1ad47SJeff Kirsher case ixgbe_phy_tn: 287dee1ad47SJeff Kirsher media_type = ixgbe_media_type_copper; 288dee1ad47SJeff Kirsher goto out; 289dee1ad47SJeff Kirsher default: 290dee1ad47SJeff Kirsher break; 291dee1ad47SJeff Kirsher } 292dee1ad47SJeff Kirsher 293dee1ad47SJeff Kirsher /* Media type for I82598 is based on device ID */ 294dee1ad47SJeff Kirsher switch (hw->device_id) { 295dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598: 296dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598_BX: 297dee1ad47SJeff Kirsher /* Default device ID is mezzanine card KX/KX4 */ 298dee1ad47SJeff Kirsher media_type = ixgbe_media_type_backplane; 299dee1ad47SJeff Kirsher break; 300dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598AF_DUAL_PORT: 301dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 302dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 303dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 304dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598EB_XF_LR: 305dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598EB_SFP_LOM: 306dee1ad47SJeff Kirsher media_type = ixgbe_media_type_fiber; 307dee1ad47SJeff Kirsher break; 308dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598EB_CX4: 309dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 310dee1ad47SJeff Kirsher media_type = ixgbe_media_type_cx4; 311dee1ad47SJeff Kirsher break; 312dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598AT: 313dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598AT2: 314dee1ad47SJeff Kirsher media_type = ixgbe_media_type_copper; 315dee1ad47SJeff Kirsher break; 316dee1ad47SJeff Kirsher default: 317dee1ad47SJeff Kirsher media_type = ixgbe_media_type_unknown; 318dee1ad47SJeff Kirsher break; 319dee1ad47SJeff Kirsher } 320dee1ad47SJeff Kirsher out: 321dee1ad47SJeff Kirsher return media_type; 322dee1ad47SJeff Kirsher } 323dee1ad47SJeff Kirsher 324dee1ad47SJeff Kirsher /** 325dee1ad47SJeff Kirsher * ixgbe_fc_enable_82598 - Enable flow control 326dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 327dee1ad47SJeff Kirsher * @packetbuf_num: packet buffer number (0-7) 328dee1ad47SJeff Kirsher * 329dee1ad47SJeff Kirsher * Enable flow control according to the current settings. 330dee1ad47SJeff Kirsher **/ 331dee1ad47SJeff Kirsher static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) 332dee1ad47SJeff Kirsher { 333dee1ad47SJeff Kirsher s32 ret_val = 0; 334dee1ad47SJeff Kirsher u32 fctrl_reg; 335dee1ad47SJeff Kirsher u32 rmcs_reg; 336dee1ad47SJeff Kirsher u32 reg; 337dee1ad47SJeff Kirsher u32 link_speed = 0; 338dee1ad47SJeff Kirsher bool link_up; 339dee1ad47SJeff Kirsher 340dee1ad47SJeff Kirsher #ifdef CONFIG_DCB 341dee1ad47SJeff Kirsher if (hw->fc.requested_mode == ixgbe_fc_pfc) 342dee1ad47SJeff Kirsher goto out; 343dee1ad47SJeff Kirsher 344dee1ad47SJeff Kirsher #endif /* CONFIG_DCB */ 345dee1ad47SJeff Kirsher /* 346dee1ad47SJeff Kirsher * On 82598 having Rx FC on causes resets while doing 1G 347dee1ad47SJeff Kirsher * so if it's on turn it off once we know link_speed. For 348dee1ad47SJeff Kirsher * more details see 82598 Specification update. 349dee1ad47SJeff Kirsher */ 350dee1ad47SJeff Kirsher hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 351dee1ad47SJeff Kirsher if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) { 352dee1ad47SJeff Kirsher switch (hw->fc.requested_mode) { 353dee1ad47SJeff Kirsher case ixgbe_fc_full: 354dee1ad47SJeff Kirsher hw->fc.requested_mode = ixgbe_fc_tx_pause; 355dee1ad47SJeff Kirsher break; 356dee1ad47SJeff Kirsher case ixgbe_fc_rx_pause: 357dee1ad47SJeff Kirsher hw->fc.requested_mode = ixgbe_fc_none; 358dee1ad47SJeff Kirsher break; 359dee1ad47SJeff Kirsher default: 360dee1ad47SJeff Kirsher /* no change */ 361dee1ad47SJeff Kirsher break; 362dee1ad47SJeff Kirsher } 363dee1ad47SJeff Kirsher } 364dee1ad47SJeff Kirsher 365dee1ad47SJeff Kirsher /* Negotiate the fc mode to use */ 366786e9a5fSAlexander Duyck ixgbe_fc_autoneg(hw); 367dee1ad47SJeff Kirsher 368dee1ad47SJeff Kirsher /* Disable any previous flow control settings */ 369dee1ad47SJeff Kirsher fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 370dee1ad47SJeff Kirsher fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 371dee1ad47SJeff Kirsher 372dee1ad47SJeff Kirsher rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 373dee1ad47SJeff Kirsher rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 374dee1ad47SJeff Kirsher 375dee1ad47SJeff Kirsher /* 376dee1ad47SJeff Kirsher * The possible values of fc.current_mode are: 377dee1ad47SJeff Kirsher * 0: Flow control is completely disabled 378dee1ad47SJeff Kirsher * 1: Rx flow control is enabled (we can receive pause frames, 379dee1ad47SJeff Kirsher * but not send pause frames). 380dee1ad47SJeff Kirsher * 2: Tx flow control is enabled (we can send pause frames but 381dee1ad47SJeff Kirsher * we do not support receiving pause frames). 382dee1ad47SJeff Kirsher * 3: Both Rx and Tx flow control (symmetric) are enabled. 383dee1ad47SJeff Kirsher #ifdef CONFIG_DCB 384dee1ad47SJeff Kirsher * 4: Priority Flow Control is enabled. 385dee1ad47SJeff Kirsher #endif 386dee1ad47SJeff Kirsher * other: Invalid. 387dee1ad47SJeff Kirsher */ 388dee1ad47SJeff Kirsher switch (hw->fc.current_mode) { 389dee1ad47SJeff Kirsher case ixgbe_fc_none: 390dee1ad47SJeff Kirsher /* 391dee1ad47SJeff Kirsher * Flow control is disabled by software override or autoneg. 392dee1ad47SJeff Kirsher * The code below will actually disable it in the HW. 393dee1ad47SJeff Kirsher */ 394dee1ad47SJeff Kirsher break; 395dee1ad47SJeff Kirsher case ixgbe_fc_rx_pause: 396dee1ad47SJeff Kirsher /* 397dee1ad47SJeff Kirsher * Rx Flow control is enabled and Tx Flow control is 398dee1ad47SJeff Kirsher * disabled by software override. Since there really 399dee1ad47SJeff Kirsher * isn't a way to advertise that we are capable of RX 400dee1ad47SJeff Kirsher * Pause ONLY, we will advertise that we support both 401dee1ad47SJeff Kirsher * symmetric and asymmetric Rx PAUSE. Later, we will 402dee1ad47SJeff Kirsher * disable the adapter's ability to send PAUSE frames. 403dee1ad47SJeff Kirsher */ 404dee1ad47SJeff Kirsher fctrl_reg |= IXGBE_FCTRL_RFCE; 405dee1ad47SJeff Kirsher break; 406dee1ad47SJeff Kirsher case ixgbe_fc_tx_pause: 407dee1ad47SJeff Kirsher /* 408dee1ad47SJeff Kirsher * Tx Flow control is enabled, and Rx Flow control is 409dee1ad47SJeff Kirsher * disabled by software override. 410dee1ad47SJeff Kirsher */ 411dee1ad47SJeff Kirsher rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 412dee1ad47SJeff Kirsher break; 413dee1ad47SJeff Kirsher case ixgbe_fc_full: 414dee1ad47SJeff Kirsher /* Flow control (both Rx and Tx) is enabled by SW override. */ 415dee1ad47SJeff Kirsher fctrl_reg |= IXGBE_FCTRL_RFCE; 416dee1ad47SJeff Kirsher rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 417dee1ad47SJeff Kirsher break; 418dee1ad47SJeff Kirsher #ifdef CONFIG_DCB 419dee1ad47SJeff Kirsher case ixgbe_fc_pfc: 420dee1ad47SJeff Kirsher goto out; 421dee1ad47SJeff Kirsher break; 422dee1ad47SJeff Kirsher #endif /* CONFIG_DCB */ 423dee1ad47SJeff Kirsher default: 424dee1ad47SJeff Kirsher hw_dbg(hw, "Flow control param set incorrectly\n"); 425dee1ad47SJeff Kirsher ret_val = IXGBE_ERR_CONFIG; 426dee1ad47SJeff Kirsher goto out; 427dee1ad47SJeff Kirsher break; 428dee1ad47SJeff Kirsher } 429dee1ad47SJeff Kirsher 430dee1ad47SJeff Kirsher /* Set 802.3x based flow control settings. */ 431dee1ad47SJeff Kirsher fctrl_reg |= IXGBE_FCTRL_DPF; 432dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); 433dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 434dee1ad47SJeff Kirsher 435dee1ad47SJeff Kirsher /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 436dee1ad47SJeff Kirsher if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 4379da712d2SJohn Fastabend reg = hw->fc.low_water << 6; 438dee1ad47SJeff Kirsher if (hw->fc.send_xon) 439dee1ad47SJeff Kirsher reg |= IXGBE_FCRTL_XONE; 440dee1ad47SJeff Kirsher 441dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg); 442dee1ad47SJeff Kirsher 4439da712d2SJohn Fastabend reg = hw->fc.high_water[packetbuf_num] << 6; 444dee1ad47SJeff Kirsher reg |= IXGBE_FCRTH_FCEN; 445dee1ad47SJeff Kirsher 446dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg); 447dee1ad47SJeff Kirsher } 448dee1ad47SJeff Kirsher 449dee1ad47SJeff Kirsher /* Configure pause time (2 TCs per register) */ 450dee1ad47SJeff Kirsher reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); 451dee1ad47SJeff Kirsher if ((packetbuf_num & 1) == 0) 452dee1ad47SJeff Kirsher reg = (reg & 0xFFFF0000) | hw->fc.pause_time; 453dee1ad47SJeff Kirsher else 454dee1ad47SJeff Kirsher reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); 455dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); 456dee1ad47SJeff Kirsher 457dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 458dee1ad47SJeff Kirsher 459dee1ad47SJeff Kirsher out: 460dee1ad47SJeff Kirsher return ret_val; 461dee1ad47SJeff Kirsher } 462dee1ad47SJeff Kirsher 463dee1ad47SJeff Kirsher /** 464dee1ad47SJeff Kirsher * ixgbe_start_mac_link_82598 - Configures MAC link settings 465dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 466dee1ad47SJeff Kirsher * 467dee1ad47SJeff Kirsher * Configures link settings based on values in the ixgbe_hw struct. 468dee1ad47SJeff Kirsher * Restarts the link. Performs autonegotiation if needed. 469dee1ad47SJeff Kirsher **/ 470dee1ad47SJeff Kirsher static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, 471dee1ad47SJeff Kirsher bool autoneg_wait_to_complete) 472dee1ad47SJeff Kirsher { 473dee1ad47SJeff Kirsher u32 autoc_reg; 474dee1ad47SJeff Kirsher u32 links_reg; 475dee1ad47SJeff Kirsher u32 i; 476dee1ad47SJeff Kirsher s32 status = 0; 477dee1ad47SJeff Kirsher 478dee1ad47SJeff Kirsher /* Restart link */ 479dee1ad47SJeff Kirsher autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 480dee1ad47SJeff Kirsher autoc_reg |= IXGBE_AUTOC_AN_RESTART; 481dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 482dee1ad47SJeff Kirsher 483dee1ad47SJeff Kirsher /* Only poll for autoneg to complete if specified to do so */ 484dee1ad47SJeff Kirsher if (autoneg_wait_to_complete) { 485dee1ad47SJeff Kirsher if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 486dee1ad47SJeff Kirsher IXGBE_AUTOC_LMS_KX4_AN || 487dee1ad47SJeff Kirsher (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 488dee1ad47SJeff Kirsher IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 489dee1ad47SJeff Kirsher links_reg = 0; /* Just in case Autoneg time = 0 */ 490dee1ad47SJeff Kirsher for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 491dee1ad47SJeff Kirsher links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 492dee1ad47SJeff Kirsher if (links_reg & IXGBE_LINKS_KX_AN_COMP) 493dee1ad47SJeff Kirsher break; 494dee1ad47SJeff Kirsher msleep(100); 495dee1ad47SJeff Kirsher } 496dee1ad47SJeff Kirsher if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 497dee1ad47SJeff Kirsher status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 498dee1ad47SJeff Kirsher hw_dbg(hw, "Autonegotiation did not complete.\n"); 499dee1ad47SJeff Kirsher } 500dee1ad47SJeff Kirsher } 501dee1ad47SJeff Kirsher } 502dee1ad47SJeff Kirsher 503dee1ad47SJeff Kirsher /* Add delay to filter out noises during initial link setup */ 504dee1ad47SJeff Kirsher msleep(50); 505dee1ad47SJeff Kirsher 506dee1ad47SJeff Kirsher return status; 507dee1ad47SJeff Kirsher } 508dee1ad47SJeff Kirsher 509dee1ad47SJeff Kirsher /** 510dee1ad47SJeff Kirsher * ixgbe_validate_link_ready - Function looks for phy link 511dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 512dee1ad47SJeff Kirsher * 513dee1ad47SJeff Kirsher * Function indicates success when phy link is available. If phy is not ready 514dee1ad47SJeff Kirsher * within 5 seconds of MAC indicating link, the function returns error. 515dee1ad47SJeff Kirsher **/ 516dee1ad47SJeff Kirsher static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) 517dee1ad47SJeff Kirsher { 518dee1ad47SJeff Kirsher u32 timeout; 519dee1ad47SJeff Kirsher u16 an_reg; 520dee1ad47SJeff Kirsher 521dee1ad47SJeff Kirsher if (hw->device_id != IXGBE_DEV_ID_82598AT2) 522dee1ad47SJeff Kirsher return 0; 523dee1ad47SJeff Kirsher 524dee1ad47SJeff Kirsher for (timeout = 0; 525dee1ad47SJeff Kirsher timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) { 526dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg); 527dee1ad47SJeff Kirsher 528dee1ad47SJeff Kirsher if ((an_reg & MDIO_AN_STAT1_COMPLETE) && 529dee1ad47SJeff Kirsher (an_reg & MDIO_STAT1_LSTATUS)) 530dee1ad47SJeff Kirsher break; 531dee1ad47SJeff Kirsher 532dee1ad47SJeff Kirsher msleep(100); 533dee1ad47SJeff Kirsher } 534dee1ad47SJeff Kirsher 535dee1ad47SJeff Kirsher if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) { 536dee1ad47SJeff Kirsher hw_dbg(hw, "Link was indicated but link is down\n"); 537dee1ad47SJeff Kirsher return IXGBE_ERR_LINK_SETUP; 538dee1ad47SJeff Kirsher } 539dee1ad47SJeff Kirsher 540dee1ad47SJeff Kirsher return 0; 541dee1ad47SJeff Kirsher } 542dee1ad47SJeff Kirsher 543dee1ad47SJeff Kirsher /** 544dee1ad47SJeff Kirsher * ixgbe_check_mac_link_82598 - Get link/speed status 545dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 546dee1ad47SJeff Kirsher * @speed: pointer to link speed 547dee1ad47SJeff Kirsher * @link_up: true is link is up, false otherwise 548dee1ad47SJeff Kirsher * @link_up_wait_to_complete: bool used to wait for link up or not 549dee1ad47SJeff Kirsher * 550dee1ad47SJeff Kirsher * Reads the links register to determine if link is up and the current speed 551dee1ad47SJeff Kirsher **/ 552dee1ad47SJeff Kirsher static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 553dee1ad47SJeff Kirsher ixgbe_link_speed *speed, bool *link_up, 554dee1ad47SJeff Kirsher bool link_up_wait_to_complete) 555dee1ad47SJeff Kirsher { 556dee1ad47SJeff Kirsher u32 links_reg; 557dee1ad47SJeff Kirsher u32 i; 558dee1ad47SJeff Kirsher u16 link_reg, adapt_comp_reg; 559dee1ad47SJeff Kirsher 560dee1ad47SJeff Kirsher /* 561dee1ad47SJeff Kirsher * SERDES PHY requires us to read link status from register 0xC79F. 562dee1ad47SJeff Kirsher * Bit 0 set indicates link is up/ready; clear indicates link down. 563dee1ad47SJeff Kirsher * 0xC00C is read to check that the XAUI lanes are active. Bit 0 564dee1ad47SJeff Kirsher * clear indicates active; set indicates inactive. 565dee1ad47SJeff Kirsher */ 566dee1ad47SJeff Kirsher if (hw->phy.type == ixgbe_phy_nl) { 567dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); 568dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); 569dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD, 570dee1ad47SJeff Kirsher &adapt_comp_reg); 571dee1ad47SJeff Kirsher if (link_up_wait_to_complete) { 572dee1ad47SJeff Kirsher for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 573dee1ad47SJeff Kirsher if ((link_reg & 1) && 574dee1ad47SJeff Kirsher ((adapt_comp_reg & 1) == 0)) { 575dee1ad47SJeff Kirsher *link_up = true; 576dee1ad47SJeff Kirsher break; 577dee1ad47SJeff Kirsher } else { 578dee1ad47SJeff Kirsher *link_up = false; 579dee1ad47SJeff Kirsher } 580dee1ad47SJeff Kirsher msleep(100); 581dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, 0xC79F, 582dee1ad47SJeff Kirsher MDIO_MMD_PMAPMD, 583dee1ad47SJeff Kirsher &link_reg); 584dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, 0xC00C, 585dee1ad47SJeff Kirsher MDIO_MMD_PMAPMD, 586dee1ad47SJeff Kirsher &adapt_comp_reg); 587dee1ad47SJeff Kirsher } 588dee1ad47SJeff Kirsher } else { 589dee1ad47SJeff Kirsher if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) 590dee1ad47SJeff Kirsher *link_up = true; 591dee1ad47SJeff Kirsher else 592dee1ad47SJeff Kirsher *link_up = false; 593dee1ad47SJeff Kirsher } 594dee1ad47SJeff Kirsher 59523677ce3SJoe Perches if (!*link_up) 596dee1ad47SJeff Kirsher goto out; 597dee1ad47SJeff Kirsher } 598dee1ad47SJeff Kirsher 599dee1ad47SJeff Kirsher links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 600dee1ad47SJeff Kirsher if (link_up_wait_to_complete) { 601dee1ad47SJeff Kirsher for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 602dee1ad47SJeff Kirsher if (links_reg & IXGBE_LINKS_UP) { 603dee1ad47SJeff Kirsher *link_up = true; 604dee1ad47SJeff Kirsher break; 605dee1ad47SJeff Kirsher } else { 606dee1ad47SJeff Kirsher *link_up = false; 607dee1ad47SJeff Kirsher } 608dee1ad47SJeff Kirsher msleep(100); 609dee1ad47SJeff Kirsher links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 610dee1ad47SJeff Kirsher } 611dee1ad47SJeff Kirsher } else { 612dee1ad47SJeff Kirsher if (links_reg & IXGBE_LINKS_UP) 613dee1ad47SJeff Kirsher *link_up = true; 614dee1ad47SJeff Kirsher else 615dee1ad47SJeff Kirsher *link_up = false; 616dee1ad47SJeff Kirsher } 617dee1ad47SJeff Kirsher 618dee1ad47SJeff Kirsher if (links_reg & IXGBE_LINKS_SPEED) 619dee1ad47SJeff Kirsher *speed = IXGBE_LINK_SPEED_10GB_FULL; 620dee1ad47SJeff Kirsher else 621dee1ad47SJeff Kirsher *speed = IXGBE_LINK_SPEED_1GB_FULL; 622dee1ad47SJeff Kirsher 62323677ce3SJoe Perches if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && *link_up && 624dee1ad47SJeff Kirsher (ixgbe_validate_link_ready(hw) != 0)) 625dee1ad47SJeff Kirsher *link_up = false; 626dee1ad47SJeff Kirsher 627dee1ad47SJeff Kirsher out: 628dee1ad47SJeff Kirsher return 0; 629dee1ad47SJeff Kirsher } 630dee1ad47SJeff Kirsher 631dee1ad47SJeff Kirsher /** 632dee1ad47SJeff Kirsher * ixgbe_setup_mac_link_82598 - Set MAC link speed 633dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 634dee1ad47SJeff Kirsher * @speed: new link speed 635dee1ad47SJeff Kirsher * @autoneg: true if auto-negotiation enabled 636dee1ad47SJeff Kirsher * @autoneg_wait_to_complete: true when waiting for completion is needed 637dee1ad47SJeff Kirsher * 638dee1ad47SJeff Kirsher * Set the link speed in the AUTOC register and restarts link. 639dee1ad47SJeff Kirsher **/ 640dee1ad47SJeff Kirsher static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, 641dee1ad47SJeff Kirsher ixgbe_link_speed speed, bool autoneg, 642dee1ad47SJeff Kirsher bool autoneg_wait_to_complete) 643dee1ad47SJeff Kirsher { 644dee1ad47SJeff Kirsher s32 status = 0; 645dee1ad47SJeff Kirsher ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 646dee1ad47SJeff Kirsher u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 647dee1ad47SJeff Kirsher u32 autoc = curr_autoc; 648dee1ad47SJeff Kirsher u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 649dee1ad47SJeff Kirsher 650dee1ad47SJeff Kirsher /* Check to see if speed passed in is supported. */ 651dee1ad47SJeff Kirsher ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg); 652dee1ad47SJeff Kirsher speed &= link_capabilities; 653dee1ad47SJeff Kirsher 654dee1ad47SJeff Kirsher if (speed == IXGBE_LINK_SPEED_UNKNOWN) 655dee1ad47SJeff Kirsher status = IXGBE_ERR_LINK_SETUP; 656dee1ad47SJeff Kirsher 657dee1ad47SJeff Kirsher /* Set KX4/KX support according to speed requested */ 658dee1ad47SJeff Kirsher else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || 659dee1ad47SJeff Kirsher link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 660dee1ad47SJeff Kirsher autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; 661dee1ad47SJeff Kirsher if (speed & IXGBE_LINK_SPEED_10GB_FULL) 662dee1ad47SJeff Kirsher autoc |= IXGBE_AUTOC_KX4_SUPP; 663dee1ad47SJeff Kirsher if (speed & IXGBE_LINK_SPEED_1GB_FULL) 664dee1ad47SJeff Kirsher autoc |= IXGBE_AUTOC_KX_SUPP; 665dee1ad47SJeff Kirsher if (autoc != curr_autoc) 666dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 667dee1ad47SJeff Kirsher } 668dee1ad47SJeff Kirsher 669dee1ad47SJeff Kirsher if (status == 0) { 670dee1ad47SJeff Kirsher /* 671dee1ad47SJeff Kirsher * Setup and restart the link based on the new values in 672dee1ad47SJeff Kirsher * ixgbe_hw This will write the AUTOC register based on the new 673dee1ad47SJeff Kirsher * stored values 674dee1ad47SJeff Kirsher */ 675dee1ad47SJeff Kirsher status = ixgbe_start_mac_link_82598(hw, 676dee1ad47SJeff Kirsher autoneg_wait_to_complete); 677dee1ad47SJeff Kirsher } 678dee1ad47SJeff Kirsher 679dee1ad47SJeff Kirsher return status; 680dee1ad47SJeff Kirsher } 681dee1ad47SJeff Kirsher 682dee1ad47SJeff Kirsher 683dee1ad47SJeff Kirsher /** 684dee1ad47SJeff Kirsher * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field 685dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 686dee1ad47SJeff Kirsher * @speed: new link speed 687dee1ad47SJeff Kirsher * @autoneg: true if autonegotiation enabled 688dee1ad47SJeff Kirsher * @autoneg_wait_to_complete: true if waiting is needed to complete 689dee1ad47SJeff Kirsher * 690dee1ad47SJeff Kirsher * Sets the link speed in the AUTOC register in the MAC and restarts link. 691dee1ad47SJeff Kirsher **/ 692dee1ad47SJeff Kirsher static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 693dee1ad47SJeff Kirsher ixgbe_link_speed speed, 694dee1ad47SJeff Kirsher bool autoneg, 695dee1ad47SJeff Kirsher bool autoneg_wait_to_complete) 696dee1ad47SJeff Kirsher { 697dee1ad47SJeff Kirsher s32 status; 698dee1ad47SJeff Kirsher 699dee1ad47SJeff Kirsher /* Setup the PHY according to input speed */ 700dee1ad47SJeff Kirsher status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, 701dee1ad47SJeff Kirsher autoneg_wait_to_complete); 702dee1ad47SJeff Kirsher /* Set up MAC */ 703dee1ad47SJeff Kirsher ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); 704dee1ad47SJeff Kirsher 705dee1ad47SJeff Kirsher return status; 706dee1ad47SJeff Kirsher } 707dee1ad47SJeff Kirsher 708dee1ad47SJeff Kirsher /** 709dee1ad47SJeff Kirsher * ixgbe_reset_hw_82598 - Performs hardware reset 710dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 711dee1ad47SJeff Kirsher * 712dee1ad47SJeff Kirsher * Resets the hardware by resetting the transmit and receive units, masks and 713dee1ad47SJeff Kirsher * clears all interrupts, performing a PHY reset, and performing a link (MAC) 714dee1ad47SJeff Kirsher * reset. 715dee1ad47SJeff Kirsher **/ 716dee1ad47SJeff Kirsher static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 717dee1ad47SJeff Kirsher { 718dee1ad47SJeff Kirsher s32 status = 0; 719dee1ad47SJeff Kirsher s32 phy_status = 0; 720dee1ad47SJeff Kirsher u32 ctrl; 721dee1ad47SJeff Kirsher u32 gheccr; 722dee1ad47SJeff Kirsher u32 i; 723dee1ad47SJeff Kirsher u32 autoc; 724dee1ad47SJeff Kirsher u8 analog_val; 725dee1ad47SJeff Kirsher 726dee1ad47SJeff Kirsher /* Call adapter stop to disable tx/rx and clear interrupts */ 727ff9d1a5aSEmil Tantilov status = hw->mac.ops.stop_adapter(hw); 728ff9d1a5aSEmil Tantilov if (status != 0) 729ff9d1a5aSEmil Tantilov goto reset_hw_out; 730dee1ad47SJeff Kirsher 731dee1ad47SJeff Kirsher /* 732dee1ad47SJeff Kirsher * Power up the Atlas Tx lanes if they are currently powered down. 733dee1ad47SJeff Kirsher * Atlas Tx lanes are powered down for MAC loopback tests, but 734dee1ad47SJeff Kirsher * they are not automatically restored on reset. 735dee1ad47SJeff Kirsher */ 736dee1ad47SJeff Kirsher hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 737dee1ad47SJeff Kirsher if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 738dee1ad47SJeff Kirsher /* Enable Tx Atlas so packets can be transmitted again */ 739dee1ad47SJeff Kirsher hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 740dee1ad47SJeff Kirsher &analog_val); 741dee1ad47SJeff Kirsher analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 742dee1ad47SJeff Kirsher hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 743dee1ad47SJeff Kirsher analog_val); 744dee1ad47SJeff Kirsher 745dee1ad47SJeff Kirsher hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 746dee1ad47SJeff Kirsher &analog_val); 747dee1ad47SJeff Kirsher analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 748dee1ad47SJeff Kirsher hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 749dee1ad47SJeff Kirsher analog_val); 750dee1ad47SJeff Kirsher 751dee1ad47SJeff Kirsher hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 752dee1ad47SJeff Kirsher &analog_val); 753dee1ad47SJeff Kirsher analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 754dee1ad47SJeff Kirsher hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 755dee1ad47SJeff Kirsher analog_val); 756dee1ad47SJeff Kirsher 757dee1ad47SJeff Kirsher hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 758dee1ad47SJeff Kirsher &analog_val); 759dee1ad47SJeff Kirsher analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 760dee1ad47SJeff Kirsher hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 761dee1ad47SJeff Kirsher analog_val); 762dee1ad47SJeff Kirsher } 763dee1ad47SJeff Kirsher 764dee1ad47SJeff Kirsher /* Reset PHY */ 765dee1ad47SJeff Kirsher if (hw->phy.reset_disable == false) { 766dee1ad47SJeff Kirsher /* PHY ops must be identified and initialized prior to reset */ 767dee1ad47SJeff Kirsher 768dee1ad47SJeff Kirsher /* Init PHY and function pointers, perform SFP setup */ 769dee1ad47SJeff Kirsher phy_status = hw->phy.ops.init(hw); 770dee1ad47SJeff Kirsher if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) 771dee1ad47SJeff Kirsher goto reset_hw_out; 772ff9d1a5aSEmil Tantilov if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) 773ff9d1a5aSEmil Tantilov goto mac_reset_top; 774dee1ad47SJeff Kirsher 775dee1ad47SJeff Kirsher hw->phy.ops.reset(hw); 776dee1ad47SJeff Kirsher } 777dee1ad47SJeff Kirsher 778dee1ad47SJeff Kirsher mac_reset_top: 779dee1ad47SJeff Kirsher /* 780dee1ad47SJeff Kirsher * Issue global reset to the MAC. This needs to be a SW reset. 781dee1ad47SJeff Kirsher * If link reset is used, it might reset the MAC when mng is using it 782dee1ad47SJeff Kirsher */ 7838132b54eSAlexander Duyck ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST; 7848132b54eSAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 785dee1ad47SJeff Kirsher IXGBE_WRITE_FLUSH(hw); 786dee1ad47SJeff Kirsher 787dee1ad47SJeff Kirsher /* Poll for reset bit to self-clear indicating reset is complete */ 788dee1ad47SJeff Kirsher for (i = 0; i < 10; i++) { 789dee1ad47SJeff Kirsher udelay(1); 790dee1ad47SJeff Kirsher ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 791dee1ad47SJeff Kirsher if (!(ctrl & IXGBE_CTRL_RST)) 792dee1ad47SJeff Kirsher break; 793dee1ad47SJeff Kirsher } 794dee1ad47SJeff Kirsher if (ctrl & IXGBE_CTRL_RST) { 795dee1ad47SJeff Kirsher status = IXGBE_ERR_RESET_FAILED; 796dee1ad47SJeff Kirsher hw_dbg(hw, "Reset polling failed to complete.\n"); 797dee1ad47SJeff Kirsher } 798dee1ad47SJeff Kirsher 7998132b54eSAlexander Duyck msleep(50); 8008132b54eSAlexander Duyck 801dee1ad47SJeff Kirsher /* 802dee1ad47SJeff Kirsher * Double resets are required for recovery from certain error 803dee1ad47SJeff Kirsher * conditions. Between resets, it is necessary to stall to allow time 8048132b54eSAlexander Duyck * for any pending HW events to complete. 805dee1ad47SJeff Kirsher */ 806dee1ad47SJeff Kirsher if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 807dee1ad47SJeff Kirsher hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 808dee1ad47SJeff Kirsher goto mac_reset_top; 809dee1ad47SJeff Kirsher } 810dee1ad47SJeff Kirsher 811dee1ad47SJeff Kirsher gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 812dee1ad47SJeff Kirsher gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 813dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 814dee1ad47SJeff Kirsher 815dee1ad47SJeff Kirsher /* 816dee1ad47SJeff Kirsher * Store the original AUTOC value if it has not been 817dee1ad47SJeff Kirsher * stored off yet. Otherwise restore the stored original 818dee1ad47SJeff Kirsher * AUTOC value since the reset operation sets back to deaults. 819dee1ad47SJeff Kirsher */ 820dee1ad47SJeff Kirsher autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 821dee1ad47SJeff Kirsher if (hw->mac.orig_link_settings_stored == false) { 822dee1ad47SJeff Kirsher hw->mac.orig_autoc = autoc; 823dee1ad47SJeff Kirsher hw->mac.orig_link_settings_stored = true; 824dee1ad47SJeff Kirsher } else if (autoc != hw->mac.orig_autoc) { 825dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); 826dee1ad47SJeff Kirsher } 827dee1ad47SJeff Kirsher 828dee1ad47SJeff Kirsher /* Store the permanent mac address */ 829dee1ad47SJeff Kirsher hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 830dee1ad47SJeff Kirsher 831dee1ad47SJeff Kirsher /* 832dee1ad47SJeff Kirsher * Store MAC address from RAR0, clear receive address registers, and 833dee1ad47SJeff Kirsher * clear the multicast table 834dee1ad47SJeff Kirsher */ 835dee1ad47SJeff Kirsher hw->mac.ops.init_rx_addrs(hw); 836dee1ad47SJeff Kirsher 837dee1ad47SJeff Kirsher reset_hw_out: 838dee1ad47SJeff Kirsher if (phy_status) 839dee1ad47SJeff Kirsher status = phy_status; 840dee1ad47SJeff Kirsher 841dee1ad47SJeff Kirsher return status; 842dee1ad47SJeff Kirsher } 843dee1ad47SJeff Kirsher 844dee1ad47SJeff Kirsher /** 845dee1ad47SJeff Kirsher * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 846dee1ad47SJeff Kirsher * @hw: pointer to hardware struct 847dee1ad47SJeff Kirsher * @rar: receive address register index to associate with a VMDq index 848dee1ad47SJeff Kirsher * @vmdq: VMDq set index 849dee1ad47SJeff Kirsher **/ 850dee1ad47SJeff Kirsher static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 851dee1ad47SJeff Kirsher { 852dee1ad47SJeff Kirsher u32 rar_high; 853dee1ad47SJeff Kirsher u32 rar_entries = hw->mac.num_rar_entries; 854dee1ad47SJeff Kirsher 855dee1ad47SJeff Kirsher /* Make sure we are using a valid rar index range */ 856dee1ad47SJeff Kirsher if (rar >= rar_entries) { 857dee1ad47SJeff Kirsher hw_dbg(hw, "RAR index %d is out of range.\n", rar); 858dee1ad47SJeff Kirsher return IXGBE_ERR_INVALID_ARGUMENT; 859dee1ad47SJeff Kirsher } 860dee1ad47SJeff Kirsher 861dee1ad47SJeff Kirsher rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 862dee1ad47SJeff Kirsher rar_high &= ~IXGBE_RAH_VIND_MASK; 863dee1ad47SJeff Kirsher rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 864dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 865dee1ad47SJeff Kirsher return 0; 866dee1ad47SJeff Kirsher } 867dee1ad47SJeff Kirsher 868dee1ad47SJeff Kirsher /** 869dee1ad47SJeff Kirsher * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address 870dee1ad47SJeff Kirsher * @hw: pointer to hardware struct 871dee1ad47SJeff Kirsher * @rar: receive address register index to associate with a VMDq index 872dee1ad47SJeff Kirsher * @vmdq: VMDq clear index (not used in 82598, but elsewhere) 873dee1ad47SJeff Kirsher **/ 874dee1ad47SJeff Kirsher static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 875dee1ad47SJeff Kirsher { 876dee1ad47SJeff Kirsher u32 rar_high; 877dee1ad47SJeff Kirsher u32 rar_entries = hw->mac.num_rar_entries; 878dee1ad47SJeff Kirsher 879dee1ad47SJeff Kirsher 880dee1ad47SJeff Kirsher /* Make sure we are using a valid rar index range */ 881dee1ad47SJeff Kirsher if (rar >= rar_entries) { 882dee1ad47SJeff Kirsher hw_dbg(hw, "RAR index %d is out of range.\n", rar); 883dee1ad47SJeff Kirsher return IXGBE_ERR_INVALID_ARGUMENT; 884dee1ad47SJeff Kirsher } 885dee1ad47SJeff Kirsher 886dee1ad47SJeff Kirsher rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 887dee1ad47SJeff Kirsher if (rar_high & IXGBE_RAH_VIND_MASK) { 888dee1ad47SJeff Kirsher rar_high &= ~IXGBE_RAH_VIND_MASK; 889dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 890dee1ad47SJeff Kirsher } 891dee1ad47SJeff Kirsher 892dee1ad47SJeff Kirsher return 0; 893dee1ad47SJeff Kirsher } 894dee1ad47SJeff Kirsher 895dee1ad47SJeff Kirsher /** 896dee1ad47SJeff Kirsher * ixgbe_set_vfta_82598 - Set VLAN filter table 897dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 898dee1ad47SJeff Kirsher * @vlan: VLAN id to write to VLAN filter 899dee1ad47SJeff Kirsher * @vind: VMDq output index that maps queue to VLAN id in VFTA 900dee1ad47SJeff Kirsher * @vlan_on: boolean flag to turn on/off VLAN in VFTA 901dee1ad47SJeff Kirsher * 902dee1ad47SJeff Kirsher * Turn on/off specified VLAN in the VLAN filter table. 903dee1ad47SJeff Kirsher **/ 904dee1ad47SJeff Kirsher static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, 905dee1ad47SJeff Kirsher bool vlan_on) 906dee1ad47SJeff Kirsher { 907dee1ad47SJeff Kirsher u32 regindex; 908dee1ad47SJeff Kirsher u32 bitindex; 909dee1ad47SJeff Kirsher u32 bits; 910dee1ad47SJeff Kirsher u32 vftabyte; 911dee1ad47SJeff Kirsher 912dee1ad47SJeff Kirsher if (vlan > 4095) 913dee1ad47SJeff Kirsher return IXGBE_ERR_PARAM; 914dee1ad47SJeff Kirsher 915dee1ad47SJeff Kirsher /* Determine 32-bit word position in array */ 916dee1ad47SJeff Kirsher regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ 917dee1ad47SJeff Kirsher 918dee1ad47SJeff Kirsher /* Determine the location of the (VMD) queue index */ 919dee1ad47SJeff Kirsher vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 920dee1ad47SJeff Kirsher bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 921dee1ad47SJeff Kirsher 922dee1ad47SJeff Kirsher /* Set the nibble for VMD queue index */ 923dee1ad47SJeff Kirsher bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); 924dee1ad47SJeff Kirsher bits &= (~(0x0F << bitindex)); 925dee1ad47SJeff Kirsher bits |= (vind << bitindex); 926dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); 927dee1ad47SJeff Kirsher 928dee1ad47SJeff Kirsher /* Determine the location of the bit for this VLAN id */ 929dee1ad47SJeff Kirsher bitindex = vlan & 0x1F; /* lower five bits */ 930dee1ad47SJeff Kirsher 931dee1ad47SJeff Kirsher bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 932dee1ad47SJeff Kirsher if (vlan_on) 933dee1ad47SJeff Kirsher /* Turn on this VLAN id */ 934dee1ad47SJeff Kirsher bits |= (1 << bitindex); 935dee1ad47SJeff Kirsher else 936dee1ad47SJeff Kirsher /* Turn off this VLAN id */ 937dee1ad47SJeff Kirsher bits &= ~(1 << bitindex); 938dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 939dee1ad47SJeff Kirsher 940dee1ad47SJeff Kirsher return 0; 941dee1ad47SJeff Kirsher } 942dee1ad47SJeff Kirsher 943dee1ad47SJeff Kirsher /** 944dee1ad47SJeff Kirsher * ixgbe_clear_vfta_82598 - Clear VLAN filter table 945dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 946dee1ad47SJeff Kirsher * 947dee1ad47SJeff Kirsher * Clears the VLAN filer table, and the VMDq index associated with the filter 948dee1ad47SJeff Kirsher **/ 949dee1ad47SJeff Kirsher static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) 950dee1ad47SJeff Kirsher { 951dee1ad47SJeff Kirsher u32 offset; 952dee1ad47SJeff Kirsher u32 vlanbyte; 953dee1ad47SJeff Kirsher 954dee1ad47SJeff Kirsher for (offset = 0; offset < hw->mac.vft_size; offset++) 955dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 956dee1ad47SJeff Kirsher 957dee1ad47SJeff Kirsher for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 958dee1ad47SJeff Kirsher for (offset = 0; offset < hw->mac.vft_size; offset++) 959dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), 960dee1ad47SJeff Kirsher 0); 961dee1ad47SJeff Kirsher 962dee1ad47SJeff Kirsher return 0; 963dee1ad47SJeff Kirsher } 964dee1ad47SJeff Kirsher 965dee1ad47SJeff Kirsher /** 966dee1ad47SJeff Kirsher * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register 967dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 968dee1ad47SJeff Kirsher * @reg: analog register to read 969dee1ad47SJeff Kirsher * @val: read value 970dee1ad47SJeff Kirsher * 971dee1ad47SJeff Kirsher * Performs read operation to Atlas analog register specified. 972dee1ad47SJeff Kirsher **/ 973dee1ad47SJeff Kirsher static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) 974dee1ad47SJeff Kirsher { 975dee1ad47SJeff Kirsher u32 atlas_ctl; 976dee1ad47SJeff Kirsher 977dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, 978dee1ad47SJeff Kirsher IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 979dee1ad47SJeff Kirsher IXGBE_WRITE_FLUSH(hw); 980dee1ad47SJeff Kirsher udelay(10); 981dee1ad47SJeff Kirsher atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 982dee1ad47SJeff Kirsher *val = (u8)atlas_ctl; 983dee1ad47SJeff Kirsher 984dee1ad47SJeff Kirsher return 0; 985dee1ad47SJeff Kirsher } 986dee1ad47SJeff Kirsher 987dee1ad47SJeff Kirsher /** 988dee1ad47SJeff Kirsher * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register 989dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 990dee1ad47SJeff Kirsher * @reg: atlas register to write 991dee1ad47SJeff Kirsher * @val: value to write 992dee1ad47SJeff Kirsher * 993dee1ad47SJeff Kirsher * Performs write operation to Atlas analog register specified. 994dee1ad47SJeff Kirsher **/ 995dee1ad47SJeff Kirsher static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) 996dee1ad47SJeff Kirsher { 997dee1ad47SJeff Kirsher u32 atlas_ctl; 998dee1ad47SJeff Kirsher 999dee1ad47SJeff Kirsher atlas_ctl = (reg << 8) | val; 1000dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 1001dee1ad47SJeff Kirsher IXGBE_WRITE_FLUSH(hw); 1002dee1ad47SJeff Kirsher udelay(10); 1003dee1ad47SJeff Kirsher 1004dee1ad47SJeff Kirsher return 0; 1005dee1ad47SJeff Kirsher } 1006dee1ad47SJeff Kirsher 1007dee1ad47SJeff Kirsher /** 1008dee1ad47SJeff Kirsher * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. 1009dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 1010dee1ad47SJeff Kirsher * @byte_offset: EEPROM byte offset to read 1011dee1ad47SJeff Kirsher * @eeprom_data: value read 1012dee1ad47SJeff Kirsher * 1013dee1ad47SJeff Kirsher * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 1014dee1ad47SJeff Kirsher **/ 1015dee1ad47SJeff Kirsher static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 1016dee1ad47SJeff Kirsher u8 *eeprom_data) 1017dee1ad47SJeff Kirsher { 1018dee1ad47SJeff Kirsher s32 status = 0; 1019dee1ad47SJeff Kirsher u16 sfp_addr = 0; 1020dee1ad47SJeff Kirsher u16 sfp_data = 0; 1021dee1ad47SJeff Kirsher u16 sfp_stat = 0; 1022dee1ad47SJeff Kirsher u32 i; 1023dee1ad47SJeff Kirsher 1024dee1ad47SJeff Kirsher if (hw->phy.type == ixgbe_phy_nl) { 1025dee1ad47SJeff Kirsher /* 1026dee1ad47SJeff Kirsher * phy SDA/SCL registers are at addresses 0xC30A to 1027dee1ad47SJeff Kirsher * 0xC30D. These registers are used to talk to the SFP+ 1028dee1ad47SJeff Kirsher * module's EEPROM through the SDA/SCL (I2C) interface. 1029dee1ad47SJeff Kirsher */ 1030dee1ad47SJeff Kirsher sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset; 1031dee1ad47SJeff Kirsher sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); 1032dee1ad47SJeff Kirsher hw->phy.ops.write_reg(hw, 1033dee1ad47SJeff Kirsher IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, 1034dee1ad47SJeff Kirsher MDIO_MMD_PMAPMD, 1035dee1ad47SJeff Kirsher sfp_addr); 1036dee1ad47SJeff Kirsher 1037dee1ad47SJeff Kirsher /* Poll status */ 1038dee1ad47SJeff Kirsher for (i = 0; i < 100; i++) { 1039dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, 1040dee1ad47SJeff Kirsher IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, 1041dee1ad47SJeff Kirsher MDIO_MMD_PMAPMD, 1042dee1ad47SJeff Kirsher &sfp_stat); 1043dee1ad47SJeff Kirsher sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; 1044dee1ad47SJeff Kirsher if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) 1045dee1ad47SJeff Kirsher break; 1046dee1ad47SJeff Kirsher usleep_range(10000, 20000); 1047dee1ad47SJeff Kirsher } 1048dee1ad47SJeff Kirsher 1049dee1ad47SJeff Kirsher if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { 1050dee1ad47SJeff Kirsher hw_dbg(hw, "EEPROM read did not pass.\n"); 1051dee1ad47SJeff Kirsher status = IXGBE_ERR_SFP_NOT_PRESENT; 1052dee1ad47SJeff Kirsher goto out; 1053dee1ad47SJeff Kirsher } 1054dee1ad47SJeff Kirsher 1055dee1ad47SJeff Kirsher /* Read data */ 1056dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, 1057dee1ad47SJeff Kirsher MDIO_MMD_PMAPMD, &sfp_data); 1058dee1ad47SJeff Kirsher 1059dee1ad47SJeff Kirsher *eeprom_data = (u8)(sfp_data >> 8); 1060dee1ad47SJeff Kirsher } else { 1061dee1ad47SJeff Kirsher status = IXGBE_ERR_PHY; 1062dee1ad47SJeff Kirsher goto out; 1063dee1ad47SJeff Kirsher } 1064dee1ad47SJeff Kirsher 1065dee1ad47SJeff Kirsher out: 1066dee1ad47SJeff Kirsher return status; 1067dee1ad47SJeff Kirsher } 1068dee1ad47SJeff Kirsher 1069dee1ad47SJeff Kirsher /** 1070dee1ad47SJeff Kirsher * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type 1071dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 1072dee1ad47SJeff Kirsher * 1073dee1ad47SJeff Kirsher * Determines physical layer capabilities of the current configuration. 1074dee1ad47SJeff Kirsher **/ 1075dee1ad47SJeff Kirsher static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) 1076dee1ad47SJeff Kirsher { 1077dee1ad47SJeff Kirsher u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1078dee1ad47SJeff Kirsher u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1079dee1ad47SJeff Kirsher u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1080dee1ad47SJeff Kirsher u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1081dee1ad47SJeff Kirsher u16 ext_ability = 0; 1082dee1ad47SJeff Kirsher 1083dee1ad47SJeff Kirsher hw->phy.ops.identify(hw); 1084dee1ad47SJeff Kirsher 1085dee1ad47SJeff Kirsher /* Copper PHY must be checked before AUTOC LMS to determine correct 1086dee1ad47SJeff Kirsher * physical layer because 10GBase-T PHYs use LMS = KX4/KX */ 1087dee1ad47SJeff Kirsher switch (hw->phy.type) { 1088dee1ad47SJeff Kirsher case ixgbe_phy_tn: 1089dee1ad47SJeff Kirsher case ixgbe_phy_cu_unknown: 1090dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, 1091dee1ad47SJeff Kirsher MDIO_MMD_PMAPMD, &ext_ability); 1092dee1ad47SJeff Kirsher if (ext_ability & MDIO_PMA_EXTABLE_10GBT) 1093dee1ad47SJeff Kirsher physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1094dee1ad47SJeff Kirsher if (ext_ability & MDIO_PMA_EXTABLE_1000BT) 1095dee1ad47SJeff Kirsher physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1096dee1ad47SJeff Kirsher if (ext_ability & MDIO_PMA_EXTABLE_100BTX) 1097dee1ad47SJeff Kirsher physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1098dee1ad47SJeff Kirsher goto out; 1099dee1ad47SJeff Kirsher default: 1100dee1ad47SJeff Kirsher break; 1101dee1ad47SJeff Kirsher } 1102dee1ad47SJeff Kirsher 1103dee1ad47SJeff Kirsher switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1104dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_1G_AN: 1105dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1106dee1ad47SJeff Kirsher if (pma_pmd_1g == IXGBE_AUTOC_1G_KX) 1107dee1ad47SJeff Kirsher physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1108dee1ad47SJeff Kirsher else 1109dee1ad47SJeff Kirsher physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1110dee1ad47SJeff Kirsher break; 1111dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1112dee1ad47SJeff Kirsher if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4) 1113dee1ad47SJeff Kirsher physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1114dee1ad47SJeff Kirsher else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4) 1115dee1ad47SJeff Kirsher physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1116dee1ad47SJeff Kirsher else /* XAUI */ 1117dee1ad47SJeff Kirsher physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1118dee1ad47SJeff Kirsher break; 1119dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_KX4_AN: 1120dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 1121dee1ad47SJeff Kirsher if (autoc & IXGBE_AUTOC_KX_SUPP) 1122dee1ad47SJeff Kirsher physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1123dee1ad47SJeff Kirsher if (autoc & IXGBE_AUTOC_KX4_SUPP) 1124dee1ad47SJeff Kirsher physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1125dee1ad47SJeff Kirsher break; 1126dee1ad47SJeff Kirsher default: 1127dee1ad47SJeff Kirsher break; 1128dee1ad47SJeff Kirsher } 1129dee1ad47SJeff Kirsher 1130dee1ad47SJeff Kirsher if (hw->phy.type == ixgbe_phy_nl) { 1131dee1ad47SJeff Kirsher hw->phy.ops.identify_sfp(hw); 1132dee1ad47SJeff Kirsher 1133dee1ad47SJeff Kirsher switch (hw->phy.sfp_type) { 1134dee1ad47SJeff Kirsher case ixgbe_sfp_type_da_cu: 1135dee1ad47SJeff Kirsher physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1136dee1ad47SJeff Kirsher break; 1137dee1ad47SJeff Kirsher case ixgbe_sfp_type_sr: 1138dee1ad47SJeff Kirsher physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1139dee1ad47SJeff Kirsher break; 1140dee1ad47SJeff Kirsher case ixgbe_sfp_type_lr: 1141dee1ad47SJeff Kirsher physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1142dee1ad47SJeff Kirsher break; 1143dee1ad47SJeff Kirsher default: 1144dee1ad47SJeff Kirsher physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1145dee1ad47SJeff Kirsher break; 1146dee1ad47SJeff Kirsher } 1147dee1ad47SJeff Kirsher } 1148dee1ad47SJeff Kirsher 1149dee1ad47SJeff Kirsher switch (hw->device_id) { 1150dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 1151dee1ad47SJeff Kirsher physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1152dee1ad47SJeff Kirsher break; 1153dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598AF_DUAL_PORT: 1154dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 1155dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 1156dee1ad47SJeff Kirsher physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1157dee1ad47SJeff Kirsher break; 1158dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598EB_XF_LR: 1159dee1ad47SJeff Kirsher physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1160dee1ad47SJeff Kirsher break; 1161dee1ad47SJeff Kirsher default: 1162dee1ad47SJeff Kirsher break; 1163dee1ad47SJeff Kirsher } 1164dee1ad47SJeff Kirsher 1165dee1ad47SJeff Kirsher out: 1166dee1ad47SJeff Kirsher return physical_layer; 1167dee1ad47SJeff Kirsher } 1168dee1ad47SJeff Kirsher 1169dee1ad47SJeff Kirsher /** 1170dee1ad47SJeff Kirsher * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple 1171dee1ad47SJeff Kirsher * port devices. 1172dee1ad47SJeff Kirsher * @hw: pointer to the HW structure 1173dee1ad47SJeff Kirsher * 1174dee1ad47SJeff Kirsher * Calls common function and corrects issue with some single port devices 1175dee1ad47SJeff Kirsher * that enable LAN1 but not LAN0. 1176dee1ad47SJeff Kirsher **/ 1177dee1ad47SJeff Kirsher static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw) 1178dee1ad47SJeff Kirsher { 1179dee1ad47SJeff Kirsher struct ixgbe_bus_info *bus = &hw->bus; 1180dee1ad47SJeff Kirsher u16 pci_gen = 0; 1181dee1ad47SJeff Kirsher u16 pci_ctrl2 = 0; 1182dee1ad47SJeff Kirsher 1183dee1ad47SJeff Kirsher ixgbe_set_lan_id_multi_port_pcie(hw); 1184dee1ad47SJeff Kirsher 1185dee1ad47SJeff Kirsher /* check if LAN0 is disabled */ 1186dee1ad47SJeff Kirsher hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen); 1187dee1ad47SJeff Kirsher if ((pci_gen != 0) && (pci_gen != 0xFFFF)) { 1188dee1ad47SJeff Kirsher 1189dee1ad47SJeff Kirsher hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2); 1190dee1ad47SJeff Kirsher 1191dee1ad47SJeff Kirsher /* if LAN0 is completely disabled force function to 0 */ 1192dee1ad47SJeff Kirsher if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) && 1193dee1ad47SJeff Kirsher !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) && 1194dee1ad47SJeff Kirsher !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) { 1195dee1ad47SJeff Kirsher 1196dee1ad47SJeff Kirsher bus->func = 0; 1197dee1ad47SJeff Kirsher } 1198dee1ad47SJeff Kirsher } 1199dee1ad47SJeff Kirsher } 1200dee1ad47SJeff Kirsher 1201dee1ad47SJeff Kirsher /** 1202dee1ad47SJeff Kirsher * ixgbe_set_rxpba_82598 - Configure packet buffers 1203dee1ad47SJeff Kirsher * @hw: pointer to hardware structure 1204dee1ad47SJeff Kirsher * @dcb_config: pointer to ixgbe_dcb_config structure 1205dee1ad47SJeff Kirsher * 1206dee1ad47SJeff Kirsher * Configure packet buffers. 1207dee1ad47SJeff Kirsher */ 1208dee1ad47SJeff Kirsher static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, u32 headroom, 1209dee1ad47SJeff Kirsher int strategy) 1210dee1ad47SJeff Kirsher { 1211dee1ad47SJeff Kirsher u32 rxpktsize = IXGBE_RXPBSIZE_64KB; 1212dee1ad47SJeff Kirsher u8 i = 0; 1213dee1ad47SJeff Kirsher 1214dee1ad47SJeff Kirsher if (!num_pb) 1215dee1ad47SJeff Kirsher return; 1216dee1ad47SJeff Kirsher 1217dee1ad47SJeff Kirsher /* Setup Rx packet buffer sizes */ 1218dee1ad47SJeff Kirsher switch (strategy) { 1219dee1ad47SJeff Kirsher case PBA_STRATEGY_WEIGHTED: 1220dee1ad47SJeff Kirsher /* Setup the first four at 80KB */ 1221dee1ad47SJeff Kirsher rxpktsize = IXGBE_RXPBSIZE_80KB; 1222dee1ad47SJeff Kirsher for (; i < 4; i++) 1223dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 1224dee1ad47SJeff Kirsher /* Setup the last four at 48KB...don't re-init i */ 1225dee1ad47SJeff Kirsher rxpktsize = IXGBE_RXPBSIZE_48KB; 1226dee1ad47SJeff Kirsher /* Fall Through */ 1227dee1ad47SJeff Kirsher case PBA_STRATEGY_EQUAL: 1228dee1ad47SJeff Kirsher default: 1229dee1ad47SJeff Kirsher /* Divide the remaining Rx packet buffer evenly among the TCs */ 1230dee1ad47SJeff Kirsher for (; i < IXGBE_MAX_PACKET_BUFFERS; i++) 1231dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 1232dee1ad47SJeff Kirsher break; 1233dee1ad47SJeff Kirsher } 1234dee1ad47SJeff Kirsher 1235dee1ad47SJeff Kirsher /* Setup Tx packet buffer sizes */ 1236dee1ad47SJeff Kirsher for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) 1237dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB); 1238dee1ad47SJeff Kirsher 1239dee1ad47SJeff Kirsher return; 1240dee1ad47SJeff Kirsher } 1241dee1ad47SJeff Kirsher 1242dee1ad47SJeff Kirsher static struct ixgbe_mac_operations mac_ops_82598 = { 1243dee1ad47SJeff Kirsher .init_hw = &ixgbe_init_hw_generic, 1244dee1ad47SJeff Kirsher .reset_hw = &ixgbe_reset_hw_82598, 1245dee1ad47SJeff Kirsher .start_hw = &ixgbe_start_hw_82598, 1246dee1ad47SJeff Kirsher .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 1247dee1ad47SJeff Kirsher .get_media_type = &ixgbe_get_media_type_82598, 1248dee1ad47SJeff Kirsher .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598, 1249dee1ad47SJeff Kirsher .enable_rx_dma = &ixgbe_enable_rx_dma_generic, 1250dee1ad47SJeff Kirsher .get_mac_addr = &ixgbe_get_mac_addr_generic, 1251dee1ad47SJeff Kirsher .stop_adapter = &ixgbe_stop_adapter_generic, 1252dee1ad47SJeff Kirsher .get_bus_info = &ixgbe_get_bus_info_generic, 1253dee1ad47SJeff Kirsher .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598, 1254dee1ad47SJeff Kirsher .read_analog_reg8 = &ixgbe_read_analog_reg8_82598, 1255dee1ad47SJeff Kirsher .write_analog_reg8 = &ixgbe_write_analog_reg8_82598, 1256dee1ad47SJeff Kirsher .setup_link = &ixgbe_setup_mac_link_82598, 1257dee1ad47SJeff Kirsher .set_rxpba = &ixgbe_set_rxpba_82598, 1258dee1ad47SJeff Kirsher .check_link = &ixgbe_check_mac_link_82598, 1259dee1ad47SJeff Kirsher .get_link_capabilities = &ixgbe_get_link_capabilities_82598, 1260dee1ad47SJeff Kirsher .led_on = &ixgbe_led_on_generic, 1261dee1ad47SJeff Kirsher .led_off = &ixgbe_led_off_generic, 1262dee1ad47SJeff Kirsher .blink_led_start = &ixgbe_blink_led_start_generic, 1263dee1ad47SJeff Kirsher .blink_led_stop = &ixgbe_blink_led_stop_generic, 1264dee1ad47SJeff Kirsher .set_rar = &ixgbe_set_rar_generic, 1265dee1ad47SJeff Kirsher .clear_rar = &ixgbe_clear_rar_generic, 1266dee1ad47SJeff Kirsher .set_vmdq = &ixgbe_set_vmdq_82598, 1267dee1ad47SJeff Kirsher .clear_vmdq = &ixgbe_clear_vmdq_82598, 1268dee1ad47SJeff Kirsher .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 1269dee1ad47SJeff Kirsher .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 1270dee1ad47SJeff Kirsher .enable_mc = &ixgbe_enable_mc_generic, 1271dee1ad47SJeff Kirsher .disable_mc = &ixgbe_disable_mc_generic, 1272dee1ad47SJeff Kirsher .clear_vfta = &ixgbe_clear_vfta_82598, 1273dee1ad47SJeff Kirsher .set_vfta = &ixgbe_set_vfta_82598, 1274dee1ad47SJeff Kirsher .fc_enable = &ixgbe_fc_enable_82598, 1275dee1ad47SJeff Kirsher .set_fw_drv_ver = NULL, 1276dee1ad47SJeff Kirsher .acquire_swfw_sync = &ixgbe_acquire_swfw_sync, 1277dee1ad47SJeff Kirsher .release_swfw_sync = &ixgbe_release_swfw_sync, 12783ca8bc6dSDon Skidmore .get_thermal_sensor_data = NULL, 12793ca8bc6dSDon Skidmore .init_thermal_sensor_thresh = NULL, 1280dee1ad47SJeff Kirsher }; 1281dee1ad47SJeff Kirsher 1282dee1ad47SJeff Kirsher static struct ixgbe_eeprom_operations eeprom_ops_82598 = { 1283dee1ad47SJeff Kirsher .init_params = &ixgbe_init_eeprom_params_generic, 1284dee1ad47SJeff Kirsher .read = &ixgbe_read_eerd_generic, 12852fa5eef4SEmil Tantilov .write = &ixgbe_write_eeprom_generic, 12862fa5eef4SEmil Tantilov .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic, 1287dee1ad47SJeff Kirsher .read_buffer = &ixgbe_read_eerd_buffer_generic, 1288dee1ad47SJeff Kirsher .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, 1289dee1ad47SJeff Kirsher .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, 1290dee1ad47SJeff Kirsher .update_checksum = &ixgbe_update_eeprom_checksum_generic, 1291dee1ad47SJeff Kirsher }; 1292dee1ad47SJeff Kirsher 1293dee1ad47SJeff Kirsher static struct ixgbe_phy_operations phy_ops_82598 = { 1294dee1ad47SJeff Kirsher .identify = &ixgbe_identify_phy_generic, 1295dee1ad47SJeff Kirsher .identify_sfp = &ixgbe_identify_sfp_module_generic, 1296dee1ad47SJeff Kirsher .init = &ixgbe_init_phy_ops_82598, 1297dee1ad47SJeff Kirsher .reset = &ixgbe_reset_phy_generic, 1298dee1ad47SJeff Kirsher .read_reg = &ixgbe_read_phy_reg_generic, 1299dee1ad47SJeff Kirsher .write_reg = &ixgbe_write_phy_reg_generic, 1300dee1ad47SJeff Kirsher .setup_link = &ixgbe_setup_phy_link_generic, 1301dee1ad47SJeff Kirsher .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 1302dee1ad47SJeff Kirsher .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598, 1303dee1ad47SJeff Kirsher .check_overtemp = &ixgbe_tn_check_overtemp, 1304dee1ad47SJeff Kirsher }; 1305dee1ad47SJeff Kirsher 1306dee1ad47SJeff Kirsher struct ixgbe_info ixgbe_82598_info = { 1307dee1ad47SJeff Kirsher .mac = ixgbe_mac_82598EB, 1308dee1ad47SJeff Kirsher .get_invariants = &ixgbe_get_invariants_82598, 1309dee1ad47SJeff Kirsher .mac_ops = &mac_ops_82598, 1310dee1ad47SJeff Kirsher .eeprom_ops = &eeprom_ops_82598, 1311dee1ad47SJeff Kirsher .phy_ops = &phy_ops_82598, 1312dee1ad47SJeff Kirsher }; 1313dee1ad47SJeff Kirsher 1314