1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #ifndef _IXGBE_H_ 30 #define _IXGBE_H_ 31 32 #include <linux/bitops.h> 33 #include <linux/types.h> 34 #include <linux/pci.h> 35 #include <linux/netdevice.h> 36 #include <linux/cpumask.h> 37 #include <linux/aer.h> 38 #include <linux/if_vlan.h> 39 #include <linux/jiffies.h> 40 41 #include <linux/clocksource.h> 42 #include <linux/net_tstamp.h> 43 #include <linux/ptp_clock_kernel.h> 44 45 #include "ixgbe_type.h" 46 #include "ixgbe_common.h" 47 #include "ixgbe_dcb.h" 48 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) 49 #define IXGBE_FCOE 50 #include "ixgbe_fcoe.h" 51 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ 52 #ifdef CONFIG_IXGBE_DCA 53 #include <linux/dca.h> 54 #endif 55 56 #include <net/busy_poll.h> 57 58 #ifdef CONFIG_NET_RX_BUSY_POLL 59 #define BP_EXTENDED_STATS 60 #endif 61 /* common prefix used by pr_<> macros */ 62 #undef pr_fmt 63 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 64 65 /* TX/RX descriptor defines */ 66 #define IXGBE_DEFAULT_TXD 512 67 #define IXGBE_DEFAULT_TX_WORK 256 68 #define IXGBE_MAX_TXD 4096 69 #define IXGBE_MIN_TXD 64 70 71 #if (PAGE_SIZE < 8192) 72 #define IXGBE_DEFAULT_RXD 512 73 #else 74 #define IXGBE_DEFAULT_RXD 128 75 #endif 76 #define IXGBE_MAX_RXD 4096 77 #define IXGBE_MIN_RXD 64 78 79 /* flow control */ 80 #define IXGBE_MIN_FCRTL 0x40 81 #define IXGBE_MAX_FCRTL 0x7FF80 82 #define IXGBE_MIN_FCRTH 0x600 83 #define IXGBE_MAX_FCRTH 0x7FFF0 84 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF 85 #define IXGBE_MIN_FCPAUSE 0 86 #define IXGBE_MAX_FCPAUSE 0xFFFF 87 88 /* Supported Rx Buffer Sizes */ 89 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ 90 #define IXGBE_RXBUFFER_2K 2048 91 #define IXGBE_RXBUFFER_3K 3072 92 #define IXGBE_RXBUFFER_4K 4096 93 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 94 95 /* 96 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 97 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, 98 * this adds up to 448 bytes of extra data. 99 * 100 * Since netdev_alloc_skb now allocates a page fragment we can use a value 101 * of 256 and the resultant skb will have a truesize of 960 or less. 102 */ 103 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 104 105 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 106 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 107 108 enum ixgbe_tx_flags { 109 /* cmd_type flags */ 110 IXGBE_TX_FLAGS_HW_VLAN = 0x01, 111 IXGBE_TX_FLAGS_TSO = 0x02, 112 IXGBE_TX_FLAGS_TSTAMP = 0x04, 113 114 /* olinfo flags */ 115 IXGBE_TX_FLAGS_CC = 0x08, 116 IXGBE_TX_FLAGS_IPV4 = 0x10, 117 IXGBE_TX_FLAGS_CSUM = 0x20, 118 119 /* software defined flags */ 120 IXGBE_TX_FLAGS_SW_VLAN = 0x40, 121 IXGBE_TX_FLAGS_FCOE = 0x80, 122 }; 123 124 /* VLAN info */ 125 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 126 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 127 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 128 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 129 130 #define IXGBE_MAX_VF_MC_ENTRIES 30 131 #define IXGBE_MAX_VF_FUNCTIONS 64 132 #define IXGBE_MAX_VFTA_ENTRIES 128 133 #define MAX_EMULATION_MAC_ADDRS 16 134 #define IXGBE_MAX_PF_MACVLANS 15 135 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) 136 #define IXGBE_82599_VF_DEVICE_ID 0x10ED 137 #define IXGBE_X540_VF_DEVICE_ID 0x1515 138 139 struct vf_data_storage { 140 unsigned char vf_mac_addresses[ETH_ALEN]; 141 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 142 u16 num_vf_mc_hashes; 143 u16 default_vf_vlan_id; 144 u16 vlans_enabled; 145 bool clear_to_send; 146 bool pf_set_mac; 147 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 148 u16 pf_qos; 149 u16 tx_rate; 150 u16 vlan_count; 151 u8 spoofchk_enabled; 152 unsigned int vf_api; 153 }; 154 155 struct vf_macvlans { 156 struct list_head l; 157 int vf; 158 bool free; 159 bool is_macvlan; 160 u8 vf_macvlan[ETH_ALEN]; 161 }; 162 163 #define IXGBE_MAX_TXD_PWR 14 164 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) 165 166 /* Tx Descriptors needed, worst case */ 167 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 168 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 169 170 /* wrapper around a pointer to a socket buffer, 171 * so a DMA handle can be stored along with the buffer */ 172 struct ixgbe_tx_buffer { 173 union ixgbe_adv_tx_desc *next_to_watch; 174 unsigned long time_stamp; 175 struct sk_buff *skb; 176 unsigned int bytecount; 177 unsigned short gso_segs; 178 __be16 protocol; 179 DEFINE_DMA_UNMAP_ADDR(dma); 180 DEFINE_DMA_UNMAP_LEN(len); 181 u32 tx_flags; 182 }; 183 184 struct ixgbe_rx_buffer { 185 struct sk_buff *skb; 186 dma_addr_t dma; 187 struct page *page; 188 unsigned int page_offset; 189 }; 190 191 struct ixgbe_queue_stats { 192 u64 packets; 193 u64 bytes; 194 #ifdef BP_EXTENDED_STATS 195 u64 yields; 196 u64 misses; 197 u64 cleaned; 198 #endif /* BP_EXTENDED_STATS */ 199 }; 200 201 struct ixgbe_tx_queue_stats { 202 u64 restart_queue; 203 u64 tx_busy; 204 u64 tx_done_old; 205 }; 206 207 struct ixgbe_rx_queue_stats { 208 u64 rsc_count; 209 u64 rsc_flush; 210 u64 non_eop_descs; 211 u64 alloc_rx_page_failed; 212 u64 alloc_rx_buff_failed; 213 u64 csum_err; 214 }; 215 216 enum ixgbe_ring_state_t { 217 __IXGBE_TX_FDIR_INIT_DONE, 218 __IXGBE_TX_XPS_INIT_DONE, 219 __IXGBE_TX_DETECT_HANG, 220 __IXGBE_HANG_CHECK_ARMED, 221 __IXGBE_RX_RSC_ENABLED, 222 __IXGBE_RX_CSUM_UDP_ZERO_ERR, 223 __IXGBE_RX_FCOE, 224 }; 225 226 struct ixgbe_fwd_adapter { 227 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 228 struct net_device *netdev; 229 struct ixgbe_adapter *real_adapter; 230 unsigned int tx_base_queue; 231 unsigned int rx_base_queue; 232 int pool; 233 }; 234 235 #define check_for_tx_hang(ring) \ 236 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 237 #define set_check_for_tx_hang(ring) \ 238 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 239 #define clear_check_for_tx_hang(ring) \ 240 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 241 #define ring_is_rsc_enabled(ring) \ 242 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 243 #define set_ring_rsc_enabled(ring) \ 244 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 245 #define clear_ring_rsc_enabled(ring) \ 246 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 247 struct ixgbe_ring { 248 struct ixgbe_ring *next; /* pointer to next ring in q_vector */ 249 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ 250 struct net_device *netdev; /* netdev ring belongs to */ 251 struct device *dev; /* device for DMA mapping */ 252 struct ixgbe_fwd_adapter *l2_accel_priv; 253 void *desc; /* descriptor ring memory */ 254 union { 255 struct ixgbe_tx_buffer *tx_buffer_info; 256 struct ixgbe_rx_buffer *rx_buffer_info; 257 }; 258 unsigned long state; 259 u8 __iomem *tail; 260 dma_addr_t dma; /* phys. address of descriptor ring */ 261 unsigned int size; /* length in bytes */ 262 263 u16 count; /* amount of descriptors */ 264 265 u8 queue_index; /* needed for multiqueue queue management */ 266 u8 reg_idx; /* holds the special value that gets 267 * the hardware register offset 268 * associated with this ring, which is 269 * different for DCB and RSS modes 270 */ 271 u16 next_to_use; 272 u16 next_to_clean; 273 274 union { 275 u16 next_to_alloc; 276 struct { 277 u8 atr_sample_rate; 278 u8 atr_count; 279 }; 280 }; 281 282 u8 dcb_tc; 283 struct ixgbe_queue_stats stats; 284 struct u64_stats_sync syncp; 285 union { 286 struct ixgbe_tx_queue_stats tx_stats; 287 struct ixgbe_rx_queue_stats rx_stats; 288 }; 289 } ____cacheline_internodealigned_in_smp; 290 291 enum ixgbe_ring_f_enum { 292 RING_F_NONE = 0, 293 RING_F_VMDQ, /* SR-IOV uses the same ring feature */ 294 RING_F_RSS, 295 RING_F_FDIR, 296 #ifdef IXGBE_FCOE 297 RING_F_FCOE, 298 #endif /* IXGBE_FCOE */ 299 300 RING_F_ARRAY_SIZE /* must be last in enum set */ 301 }; 302 303 #define IXGBE_MAX_RSS_INDICES 16 304 #define IXGBE_MAX_RSS_INDICES_X550 64 305 #define IXGBE_MAX_VMDQ_INDICES 64 306 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ 307 #define IXGBE_MAX_FCOE_INDICES 8 308 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 309 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 310 #define IXGBE_MAX_L2A_QUEUES 4 311 #define IXGBE_BAD_L2A_QUEUE 3 312 #define IXGBE_MAX_MACVLANS 31 313 #define IXGBE_MAX_DCBMACVLANS 8 314 315 struct ixgbe_ring_feature { 316 u16 limit; /* upper limit on feature indices */ 317 u16 indices; /* current value of indices */ 318 u16 mask; /* Mask used for feature to ring mapping */ 319 u16 offset; /* offset to start of feature */ 320 } ____cacheline_internodealigned_in_smp; 321 322 #define IXGBE_82599_VMDQ_8Q_MASK 0x78 323 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C 324 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E 325 326 /* 327 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since 328 * this is twice the size of a half page we need to double the page order 329 * for FCoE enabled Rx queues. 330 */ 331 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) 332 { 333 #ifdef IXGBE_FCOE 334 if (test_bit(__IXGBE_RX_FCOE, &ring->state)) 335 return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K : 336 IXGBE_RXBUFFER_3K; 337 #endif 338 return IXGBE_RXBUFFER_2K; 339 } 340 341 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) 342 { 343 #ifdef IXGBE_FCOE 344 if (test_bit(__IXGBE_RX_FCOE, &ring->state)) 345 return (PAGE_SIZE < 8192) ? 1 : 0; 346 #endif 347 return 0; 348 } 349 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) 350 351 struct ixgbe_ring_container { 352 struct ixgbe_ring *ring; /* pointer to linked list of rings */ 353 unsigned int total_bytes; /* total bytes processed this int */ 354 unsigned int total_packets; /* total packets processed this int */ 355 u16 work_limit; /* total work allowed per interrupt */ 356 u8 count; /* total number of rings in vector */ 357 u8 itr; /* current ITR setting for ring */ 358 }; 359 360 /* iterator for handling rings in ring container */ 361 #define ixgbe_for_each_ring(pos, head) \ 362 for (pos = (head).ring; pos != NULL; pos = pos->next) 363 364 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ 365 ? 8 : 1) 366 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS 367 368 /* MAX_Q_VECTORS of these are allocated, 369 * but we only use one per queue-specific vector. 370 */ 371 struct ixgbe_q_vector { 372 struct ixgbe_adapter *adapter; 373 #ifdef CONFIG_IXGBE_DCA 374 int cpu; /* CPU for DCA */ 375 #endif 376 u16 v_idx; /* index of q_vector within array, also used for 377 * finding the bit in EICR and friends that 378 * represents the vector for this ring */ 379 u16 itr; /* Interrupt throttle rate written to EITR */ 380 struct ixgbe_ring_container rx, tx; 381 382 struct napi_struct napi; 383 cpumask_t affinity_mask; 384 int numa_node; 385 struct rcu_head rcu; /* to avoid race with update stats on free */ 386 char name[IFNAMSIZ + 9]; 387 388 #ifdef CONFIG_NET_RX_BUSY_POLL 389 atomic_t state; 390 #endif /* CONFIG_NET_RX_BUSY_POLL */ 391 392 /* for dynamic allocation of rings associated with this q_vector */ 393 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; 394 }; 395 396 #ifdef CONFIG_NET_RX_BUSY_POLL 397 enum ixgbe_qv_state_t { 398 IXGBE_QV_STATE_IDLE = 0, 399 IXGBE_QV_STATE_NAPI, 400 IXGBE_QV_STATE_POLL, 401 IXGBE_QV_STATE_DISABLE 402 }; 403 404 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) 405 { 406 /* reset state to idle */ 407 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); 408 } 409 410 /* called from the device poll routine to get ownership of a q_vector */ 411 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) 412 { 413 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, 414 IXGBE_QV_STATE_NAPI); 415 #ifdef BP_EXTENDED_STATS 416 if (rc != IXGBE_QV_STATE_IDLE) 417 q_vector->tx.ring->stats.yields++; 418 #endif 419 420 return rc == IXGBE_QV_STATE_IDLE; 421 } 422 423 /* returns true is someone tried to get the qv while napi had it */ 424 static inline void ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) 425 { 426 WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_NAPI); 427 428 /* flush any outstanding Rx frames */ 429 if (q_vector->napi.gro_list) 430 napi_gro_flush(&q_vector->napi, false); 431 432 /* reset state to idle */ 433 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); 434 } 435 436 /* called from ixgbe_low_latency_poll() */ 437 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) 438 { 439 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, 440 IXGBE_QV_STATE_POLL); 441 #ifdef BP_EXTENDED_STATS 442 if (rc != IXGBE_QV_STATE_IDLE) 443 q_vector->tx.ring->stats.yields++; 444 #endif 445 return rc == IXGBE_QV_STATE_IDLE; 446 } 447 448 /* returns true if someone tried to get the qv while it was locked */ 449 static inline void ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) 450 { 451 WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_POLL); 452 453 /* reset state to idle */ 454 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); 455 } 456 457 /* true if a socket is polling, even if it did not get the lock */ 458 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) 459 { 460 return atomic_read(&q_vector->state) == IXGBE_QV_STATE_POLL; 461 } 462 463 /* false if QV is currently owned */ 464 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) 465 { 466 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, 467 IXGBE_QV_STATE_DISABLE); 468 469 return rc == IXGBE_QV_STATE_IDLE; 470 } 471 472 #else /* CONFIG_NET_RX_BUSY_POLL */ 473 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) 474 { 475 } 476 477 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) 478 { 479 return true; 480 } 481 482 static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) 483 { 484 return false; 485 } 486 487 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) 488 { 489 return false; 490 } 491 492 static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) 493 { 494 return false; 495 } 496 497 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) 498 { 499 return false; 500 } 501 502 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) 503 { 504 return true; 505 } 506 507 #endif /* CONFIG_NET_RX_BUSY_POLL */ 508 509 #ifdef CONFIG_IXGBE_HWMON 510 511 #define IXGBE_HWMON_TYPE_LOC 0 512 #define IXGBE_HWMON_TYPE_TEMP 1 513 #define IXGBE_HWMON_TYPE_CAUTION 2 514 #define IXGBE_HWMON_TYPE_MAX 3 515 516 struct hwmon_attr { 517 struct device_attribute dev_attr; 518 struct ixgbe_hw *hw; 519 struct ixgbe_thermal_diode_data *sensor; 520 char name[12]; 521 }; 522 523 struct hwmon_buff { 524 struct attribute_group group; 525 const struct attribute_group *groups[2]; 526 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; 527 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; 528 unsigned int n_hwmon; 529 }; 530 #endif /* CONFIG_IXGBE_HWMON */ 531 532 /* 533 * microsecond values for various ITR rates shifted by 2 to fit itr register 534 * with the first 3 bits reserved 0 535 */ 536 #define IXGBE_MIN_RSC_ITR 24 537 #define IXGBE_100K_ITR 40 538 #define IXGBE_20K_ITR 200 539 #define IXGBE_10K_ITR 400 540 #define IXGBE_8K_ITR 500 541 542 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ 543 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, 544 const u32 stat_err_bits) 545 { 546 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 547 } 548 549 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) 550 { 551 u16 ntc = ring->next_to_clean; 552 u16 ntu = ring->next_to_use; 553 554 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 555 } 556 557 #define IXGBE_RX_DESC(R, i) \ 558 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 559 #define IXGBE_TX_DESC(R, i) \ 560 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 561 #define IXGBE_TX_CTXTDESC(R, i) \ 562 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 563 564 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ 565 #ifdef IXGBE_FCOE 566 /* Use 3K as the baby jumbo frame size for FCoE */ 567 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 568 #endif /* IXGBE_FCOE */ 569 570 #define OTHER_VECTOR 1 571 #define NON_Q_VECTORS (OTHER_VECTOR) 572 573 #define MAX_MSIX_VECTORS_82599 64 574 #define MAX_Q_VECTORS_82599 64 575 #define MAX_MSIX_VECTORS_82598 18 576 #define MAX_Q_VECTORS_82598 16 577 578 struct ixgbe_mac_addr { 579 u8 addr[ETH_ALEN]; 580 u16 queue; 581 u16 state; /* bitmask */ 582 }; 583 #define IXGBE_MAC_STATE_DEFAULT 0x1 584 #define IXGBE_MAC_STATE_MODIFIED 0x2 585 #define IXGBE_MAC_STATE_IN_USE 0x4 586 587 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 588 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 589 590 #define MIN_MSIX_Q_VECTORS 1 591 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 592 593 /* default to trying for four seconds */ 594 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 595 596 /* board specific private data structure */ 597 struct ixgbe_adapter { 598 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 599 /* OS defined structs */ 600 struct net_device *netdev; 601 struct pci_dev *pdev; 602 603 unsigned long state; 604 605 /* Some features need tri-state capability, 606 * thus the additional *_CAPABLE flags. 607 */ 608 u32 flags; 609 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1) 610 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3) 611 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4) 612 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5) 613 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6) 614 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 7) 615 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8) 616 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9) 617 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10) 618 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11) 619 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12) 620 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13) 621 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14) 622 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15) 623 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16) 624 #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17) 625 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18) 626 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19) 627 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20) 628 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21) 629 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22) 630 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23) 631 632 u32 flags2; 633 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0) 634 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) 635 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) 636 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3) 637 #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4) 638 #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5) 639 #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6) 640 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7) 641 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8) 642 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9) 643 #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10) 644 #define IXGBE_FLAG2_BRIDGE_MODE_VEB (u32)(1 << 11) 645 646 /* Tx fast path data */ 647 int num_tx_queues; 648 u16 tx_itr_setting; 649 u16 tx_work_limit; 650 651 /* Rx fast path data */ 652 int num_rx_queues; 653 u16 rx_itr_setting; 654 655 /* TX */ 656 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; 657 658 u64 restart_queue; 659 u64 lsc_int; 660 u32 tx_timeout_count; 661 662 /* RX */ 663 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; 664 int num_rx_pools; /* == num_rx_queues in 82598 */ 665 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ 666 u64 hw_csum_rx_error; 667 u64 hw_rx_no_dma_resources; 668 u64 rsc_total_count; 669 u64 rsc_total_flush; 670 u64 non_eop_descs; 671 u32 alloc_rx_page_failed; 672 u32 alloc_rx_buff_failed; 673 674 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; 675 676 /* DCB parameters */ 677 struct ieee_pfc *ixgbe_ieee_pfc; 678 struct ieee_ets *ixgbe_ieee_ets; 679 struct ixgbe_dcb_config dcb_cfg; 680 struct ixgbe_dcb_config temp_dcb_cfg; 681 u8 dcb_set_bitmap; 682 u8 dcbx_cap; 683 enum ixgbe_fc_mode last_lfc_mode; 684 685 int num_q_vectors; /* current number of q_vectors for device */ 686 int max_q_vectors; /* true count of q_vectors for device */ 687 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; 688 struct msix_entry *msix_entries; 689 690 u32 test_icr; 691 struct ixgbe_ring test_tx_ring; 692 struct ixgbe_ring test_rx_ring; 693 694 /* structs defined in ixgbe_hw.h */ 695 struct ixgbe_hw hw; 696 u16 msg_enable; 697 struct ixgbe_hw_stats stats; 698 699 u64 tx_busy; 700 unsigned int tx_ring_count; 701 unsigned int rx_ring_count; 702 703 u32 link_speed; 704 bool link_up; 705 unsigned long link_check_timeout; 706 707 struct timer_list service_timer; 708 struct work_struct service_task; 709 710 struct hlist_head fdir_filter_list; 711 unsigned long fdir_overflow; /* number of times ATR was backed off */ 712 union ixgbe_atr_input fdir_mask; 713 int fdir_filter_count; 714 u32 fdir_pballoc; 715 u32 atr_sample_rate; 716 spinlock_t fdir_perfect_lock; 717 718 #ifdef IXGBE_FCOE 719 struct ixgbe_fcoe fcoe; 720 #endif /* IXGBE_FCOE */ 721 u8 __iomem *io_addr; /* Mainly for iounmap use */ 722 u32 wol; 723 724 u16 eeprom_verh; 725 u16 eeprom_verl; 726 u16 eeprom_cap; 727 728 u32 interrupt_event; 729 u32 led_reg; 730 731 struct ptp_clock *ptp_clock; 732 struct ptp_clock_info ptp_caps; 733 struct work_struct ptp_tx_work; 734 struct sk_buff *ptp_tx_skb; 735 struct hwtstamp_config tstamp_config; 736 unsigned long ptp_tx_start; 737 unsigned long last_overflow_check; 738 unsigned long last_rx_ptp_check; 739 unsigned long last_rx_timestamp; 740 spinlock_t tmreg_lock; 741 struct cyclecounter cc; 742 struct timecounter tc; 743 u32 base_incval; 744 745 /* SR-IOV */ 746 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 747 unsigned int num_vfs; 748 struct vf_data_storage *vfinfo; 749 int vf_rate_link_speed; 750 struct vf_macvlans vf_mvs; 751 struct vf_macvlans *mv_list; 752 753 u32 timer_event_accumulator; 754 u32 vferr_refcount; 755 struct ixgbe_mac_addr *mac_table; 756 struct kobject *info_kobj; 757 #ifdef CONFIG_IXGBE_HWMON 758 struct hwmon_buff *ixgbe_hwmon_buff; 759 #endif /* CONFIG_IXGBE_HWMON */ 760 #ifdef CONFIG_DEBUG_FS 761 struct dentry *ixgbe_dbg_adapter; 762 #endif /*CONFIG_DEBUG_FS*/ 763 764 u8 default_up; 765 unsigned long fwd_bitmask; /* Bitmask indicating in use pools */ 766 }; 767 768 static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter) 769 { 770 switch (adapter->hw.mac.type) { 771 case ixgbe_mac_82598EB: 772 case ixgbe_mac_82599EB: 773 case ixgbe_mac_X540: 774 return IXGBE_MAX_RSS_INDICES; 775 case ixgbe_mac_X550: 776 case ixgbe_mac_X550EM_x: 777 return IXGBE_MAX_RSS_INDICES_X550; 778 default: 779 return 0; 780 } 781 } 782 783 struct ixgbe_fdir_filter { 784 struct hlist_node fdir_node; 785 union ixgbe_atr_input filter; 786 u16 sw_idx; 787 u16 action; 788 }; 789 790 enum ixgbe_state_t { 791 __IXGBE_TESTING, 792 __IXGBE_RESETTING, 793 __IXGBE_DOWN, 794 __IXGBE_DISABLED, 795 __IXGBE_REMOVING, 796 __IXGBE_SERVICE_SCHED, 797 __IXGBE_SERVICE_INITED, 798 __IXGBE_IN_SFP_INIT, 799 __IXGBE_PTP_RUNNING, 800 __IXGBE_PTP_TX_IN_PROGRESS, 801 }; 802 803 struct ixgbe_cb { 804 union { /* Union defining head/tail partner */ 805 struct sk_buff *head; 806 struct sk_buff *tail; 807 }; 808 dma_addr_t dma; 809 u16 append_cnt; 810 bool page_released; 811 }; 812 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) 813 814 enum ixgbe_boards { 815 board_82598, 816 board_82599, 817 board_X540, 818 board_X550, 819 board_X550EM_x, 820 }; 821 822 extern struct ixgbe_info ixgbe_82598_info; 823 extern struct ixgbe_info ixgbe_82599_info; 824 extern struct ixgbe_info ixgbe_X540_info; 825 extern struct ixgbe_info ixgbe_X550_info; 826 extern struct ixgbe_info ixgbe_X550EM_x_info; 827 #ifdef CONFIG_IXGBE_DCB 828 extern const struct dcbnl_rtnl_ops dcbnl_ops; 829 #endif 830 831 extern char ixgbe_driver_name[]; 832 extern const char ixgbe_driver_version[]; 833 #ifdef IXGBE_FCOE 834 extern char ixgbe_default_device_descr[]; 835 #endif /* IXGBE_FCOE */ 836 837 void ixgbe_up(struct ixgbe_adapter *adapter); 838 void ixgbe_down(struct ixgbe_adapter *adapter); 839 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); 840 void ixgbe_reset(struct ixgbe_adapter *adapter); 841 void ixgbe_set_ethtool_ops(struct net_device *netdev); 842 int ixgbe_setup_rx_resources(struct ixgbe_ring *); 843 int ixgbe_setup_tx_resources(struct ixgbe_ring *); 844 void ixgbe_free_rx_resources(struct ixgbe_ring *); 845 void ixgbe_free_tx_resources(struct ixgbe_ring *); 846 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 847 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 848 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *); 849 void ixgbe_update_stats(struct ixgbe_adapter *adapter); 850 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); 851 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 852 u16 subdevice_id); 853 #ifdef CONFIG_PCI_IOV 854 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter); 855 #endif 856 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 857 u8 *addr, u16 queue); 858 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 859 u8 *addr, u16 queue); 860 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); 861 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, 862 struct ixgbe_ring *); 863 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, 864 struct ixgbe_tx_buffer *); 865 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); 866 void ixgbe_write_eitr(struct ixgbe_q_vector *); 867 int ixgbe_poll(struct napi_struct *napi, int budget); 868 int ethtool_ioctl(struct ifreq *ifr); 869 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 870 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); 871 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); 872 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 873 union ixgbe_atr_hash_dword input, 874 union ixgbe_atr_hash_dword common, 875 u8 queue); 876 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 877 union ixgbe_atr_input *input_mask); 878 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 879 union ixgbe_atr_input *input, 880 u16 soft_id, u8 queue); 881 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 882 union ixgbe_atr_input *input, 883 u16 soft_id); 884 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 885 union ixgbe_atr_input *mask); 886 void ixgbe_set_rx_mode(struct net_device *netdev); 887 #ifdef CONFIG_IXGBE_DCB 888 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); 889 #endif 890 int ixgbe_setup_tc(struct net_device *dev, u8 tc); 891 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); 892 void ixgbe_do_reset(struct net_device *netdev); 893 #ifdef CONFIG_IXGBE_HWMON 894 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); 895 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); 896 #endif /* CONFIG_IXGBE_HWMON */ 897 #ifdef IXGBE_FCOE 898 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 899 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 900 u8 *hdr_len); 901 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, 902 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); 903 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, 904 struct scatterlist *sgl, unsigned int sgc); 905 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, 906 struct scatterlist *sgl, unsigned int sgc); 907 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); 908 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 909 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 910 int ixgbe_fcoe_enable(struct net_device *netdev); 911 int ixgbe_fcoe_disable(struct net_device *netdev); 912 #ifdef CONFIG_IXGBE_DCB 913 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); 914 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); 915 #endif /* CONFIG_IXGBE_DCB */ 916 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); 917 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, 918 struct netdev_fcoe_hbainfo *info); 919 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); 920 #endif /* IXGBE_FCOE */ 921 #ifdef CONFIG_DEBUG_FS 922 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); 923 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); 924 void ixgbe_dbg_init(void); 925 void ixgbe_dbg_exit(void); 926 #else 927 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} 928 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} 929 static inline void ixgbe_dbg_init(void) {} 930 static inline void ixgbe_dbg_exit(void) {} 931 #endif /* CONFIG_DEBUG_FS */ 932 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) 933 { 934 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 935 } 936 937 void ixgbe_ptp_init(struct ixgbe_adapter *adapter); 938 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter); 939 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); 940 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); 941 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); 942 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_adapter *adapter, struct sk_buff *skb); 943 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 944 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 945 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); 946 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); 947 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr); 948 #ifdef CONFIG_PCI_IOV 949 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); 950 #endif 951 952 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 953 struct ixgbe_adapter *adapter, 954 struct ixgbe_ring *tx_ring); 955 #endif /* _IXGBE_H_ */ 956