1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #ifndef _IXGBE_H_ 5 #define _IXGBE_H_ 6 7 #include <linux/bitops.h> 8 #include <linux/types.h> 9 #include <linux/pci.h> 10 #include <linux/netdevice.h> 11 #include <linux/cpumask.h> 12 #include <linux/aer.h> 13 #include <linux/if_vlan.h> 14 #include <linux/jiffies.h> 15 #include <linux/phy.h> 16 17 #include <linux/timecounter.h> 18 #include <linux/net_tstamp.h> 19 #include <linux/ptp_clock_kernel.h> 20 21 #include "ixgbe_type.h" 22 #include "ixgbe_common.h" 23 #include "ixgbe_dcb.h" 24 #if IS_ENABLED(CONFIG_FCOE) 25 #define IXGBE_FCOE 26 #include "ixgbe_fcoe.h" 27 #endif /* IS_ENABLED(CONFIG_FCOE) */ 28 #ifdef CONFIG_IXGBE_DCA 29 #include <linux/dca.h> 30 #endif 31 #include "ixgbe_ipsec.h" 32 33 #include <net/xdp.h> 34 35 /* common prefix used by pr_<> macros */ 36 #undef pr_fmt 37 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 38 39 /* TX/RX descriptor defines */ 40 #define IXGBE_DEFAULT_TXD 512 41 #define IXGBE_DEFAULT_TX_WORK 256 42 #define IXGBE_MAX_TXD 4096 43 #define IXGBE_MIN_TXD 64 44 45 #if (PAGE_SIZE < 8192) 46 #define IXGBE_DEFAULT_RXD 512 47 #else 48 #define IXGBE_DEFAULT_RXD 128 49 #endif 50 #define IXGBE_MAX_RXD 4096 51 #define IXGBE_MIN_RXD 64 52 53 /* flow control */ 54 #define IXGBE_MIN_FCRTL 0x40 55 #define IXGBE_MAX_FCRTL 0x7FF80 56 #define IXGBE_MIN_FCRTH 0x600 57 #define IXGBE_MAX_FCRTH 0x7FFF0 58 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF 59 #define IXGBE_MIN_FCPAUSE 0 60 #define IXGBE_MAX_FCPAUSE 0xFFFF 61 62 /* Supported Rx Buffer Sizes */ 63 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ 64 #define IXGBE_RXBUFFER_1536 1536 65 #define IXGBE_RXBUFFER_2K 2048 66 #define IXGBE_RXBUFFER_3K 3072 67 #define IXGBE_RXBUFFER_4K 4096 68 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 69 70 /* Attempt to maximize the headroom available for incoming frames. We 71 * use a 2K buffer for receives and need 1536/1534 to store the data for 72 * the frame. This leaves us with 512 bytes of room. From that we need 73 * to deduct the space needed for the shared info and the padding needed 74 * to IP align the frame. 75 * 76 * Note: For cache line sizes 256 or larger this value is going to end 77 * up negative. In these cases we should fall back to the 3K 78 * buffers. 79 */ 80 #if (PAGE_SIZE < 8192) 81 #define IXGBE_MAX_2K_FRAME_BUILD_SKB (IXGBE_RXBUFFER_1536 - NET_IP_ALIGN) 82 #define IXGBE_2K_TOO_SMALL_WITH_PADDING \ 83 ((NET_SKB_PAD + IXGBE_RXBUFFER_1536) > SKB_WITH_OVERHEAD(IXGBE_RXBUFFER_2K)) 84 85 static inline int ixgbe_compute_pad(int rx_buf_len) 86 { 87 int page_size, pad_size; 88 89 page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2); 90 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len; 91 92 return pad_size; 93 } 94 95 static inline int ixgbe_skb_pad(void) 96 { 97 int rx_buf_len; 98 99 /* If a 2K buffer cannot handle a standard Ethernet frame then 100 * optimize padding for a 3K buffer instead of a 1.5K buffer. 101 * 102 * For a 3K buffer we need to add enough padding to allow for 103 * tailroom due to NET_IP_ALIGN possibly shifting us out of 104 * cache-line alignment. 105 */ 106 if (IXGBE_2K_TOO_SMALL_WITH_PADDING) 107 rx_buf_len = IXGBE_RXBUFFER_3K + SKB_DATA_ALIGN(NET_IP_ALIGN); 108 else 109 rx_buf_len = IXGBE_RXBUFFER_1536; 110 111 /* if needed make room for NET_IP_ALIGN */ 112 rx_buf_len -= NET_IP_ALIGN; 113 114 return ixgbe_compute_pad(rx_buf_len); 115 } 116 117 #define IXGBE_SKB_PAD ixgbe_skb_pad() 118 #else 119 #define IXGBE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 120 #endif 121 122 /* 123 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 124 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, 125 * this adds up to 448 bytes of extra data. 126 * 127 * Since netdev_alloc_skb now allocates a page fragment we can use a value 128 * of 256 and the resultant skb will have a truesize of 960 or less. 129 */ 130 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 131 132 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 133 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 134 135 #define IXGBE_RX_DMA_ATTR \ 136 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 137 138 enum ixgbe_tx_flags { 139 /* cmd_type flags */ 140 IXGBE_TX_FLAGS_HW_VLAN = 0x01, 141 IXGBE_TX_FLAGS_TSO = 0x02, 142 IXGBE_TX_FLAGS_TSTAMP = 0x04, 143 144 /* olinfo flags */ 145 IXGBE_TX_FLAGS_CC = 0x08, 146 IXGBE_TX_FLAGS_IPV4 = 0x10, 147 IXGBE_TX_FLAGS_CSUM = 0x20, 148 IXGBE_TX_FLAGS_IPSEC = 0x40, 149 150 /* software defined flags */ 151 IXGBE_TX_FLAGS_SW_VLAN = 0x80, 152 IXGBE_TX_FLAGS_FCOE = 0x100, 153 }; 154 155 /* VLAN info */ 156 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 157 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 158 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 159 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 160 161 #define IXGBE_MAX_VF_MC_ENTRIES 30 162 #define IXGBE_MAX_VF_FUNCTIONS 64 163 #define IXGBE_MAX_VFTA_ENTRIES 128 164 #define MAX_EMULATION_MAC_ADDRS 16 165 #define IXGBE_MAX_PF_MACVLANS 15 166 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) 167 #define IXGBE_82599_VF_DEVICE_ID 0x10ED 168 #define IXGBE_X540_VF_DEVICE_ID 0x1515 169 170 struct vf_data_storage { 171 struct pci_dev *vfdev; 172 unsigned char vf_mac_addresses[ETH_ALEN]; 173 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 174 u16 num_vf_mc_hashes; 175 bool clear_to_send; 176 bool pf_set_mac; 177 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 178 u16 pf_qos; 179 u16 tx_rate; 180 u8 spoofchk_enabled; 181 bool rss_query_enabled; 182 u8 trusted; 183 int xcast_mode; 184 unsigned int vf_api; 185 }; 186 187 enum ixgbevf_xcast_modes { 188 IXGBEVF_XCAST_MODE_NONE = 0, 189 IXGBEVF_XCAST_MODE_MULTI, 190 IXGBEVF_XCAST_MODE_ALLMULTI, 191 IXGBEVF_XCAST_MODE_PROMISC, 192 }; 193 194 struct vf_macvlans { 195 struct list_head l; 196 int vf; 197 bool free; 198 bool is_macvlan; 199 u8 vf_macvlan[ETH_ALEN]; 200 }; 201 202 #define IXGBE_MAX_TXD_PWR 14 203 #define IXGBE_MAX_DATA_PER_TXD (1u << IXGBE_MAX_TXD_PWR) 204 205 /* Tx Descriptors needed, worst case */ 206 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 207 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 208 209 /* wrapper around a pointer to a socket buffer, 210 * so a DMA handle can be stored along with the buffer */ 211 struct ixgbe_tx_buffer { 212 union ixgbe_adv_tx_desc *next_to_watch; 213 unsigned long time_stamp; 214 union { 215 struct sk_buff *skb; 216 struct xdp_frame *xdpf; 217 }; 218 unsigned int bytecount; 219 unsigned short gso_segs; 220 __be16 protocol; 221 DEFINE_DMA_UNMAP_ADDR(dma); 222 DEFINE_DMA_UNMAP_LEN(len); 223 u32 tx_flags; 224 }; 225 226 struct ixgbe_rx_buffer { 227 union { 228 struct { 229 struct sk_buff *skb; 230 dma_addr_t dma; 231 struct page *page; 232 __u32 page_offset; 233 __u16 pagecnt_bias; 234 }; 235 struct { 236 bool discard; 237 struct xdp_buff *xdp; 238 }; 239 }; 240 }; 241 242 struct ixgbe_queue_stats { 243 u64 packets; 244 u64 bytes; 245 }; 246 247 struct ixgbe_tx_queue_stats { 248 u64 restart_queue; 249 u64 tx_busy; 250 u64 tx_done_old; 251 }; 252 253 struct ixgbe_rx_queue_stats { 254 u64 rsc_count; 255 u64 rsc_flush; 256 u64 non_eop_descs; 257 u64 alloc_rx_page; 258 u64 alloc_rx_page_failed; 259 u64 alloc_rx_buff_failed; 260 u64 csum_err; 261 }; 262 263 #define IXGBE_TS_HDR_LEN 8 264 265 enum ixgbe_ring_state_t { 266 __IXGBE_RX_3K_BUFFER, 267 __IXGBE_RX_BUILD_SKB_ENABLED, 268 __IXGBE_RX_RSC_ENABLED, 269 __IXGBE_RX_CSUM_UDP_ZERO_ERR, 270 __IXGBE_RX_FCOE, 271 __IXGBE_TX_FDIR_INIT_DONE, 272 __IXGBE_TX_XPS_INIT_DONE, 273 __IXGBE_TX_DETECT_HANG, 274 __IXGBE_HANG_CHECK_ARMED, 275 __IXGBE_TX_XDP_RING, 276 __IXGBE_TX_DISABLED, 277 }; 278 279 #define ring_uses_build_skb(ring) \ 280 test_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &(ring)->state) 281 282 struct ixgbe_fwd_adapter { 283 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 284 struct net_device *netdev; 285 unsigned int tx_base_queue; 286 unsigned int rx_base_queue; 287 int pool; 288 }; 289 290 #define check_for_tx_hang(ring) \ 291 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 292 #define set_check_for_tx_hang(ring) \ 293 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 294 #define clear_check_for_tx_hang(ring) \ 295 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 296 #define ring_is_rsc_enabled(ring) \ 297 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 298 #define set_ring_rsc_enabled(ring) \ 299 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 300 #define clear_ring_rsc_enabled(ring) \ 301 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 302 #define ring_is_xdp(ring) \ 303 test_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 304 #define set_ring_xdp(ring) \ 305 set_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 306 #define clear_ring_xdp(ring) \ 307 clear_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 308 struct ixgbe_ring { 309 struct ixgbe_ring *next; /* pointer to next ring in q_vector */ 310 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ 311 struct net_device *netdev; /* netdev ring belongs to */ 312 struct bpf_prog *xdp_prog; 313 struct device *dev; /* device for DMA mapping */ 314 void *desc; /* descriptor ring memory */ 315 union { 316 struct ixgbe_tx_buffer *tx_buffer_info; 317 struct ixgbe_rx_buffer *rx_buffer_info; 318 }; 319 unsigned long state; 320 u8 __iomem *tail; 321 dma_addr_t dma; /* phys. address of descriptor ring */ 322 unsigned int size; /* length in bytes */ 323 324 u16 count; /* amount of descriptors */ 325 326 u8 queue_index; /* needed for multiqueue queue management */ 327 u8 reg_idx; /* holds the special value that gets 328 * the hardware register offset 329 * associated with this ring, which is 330 * different for DCB and RSS modes 331 */ 332 u16 next_to_use; 333 u16 next_to_clean; 334 335 unsigned long last_rx_timestamp; 336 337 union { 338 u16 next_to_alloc; 339 struct { 340 u8 atr_sample_rate; 341 u8 atr_count; 342 }; 343 }; 344 345 u8 dcb_tc; 346 struct ixgbe_queue_stats stats; 347 struct u64_stats_sync syncp; 348 union { 349 struct ixgbe_tx_queue_stats tx_stats; 350 struct ixgbe_rx_queue_stats rx_stats; 351 }; 352 u16 rx_offset; 353 struct xdp_rxq_info xdp_rxq; 354 spinlock_t tx_lock; /* used in XDP mode */ 355 struct xsk_buff_pool *xsk_pool; 356 u16 ring_idx; /* {rx,tx,xdp}_ring back reference idx */ 357 u16 rx_buf_len; 358 } ____cacheline_internodealigned_in_smp; 359 360 enum ixgbe_ring_f_enum { 361 RING_F_NONE = 0, 362 RING_F_VMDQ, /* SR-IOV uses the same ring feature */ 363 RING_F_RSS, 364 RING_F_FDIR, 365 #ifdef IXGBE_FCOE 366 RING_F_FCOE, 367 #endif /* IXGBE_FCOE */ 368 369 RING_F_ARRAY_SIZE /* must be last in enum set */ 370 }; 371 372 #define IXGBE_MAX_RSS_INDICES 16 373 #define IXGBE_MAX_RSS_INDICES_X550 63 374 #define IXGBE_MAX_VMDQ_INDICES 64 375 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ 376 #define IXGBE_MAX_FCOE_INDICES 8 377 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 378 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 379 #define IXGBE_MAX_XDP_QS (IXGBE_MAX_FDIR_INDICES + 1) 380 #define IXGBE_MAX_L2A_QUEUES 4 381 #define IXGBE_BAD_L2A_QUEUE 3 382 #define IXGBE_MAX_MACVLANS 63 383 384 DECLARE_STATIC_KEY_FALSE(ixgbe_xdp_locking_key); 385 386 struct ixgbe_ring_feature { 387 u16 limit; /* upper limit on feature indices */ 388 u16 indices; /* current value of indices */ 389 u16 mask; /* Mask used for feature to ring mapping */ 390 u16 offset; /* offset to start of feature */ 391 } ____cacheline_internodealigned_in_smp; 392 393 #define IXGBE_82599_VMDQ_8Q_MASK 0x78 394 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C 395 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E 396 397 /* 398 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since 399 * this is twice the size of a half page we need to double the page order 400 * for FCoE enabled Rx queues. 401 */ 402 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) 403 { 404 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 405 return IXGBE_RXBUFFER_3K; 406 #if (PAGE_SIZE < 8192) 407 if (ring_uses_build_skb(ring)) 408 return IXGBE_MAX_2K_FRAME_BUILD_SKB; 409 #endif 410 return IXGBE_RXBUFFER_2K; 411 } 412 413 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) 414 { 415 #if (PAGE_SIZE < 8192) 416 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 417 return 1; 418 #endif 419 return 0; 420 } 421 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) 422 423 #define IXGBE_ITR_ADAPTIVE_MIN_INC 2 424 #define IXGBE_ITR_ADAPTIVE_MIN_USECS 10 425 #define IXGBE_ITR_ADAPTIVE_MAX_USECS 126 426 #define IXGBE_ITR_ADAPTIVE_LATENCY 0x80 427 #define IXGBE_ITR_ADAPTIVE_BULK 0x00 428 429 struct ixgbe_ring_container { 430 struct ixgbe_ring *ring; /* pointer to linked list of rings */ 431 unsigned long next_update; /* jiffies value of last update */ 432 unsigned int total_bytes; /* total bytes processed this int */ 433 unsigned int total_packets; /* total packets processed this int */ 434 u16 work_limit; /* total work allowed per interrupt */ 435 u8 count; /* total number of rings in vector */ 436 u8 itr; /* current ITR setting for ring */ 437 }; 438 439 /* iterator for handling rings in ring container */ 440 #define ixgbe_for_each_ring(pos, head) \ 441 for (pos = (head).ring; pos != NULL; pos = pos->next) 442 443 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ 444 ? 8 : 1) 445 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS 446 447 /* MAX_Q_VECTORS of these are allocated, 448 * but we only use one per queue-specific vector. 449 */ 450 struct ixgbe_q_vector { 451 struct ixgbe_adapter *adapter; 452 #ifdef CONFIG_IXGBE_DCA 453 int cpu; /* CPU for DCA */ 454 #endif 455 u16 v_idx; /* index of q_vector within array, also used for 456 * finding the bit in EICR and friends that 457 * represents the vector for this ring */ 458 u16 itr; /* Interrupt throttle rate written to EITR */ 459 struct ixgbe_ring_container rx, tx; 460 461 struct napi_struct napi; 462 cpumask_t affinity_mask; 463 int numa_node; 464 struct rcu_head rcu; /* to avoid race with update stats on free */ 465 char name[IFNAMSIZ + 9]; 466 467 /* for dynamic allocation of rings associated with this q_vector */ 468 struct ixgbe_ring ring[] ____cacheline_internodealigned_in_smp; 469 }; 470 471 #ifdef CONFIG_IXGBE_HWMON 472 473 #define IXGBE_HWMON_TYPE_LOC 0 474 #define IXGBE_HWMON_TYPE_TEMP 1 475 #define IXGBE_HWMON_TYPE_CAUTION 2 476 #define IXGBE_HWMON_TYPE_MAX 3 477 478 struct hwmon_attr { 479 struct device_attribute dev_attr; 480 struct ixgbe_hw *hw; 481 struct ixgbe_thermal_diode_data *sensor; 482 char name[12]; 483 }; 484 485 struct hwmon_buff { 486 struct attribute_group group; 487 const struct attribute_group *groups[2]; 488 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; 489 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; 490 unsigned int n_hwmon; 491 }; 492 #endif /* CONFIG_IXGBE_HWMON */ 493 494 /* 495 * microsecond values for various ITR rates shifted by 2 to fit itr register 496 * with the first 3 bits reserved 0 497 */ 498 #define IXGBE_MIN_RSC_ITR 24 499 #define IXGBE_100K_ITR 40 500 #define IXGBE_20K_ITR 200 501 #define IXGBE_12K_ITR 336 502 503 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ 504 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, 505 const u32 stat_err_bits) 506 { 507 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 508 } 509 510 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) 511 { 512 u16 ntc = ring->next_to_clean; 513 u16 ntu = ring->next_to_use; 514 515 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 516 } 517 518 #define IXGBE_RX_DESC(R, i) \ 519 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 520 #define IXGBE_TX_DESC(R, i) \ 521 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 522 #define IXGBE_TX_CTXTDESC(R, i) \ 523 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 524 525 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ 526 #ifdef IXGBE_FCOE 527 /* Use 3K as the baby jumbo frame size for FCoE */ 528 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 529 #endif /* IXGBE_FCOE */ 530 531 #define OTHER_VECTOR 1 532 #define NON_Q_VECTORS (OTHER_VECTOR) 533 534 #define MAX_MSIX_VECTORS_82599 64 535 #define MAX_Q_VECTORS_82599 64 536 #define MAX_MSIX_VECTORS_82598 18 537 #define MAX_Q_VECTORS_82598 16 538 539 struct ixgbe_mac_addr { 540 u8 addr[ETH_ALEN]; 541 u16 pool; 542 u16 state; /* bitmask */ 543 }; 544 545 #define IXGBE_MAC_STATE_DEFAULT 0x1 546 #define IXGBE_MAC_STATE_MODIFIED 0x2 547 #define IXGBE_MAC_STATE_IN_USE 0x4 548 549 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 550 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 551 552 #define MIN_MSIX_Q_VECTORS 1 553 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 554 555 /* default to trying for four seconds */ 556 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 557 #define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */ 558 559 /* board specific private data structure */ 560 struct ixgbe_adapter { 561 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 562 /* OS defined structs */ 563 struct net_device *netdev; 564 struct bpf_prog *xdp_prog; 565 struct pci_dev *pdev; 566 struct mii_bus *mii_bus; 567 568 unsigned long state; 569 570 /* Some features need tri-state capability, 571 * thus the additional *_CAPABLE flags. 572 */ 573 u32 flags; 574 #define IXGBE_FLAG_MSI_ENABLED BIT(1) 575 #define IXGBE_FLAG_MSIX_ENABLED BIT(3) 576 #define IXGBE_FLAG_RX_1BUF_CAPABLE BIT(4) 577 #define IXGBE_FLAG_RX_PS_CAPABLE BIT(5) 578 #define IXGBE_FLAG_RX_PS_ENABLED BIT(6) 579 #define IXGBE_FLAG_DCA_ENABLED BIT(8) 580 #define IXGBE_FLAG_DCA_CAPABLE BIT(9) 581 #define IXGBE_FLAG_IMIR_ENABLED BIT(10) 582 #define IXGBE_FLAG_MQ_CAPABLE BIT(11) 583 #define IXGBE_FLAG_DCB_ENABLED BIT(12) 584 #define IXGBE_FLAG_VMDQ_CAPABLE BIT(13) 585 #define IXGBE_FLAG_VMDQ_ENABLED BIT(14) 586 #define IXGBE_FLAG_FAN_FAIL_CAPABLE BIT(15) 587 #define IXGBE_FLAG_NEED_LINK_UPDATE BIT(16) 588 #define IXGBE_FLAG_NEED_LINK_CONFIG BIT(17) 589 #define IXGBE_FLAG_FDIR_HASH_CAPABLE BIT(18) 590 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE BIT(19) 591 #define IXGBE_FLAG_FCOE_CAPABLE BIT(20) 592 #define IXGBE_FLAG_FCOE_ENABLED BIT(21) 593 #define IXGBE_FLAG_SRIOV_CAPABLE BIT(22) 594 #define IXGBE_FLAG_SRIOV_ENABLED BIT(23) 595 #define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25) 596 #define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26) 597 #define IXGBE_FLAG_DCB_CAPABLE BIT(27) 598 599 u32 flags2; 600 #define IXGBE_FLAG2_RSC_CAPABLE BIT(0) 601 #define IXGBE_FLAG2_RSC_ENABLED BIT(1) 602 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE BIT(2) 603 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT BIT(3) 604 #define IXGBE_FLAG2_SEARCH_FOR_SFP BIT(4) 605 #define IXGBE_FLAG2_SFP_NEEDS_RESET BIT(5) 606 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT BIT(7) 607 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP BIT(8) 608 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP BIT(9) 609 #define IXGBE_FLAG2_PTP_PPS_ENABLED BIT(10) 610 #define IXGBE_FLAG2_PHY_INTERRUPT BIT(11) 611 #define IXGBE_FLAG2_VLAN_PROMISC BIT(13) 612 #define IXGBE_FLAG2_EEE_CAPABLE BIT(14) 613 #define IXGBE_FLAG2_EEE_ENABLED BIT(15) 614 #define IXGBE_FLAG2_RX_LEGACY BIT(16) 615 #define IXGBE_FLAG2_IPSEC_ENABLED BIT(17) 616 #define IXGBE_FLAG2_VF_IPSEC_ENABLED BIT(18) 617 618 /* Tx fast path data */ 619 int num_tx_queues; 620 u16 tx_itr_setting; 621 u16 tx_work_limit; 622 u64 tx_ipsec; 623 624 /* Rx fast path data */ 625 int num_rx_queues; 626 u16 rx_itr_setting; 627 u64 rx_ipsec; 628 629 /* Port number used to identify VXLAN traffic */ 630 __be16 vxlan_port; 631 __be16 geneve_port; 632 633 /* XDP */ 634 int num_xdp_queues; 635 struct ixgbe_ring *xdp_ring[IXGBE_MAX_XDP_QS]; 636 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled rings */ 637 638 /* TX */ 639 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; 640 641 u64 restart_queue; 642 u64 lsc_int; 643 u32 tx_timeout_count; 644 645 /* RX */ 646 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; 647 int num_rx_pools; /* == num_rx_queues in 82598 */ 648 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ 649 u64 hw_csum_rx_error; 650 u64 hw_rx_no_dma_resources; 651 u64 rsc_total_count; 652 u64 rsc_total_flush; 653 u64 non_eop_descs; 654 u32 alloc_rx_page; 655 u32 alloc_rx_page_failed; 656 u32 alloc_rx_buff_failed; 657 658 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; 659 660 /* DCB parameters */ 661 struct ieee_pfc *ixgbe_ieee_pfc; 662 struct ieee_ets *ixgbe_ieee_ets; 663 struct ixgbe_dcb_config dcb_cfg; 664 struct ixgbe_dcb_config temp_dcb_cfg; 665 u8 hw_tcs; 666 u8 dcb_set_bitmap; 667 u8 dcbx_cap; 668 enum ixgbe_fc_mode last_lfc_mode; 669 670 int num_q_vectors; /* current number of q_vectors for device */ 671 int max_q_vectors; /* true count of q_vectors for device */ 672 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; 673 struct msix_entry *msix_entries; 674 675 u32 test_icr; 676 struct ixgbe_ring test_tx_ring; 677 struct ixgbe_ring test_rx_ring; 678 679 /* structs defined in ixgbe_hw.h */ 680 struct ixgbe_hw hw; 681 u16 msg_enable; 682 struct ixgbe_hw_stats stats; 683 684 u64 tx_busy; 685 unsigned int tx_ring_count; 686 unsigned int xdp_ring_count; 687 unsigned int rx_ring_count; 688 689 u32 link_speed; 690 bool link_up; 691 unsigned long sfp_poll_time; 692 unsigned long link_check_timeout; 693 694 struct timer_list service_timer; 695 struct work_struct service_task; 696 697 struct hlist_head fdir_filter_list; 698 unsigned long fdir_overflow; /* number of times ATR was backed off */ 699 union ixgbe_atr_input fdir_mask; 700 int fdir_filter_count; 701 u32 fdir_pballoc; 702 u32 atr_sample_rate; 703 spinlock_t fdir_perfect_lock; 704 705 #ifdef IXGBE_FCOE 706 struct ixgbe_fcoe fcoe; 707 #endif /* IXGBE_FCOE */ 708 u8 __iomem *io_addr; /* Mainly for iounmap use */ 709 u32 wol; 710 711 u16 bridge_mode; 712 713 char eeprom_id[NVM_VER_SIZE]; 714 u16 eeprom_cap; 715 716 u32 interrupt_event; 717 u32 led_reg; 718 719 struct ptp_clock *ptp_clock; 720 struct ptp_clock_info ptp_caps; 721 struct work_struct ptp_tx_work; 722 struct sk_buff *ptp_tx_skb; 723 struct hwtstamp_config tstamp_config; 724 unsigned long ptp_tx_start; 725 unsigned long last_overflow_check; 726 unsigned long last_rx_ptp_check; 727 unsigned long last_rx_timestamp; 728 spinlock_t tmreg_lock; 729 struct cyclecounter hw_cc; 730 struct timecounter hw_tc; 731 u32 base_incval; 732 u32 tx_hwtstamp_timeouts; 733 u32 tx_hwtstamp_skipped; 734 u32 rx_hwtstamp_cleared; 735 void (*ptp_setup_sdp)(struct ixgbe_adapter *); 736 737 /* SR-IOV */ 738 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 739 unsigned int num_vfs; 740 struct vf_data_storage *vfinfo; 741 int vf_rate_link_speed; 742 struct vf_macvlans vf_mvs; 743 struct vf_macvlans *mv_list; 744 745 u32 timer_event_accumulator; 746 u32 vferr_refcount; 747 struct ixgbe_mac_addr *mac_table; 748 struct kobject *info_kobj; 749 #ifdef CONFIG_IXGBE_HWMON 750 struct hwmon_buff *ixgbe_hwmon_buff; 751 #endif /* CONFIG_IXGBE_HWMON */ 752 #ifdef CONFIG_DEBUG_FS 753 struct dentry *ixgbe_dbg_adapter; 754 #endif /*CONFIG_DEBUG_FS*/ 755 756 u8 default_up; 757 /* Bitmask indicating in use pools */ 758 DECLARE_BITMAP(fwd_bitmask, IXGBE_MAX_MACVLANS + 1); 759 760 #define IXGBE_MAX_LINK_HANDLE 10 761 struct ixgbe_jump_table *jump_tables[IXGBE_MAX_LINK_HANDLE]; 762 unsigned long tables; 763 764 /* maximum number of RETA entries among all devices supported by ixgbe 765 * driver: currently it's x550 device in non-SRIOV mode 766 */ 767 #define IXGBE_MAX_RETA_ENTRIES 512 768 u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES]; 769 770 #define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */ 771 u32 *rss_key; 772 773 #ifdef CONFIG_IXGBE_IPSEC 774 struct ixgbe_ipsec *ipsec; 775 #endif /* CONFIG_IXGBE_IPSEC */ 776 }; 777 778 static inline int ixgbe_determine_xdp_q_idx(int cpu) 779 { 780 if (static_key_enabled(&ixgbe_xdp_locking_key)) 781 return cpu % IXGBE_MAX_XDP_QS; 782 else 783 return cpu; 784 } 785 786 static inline 787 struct ixgbe_ring *ixgbe_determine_xdp_ring(struct ixgbe_adapter *adapter) 788 { 789 int index = ixgbe_determine_xdp_q_idx(smp_processor_id()); 790 791 return adapter->xdp_ring[index]; 792 } 793 794 static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter) 795 { 796 switch (adapter->hw.mac.type) { 797 case ixgbe_mac_82598EB: 798 case ixgbe_mac_82599EB: 799 case ixgbe_mac_X540: 800 return IXGBE_MAX_RSS_INDICES; 801 case ixgbe_mac_X550: 802 case ixgbe_mac_X550EM_x: 803 case ixgbe_mac_x550em_a: 804 return IXGBE_MAX_RSS_INDICES_X550; 805 default: 806 return 0; 807 } 808 } 809 810 struct ixgbe_fdir_filter { 811 struct hlist_node fdir_node; 812 union ixgbe_atr_input filter; 813 u16 sw_idx; 814 u64 action; 815 }; 816 817 enum ixgbe_state_t { 818 __IXGBE_TESTING, 819 __IXGBE_RESETTING, 820 __IXGBE_DOWN, 821 __IXGBE_DISABLED, 822 __IXGBE_REMOVING, 823 __IXGBE_SERVICE_SCHED, 824 __IXGBE_SERVICE_INITED, 825 __IXGBE_IN_SFP_INIT, 826 __IXGBE_PTP_RUNNING, 827 __IXGBE_PTP_TX_IN_PROGRESS, 828 __IXGBE_RESET_REQUESTED, 829 }; 830 831 struct ixgbe_cb { 832 union { /* Union defining head/tail partner */ 833 struct sk_buff *head; 834 struct sk_buff *tail; 835 }; 836 dma_addr_t dma; 837 u16 append_cnt; 838 bool page_released; 839 }; 840 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) 841 842 enum ixgbe_boards { 843 board_82598, 844 board_82599, 845 board_X540, 846 board_X550, 847 board_X550EM_x, 848 board_x550em_x_fw, 849 board_x550em_a, 850 board_x550em_a_fw, 851 }; 852 853 extern const struct ixgbe_info ixgbe_82598_info; 854 extern const struct ixgbe_info ixgbe_82599_info; 855 extern const struct ixgbe_info ixgbe_X540_info; 856 extern const struct ixgbe_info ixgbe_X550_info; 857 extern const struct ixgbe_info ixgbe_X550EM_x_info; 858 extern const struct ixgbe_info ixgbe_x550em_x_fw_info; 859 extern const struct ixgbe_info ixgbe_x550em_a_info; 860 extern const struct ixgbe_info ixgbe_x550em_a_fw_info; 861 #ifdef CONFIG_IXGBE_DCB 862 extern const struct dcbnl_rtnl_ops ixgbe_dcbnl_ops; 863 #endif 864 865 extern char ixgbe_driver_name[]; 866 #ifdef IXGBE_FCOE 867 extern char ixgbe_default_device_descr[]; 868 #endif /* IXGBE_FCOE */ 869 870 int ixgbe_open(struct net_device *netdev); 871 int ixgbe_close(struct net_device *netdev); 872 void ixgbe_up(struct ixgbe_adapter *adapter); 873 void ixgbe_down(struct ixgbe_adapter *adapter); 874 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); 875 void ixgbe_reset(struct ixgbe_adapter *adapter); 876 void ixgbe_set_ethtool_ops(struct net_device *netdev); 877 int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); 878 int ixgbe_setup_tx_resources(struct ixgbe_ring *); 879 void ixgbe_free_rx_resources(struct ixgbe_ring *); 880 void ixgbe_free_tx_resources(struct ixgbe_ring *); 881 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 882 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 883 void ixgbe_disable_rx(struct ixgbe_adapter *adapter); 884 void ixgbe_disable_tx(struct ixgbe_adapter *adapter); 885 void ixgbe_update_stats(struct ixgbe_adapter *adapter); 886 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); 887 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 888 u16 subdevice_id); 889 #ifdef CONFIG_PCI_IOV 890 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter); 891 #endif 892 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 893 const u8 *addr, u16 queue); 894 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 895 const u8 *addr, u16 queue); 896 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid); 897 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); 898 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, 899 struct ixgbe_ring *); 900 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, 901 struct ixgbe_tx_buffer *); 902 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); 903 void ixgbe_write_eitr(struct ixgbe_q_vector *); 904 int ixgbe_poll(struct napi_struct *napi, int budget); 905 int ethtool_ioctl(struct ifreq *ifr); 906 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 907 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); 908 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); 909 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 910 union ixgbe_atr_hash_dword input, 911 union ixgbe_atr_hash_dword common, 912 u8 queue); 913 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 914 union ixgbe_atr_input *input_mask); 915 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 916 union ixgbe_atr_input *input, 917 u16 soft_id, u8 queue); 918 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 919 union ixgbe_atr_input *input, 920 u16 soft_id); 921 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 922 union ixgbe_atr_input *mask); 923 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 924 struct ixgbe_fdir_filter *input, 925 u16 sw_idx); 926 void ixgbe_set_rx_mode(struct net_device *netdev); 927 #ifdef CONFIG_IXGBE_DCB 928 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); 929 #endif 930 int ixgbe_setup_tc(struct net_device *dev, u8 tc); 931 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); 932 void ixgbe_do_reset(struct net_device *netdev); 933 #ifdef CONFIG_IXGBE_HWMON 934 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); 935 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); 936 #endif /* CONFIG_IXGBE_HWMON */ 937 #ifdef IXGBE_FCOE 938 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 939 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 940 u8 *hdr_len); 941 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, 942 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); 943 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, 944 struct scatterlist *sgl, unsigned int sgc); 945 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, 946 struct scatterlist *sgl, unsigned int sgc); 947 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); 948 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 949 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 950 int ixgbe_fcoe_enable(struct net_device *netdev); 951 int ixgbe_fcoe_disable(struct net_device *netdev); 952 #ifdef CONFIG_IXGBE_DCB 953 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); 954 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); 955 #endif /* CONFIG_IXGBE_DCB */ 956 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); 957 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, 958 struct netdev_fcoe_hbainfo *info); 959 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); 960 #endif /* IXGBE_FCOE */ 961 #ifdef CONFIG_DEBUG_FS 962 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); 963 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); 964 void ixgbe_dbg_init(void); 965 void ixgbe_dbg_exit(void); 966 #else 967 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} 968 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} 969 static inline void ixgbe_dbg_init(void) {} 970 static inline void ixgbe_dbg_exit(void) {} 971 #endif /* CONFIG_DEBUG_FS */ 972 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) 973 { 974 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 975 } 976 977 void ixgbe_ptp_init(struct ixgbe_adapter *adapter); 978 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter); 979 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); 980 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); 981 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); 982 void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter); 983 void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *); 984 void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb); 985 static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring, 986 union ixgbe_adv_rx_desc *rx_desc, 987 struct sk_buff *skb) 988 { 989 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) { 990 ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb); 991 return; 992 } 993 994 if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) 995 return; 996 997 ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 998 999 /* Update the last_rx_timestamp timer in order to enable watchdog check 1000 * for error case of latched timestamp on a dropped packet. 1001 */ 1002 rx_ring->last_rx_timestamp = jiffies; 1003 } 1004 1005 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 1006 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 1007 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); 1008 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); 1009 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter); 1010 #ifdef CONFIG_PCI_IOV 1011 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); 1012 #endif 1013 1014 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 1015 struct ixgbe_adapter *adapter, 1016 struct ixgbe_ring *tx_ring); 1017 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter); 1018 void ixgbe_store_key(struct ixgbe_adapter *adapter); 1019 void ixgbe_store_reta(struct ixgbe_adapter *adapter); 1020 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 1021 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm); 1022 #ifdef CONFIG_IXGBE_IPSEC 1023 void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter); 1024 void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter); 1025 void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter); 1026 void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring, 1027 union ixgbe_adv_rx_desc *rx_desc, 1028 struct sk_buff *skb); 1029 int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 1030 struct ixgbe_ipsec_tx_data *itd); 1031 void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter, u32 vf); 1032 int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf); 1033 int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf); 1034 #else 1035 static inline void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter) { } 1036 static inline void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter) { } 1037 static inline void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter) { } 1038 static inline void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring, 1039 union ixgbe_adv_rx_desc *rx_desc, 1040 struct sk_buff *skb) { } 1041 static inline int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring, 1042 struct ixgbe_tx_buffer *first, 1043 struct ixgbe_ipsec_tx_data *itd) { return 0; } 1044 static inline void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter, 1045 u32 vf) { } 1046 static inline int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter, 1047 u32 *mbuf, u32 vf) { return -EACCES; } 1048 static inline int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter, 1049 u32 *mbuf, u32 vf) { return -EACCES; } 1050 #endif /* CONFIG_IXGBE_IPSEC */ 1051 1052 static inline bool ixgbe_enabled_xdp_adapter(struct ixgbe_adapter *adapter) 1053 { 1054 return !!adapter->xdp_prog; 1055 } 1056 1057 #endif /* _IXGBE_H_ */ 1058