1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #ifndef _IXGBE_H_ 30 #define _IXGBE_H_ 31 32 #include <linux/bitops.h> 33 #include <linux/types.h> 34 #include <linux/pci.h> 35 #include <linux/netdevice.h> 36 #include <linux/cpumask.h> 37 #include <linux/aer.h> 38 #include <linux/if_vlan.h> 39 #include <linux/jiffies.h> 40 41 #include <linux/timecounter.h> 42 #include <linux/net_tstamp.h> 43 #include <linux/ptp_clock_kernel.h> 44 45 #include "ixgbe_type.h" 46 #include "ixgbe_common.h" 47 #include "ixgbe_dcb.h" 48 #if IS_ENABLED(CONFIG_FCOE) 49 #define IXGBE_FCOE 50 #include "ixgbe_fcoe.h" 51 #endif /* IS_ENABLED(CONFIG_FCOE) */ 52 #ifdef CONFIG_IXGBE_DCA 53 #include <linux/dca.h> 54 #endif 55 56 #include <net/xdp.h> 57 #include <net/busy_poll.h> 58 59 /* common prefix used by pr_<> macros */ 60 #undef pr_fmt 61 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 62 63 /* TX/RX descriptor defines */ 64 #define IXGBE_DEFAULT_TXD 512 65 #define IXGBE_DEFAULT_TX_WORK 256 66 #define IXGBE_MAX_TXD 4096 67 #define IXGBE_MIN_TXD 64 68 69 #if (PAGE_SIZE < 8192) 70 #define IXGBE_DEFAULT_RXD 512 71 #else 72 #define IXGBE_DEFAULT_RXD 128 73 #endif 74 #define IXGBE_MAX_RXD 4096 75 #define IXGBE_MIN_RXD 64 76 77 #define IXGBE_ETH_P_LLDP 0x88CC 78 79 /* flow control */ 80 #define IXGBE_MIN_FCRTL 0x40 81 #define IXGBE_MAX_FCRTL 0x7FF80 82 #define IXGBE_MIN_FCRTH 0x600 83 #define IXGBE_MAX_FCRTH 0x7FFF0 84 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF 85 #define IXGBE_MIN_FCPAUSE 0 86 #define IXGBE_MAX_FCPAUSE 0xFFFF 87 88 /* Supported Rx Buffer Sizes */ 89 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ 90 #define IXGBE_RXBUFFER_1536 1536 91 #define IXGBE_RXBUFFER_2K 2048 92 #define IXGBE_RXBUFFER_3K 3072 93 #define IXGBE_RXBUFFER_4K 4096 94 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 95 96 /* Attempt to maximize the headroom available for incoming frames. We 97 * use a 2K buffer for receives and need 1536/1534 to store the data for 98 * the frame. This leaves us with 512 bytes of room. From that we need 99 * to deduct the space needed for the shared info and the padding needed 100 * to IP align the frame. 101 * 102 * Note: For cache line sizes 256 or larger this value is going to end 103 * up negative. In these cases we should fall back to the 3K 104 * buffers. 105 */ 106 #if (PAGE_SIZE < 8192) 107 #define IXGBE_MAX_2K_FRAME_BUILD_SKB (IXGBE_RXBUFFER_1536 - NET_IP_ALIGN) 108 #define IXGBE_2K_TOO_SMALL_WITH_PADDING \ 109 ((NET_SKB_PAD + IXGBE_RXBUFFER_1536) > SKB_WITH_OVERHEAD(IXGBE_RXBUFFER_2K)) 110 111 static inline int ixgbe_compute_pad(int rx_buf_len) 112 { 113 int page_size, pad_size; 114 115 page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2); 116 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len; 117 118 return pad_size; 119 } 120 121 static inline int ixgbe_skb_pad(void) 122 { 123 int rx_buf_len; 124 125 /* If a 2K buffer cannot handle a standard Ethernet frame then 126 * optimize padding for a 3K buffer instead of a 1.5K buffer. 127 * 128 * For a 3K buffer we need to add enough padding to allow for 129 * tailroom due to NET_IP_ALIGN possibly shifting us out of 130 * cache-line alignment. 131 */ 132 if (IXGBE_2K_TOO_SMALL_WITH_PADDING) 133 rx_buf_len = IXGBE_RXBUFFER_3K + SKB_DATA_ALIGN(NET_IP_ALIGN); 134 else 135 rx_buf_len = IXGBE_RXBUFFER_1536; 136 137 /* if needed make room for NET_IP_ALIGN */ 138 rx_buf_len -= NET_IP_ALIGN; 139 140 return ixgbe_compute_pad(rx_buf_len); 141 } 142 143 #define IXGBE_SKB_PAD ixgbe_skb_pad() 144 #else 145 #define IXGBE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 146 #endif 147 148 /* 149 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 150 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, 151 * this adds up to 448 bytes of extra data. 152 * 153 * Since netdev_alloc_skb now allocates a page fragment we can use a value 154 * of 256 and the resultant skb will have a truesize of 960 or less. 155 */ 156 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 157 158 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 159 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 160 161 #define IXGBE_RX_DMA_ATTR \ 162 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 163 164 enum ixgbe_tx_flags { 165 /* cmd_type flags */ 166 IXGBE_TX_FLAGS_HW_VLAN = 0x01, 167 IXGBE_TX_FLAGS_TSO = 0x02, 168 IXGBE_TX_FLAGS_TSTAMP = 0x04, 169 170 /* olinfo flags */ 171 IXGBE_TX_FLAGS_CC = 0x08, 172 IXGBE_TX_FLAGS_IPV4 = 0x10, 173 IXGBE_TX_FLAGS_CSUM = 0x20, 174 175 /* software defined flags */ 176 IXGBE_TX_FLAGS_SW_VLAN = 0x40, 177 IXGBE_TX_FLAGS_FCOE = 0x80, 178 }; 179 180 /* VLAN info */ 181 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 182 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 183 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 184 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 185 186 #define IXGBE_MAX_VF_MC_ENTRIES 30 187 #define IXGBE_MAX_VF_FUNCTIONS 64 188 #define IXGBE_MAX_VFTA_ENTRIES 128 189 #define MAX_EMULATION_MAC_ADDRS 16 190 #define IXGBE_MAX_PF_MACVLANS 15 191 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) 192 #define IXGBE_82599_VF_DEVICE_ID 0x10ED 193 #define IXGBE_X540_VF_DEVICE_ID 0x1515 194 195 struct vf_data_storage { 196 struct pci_dev *vfdev; 197 unsigned char vf_mac_addresses[ETH_ALEN]; 198 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 199 u16 num_vf_mc_hashes; 200 bool clear_to_send; 201 bool pf_set_mac; 202 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 203 u16 pf_qos; 204 u16 tx_rate; 205 u8 spoofchk_enabled; 206 bool rss_query_enabled; 207 u8 trusted; 208 int xcast_mode; 209 unsigned int vf_api; 210 }; 211 212 enum ixgbevf_xcast_modes { 213 IXGBEVF_XCAST_MODE_NONE = 0, 214 IXGBEVF_XCAST_MODE_MULTI, 215 IXGBEVF_XCAST_MODE_ALLMULTI, 216 IXGBEVF_XCAST_MODE_PROMISC, 217 }; 218 219 struct vf_macvlans { 220 struct list_head l; 221 int vf; 222 bool free; 223 bool is_macvlan; 224 u8 vf_macvlan[ETH_ALEN]; 225 }; 226 227 #define IXGBE_MAX_TXD_PWR 14 228 #define IXGBE_MAX_DATA_PER_TXD (1u << IXGBE_MAX_TXD_PWR) 229 230 /* Tx Descriptors needed, worst case */ 231 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 232 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 233 234 /* wrapper around a pointer to a socket buffer, 235 * so a DMA handle can be stored along with the buffer */ 236 struct ixgbe_tx_buffer { 237 union ixgbe_adv_tx_desc *next_to_watch; 238 unsigned long time_stamp; 239 union { 240 struct sk_buff *skb; 241 /* XDP uses address ptr on irq_clean */ 242 void *data; 243 }; 244 unsigned int bytecount; 245 unsigned short gso_segs; 246 __be16 protocol; 247 DEFINE_DMA_UNMAP_ADDR(dma); 248 DEFINE_DMA_UNMAP_LEN(len); 249 u32 tx_flags; 250 }; 251 252 struct ixgbe_rx_buffer { 253 struct sk_buff *skb; 254 dma_addr_t dma; 255 struct page *page; 256 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 257 __u32 page_offset; 258 #else 259 __u16 page_offset; 260 #endif 261 __u16 pagecnt_bias; 262 }; 263 264 struct ixgbe_queue_stats { 265 u64 packets; 266 u64 bytes; 267 }; 268 269 struct ixgbe_tx_queue_stats { 270 u64 restart_queue; 271 u64 tx_busy; 272 u64 tx_done_old; 273 }; 274 275 struct ixgbe_rx_queue_stats { 276 u64 rsc_count; 277 u64 rsc_flush; 278 u64 non_eop_descs; 279 u64 alloc_rx_page; 280 u64 alloc_rx_page_failed; 281 u64 alloc_rx_buff_failed; 282 u64 csum_err; 283 }; 284 285 #define IXGBE_TS_HDR_LEN 8 286 287 enum ixgbe_ring_state_t { 288 __IXGBE_RX_3K_BUFFER, 289 __IXGBE_RX_BUILD_SKB_ENABLED, 290 __IXGBE_RX_RSC_ENABLED, 291 __IXGBE_RX_CSUM_UDP_ZERO_ERR, 292 __IXGBE_RX_FCOE, 293 __IXGBE_TX_FDIR_INIT_DONE, 294 __IXGBE_TX_XPS_INIT_DONE, 295 __IXGBE_TX_DETECT_HANG, 296 __IXGBE_HANG_CHECK_ARMED, 297 __IXGBE_TX_XDP_RING, 298 }; 299 300 #define ring_uses_build_skb(ring) \ 301 test_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &(ring)->state) 302 303 struct ixgbe_fwd_adapter { 304 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 305 struct net_device *netdev; 306 struct ixgbe_adapter *real_adapter; 307 unsigned int tx_base_queue; 308 unsigned int rx_base_queue; 309 int pool; 310 }; 311 312 #define check_for_tx_hang(ring) \ 313 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 314 #define set_check_for_tx_hang(ring) \ 315 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 316 #define clear_check_for_tx_hang(ring) \ 317 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 318 #define ring_is_rsc_enabled(ring) \ 319 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 320 #define set_ring_rsc_enabled(ring) \ 321 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 322 #define clear_ring_rsc_enabled(ring) \ 323 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 324 #define ring_is_xdp(ring) \ 325 test_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 326 #define set_ring_xdp(ring) \ 327 set_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 328 #define clear_ring_xdp(ring) \ 329 clear_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 330 struct ixgbe_ring { 331 struct ixgbe_ring *next; /* pointer to next ring in q_vector */ 332 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ 333 struct net_device *netdev; /* netdev ring belongs to */ 334 struct bpf_prog *xdp_prog; 335 struct device *dev; /* device for DMA mapping */ 336 struct ixgbe_fwd_adapter *l2_accel_priv; 337 void *desc; /* descriptor ring memory */ 338 union { 339 struct ixgbe_tx_buffer *tx_buffer_info; 340 struct ixgbe_rx_buffer *rx_buffer_info; 341 }; 342 unsigned long state; 343 u8 __iomem *tail; 344 dma_addr_t dma; /* phys. address of descriptor ring */ 345 unsigned int size; /* length in bytes */ 346 347 u16 count; /* amount of descriptors */ 348 349 u8 queue_index; /* needed for multiqueue queue management */ 350 u8 reg_idx; /* holds the special value that gets 351 * the hardware register offset 352 * associated with this ring, which is 353 * different for DCB and RSS modes 354 */ 355 u16 next_to_use; 356 u16 next_to_clean; 357 358 unsigned long last_rx_timestamp; 359 360 union { 361 u16 next_to_alloc; 362 struct { 363 u8 atr_sample_rate; 364 u8 atr_count; 365 }; 366 }; 367 368 u8 dcb_tc; 369 struct ixgbe_queue_stats stats; 370 struct u64_stats_sync syncp; 371 union { 372 struct ixgbe_tx_queue_stats tx_stats; 373 struct ixgbe_rx_queue_stats rx_stats; 374 }; 375 struct xdp_rxq_info xdp_rxq; 376 } ____cacheline_internodealigned_in_smp; 377 378 enum ixgbe_ring_f_enum { 379 RING_F_NONE = 0, 380 RING_F_VMDQ, /* SR-IOV uses the same ring feature */ 381 RING_F_RSS, 382 RING_F_FDIR, 383 #ifdef IXGBE_FCOE 384 RING_F_FCOE, 385 #endif /* IXGBE_FCOE */ 386 387 RING_F_ARRAY_SIZE /* must be last in enum set */ 388 }; 389 390 #define IXGBE_MAX_RSS_INDICES 16 391 #define IXGBE_MAX_RSS_INDICES_X550 63 392 #define IXGBE_MAX_VMDQ_INDICES 64 393 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ 394 #define IXGBE_MAX_FCOE_INDICES 8 395 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 396 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 397 #define MAX_XDP_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 398 #define IXGBE_MAX_L2A_QUEUES 4 399 #define IXGBE_BAD_L2A_QUEUE 3 400 #define IXGBE_MAX_MACVLANS 31 401 #define IXGBE_MAX_DCBMACVLANS 8 402 403 struct ixgbe_ring_feature { 404 u16 limit; /* upper limit on feature indices */ 405 u16 indices; /* current value of indices */ 406 u16 mask; /* Mask used for feature to ring mapping */ 407 u16 offset; /* offset to start of feature */ 408 } ____cacheline_internodealigned_in_smp; 409 410 #define IXGBE_82599_VMDQ_8Q_MASK 0x78 411 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C 412 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E 413 414 /* 415 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since 416 * this is twice the size of a half page we need to double the page order 417 * for FCoE enabled Rx queues. 418 */ 419 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) 420 { 421 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 422 return IXGBE_RXBUFFER_3K; 423 #if (PAGE_SIZE < 8192) 424 if (ring_uses_build_skb(ring)) 425 return IXGBE_MAX_2K_FRAME_BUILD_SKB; 426 #endif 427 return IXGBE_RXBUFFER_2K; 428 } 429 430 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) 431 { 432 #if (PAGE_SIZE < 8192) 433 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 434 return 1; 435 #endif 436 return 0; 437 } 438 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) 439 440 #define IXGBE_ITR_ADAPTIVE_MIN_INC 2 441 #define IXGBE_ITR_ADAPTIVE_MIN_USECS 10 442 #define IXGBE_ITR_ADAPTIVE_MAX_USECS 126 443 #define IXGBE_ITR_ADAPTIVE_LATENCY 0x80 444 #define IXGBE_ITR_ADAPTIVE_BULK 0x00 445 446 struct ixgbe_ring_container { 447 struct ixgbe_ring *ring; /* pointer to linked list of rings */ 448 unsigned long next_update; /* jiffies value of last update */ 449 unsigned int total_bytes; /* total bytes processed this int */ 450 unsigned int total_packets; /* total packets processed this int */ 451 u16 work_limit; /* total work allowed per interrupt */ 452 u8 count; /* total number of rings in vector */ 453 u8 itr; /* current ITR setting for ring */ 454 }; 455 456 /* iterator for handling rings in ring container */ 457 #define ixgbe_for_each_ring(pos, head) \ 458 for (pos = (head).ring; pos != NULL; pos = pos->next) 459 460 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ 461 ? 8 : 1) 462 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS 463 464 /* MAX_Q_VECTORS of these are allocated, 465 * but we only use one per queue-specific vector. 466 */ 467 struct ixgbe_q_vector { 468 struct ixgbe_adapter *adapter; 469 #ifdef CONFIG_IXGBE_DCA 470 int cpu; /* CPU for DCA */ 471 #endif 472 u16 v_idx; /* index of q_vector within array, also used for 473 * finding the bit in EICR and friends that 474 * represents the vector for this ring */ 475 u16 itr; /* Interrupt throttle rate written to EITR */ 476 struct ixgbe_ring_container rx, tx; 477 478 struct napi_struct napi; 479 cpumask_t affinity_mask; 480 int numa_node; 481 struct rcu_head rcu; /* to avoid race with update stats on free */ 482 char name[IFNAMSIZ + 9]; 483 484 /* for dynamic allocation of rings associated with this q_vector */ 485 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; 486 }; 487 488 #ifdef CONFIG_IXGBE_HWMON 489 490 #define IXGBE_HWMON_TYPE_LOC 0 491 #define IXGBE_HWMON_TYPE_TEMP 1 492 #define IXGBE_HWMON_TYPE_CAUTION 2 493 #define IXGBE_HWMON_TYPE_MAX 3 494 495 struct hwmon_attr { 496 struct device_attribute dev_attr; 497 struct ixgbe_hw *hw; 498 struct ixgbe_thermal_diode_data *sensor; 499 char name[12]; 500 }; 501 502 struct hwmon_buff { 503 struct attribute_group group; 504 const struct attribute_group *groups[2]; 505 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; 506 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; 507 unsigned int n_hwmon; 508 }; 509 #endif /* CONFIG_IXGBE_HWMON */ 510 511 /* 512 * microsecond values for various ITR rates shifted by 2 to fit itr register 513 * with the first 3 bits reserved 0 514 */ 515 #define IXGBE_MIN_RSC_ITR 24 516 #define IXGBE_100K_ITR 40 517 #define IXGBE_20K_ITR 200 518 #define IXGBE_12K_ITR 336 519 520 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ 521 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, 522 const u32 stat_err_bits) 523 { 524 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 525 } 526 527 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) 528 { 529 u16 ntc = ring->next_to_clean; 530 u16 ntu = ring->next_to_use; 531 532 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 533 } 534 535 #define IXGBE_RX_DESC(R, i) \ 536 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 537 #define IXGBE_TX_DESC(R, i) \ 538 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 539 #define IXGBE_TX_CTXTDESC(R, i) \ 540 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 541 542 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ 543 #ifdef IXGBE_FCOE 544 /* Use 3K as the baby jumbo frame size for FCoE */ 545 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 546 #endif /* IXGBE_FCOE */ 547 548 #define OTHER_VECTOR 1 549 #define NON_Q_VECTORS (OTHER_VECTOR) 550 551 #define MAX_MSIX_VECTORS_82599 64 552 #define MAX_Q_VECTORS_82599 64 553 #define MAX_MSIX_VECTORS_82598 18 554 #define MAX_Q_VECTORS_82598 16 555 556 struct ixgbe_mac_addr { 557 u8 addr[ETH_ALEN]; 558 u16 pool; 559 u16 state; /* bitmask */ 560 }; 561 562 #define IXGBE_MAC_STATE_DEFAULT 0x1 563 #define IXGBE_MAC_STATE_MODIFIED 0x2 564 #define IXGBE_MAC_STATE_IN_USE 0x4 565 566 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 567 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 568 569 #define MIN_MSIX_Q_VECTORS 1 570 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 571 572 /* default to trying for four seconds */ 573 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 574 #define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */ 575 576 /* board specific private data structure */ 577 struct ixgbe_adapter { 578 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 579 /* OS defined structs */ 580 struct net_device *netdev; 581 struct bpf_prog *xdp_prog; 582 struct pci_dev *pdev; 583 584 unsigned long state; 585 586 /* Some features need tri-state capability, 587 * thus the additional *_CAPABLE flags. 588 */ 589 u32 flags; 590 #define IXGBE_FLAG_MSI_ENABLED BIT(1) 591 #define IXGBE_FLAG_MSIX_ENABLED BIT(3) 592 #define IXGBE_FLAG_RX_1BUF_CAPABLE BIT(4) 593 #define IXGBE_FLAG_RX_PS_CAPABLE BIT(5) 594 #define IXGBE_FLAG_RX_PS_ENABLED BIT(6) 595 #define IXGBE_FLAG_DCA_ENABLED BIT(8) 596 #define IXGBE_FLAG_DCA_CAPABLE BIT(9) 597 #define IXGBE_FLAG_IMIR_ENABLED BIT(10) 598 #define IXGBE_FLAG_MQ_CAPABLE BIT(11) 599 #define IXGBE_FLAG_DCB_ENABLED BIT(12) 600 #define IXGBE_FLAG_VMDQ_CAPABLE BIT(13) 601 #define IXGBE_FLAG_VMDQ_ENABLED BIT(14) 602 #define IXGBE_FLAG_FAN_FAIL_CAPABLE BIT(15) 603 #define IXGBE_FLAG_NEED_LINK_UPDATE BIT(16) 604 #define IXGBE_FLAG_NEED_LINK_CONFIG BIT(17) 605 #define IXGBE_FLAG_FDIR_HASH_CAPABLE BIT(18) 606 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE BIT(19) 607 #define IXGBE_FLAG_FCOE_CAPABLE BIT(20) 608 #define IXGBE_FLAG_FCOE_ENABLED BIT(21) 609 #define IXGBE_FLAG_SRIOV_CAPABLE BIT(22) 610 #define IXGBE_FLAG_SRIOV_ENABLED BIT(23) 611 #define IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE BIT(24) 612 #define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25) 613 #define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26) 614 #define IXGBE_FLAG_DCB_CAPABLE BIT(27) 615 #define IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE BIT(28) 616 617 u32 flags2; 618 #define IXGBE_FLAG2_RSC_CAPABLE BIT(0) 619 #define IXGBE_FLAG2_RSC_ENABLED BIT(1) 620 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE BIT(2) 621 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT BIT(3) 622 #define IXGBE_FLAG2_SEARCH_FOR_SFP BIT(4) 623 #define IXGBE_FLAG2_SFP_NEEDS_RESET BIT(5) 624 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT BIT(7) 625 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP BIT(8) 626 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP BIT(9) 627 #define IXGBE_FLAG2_PTP_PPS_ENABLED BIT(10) 628 #define IXGBE_FLAG2_PHY_INTERRUPT BIT(11) 629 #define IXGBE_FLAG2_UDP_TUN_REREG_NEEDED BIT(12) 630 #define IXGBE_FLAG2_VLAN_PROMISC BIT(13) 631 #define IXGBE_FLAG2_EEE_CAPABLE BIT(14) 632 #define IXGBE_FLAG2_EEE_ENABLED BIT(15) 633 #define IXGBE_FLAG2_RX_LEGACY BIT(16) 634 635 /* Tx fast path data */ 636 int num_tx_queues; 637 u16 tx_itr_setting; 638 u16 tx_work_limit; 639 640 /* Rx fast path data */ 641 int num_rx_queues; 642 u16 rx_itr_setting; 643 644 /* Port number used to identify VXLAN traffic */ 645 __be16 vxlan_port; 646 __be16 geneve_port; 647 648 /* XDP */ 649 int num_xdp_queues; 650 struct ixgbe_ring *xdp_ring[MAX_XDP_QUEUES]; 651 652 /* TX */ 653 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; 654 655 u64 restart_queue; 656 u64 lsc_int; 657 u32 tx_timeout_count; 658 659 /* RX */ 660 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; 661 int num_rx_pools; /* == num_rx_queues in 82598 */ 662 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ 663 u64 hw_csum_rx_error; 664 u64 hw_rx_no_dma_resources; 665 u64 rsc_total_count; 666 u64 rsc_total_flush; 667 u64 non_eop_descs; 668 u32 alloc_rx_page; 669 u32 alloc_rx_page_failed; 670 u32 alloc_rx_buff_failed; 671 672 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; 673 674 /* DCB parameters */ 675 struct ieee_pfc *ixgbe_ieee_pfc; 676 struct ieee_ets *ixgbe_ieee_ets; 677 struct ixgbe_dcb_config dcb_cfg; 678 struct ixgbe_dcb_config temp_dcb_cfg; 679 u8 dcb_set_bitmap; 680 u8 dcbx_cap; 681 enum ixgbe_fc_mode last_lfc_mode; 682 683 int num_q_vectors; /* current number of q_vectors for device */ 684 int max_q_vectors; /* true count of q_vectors for device */ 685 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; 686 struct msix_entry *msix_entries; 687 688 u32 test_icr; 689 struct ixgbe_ring test_tx_ring; 690 struct ixgbe_ring test_rx_ring; 691 692 /* structs defined in ixgbe_hw.h */ 693 struct ixgbe_hw hw; 694 u16 msg_enable; 695 struct ixgbe_hw_stats stats; 696 697 u64 tx_busy; 698 unsigned int tx_ring_count; 699 unsigned int xdp_ring_count; 700 unsigned int rx_ring_count; 701 702 u32 link_speed; 703 bool link_up; 704 unsigned long sfp_poll_time; 705 unsigned long link_check_timeout; 706 707 struct timer_list service_timer; 708 struct work_struct service_task; 709 710 struct hlist_head fdir_filter_list; 711 unsigned long fdir_overflow; /* number of times ATR was backed off */ 712 union ixgbe_atr_input fdir_mask; 713 int fdir_filter_count; 714 u32 fdir_pballoc; 715 u32 atr_sample_rate; 716 spinlock_t fdir_perfect_lock; 717 718 #ifdef IXGBE_FCOE 719 struct ixgbe_fcoe fcoe; 720 #endif /* IXGBE_FCOE */ 721 u8 __iomem *io_addr; /* Mainly for iounmap use */ 722 u32 wol; 723 724 u16 bridge_mode; 725 726 u16 eeprom_verh; 727 u16 eeprom_verl; 728 u16 eeprom_cap; 729 730 u32 interrupt_event; 731 u32 led_reg; 732 733 struct ptp_clock *ptp_clock; 734 struct ptp_clock_info ptp_caps; 735 struct work_struct ptp_tx_work; 736 struct sk_buff *ptp_tx_skb; 737 struct hwtstamp_config tstamp_config; 738 unsigned long ptp_tx_start; 739 unsigned long last_overflow_check; 740 unsigned long last_rx_ptp_check; 741 unsigned long last_rx_timestamp; 742 spinlock_t tmreg_lock; 743 struct cyclecounter hw_cc; 744 struct timecounter hw_tc; 745 u32 base_incval; 746 u32 tx_hwtstamp_timeouts; 747 u32 tx_hwtstamp_skipped; 748 u32 rx_hwtstamp_cleared; 749 void (*ptp_setup_sdp)(struct ixgbe_adapter *); 750 751 /* SR-IOV */ 752 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 753 unsigned int num_vfs; 754 struct vf_data_storage *vfinfo; 755 int vf_rate_link_speed; 756 struct vf_macvlans vf_mvs; 757 struct vf_macvlans *mv_list; 758 759 u32 timer_event_accumulator; 760 u32 vferr_refcount; 761 struct ixgbe_mac_addr *mac_table; 762 struct kobject *info_kobj; 763 #ifdef CONFIG_IXGBE_HWMON 764 struct hwmon_buff *ixgbe_hwmon_buff; 765 #endif /* CONFIG_IXGBE_HWMON */ 766 #ifdef CONFIG_DEBUG_FS 767 struct dentry *ixgbe_dbg_adapter; 768 #endif /*CONFIG_DEBUG_FS*/ 769 770 u8 default_up; 771 unsigned long fwd_bitmask; /* Bitmask indicating in use pools */ 772 773 #define IXGBE_MAX_LINK_HANDLE 10 774 struct ixgbe_jump_table *jump_tables[IXGBE_MAX_LINK_HANDLE]; 775 unsigned long tables; 776 777 /* maximum number of RETA entries among all devices supported by ixgbe 778 * driver: currently it's x550 device in non-SRIOV mode 779 */ 780 #define IXGBE_MAX_RETA_ENTRIES 512 781 u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES]; 782 783 #define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */ 784 u32 *rss_key; 785 }; 786 787 static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter) 788 { 789 switch (adapter->hw.mac.type) { 790 case ixgbe_mac_82598EB: 791 case ixgbe_mac_82599EB: 792 case ixgbe_mac_X540: 793 return IXGBE_MAX_RSS_INDICES; 794 case ixgbe_mac_X550: 795 case ixgbe_mac_X550EM_x: 796 case ixgbe_mac_x550em_a: 797 return IXGBE_MAX_RSS_INDICES_X550; 798 default: 799 return 0; 800 } 801 } 802 803 struct ixgbe_fdir_filter { 804 struct hlist_node fdir_node; 805 union ixgbe_atr_input filter; 806 u16 sw_idx; 807 u64 action; 808 }; 809 810 enum ixgbe_state_t { 811 __IXGBE_TESTING, 812 __IXGBE_RESETTING, 813 __IXGBE_DOWN, 814 __IXGBE_DISABLED, 815 __IXGBE_REMOVING, 816 __IXGBE_SERVICE_SCHED, 817 __IXGBE_SERVICE_INITED, 818 __IXGBE_IN_SFP_INIT, 819 __IXGBE_PTP_RUNNING, 820 __IXGBE_PTP_TX_IN_PROGRESS, 821 __IXGBE_RESET_REQUESTED, 822 }; 823 824 struct ixgbe_cb { 825 union { /* Union defining head/tail partner */ 826 struct sk_buff *head; 827 struct sk_buff *tail; 828 }; 829 dma_addr_t dma; 830 u16 append_cnt; 831 bool page_released; 832 }; 833 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) 834 835 enum ixgbe_boards { 836 board_82598, 837 board_82599, 838 board_X540, 839 board_X550, 840 board_X550EM_x, 841 board_x550em_x_fw, 842 board_x550em_a, 843 board_x550em_a_fw, 844 }; 845 846 extern const struct ixgbe_info ixgbe_82598_info; 847 extern const struct ixgbe_info ixgbe_82599_info; 848 extern const struct ixgbe_info ixgbe_X540_info; 849 extern const struct ixgbe_info ixgbe_X550_info; 850 extern const struct ixgbe_info ixgbe_X550EM_x_info; 851 extern const struct ixgbe_info ixgbe_x550em_x_fw_info; 852 extern const struct ixgbe_info ixgbe_x550em_a_info; 853 extern const struct ixgbe_info ixgbe_x550em_a_fw_info; 854 #ifdef CONFIG_IXGBE_DCB 855 extern const struct dcbnl_rtnl_ops ixgbe_dcbnl_ops; 856 #endif 857 858 extern char ixgbe_driver_name[]; 859 extern const char ixgbe_driver_version[]; 860 #ifdef IXGBE_FCOE 861 extern char ixgbe_default_device_descr[]; 862 #endif /* IXGBE_FCOE */ 863 864 int ixgbe_open(struct net_device *netdev); 865 int ixgbe_close(struct net_device *netdev); 866 void ixgbe_up(struct ixgbe_adapter *adapter); 867 void ixgbe_down(struct ixgbe_adapter *adapter); 868 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); 869 void ixgbe_reset(struct ixgbe_adapter *adapter); 870 void ixgbe_set_ethtool_ops(struct net_device *netdev); 871 int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); 872 int ixgbe_setup_tx_resources(struct ixgbe_ring *); 873 void ixgbe_free_rx_resources(struct ixgbe_ring *); 874 void ixgbe_free_tx_resources(struct ixgbe_ring *); 875 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 876 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 877 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *); 878 void ixgbe_update_stats(struct ixgbe_adapter *adapter); 879 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); 880 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 881 u16 subdevice_id); 882 #ifdef CONFIG_PCI_IOV 883 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter); 884 #endif 885 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 886 const u8 *addr, u16 queue); 887 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 888 const u8 *addr, u16 queue); 889 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid); 890 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); 891 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, 892 struct ixgbe_ring *); 893 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, 894 struct ixgbe_tx_buffer *); 895 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); 896 void ixgbe_write_eitr(struct ixgbe_q_vector *); 897 int ixgbe_poll(struct napi_struct *napi, int budget); 898 int ethtool_ioctl(struct ifreq *ifr); 899 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 900 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); 901 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); 902 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 903 union ixgbe_atr_hash_dword input, 904 union ixgbe_atr_hash_dword common, 905 u8 queue); 906 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 907 union ixgbe_atr_input *input_mask); 908 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 909 union ixgbe_atr_input *input, 910 u16 soft_id, u8 queue); 911 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 912 union ixgbe_atr_input *input, 913 u16 soft_id); 914 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 915 union ixgbe_atr_input *mask); 916 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 917 struct ixgbe_fdir_filter *input, 918 u16 sw_idx); 919 void ixgbe_set_rx_mode(struct net_device *netdev); 920 #ifdef CONFIG_IXGBE_DCB 921 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); 922 #endif 923 int ixgbe_setup_tc(struct net_device *dev, u8 tc); 924 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); 925 void ixgbe_do_reset(struct net_device *netdev); 926 #ifdef CONFIG_IXGBE_HWMON 927 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); 928 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); 929 #endif /* CONFIG_IXGBE_HWMON */ 930 #ifdef IXGBE_FCOE 931 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 932 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 933 u8 *hdr_len); 934 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, 935 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); 936 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, 937 struct scatterlist *sgl, unsigned int sgc); 938 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, 939 struct scatterlist *sgl, unsigned int sgc); 940 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); 941 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 942 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 943 int ixgbe_fcoe_enable(struct net_device *netdev); 944 int ixgbe_fcoe_disable(struct net_device *netdev); 945 #ifdef CONFIG_IXGBE_DCB 946 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); 947 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); 948 #endif /* CONFIG_IXGBE_DCB */ 949 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); 950 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, 951 struct netdev_fcoe_hbainfo *info); 952 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); 953 #endif /* IXGBE_FCOE */ 954 #ifdef CONFIG_DEBUG_FS 955 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); 956 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); 957 void ixgbe_dbg_init(void); 958 void ixgbe_dbg_exit(void); 959 #else 960 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} 961 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} 962 static inline void ixgbe_dbg_init(void) {} 963 static inline void ixgbe_dbg_exit(void) {} 964 #endif /* CONFIG_DEBUG_FS */ 965 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) 966 { 967 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 968 } 969 970 void ixgbe_ptp_init(struct ixgbe_adapter *adapter); 971 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter); 972 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); 973 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); 974 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); 975 void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter); 976 void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *); 977 void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb); 978 static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring, 979 union ixgbe_adv_rx_desc *rx_desc, 980 struct sk_buff *skb) 981 { 982 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) { 983 ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb); 984 return; 985 } 986 987 if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) 988 return; 989 990 ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 991 992 /* Update the last_rx_timestamp timer in order to enable watchdog check 993 * for error case of latched timestamp on a dropped packet. 994 */ 995 rx_ring->last_rx_timestamp = jiffies; 996 } 997 998 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 999 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 1000 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); 1001 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); 1002 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter); 1003 #ifdef CONFIG_PCI_IOV 1004 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); 1005 #endif 1006 1007 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 1008 struct ixgbe_adapter *adapter, 1009 struct ixgbe_ring *tx_ring); 1010 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter); 1011 void ixgbe_store_key(struct ixgbe_adapter *adapter); 1012 void ixgbe_store_reta(struct ixgbe_adapter *adapter); 1013 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 1014 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm); 1015 #endif /* _IXGBE_H_ */ 1016