1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #ifndef _IXGBE_H_ 29 #define _IXGBE_H_ 30 31 #include <linux/bitops.h> 32 #include <linux/types.h> 33 #include <linux/pci.h> 34 #include <linux/netdevice.h> 35 #include <linux/cpumask.h> 36 #include <linux/aer.h> 37 #include <linux/if_vlan.h> 38 #include <linux/jiffies.h> 39 40 #include <linux/clocksource.h> 41 #include <linux/net_tstamp.h> 42 #include <linux/ptp_clock_kernel.h> 43 44 #include "ixgbe_type.h" 45 #include "ixgbe_common.h" 46 #include "ixgbe_dcb.h" 47 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) 48 #define IXGBE_FCOE 49 #include "ixgbe_fcoe.h" 50 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ 51 #ifdef CONFIG_IXGBE_DCA 52 #include <linux/dca.h> 53 #endif 54 55 /* common prefix used by pr_<> macros */ 56 #undef pr_fmt 57 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 58 59 /* TX/RX descriptor defines */ 60 #define IXGBE_DEFAULT_TXD 512 61 #define IXGBE_DEFAULT_TX_WORK 256 62 #define IXGBE_MAX_TXD 4096 63 #define IXGBE_MIN_TXD 64 64 65 #define IXGBE_DEFAULT_RXD 512 66 #define IXGBE_MAX_RXD 4096 67 #define IXGBE_MIN_RXD 64 68 69 /* flow control */ 70 #define IXGBE_MIN_FCRTL 0x40 71 #define IXGBE_MAX_FCRTL 0x7FF80 72 #define IXGBE_MIN_FCRTH 0x600 73 #define IXGBE_MAX_FCRTH 0x7FFF0 74 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF 75 #define IXGBE_MIN_FCPAUSE 0 76 #define IXGBE_MAX_FCPAUSE 0xFFFF 77 78 /* Supported Rx Buffer Sizes */ 79 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ 80 #define IXGBE_RXBUFFER_2K 2048 81 #define IXGBE_RXBUFFER_3K 3072 82 #define IXGBE_RXBUFFER_4K 4096 83 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 84 85 /* 86 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 87 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, 88 * this adds up to 448 bytes of extra data. 89 * 90 * Since netdev_alloc_skb now allocates a page fragment we can use a value 91 * of 256 and the resultant skb will have a truesize of 960 or less. 92 */ 93 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 94 95 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 96 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 97 98 enum ixgbe_tx_flags { 99 /* cmd_type flags */ 100 IXGBE_TX_FLAGS_HW_VLAN = 0x01, 101 IXGBE_TX_FLAGS_TSO = 0x02, 102 IXGBE_TX_FLAGS_TSTAMP = 0x04, 103 104 /* olinfo flags */ 105 IXGBE_TX_FLAGS_CC = 0x08, 106 IXGBE_TX_FLAGS_IPV4 = 0x10, 107 IXGBE_TX_FLAGS_CSUM = 0x20, 108 109 /* software defined flags */ 110 IXGBE_TX_FLAGS_SW_VLAN = 0x40, 111 IXGBE_TX_FLAGS_FCOE = 0x80, 112 }; 113 114 /* VLAN info */ 115 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 116 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 117 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 118 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 119 120 #define IXGBE_MAX_VF_MC_ENTRIES 30 121 #define IXGBE_MAX_VF_FUNCTIONS 64 122 #define IXGBE_MAX_VFTA_ENTRIES 128 123 #define MAX_EMULATION_MAC_ADDRS 16 124 #define IXGBE_MAX_PF_MACVLANS 15 125 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) 126 #define IXGBE_82599_VF_DEVICE_ID 0x10ED 127 #define IXGBE_X540_VF_DEVICE_ID 0x1515 128 129 struct vf_data_storage { 130 unsigned char vf_mac_addresses[ETH_ALEN]; 131 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 132 u16 num_vf_mc_hashes; 133 u16 default_vf_vlan_id; 134 u16 vlans_enabled; 135 bool clear_to_send; 136 bool pf_set_mac; 137 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 138 u16 pf_qos; 139 u16 tx_rate; 140 u16 vlan_count; 141 u8 spoofchk_enabled; 142 unsigned int vf_api; 143 }; 144 145 struct vf_macvlans { 146 struct list_head l; 147 int vf; 148 int rar_entry; 149 bool free; 150 bool is_macvlan; 151 u8 vf_macvlan[ETH_ALEN]; 152 }; 153 154 #define IXGBE_MAX_TXD_PWR 14 155 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) 156 157 /* Tx Descriptors needed, worst case */ 158 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 159 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 160 161 /* wrapper around a pointer to a socket buffer, 162 * so a DMA handle can be stored along with the buffer */ 163 struct ixgbe_tx_buffer { 164 union ixgbe_adv_tx_desc *next_to_watch; 165 unsigned long time_stamp; 166 struct sk_buff *skb; 167 unsigned int bytecount; 168 unsigned short gso_segs; 169 __be16 protocol; 170 DEFINE_DMA_UNMAP_ADDR(dma); 171 DEFINE_DMA_UNMAP_LEN(len); 172 u32 tx_flags; 173 }; 174 175 struct ixgbe_rx_buffer { 176 struct sk_buff *skb; 177 dma_addr_t dma; 178 struct page *page; 179 unsigned int page_offset; 180 }; 181 182 struct ixgbe_queue_stats { 183 u64 packets; 184 u64 bytes; 185 }; 186 187 struct ixgbe_tx_queue_stats { 188 u64 restart_queue; 189 u64 tx_busy; 190 u64 tx_done_old; 191 }; 192 193 struct ixgbe_rx_queue_stats { 194 u64 rsc_count; 195 u64 rsc_flush; 196 u64 non_eop_descs; 197 u64 alloc_rx_page_failed; 198 u64 alloc_rx_buff_failed; 199 u64 csum_err; 200 }; 201 202 enum ixgbe_ring_state_t { 203 __IXGBE_TX_FDIR_INIT_DONE, 204 __IXGBE_TX_XPS_INIT_DONE, 205 __IXGBE_TX_DETECT_HANG, 206 __IXGBE_HANG_CHECK_ARMED, 207 __IXGBE_RX_RSC_ENABLED, 208 __IXGBE_RX_CSUM_UDP_ZERO_ERR, 209 __IXGBE_RX_FCOE, 210 }; 211 212 #define check_for_tx_hang(ring) \ 213 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 214 #define set_check_for_tx_hang(ring) \ 215 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 216 #define clear_check_for_tx_hang(ring) \ 217 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 218 #define ring_is_rsc_enabled(ring) \ 219 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 220 #define set_ring_rsc_enabled(ring) \ 221 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 222 #define clear_ring_rsc_enabled(ring) \ 223 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 224 struct ixgbe_ring { 225 struct ixgbe_ring *next; /* pointer to next ring in q_vector */ 226 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ 227 struct net_device *netdev; /* netdev ring belongs to */ 228 struct device *dev; /* device for DMA mapping */ 229 void *desc; /* descriptor ring memory */ 230 union { 231 struct ixgbe_tx_buffer *tx_buffer_info; 232 struct ixgbe_rx_buffer *rx_buffer_info; 233 }; 234 unsigned long last_rx_timestamp; 235 unsigned long state; 236 u8 __iomem *tail; 237 dma_addr_t dma; /* phys. address of descriptor ring */ 238 unsigned int size; /* length in bytes */ 239 240 u16 count; /* amount of descriptors */ 241 242 u8 queue_index; /* needed for multiqueue queue management */ 243 u8 reg_idx; /* holds the special value that gets 244 * the hardware register offset 245 * associated with this ring, which is 246 * different for DCB and RSS modes 247 */ 248 u16 next_to_use; 249 u16 next_to_clean; 250 251 union { 252 u16 next_to_alloc; 253 struct { 254 u8 atr_sample_rate; 255 u8 atr_count; 256 }; 257 }; 258 259 u8 dcb_tc; 260 struct ixgbe_queue_stats stats; 261 struct u64_stats_sync syncp; 262 union { 263 struct ixgbe_tx_queue_stats tx_stats; 264 struct ixgbe_rx_queue_stats rx_stats; 265 }; 266 } ____cacheline_internodealigned_in_smp; 267 268 enum ixgbe_ring_f_enum { 269 RING_F_NONE = 0, 270 RING_F_VMDQ, /* SR-IOV uses the same ring feature */ 271 RING_F_RSS, 272 RING_F_FDIR, 273 #ifdef IXGBE_FCOE 274 RING_F_FCOE, 275 #endif /* IXGBE_FCOE */ 276 277 RING_F_ARRAY_SIZE /* must be last in enum set */ 278 }; 279 280 #define IXGBE_MAX_RSS_INDICES 16 281 #define IXGBE_MAX_VMDQ_INDICES 64 282 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ 283 #define IXGBE_MAX_FCOE_INDICES 8 284 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 285 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 286 struct ixgbe_ring_feature { 287 u16 limit; /* upper limit on feature indices */ 288 u16 indices; /* current value of indices */ 289 u16 mask; /* Mask used for feature to ring mapping */ 290 u16 offset; /* offset to start of feature */ 291 } ____cacheline_internodealigned_in_smp; 292 293 #define IXGBE_82599_VMDQ_8Q_MASK 0x78 294 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C 295 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E 296 297 /* 298 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since 299 * this is twice the size of a half page we need to double the page order 300 * for FCoE enabled Rx queues. 301 */ 302 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) 303 { 304 #ifdef IXGBE_FCOE 305 if (test_bit(__IXGBE_RX_FCOE, &ring->state)) 306 return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K : 307 IXGBE_RXBUFFER_3K; 308 #endif 309 return IXGBE_RXBUFFER_2K; 310 } 311 312 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) 313 { 314 #ifdef IXGBE_FCOE 315 if (test_bit(__IXGBE_RX_FCOE, &ring->state)) 316 return (PAGE_SIZE < 8192) ? 1 : 0; 317 #endif 318 return 0; 319 } 320 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) 321 322 struct ixgbe_ring_container { 323 struct ixgbe_ring *ring; /* pointer to linked list of rings */ 324 unsigned int total_bytes; /* total bytes processed this int */ 325 unsigned int total_packets; /* total packets processed this int */ 326 u16 work_limit; /* total work allowed per interrupt */ 327 u8 count; /* total number of rings in vector */ 328 u8 itr; /* current ITR setting for ring */ 329 }; 330 331 /* iterator for handling rings in ring container */ 332 #define ixgbe_for_each_ring(pos, head) \ 333 for (pos = (head).ring; pos != NULL; pos = pos->next) 334 335 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ 336 ? 8 : 1) 337 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS 338 339 /* MAX_Q_VECTORS of these are allocated, 340 * but we only use one per queue-specific vector. 341 */ 342 struct ixgbe_q_vector { 343 struct ixgbe_adapter *adapter; 344 #ifdef CONFIG_IXGBE_DCA 345 int cpu; /* CPU for DCA */ 346 #endif 347 u16 v_idx; /* index of q_vector within array, also used for 348 * finding the bit in EICR and friends that 349 * represents the vector for this ring */ 350 u16 itr; /* Interrupt throttle rate written to EITR */ 351 struct ixgbe_ring_container rx, tx; 352 353 struct napi_struct napi; 354 cpumask_t affinity_mask; 355 int numa_node; 356 struct rcu_head rcu; /* to avoid race with update stats on free */ 357 char name[IFNAMSIZ + 9]; 358 359 /* for dynamic allocation of rings associated with this q_vector */ 360 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; 361 }; 362 #ifdef CONFIG_IXGBE_HWMON 363 364 #define IXGBE_HWMON_TYPE_LOC 0 365 #define IXGBE_HWMON_TYPE_TEMP 1 366 #define IXGBE_HWMON_TYPE_CAUTION 2 367 #define IXGBE_HWMON_TYPE_MAX 3 368 369 struct hwmon_attr { 370 struct device_attribute dev_attr; 371 struct ixgbe_hw *hw; 372 struct ixgbe_thermal_diode_data *sensor; 373 char name[12]; 374 }; 375 376 struct hwmon_buff { 377 struct device *device; 378 struct hwmon_attr *hwmon_list; 379 unsigned int n_hwmon; 380 }; 381 #endif /* CONFIG_IXGBE_HWMON */ 382 383 /* 384 * microsecond values for various ITR rates shifted by 2 to fit itr register 385 * with the first 3 bits reserved 0 386 */ 387 #define IXGBE_MIN_RSC_ITR 24 388 #define IXGBE_100K_ITR 40 389 #define IXGBE_20K_ITR 200 390 #define IXGBE_10K_ITR 400 391 #define IXGBE_8K_ITR 500 392 393 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ 394 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, 395 const u32 stat_err_bits) 396 { 397 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 398 } 399 400 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) 401 { 402 u16 ntc = ring->next_to_clean; 403 u16 ntu = ring->next_to_use; 404 405 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 406 } 407 408 #define IXGBE_RX_DESC(R, i) \ 409 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 410 #define IXGBE_TX_DESC(R, i) \ 411 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 412 #define IXGBE_TX_CTXTDESC(R, i) \ 413 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 414 415 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ 416 #ifdef IXGBE_FCOE 417 /* Use 3K as the baby jumbo frame size for FCoE */ 418 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 419 #endif /* IXGBE_FCOE */ 420 421 #define OTHER_VECTOR 1 422 #define NON_Q_VECTORS (OTHER_VECTOR) 423 424 #define MAX_MSIX_VECTORS_82599 64 425 #define MAX_Q_VECTORS_82599 64 426 #define MAX_MSIX_VECTORS_82598 18 427 #define MAX_Q_VECTORS_82598 16 428 429 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 430 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 431 432 #define MIN_MSIX_Q_VECTORS 1 433 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 434 435 /* default to trying for four seconds */ 436 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 437 438 /* board specific private data structure */ 439 struct ixgbe_adapter { 440 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 441 /* OS defined structs */ 442 struct net_device *netdev; 443 struct pci_dev *pdev; 444 445 unsigned long state; 446 447 /* Some features need tri-state capability, 448 * thus the additional *_CAPABLE flags. 449 */ 450 u32 flags; 451 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 0) 452 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1) 453 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 2) 454 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3) 455 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4) 456 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5) 457 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6) 458 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 7) 459 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8) 460 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9) 461 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10) 462 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11) 463 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12) 464 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13) 465 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14) 466 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15) 467 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16) 468 #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17) 469 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18) 470 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19) 471 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20) 472 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21) 473 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22) 474 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23) 475 476 u32 flags2; 477 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0) 478 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) 479 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) 480 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3) 481 #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4) 482 #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5) 483 #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6) 484 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7) 485 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8) 486 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9) 487 #define IXGBE_FLAG2_PTP_ENABLED (u32)(1 << 10) 488 #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 11) 489 #define IXGBE_FLAG2_BRIDGE_MODE_VEB (u32)(1 << 12) 490 491 /* Tx fast path data */ 492 int num_tx_queues; 493 u16 tx_itr_setting; 494 u16 tx_work_limit; 495 496 /* Rx fast path data */ 497 int num_rx_queues; 498 u16 rx_itr_setting; 499 500 /* TX */ 501 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; 502 503 u64 restart_queue; 504 u64 lsc_int; 505 u32 tx_timeout_count; 506 507 /* RX */ 508 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; 509 int num_rx_pools; /* == num_rx_queues in 82598 */ 510 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ 511 u64 hw_csum_rx_error; 512 u64 hw_rx_no_dma_resources; 513 u64 rsc_total_count; 514 u64 rsc_total_flush; 515 u64 non_eop_descs; 516 u32 alloc_rx_page_failed; 517 u32 alloc_rx_buff_failed; 518 519 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; 520 521 /* DCB parameters */ 522 struct ieee_pfc *ixgbe_ieee_pfc; 523 struct ieee_ets *ixgbe_ieee_ets; 524 struct ixgbe_dcb_config dcb_cfg; 525 struct ixgbe_dcb_config temp_dcb_cfg; 526 u8 dcb_set_bitmap; 527 u8 dcbx_cap; 528 enum ixgbe_fc_mode last_lfc_mode; 529 530 int num_q_vectors; /* current number of q_vectors for device */ 531 int max_q_vectors; /* true count of q_vectors for device */ 532 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; 533 struct msix_entry *msix_entries; 534 535 u32 test_icr; 536 struct ixgbe_ring test_tx_ring; 537 struct ixgbe_ring test_rx_ring; 538 539 /* structs defined in ixgbe_hw.h */ 540 struct ixgbe_hw hw; 541 u16 msg_enable; 542 struct ixgbe_hw_stats stats; 543 544 u64 tx_busy; 545 unsigned int tx_ring_count; 546 unsigned int rx_ring_count; 547 548 u32 link_speed; 549 bool link_up; 550 unsigned long link_check_timeout; 551 552 struct timer_list service_timer; 553 struct work_struct service_task; 554 555 struct hlist_head fdir_filter_list; 556 unsigned long fdir_overflow; /* number of times ATR was backed off */ 557 union ixgbe_atr_input fdir_mask; 558 int fdir_filter_count; 559 u32 fdir_pballoc; 560 u32 atr_sample_rate; 561 spinlock_t fdir_perfect_lock; 562 563 #ifdef IXGBE_FCOE 564 struct ixgbe_fcoe fcoe; 565 #endif /* IXGBE_FCOE */ 566 u32 wol; 567 568 u16 bd_number; 569 570 u16 eeprom_verh; 571 u16 eeprom_verl; 572 u16 eeprom_cap; 573 574 u32 interrupt_event; 575 u32 led_reg; 576 577 struct ptp_clock *ptp_clock; 578 struct ptp_clock_info ptp_caps; 579 struct work_struct ptp_tx_work; 580 struct sk_buff *ptp_tx_skb; 581 unsigned long ptp_tx_start; 582 unsigned long last_overflow_check; 583 unsigned long last_rx_ptp_check; 584 spinlock_t tmreg_lock; 585 struct cyclecounter cc; 586 struct timecounter tc; 587 u32 base_incval; 588 589 /* SR-IOV */ 590 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 591 unsigned int num_vfs; 592 struct vf_data_storage *vfinfo; 593 int vf_rate_link_speed; 594 struct vf_macvlans vf_mvs; 595 struct vf_macvlans *mv_list; 596 597 u32 timer_event_accumulator; 598 u32 vferr_refcount; 599 struct kobject *info_kobj; 600 #ifdef CONFIG_IXGBE_HWMON 601 struct hwmon_buff ixgbe_hwmon_buff; 602 #endif /* CONFIG_IXGBE_HWMON */ 603 #ifdef CONFIG_DEBUG_FS 604 struct dentry *ixgbe_dbg_adapter; 605 #endif /*CONFIG_DEBUG_FS*/ 606 607 u8 default_up; 608 }; 609 610 struct ixgbe_fdir_filter { 611 struct hlist_node fdir_node; 612 union ixgbe_atr_input filter; 613 u16 sw_idx; 614 u16 action; 615 }; 616 617 enum ixgbe_state_t { 618 __IXGBE_TESTING, 619 __IXGBE_RESETTING, 620 __IXGBE_DOWN, 621 __IXGBE_SERVICE_SCHED, 622 __IXGBE_IN_SFP_INIT, 623 __IXGBE_READ_I2C, 624 }; 625 626 struct ixgbe_cb { 627 union { /* Union defining head/tail partner */ 628 struct sk_buff *head; 629 struct sk_buff *tail; 630 }; 631 dma_addr_t dma; 632 u16 append_cnt; 633 bool page_released; 634 }; 635 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) 636 637 enum ixgbe_boards { 638 board_82598, 639 board_82599, 640 board_X540, 641 }; 642 643 extern struct ixgbe_info ixgbe_82598_info; 644 extern struct ixgbe_info ixgbe_82599_info; 645 extern struct ixgbe_info ixgbe_X540_info; 646 #ifdef CONFIG_IXGBE_DCB 647 extern const struct dcbnl_rtnl_ops dcbnl_ops; 648 #endif 649 650 extern char ixgbe_driver_name[]; 651 extern const char ixgbe_driver_version[]; 652 #ifdef IXGBE_FCOE 653 extern char ixgbe_default_device_descr[]; 654 #endif /* IXGBE_FCOE */ 655 656 extern void ixgbe_up(struct ixgbe_adapter *adapter); 657 extern void ixgbe_down(struct ixgbe_adapter *adapter); 658 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); 659 extern void ixgbe_reset(struct ixgbe_adapter *adapter); 660 extern void ixgbe_set_ethtool_ops(struct net_device *netdev); 661 extern int ixgbe_setup_rx_resources(struct ixgbe_ring *); 662 extern int ixgbe_setup_tx_resources(struct ixgbe_ring *); 663 extern void ixgbe_free_rx_resources(struct ixgbe_ring *); 664 extern void ixgbe_free_tx_resources(struct ixgbe_ring *); 665 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *); 666 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *); 667 extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 668 struct ixgbe_ring *); 669 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter); 670 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); 671 extern int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 672 u16 subdevice_id); 673 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); 674 extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, 675 struct ixgbe_adapter *, 676 struct ixgbe_ring *); 677 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, 678 struct ixgbe_tx_buffer *); 679 extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); 680 extern void ixgbe_write_eitr(struct ixgbe_q_vector *); 681 extern int ixgbe_poll(struct napi_struct *napi, int budget); 682 extern int ethtool_ioctl(struct ifreq *ifr); 683 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 684 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); 685 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); 686 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 687 union ixgbe_atr_hash_dword input, 688 union ixgbe_atr_hash_dword common, 689 u8 queue); 690 extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 691 union ixgbe_atr_input *input_mask); 692 extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 693 union ixgbe_atr_input *input, 694 u16 soft_id, u8 queue); 695 extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 696 union ixgbe_atr_input *input, 697 u16 soft_id); 698 extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 699 union ixgbe_atr_input *mask); 700 extern bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw); 701 extern void ixgbe_set_rx_mode(struct net_device *netdev); 702 #ifdef CONFIG_IXGBE_DCB 703 extern void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); 704 #endif 705 extern int ixgbe_setup_tc(struct net_device *dev, u8 tc); 706 extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); 707 extern void ixgbe_do_reset(struct net_device *netdev); 708 #ifdef CONFIG_IXGBE_HWMON 709 extern void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); 710 extern int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); 711 #endif /* CONFIG_IXGBE_HWMON */ 712 #ifdef IXGBE_FCOE 713 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 714 extern int ixgbe_fso(struct ixgbe_ring *tx_ring, 715 struct ixgbe_tx_buffer *first, 716 u8 *hdr_len); 717 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, 718 union ixgbe_adv_rx_desc *rx_desc, 719 struct sk_buff *skb); 720 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, 721 struct scatterlist *sgl, unsigned int sgc); 722 extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, 723 struct scatterlist *sgl, unsigned int sgc); 724 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); 725 extern int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 726 extern void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 727 extern int ixgbe_fcoe_enable(struct net_device *netdev); 728 extern int ixgbe_fcoe_disable(struct net_device *netdev); 729 #ifdef CONFIG_IXGBE_DCB 730 extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); 731 extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); 732 #endif /* CONFIG_IXGBE_DCB */ 733 extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); 734 extern int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, 735 struct netdev_fcoe_hbainfo *info); 736 extern u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); 737 #endif /* IXGBE_FCOE */ 738 #ifdef CONFIG_DEBUG_FS 739 extern void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); 740 extern void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); 741 extern void ixgbe_dbg_init(void); 742 extern void ixgbe_dbg_exit(void); 743 #endif /* CONFIG_DEBUG_FS */ 744 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) 745 { 746 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 747 } 748 749 extern void ixgbe_ptp_init(struct ixgbe_adapter *adapter); 750 extern void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); 751 extern void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); 752 extern void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); 753 extern void __ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector *q_vector, 754 struct sk_buff *skb); 755 static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring, 756 union ixgbe_adv_rx_desc *rx_desc, 757 struct sk_buff *skb) 758 { 759 if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) 760 return; 761 762 __ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, skb); 763 764 /* 765 * Update the last_rx_timestamp timer in order to enable watchdog check 766 * for error case of latched timestamp on a dropped packet. 767 */ 768 rx_ring->last_rx_timestamp = jiffies; 769 } 770 771 extern int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter, 772 struct ifreq *ifr, int cmd); 773 extern void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); 774 extern void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); 775 extern void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr); 776 #ifdef CONFIG_PCI_IOV 777 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); 778 #endif 779 780 #endif /* _IXGBE_H_ */ 781