1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #ifndef _IXGBE_H_ 5 #define _IXGBE_H_ 6 7 #include <linux/bitops.h> 8 #include <linux/types.h> 9 #include <linux/pci.h> 10 #include <linux/netdevice.h> 11 #include <linux/cpumask.h> 12 #include <linux/aer.h> 13 #include <linux/if_vlan.h> 14 #include <linux/jiffies.h> 15 #include <linux/phy.h> 16 17 #include <linux/timecounter.h> 18 #include <linux/net_tstamp.h> 19 #include <linux/ptp_clock_kernel.h> 20 21 #include "ixgbe_type.h" 22 #include "ixgbe_common.h" 23 #include "ixgbe_dcb.h" 24 #if IS_ENABLED(CONFIG_FCOE) 25 #define IXGBE_FCOE 26 #include "ixgbe_fcoe.h" 27 #endif /* IS_ENABLED(CONFIG_FCOE) */ 28 #ifdef CONFIG_IXGBE_DCA 29 #include <linux/dca.h> 30 #endif 31 #include "ixgbe_ipsec.h" 32 33 #include <net/xdp.h> 34 35 /* common prefix used by pr_<> macros */ 36 #undef pr_fmt 37 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 38 39 /* TX/RX descriptor defines */ 40 #define IXGBE_DEFAULT_TXD 512 41 #define IXGBE_DEFAULT_TX_WORK 256 42 #define IXGBE_MAX_TXD 4096 43 #define IXGBE_MIN_TXD 64 44 45 #if (PAGE_SIZE < 8192) 46 #define IXGBE_DEFAULT_RXD 512 47 #else 48 #define IXGBE_DEFAULT_RXD 128 49 #endif 50 #define IXGBE_MAX_RXD 4096 51 #define IXGBE_MIN_RXD 64 52 53 /* flow control */ 54 #define IXGBE_MIN_FCRTL 0x40 55 #define IXGBE_MAX_FCRTL 0x7FF80 56 #define IXGBE_MIN_FCRTH 0x600 57 #define IXGBE_MAX_FCRTH 0x7FFF0 58 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF 59 #define IXGBE_MIN_FCPAUSE 0 60 #define IXGBE_MAX_FCPAUSE 0xFFFF 61 62 /* Supported Rx Buffer Sizes */ 63 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ 64 #define IXGBE_RXBUFFER_1536 1536 65 #define IXGBE_RXBUFFER_2K 2048 66 #define IXGBE_RXBUFFER_3K 3072 67 #define IXGBE_RXBUFFER_4K 4096 68 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 69 70 /* Attempt to maximize the headroom available for incoming frames. We 71 * use a 2K buffer for receives and need 1536/1534 to store the data for 72 * the frame. This leaves us with 512 bytes of room. From that we need 73 * to deduct the space needed for the shared info and the padding needed 74 * to IP align the frame. 75 * 76 * Note: For cache line sizes 256 or larger this value is going to end 77 * up negative. In these cases we should fall back to the 3K 78 * buffers. 79 */ 80 #if (PAGE_SIZE < 8192) 81 #define IXGBE_MAX_2K_FRAME_BUILD_SKB (IXGBE_RXBUFFER_1536 - NET_IP_ALIGN) 82 #define IXGBE_2K_TOO_SMALL_WITH_PADDING \ 83 ((NET_SKB_PAD + IXGBE_RXBUFFER_1536) > SKB_WITH_OVERHEAD(IXGBE_RXBUFFER_2K)) 84 85 static inline int ixgbe_compute_pad(int rx_buf_len) 86 { 87 int page_size, pad_size; 88 89 page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2); 90 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len; 91 92 return pad_size; 93 } 94 95 static inline int ixgbe_skb_pad(void) 96 { 97 int rx_buf_len; 98 99 /* If a 2K buffer cannot handle a standard Ethernet frame then 100 * optimize padding for a 3K buffer instead of a 1.5K buffer. 101 * 102 * For a 3K buffer we need to add enough padding to allow for 103 * tailroom due to NET_IP_ALIGN possibly shifting us out of 104 * cache-line alignment. 105 */ 106 if (IXGBE_2K_TOO_SMALL_WITH_PADDING) 107 rx_buf_len = IXGBE_RXBUFFER_3K + SKB_DATA_ALIGN(NET_IP_ALIGN); 108 else 109 rx_buf_len = IXGBE_RXBUFFER_1536; 110 111 /* if needed make room for NET_IP_ALIGN */ 112 rx_buf_len -= NET_IP_ALIGN; 113 114 return ixgbe_compute_pad(rx_buf_len); 115 } 116 117 #define IXGBE_SKB_PAD ixgbe_skb_pad() 118 #else 119 #define IXGBE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 120 #endif 121 122 /* 123 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 124 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, 125 * this adds up to 448 bytes of extra data. 126 * 127 * Since netdev_alloc_skb now allocates a page fragment we can use a value 128 * of 256 and the resultant skb will have a truesize of 960 or less. 129 */ 130 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 131 132 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 133 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 134 135 #define IXGBE_RX_DMA_ATTR \ 136 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 137 138 enum ixgbe_tx_flags { 139 /* cmd_type flags */ 140 IXGBE_TX_FLAGS_HW_VLAN = 0x01, 141 IXGBE_TX_FLAGS_TSO = 0x02, 142 IXGBE_TX_FLAGS_TSTAMP = 0x04, 143 144 /* olinfo flags */ 145 IXGBE_TX_FLAGS_CC = 0x08, 146 IXGBE_TX_FLAGS_IPV4 = 0x10, 147 IXGBE_TX_FLAGS_CSUM = 0x20, 148 IXGBE_TX_FLAGS_IPSEC = 0x40, 149 150 /* software defined flags */ 151 IXGBE_TX_FLAGS_SW_VLAN = 0x80, 152 IXGBE_TX_FLAGS_FCOE = 0x100, 153 }; 154 155 /* VLAN info */ 156 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 157 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 158 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 159 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 160 161 #define IXGBE_MAX_VF_MC_ENTRIES 30 162 #define IXGBE_MAX_VF_FUNCTIONS 64 163 #define IXGBE_MAX_VFTA_ENTRIES 128 164 #define MAX_EMULATION_MAC_ADDRS 16 165 #define IXGBE_MAX_PF_MACVLANS 15 166 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) 167 #define IXGBE_82599_VF_DEVICE_ID 0x10ED 168 #define IXGBE_X540_VF_DEVICE_ID 0x1515 169 170 #define UPDATE_VF_COUNTER_32bit(reg, last_counter, counter) \ 171 { \ 172 u32 current_counter = IXGBE_READ_REG(hw, reg); \ 173 if (current_counter < last_counter) \ 174 counter += 0x100000000LL; \ 175 last_counter = current_counter; \ 176 counter &= 0xFFFFFFFF00000000LL; \ 177 counter |= current_counter; \ 178 } 179 180 #define UPDATE_VF_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \ 181 { \ 182 u64 current_counter_lsb = IXGBE_READ_REG(hw, reg_lsb); \ 183 u64 current_counter_msb = IXGBE_READ_REG(hw, reg_msb); \ 184 u64 current_counter = (current_counter_msb << 32) | \ 185 current_counter_lsb; \ 186 if (current_counter < last_counter) \ 187 counter += 0x1000000000LL; \ 188 last_counter = current_counter; \ 189 counter &= 0xFFFFFFF000000000LL; \ 190 counter |= current_counter; \ 191 } 192 193 struct vf_stats { 194 u64 gprc; 195 u64 gorc; 196 u64 gptc; 197 u64 gotc; 198 u64 mprc; 199 }; 200 201 struct vf_data_storage { 202 struct pci_dev *vfdev; 203 unsigned char vf_mac_addresses[ETH_ALEN]; 204 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 205 u16 num_vf_mc_hashes; 206 bool clear_to_send; 207 struct vf_stats vfstats; 208 struct vf_stats last_vfstats; 209 struct vf_stats saved_rst_vfstats; 210 bool pf_set_mac; 211 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 212 u16 pf_qos; 213 u16 tx_rate; 214 int link_enable; 215 int link_state; 216 u8 spoofchk_enabled; 217 bool rss_query_enabled; 218 u8 trusted; 219 int xcast_mode; 220 unsigned int vf_api; 221 u8 primary_abort_count; 222 }; 223 224 enum ixgbevf_xcast_modes { 225 IXGBEVF_XCAST_MODE_NONE = 0, 226 IXGBEVF_XCAST_MODE_MULTI, 227 IXGBEVF_XCAST_MODE_ALLMULTI, 228 IXGBEVF_XCAST_MODE_PROMISC, 229 }; 230 231 struct vf_macvlans { 232 struct list_head l; 233 int vf; 234 bool free; 235 bool is_macvlan; 236 u8 vf_macvlan[ETH_ALEN]; 237 }; 238 239 #define IXGBE_MAX_TXD_PWR 14 240 #define IXGBE_MAX_DATA_PER_TXD (1u << IXGBE_MAX_TXD_PWR) 241 242 /* Tx Descriptors needed, worst case */ 243 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 244 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 245 246 /* wrapper around a pointer to a socket buffer, 247 * so a DMA handle can be stored along with the buffer */ 248 struct ixgbe_tx_buffer { 249 union ixgbe_adv_tx_desc *next_to_watch; 250 unsigned long time_stamp; 251 union { 252 struct sk_buff *skb; 253 struct xdp_frame *xdpf; 254 }; 255 unsigned int bytecount; 256 unsigned short gso_segs; 257 __be16 protocol; 258 DEFINE_DMA_UNMAP_ADDR(dma); 259 DEFINE_DMA_UNMAP_LEN(len); 260 u32 tx_flags; 261 }; 262 263 struct ixgbe_rx_buffer { 264 union { 265 struct { 266 struct sk_buff *skb; 267 dma_addr_t dma; 268 struct page *page; 269 __u32 page_offset; 270 __u16 pagecnt_bias; 271 }; 272 struct { 273 bool discard; 274 struct xdp_buff *xdp; 275 }; 276 }; 277 }; 278 279 struct ixgbe_queue_stats { 280 u64 packets; 281 u64 bytes; 282 }; 283 284 struct ixgbe_tx_queue_stats { 285 u64 restart_queue; 286 u64 tx_busy; 287 u64 tx_done_old; 288 }; 289 290 struct ixgbe_rx_queue_stats { 291 u64 rsc_count; 292 u64 rsc_flush; 293 u64 non_eop_descs; 294 u64 alloc_rx_page; 295 u64 alloc_rx_page_failed; 296 u64 alloc_rx_buff_failed; 297 u64 csum_err; 298 }; 299 300 #define IXGBE_TS_HDR_LEN 8 301 302 enum ixgbe_ring_state_t { 303 __IXGBE_RX_3K_BUFFER, 304 __IXGBE_RX_BUILD_SKB_ENABLED, 305 __IXGBE_RX_RSC_ENABLED, 306 __IXGBE_RX_CSUM_UDP_ZERO_ERR, 307 __IXGBE_RX_FCOE, 308 __IXGBE_TX_FDIR_INIT_DONE, 309 __IXGBE_TX_XPS_INIT_DONE, 310 __IXGBE_TX_DETECT_HANG, 311 __IXGBE_HANG_CHECK_ARMED, 312 __IXGBE_TX_XDP_RING, 313 __IXGBE_TX_DISABLED, 314 }; 315 316 #define ring_uses_build_skb(ring) \ 317 test_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &(ring)->state) 318 319 struct ixgbe_fwd_adapter { 320 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 321 struct net_device *netdev; 322 unsigned int tx_base_queue; 323 unsigned int rx_base_queue; 324 int pool; 325 }; 326 327 #define check_for_tx_hang(ring) \ 328 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 329 #define set_check_for_tx_hang(ring) \ 330 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 331 #define clear_check_for_tx_hang(ring) \ 332 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 333 #define ring_is_rsc_enabled(ring) \ 334 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 335 #define set_ring_rsc_enabled(ring) \ 336 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 337 #define clear_ring_rsc_enabled(ring) \ 338 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 339 #define ring_is_xdp(ring) \ 340 test_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 341 #define set_ring_xdp(ring) \ 342 set_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 343 #define clear_ring_xdp(ring) \ 344 clear_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 345 struct ixgbe_ring { 346 struct ixgbe_ring *next; /* pointer to next ring in q_vector */ 347 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ 348 struct net_device *netdev; /* netdev ring belongs to */ 349 struct bpf_prog *xdp_prog; 350 struct device *dev; /* device for DMA mapping */ 351 void *desc; /* descriptor ring memory */ 352 union { 353 struct ixgbe_tx_buffer *tx_buffer_info; 354 struct ixgbe_rx_buffer *rx_buffer_info; 355 }; 356 unsigned long state; 357 u8 __iomem *tail; 358 dma_addr_t dma; /* phys. address of descriptor ring */ 359 unsigned int size; /* length in bytes */ 360 361 u16 count; /* amount of descriptors */ 362 363 u8 queue_index; /* needed for multiqueue queue management */ 364 u8 reg_idx; /* holds the special value that gets 365 * the hardware register offset 366 * associated with this ring, which is 367 * different for DCB and RSS modes 368 */ 369 u16 next_to_use; 370 u16 next_to_clean; 371 372 unsigned long last_rx_timestamp; 373 374 union { 375 u16 next_to_alloc; 376 struct { 377 u8 atr_sample_rate; 378 u8 atr_count; 379 }; 380 }; 381 382 u8 dcb_tc; 383 struct ixgbe_queue_stats stats; 384 struct u64_stats_sync syncp; 385 union { 386 struct ixgbe_tx_queue_stats tx_stats; 387 struct ixgbe_rx_queue_stats rx_stats; 388 }; 389 u16 rx_offset; 390 struct xdp_rxq_info xdp_rxq; 391 spinlock_t tx_lock; /* used in XDP mode */ 392 struct xsk_buff_pool *xsk_pool; 393 u16 ring_idx; /* {rx,tx,xdp}_ring back reference idx */ 394 u16 rx_buf_len; 395 } ____cacheline_internodealigned_in_smp; 396 397 enum ixgbe_ring_f_enum { 398 RING_F_NONE = 0, 399 RING_F_VMDQ, /* SR-IOV uses the same ring feature */ 400 RING_F_RSS, 401 RING_F_FDIR, 402 #ifdef IXGBE_FCOE 403 RING_F_FCOE, 404 #endif /* IXGBE_FCOE */ 405 406 RING_F_ARRAY_SIZE /* must be last in enum set */ 407 }; 408 409 #define IXGBE_MAX_RSS_INDICES 16 410 #define IXGBE_MAX_RSS_INDICES_X550 63 411 #define IXGBE_MAX_VMDQ_INDICES 64 412 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ 413 #define IXGBE_MAX_FCOE_INDICES 8 414 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 415 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 416 #define IXGBE_MAX_XDP_QS (IXGBE_MAX_FDIR_INDICES + 1) 417 #define IXGBE_MAX_L2A_QUEUES 4 418 #define IXGBE_BAD_L2A_QUEUE 3 419 #define IXGBE_MAX_MACVLANS 63 420 421 DECLARE_STATIC_KEY_FALSE(ixgbe_xdp_locking_key); 422 423 struct ixgbe_ring_feature { 424 u16 limit; /* upper limit on feature indices */ 425 u16 indices; /* current value of indices */ 426 u16 mask; /* Mask used for feature to ring mapping */ 427 u16 offset; /* offset to start of feature */ 428 } ____cacheline_internodealigned_in_smp; 429 430 #define IXGBE_82599_VMDQ_8Q_MASK 0x78 431 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C 432 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E 433 434 /* 435 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since 436 * this is twice the size of a half page we need to double the page order 437 * for FCoE enabled Rx queues. 438 */ 439 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) 440 { 441 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 442 return IXGBE_RXBUFFER_3K; 443 #if (PAGE_SIZE < 8192) 444 if (ring_uses_build_skb(ring)) 445 return IXGBE_MAX_2K_FRAME_BUILD_SKB; 446 #endif 447 return IXGBE_RXBUFFER_2K; 448 } 449 450 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) 451 { 452 #if (PAGE_SIZE < 8192) 453 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 454 return 1; 455 #endif 456 return 0; 457 } 458 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) 459 460 #define IXGBE_ITR_ADAPTIVE_MIN_INC 2 461 #define IXGBE_ITR_ADAPTIVE_MIN_USECS 10 462 #define IXGBE_ITR_ADAPTIVE_MAX_USECS 126 463 #define IXGBE_ITR_ADAPTIVE_LATENCY 0x80 464 #define IXGBE_ITR_ADAPTIVE_BULK 0x00 465 466 struct ixgbe_ring_container { 467 struct ixgbe_ring *ring; /* pointer to linked list of rings */ 468 unsigned long next_update; /* jiffies value of last update */ 469 unsigned int total_bytes; /* total bytes processed this int */ 470 unsigned int total_packets; /* total packets processed this int */ 471 u16 work_limit; /* total work allowed per interrupt */ 472 u8 count; /* total number of rings in vector */ 473 u8 itr; /* current ITR setting for ring */ 474 }; 475 476 /* iterator for handling rings in ring container */ 477 #define ixgbe_for_each_ring(pos, head) \ 478 for (pos = (head).ring; pos != NULL; pos = pos->next) 479 480 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ 481 ? 8 : 1) 482 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS 483 484 /* MAX_Q_VECTORS of these are allocated, 485 * but we only use one per queue-specific vector. 486 */ 487 struct ixgbe_q_vector { 488 struct ixgbe_adapter *adapter; 489 #ifdef CONFIG_IXGBE_DCA 490 int cpu; /* CPU for DCA */ 491 #endif 492 u16 v_idx; /* index of q_vector within array, also used for 493 * finding the bit in EICR and friends that 494 * represents the vector for this ring */ 495 u16 itr; /* Interrupt throttle rate written to EITR */ 496 struct ixgbe_ring_container rx, tx; 497 498 struct napi_struct napi; 499 cpumask_t affinity_mask; 500 int numa_node; 501 struct rcu_head rcu; /* to avoid race with update stats on free */ 502 char name[IFNAMSIZ + 9]; 503 504 /* for dynamic allocation of rings associated with this q_vector */ 505 struct ixgbe_ring ring[] ____cacheline_internodealigned_in_smp; 506 }; 507 508 #ifdef CONFIG_IXGBE_HWMON 509 510 #define IXGBE_HWMON_TYPE_LOC 0 511 #define IXGBE_HWMON_TYPE_TEMP 1 512 #define IXGBE_HWMON_TYPE_CAUTION 2 513 #define IXGBE_HWMON_TYPE_MAX 3 514 515 struct hwmon_attr { 516 struct device_attribute dev_attr; 517 struct ixgbe_hw *hw; 518 struct ixgbe_thermal_diode_data *sensor; 519 char name[12]; 520 }; 521 522 struct hwmon_buff { 523 struct attribute_group group; 524 const struct attribute_group *groups[2]; 525 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; 526 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; 527 unsigned int n_hwmon; 528 }; 529 #endif /* CONFIG_IXGBE_HWMON */ 530 531 /* 532 * microsecond values for various ITR rates shifted by 2 to fit itr register 533 * with the first 3 bits reserved 0 534 */ 535 #define IXGBE_MIN_RSC_ITR 24 536 #define IXGBE_100K_ITR 40 537 #define IXGBE_20K_ITR 200 538 #define IXGBE_12K_ITR 336 539 540 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ 541 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, 542 const u32 stat_err_bits) 543 { 544 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 545 } 546 547 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) 548 { 549 u16 ntc = ring->next_to_clean; 550 u16 ntu = ring->next_to_use; 551 552 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 553 } 554 555 #define IXGBE_RX_DESC(R, i) \ 556 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 557 #define IXGBE_TX_DESC(R, i) \ 558 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 559 #define IXGBE_TX_CTXTDESC(R, i) \ 560 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 561 562 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ 563 #ifdef IXGBE_FCOE 564 /* Use 3K as the baby jumbo frame size for FCoE */ 565 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 566 #endif /* IXGBE_FCOE */ 567 568 #define OTHER_VECTOR 1 569 #define NON_Q_VECTORS (OTHER_VECTOR) 570 571 #define MAX_MSIX_VECTORS_82599 64 572 #define MAX_Q_VECTORS_82599 64 573 #define MAX_MSIX_VECTORS_82598 18 574 #define MAX_Q_VECTORS_82598 16 575 576 struct ixgbe_mac_addr { 577 u8 addr[ETH_ALEN]; 578 u16 pool; 579 u16 state; /* bitmask */ 580 }; 581 582 #define IXGBE_MAC_STATE_DEFAULT 0x1 583 #define IXGBE_MAC_STATE_MODIFIED 0x2 584 #define IXGBE_MAC_STATE_IN_USE 0x4 585 586 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 587 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 588 589 #define MIN_MSIX_Q_VECTORS 1 590 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 591 592 /* default to trying for four seconds */ 593 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 594 #define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */ 595 596 #define IXGBE_PRIMARY_ABORT_LIMIT 5 597 598 /* board specific private data structure */ 599 struct ixgbe_adapter { 600 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 601 /* OS defined structs */ 602 struct net_device *netdev; 603 struct bpf_prog *xdp_prog; 604 struct pci_dev *pdev; 605 struct mii_bus *mii_bus; 606 607 unsigned long state; 608 609 /* Some features need tri-state capability, 610 * thus the additional *_CAPABLE flags. 611 */ 612 u32 flags; 613 #define IXGBE_FLAG_MSI_ENABLED BIT(1) 614 #define IXGBE_FLAG_MSIX_ENABLED BIT(3) 615 #define IXGBE_FLAG_RX_1BUF_CAPABLE BIT(4) 616 #define IXGBE_FLAG_RX_PS_CAPABLE BIT(5) 617 #define IXGBE_FLAG_RX_PS_ENABLED BIT(6) 618 #define IXGBE_FLAG_DCA_ENABLED BIT(8) 619 #define IXGBE_FLAG_DCA_CAPABLE BIT(9) 620 #define IXGBE_FLAG_IMIR_ENABLED BIT(10) 621 #define IXGBE_FLAG_MQ_CAPABLE BIT(11) 622 #define IXGBE_FLAG_DCB_ENABLED BIT(12) 623 #define IXGBE_FLAG_VMDQ_CAPABLE BIT(13) 624 #define IXGBE_FLAG_VMDQ_ENABLED BIT(14) 625 #define IXGBE_FLAG_FAN_FAIL_CAPABLE BIT(15) 626 #define IXGBE_FLAG_NEED_LINK_UPDATE BIT(16) 627 #define IXGBE_FLAG_NEED_LINK_CONFIG BIT(17) 628 #define IXGBE_FLAG_FDIR_HASH_CAPABLE BIT(18) 629 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE BIT(19) 630 #define IXGBE_FLAG_FCOE_CAPABLE BIT(20) 631 #define IXGBE_FLAG_FCOE_ENABLED BIT(21) 632 #define IXGBE_FLAG_SRIOV_CAPABLE BIT(22) 633 #define IXGBE_FLAG_SRIOV_ENABLED BIT(23) 634 #define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25) 635 #define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26) 636 #define IXGBE_FLAG_DCB_CAPABLE BIT(27) 637 638 u32 flags2; 639 #define IXGBE_FLAG2_RSC_CAPABLE BIT(0) 640 #define IXGBE_FLAG2_RSC_ENABLED BIT(1) 641 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE BIT(2) 642 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT BIT(3) 643 #define IXGBE_FLAG2_SEARCH_FOR_SFP BIT(4) 644 #define IXGBE_FLAG2_SFP_NEEDS_RESET BIT(5) 645 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT BIT(7) 646 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP BIT(8) 647 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP BIT(9) 648 #define IXGBE_FLAG2_PTP_PPS_ENABLED BIT(10) 649 #define IXGBE_FLAG2_PHY_INTERRUPT BIT(11) 650 #define IXGBE_FLAG2_VLAN_PROMISC BIT(13) 651 #define IXGBE_FLAG2_EEE_CAPABLE BIT(14) 652 #define IXGBE_FLAG2_EEE_ENABLED BIT(15) 653 #define IXGBE_FLAG2_RX_LEGACY BIT(16) 654 #define IXGBE_FLAG2_IPSEC_ENABLED BIT(17) 655 #define IXGBE_FLAG2_VF_IPSEC_ENABLED BIT(18) 656 #define IXGBE_FLAG2_AUTO_DISABLE_VF BIT(19) 657 658 /* Tx fast path data */ 659 int num_tx_queues; 660 u16 tx_itr_setting; 661 u16 tx_work_limit; 662 u64 tx_ipsec; 663 664 /* Rx fast path data */ 665 int num_rx_queues; 666 u16 rx_itr_setting; 667 u64 rx_ipsec; 668 669 /* Port number used to identify VXLAN traffic */ 670 __be16 vxlan_port; 671 __be16 geneve_port; 672 673 /* XDP */ 674 int num_xdp_queues; 675 struct ixgbe_ring *xdp_ring[IXGBE_MAX_XDP_QS]; 676 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled rings */ 677 678 /* TX */ 679 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; 680 681 u64 restart_queue; 682 u64 lsc_int; 683 u32 tx_timeout_count; 684 685 /* RX */ 686 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; 687 int num_rx_pools; /* == num_rx_queues in 82598 */ 688 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ 689 u64 hw_csum_rx_error; 690 u64 hw_rx_no_dma_resources; 691 u64 rsc_total_count; 692 u64 rsc_total_flush; 693 u64 non_eop_descs; 694 u32 alloc_rx_page; 695 u32 alloc_rx_page_failed; 696 u32 alloc_rx_buff_failed; 697 698 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; 699 700 /* DCB parameters */ 701 struct ieee_pfc *ixgbe_ieee_pfc; 702 struct ieee_ets *ixgbe_ieee_ets; 703 struct ixgbe_dcb_config dcb_cfg; 704 struct ixgbe_dcb_config temp_dcb_cfg; 705 u8 hw_tcs; 706 u8 dcb_set_bitmap; 707 u8 dcbx_cap; 708 enum ixgbe_fc_mode last_lfc_mode; 709 710 int num_q_vectors; /* current number of q_vectors for device */ 711 int max_q_vectors; /* true count of q_vectors for device */ 712 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; 713 struct msix_entry *msix_entries; 714 715 u32 test_icr; 716 struct ixgbe_ring test_tx_ring; 717 struct ixgbe_ring test_rx_ring; 718 719 /* structs defined in ixgbe_hw.h */ 720 struct ixgbe_hw hw; 721 u16 msg_enable; 722 struct ixgbe_hw_stats stats; 723 724 u64 tx_busy; 725 unsigned int tx_ring_count; 726 unsigned int xdp_ring_count; 727 unsigned int rx_ring_count; 728 729 u32 link_speed; 730 bool link_up; 731 unsigned long sfp_poll_time; 732 unsigned long link_check_timeout; 733 734 struct timer_list service_timer; 735 struct work_struct service_task; 736 737 struct hlist_head fdir_filter_list; 738 unsigned long fdir_overflow; /* number of times ATR was backed off */ 739 union ixgbe_atr_input fdir_mask; 740 int fdir_filter_count; 741 u32 fdir_pballoc; 742 u32 atr_sample_rate; 743 spinlock_t fdir_perfect_lock; 744 745 #ifdef IXGBE_FCOE 746 struct ixgbe_fcoe fcoe; 747 #endif /* IXGBE_FCOE */ 748 u8 __iomem *io_addr; /* Mainly for iounmap use */ 749 u32 wol; 750 751 u16 bridge_mode; 752 753 char eeprom_id[NVM_VER_SIZE]; 754 u16 eeprom_cap; 755 756 u32 interrupt_event; 757 u32 led_reg; 758 759 struct ptp_clock *ptp_clock; 760 struct ptp_clock_info ptp_caps; 761 struct work_struct ptp_tx_work; 762 struct sk_buff *ptp_tx_skb; 763 struct hwtstamp_config tstamp_config; 764 unsigned long ptp_tx_start; 765 unsigned long last_overflow_check; 766 unsigned long last_rx_ptp_check; 767 unsigned long last_rx_timestamp; 768 spinlock_t tmreg_lock; 769 struct cyclecounter hw_cc; 770 struct timecounter hw_tc; 771 u32 base_incval; 772 u32 tx_hwtstamp_timeouts; 773 u32 tx_hwtstamp_skipped; 774 u32 rx_hwtstamp_cleared; 775 void (*ptp_setup_sdp)(struct ixgbe_adapter *); 776 777 /* SR-IOV */ 778 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 779 unsigned int num_vfs; 780 struct vf_data_storage *vfinfo; 781 int vf_rate_link_speed; 782 struct vf_macvlans vf_mvs; 783 struct vf_macvlans *mv_list; 784 785 u32 timer_event_accumulator; 786 u32 vferr_refcount; 787 struct ixgbe_mac_addr *mac_table; 788 struct kobject *info_kobj; 789 #ifdef CONFIG_IXGBE_HWMON 790 struct hwmon_buff *ixgbe_hwmon_buff; 791 #endif /* CONFIG_IXGBE_HWMON */ 792 #ifdef CONFIG_DEBUG_FS 793 struct dentry *ixgbe_dbg_adapter; 794 #endif /*CONFIG_DEBUG_FS*/ 795 796 u8 default_up; 797 /* Bitmask indicating in use pools */ 798 DECLARE_BITMAP(fwd_bitmask, IXGBE_MAX_MACVLANS + 1); 799 800 #define IXGBE_MAX_LINK_HANDLE 10 801 struct ixgbe_jump_table *jump_tables[IXGBE_MAX_LINK_HANDLE]; 802 unsigned long tables; 803 804 /* maximum number of RETA entries among all devices supported by ixgbe 805 * driver: currently it's x550 device in non-SRIOV mode 806 */ 807 #define IXGBE_MAX_RETA_ENTRIES 512 808 u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES]; 809 810 #define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */ 811 u32 *rss_key; 812 813 #ifdef CONFIG_IXGBE_IPSEC 814 struct ixgbe_ipsec *ipsec; 815 #endif /* CONFIG_IXGBE_IPSEC */ 816 spinlock_t vfs_lock; 817 }; 818 819 static inline int ixgbe_determine_xdp_q_idx(int cpu) 820 { 821 if (static_key_enabled(&ixgbe_xdp_locking_key)) 822 return cpu % IXGBE_MAX_XDP_QS; 823 else 824 return cpu; 825 } 826 827 static inline 828 struct ixgbe_ring *ixgbe_determine_xdp_ring(struct ixgbe_adapter *adapter) 829 { 830 int index = ixgbe_determine_xdp_q_idx(smp_processor_id()); 831 832 return adapter->xdp_ring[index]; 833 } 834 835 static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter) 836 { 837 switch (adapter->hw.mac.type) { 838 case ixgbe_mac_82598EB: 839 case ixgbe_mac_82599EB: 840 case ixgbe_mac_X540: 841 return IXGBE_MAX_RSS_INDICES; 842 case ixgbe_mac_X550: 843 case ixgbe_mac_X550EM_x: 844 case ixgbe_mac_x550em_a: 845 return IXGBE_MAX_RSS_INDICES_X550; 846 default: 847 return 0; 848 } 849 } 850 851 struct ixgbe_fdir_filter { 852 struct hlist_node fdir_node; 853 union ixgbe_atr_input filter; 854 u16 sw_idx; 855 u64 action; 856 }; 857 858 enum ixgbe_state_t { 859 __IXGBE_TESTING, 860 __IXGBE_RESETTING, 861 __IXGBE_DOWN, 862 __IXGBE_DISABLED, 863 __IXGBE_REMOVING, 864 __IXGBE_SERVICE_SCHED, 865 __IXGBE_SERVICE_INITED, 866 __IXGBE_IN_SFP_INIT, 867 __IXGBE_PTP_RUNNING, 868 __IXGBE_PTP_TX_IN_PROGRESS, 869 __IXGBE_RESET_REQUESTED, 870 }; 871 872 struct ixgbe_cb { 873 union { /* Union defining head/tail partner */ 874 struct sk_buff *head; 875 struct sk_buff *tail; 876 }; 877 dma_addr_t dma; 878 u16 append_cnt; 879 bool page_released; 880 }; 881 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) 882 883 enum ixgbe_boards { 884 board_82598, 885 board_82599, 886 board_X540, 887 board_X550, 888 board_X550EM_x, 889 board_x550em_x_fw, 890 board_x550em_a, 891 board_x550em_a_fw, 892 }; 893 894 extern const struct ixgbe_info ixgbe_82598_info; 895 extern const struct ixgbe_info ixgbe_82599_info; 896 extern const struct ixgbe_info ixgbe_X540_info; 897 extern const struct ixgbe_info ixgbe_X550_info; 898 extern const struct ixgbe_info ixgbe_X550EM_x_info; 899 extern const struct ixgbe_info ixgbe_x550em_x_fw_info; 900 extern const struct ixgbe_info ixgbe_x550em_a_info; 901 extern const struct ixgbe_info ixgbe_x550em_a_fw_info; 902 #ifdef CONFIG_IXGBE_DCB 903 extern const struct dcbnl_rtnl_ops ixgbe_dcbnl_ops; 904 #endif 905 906 extern char ixgbe_driver_name[]; 907 #ifdef IXGBE_FCOE 908 extern char ixgbe_default_device_descr[]; 909 #endif /* IXGBE_FCOE */ 910 911 int ixgbe_open(struct net_device *netdev); 912 int ixgbe_close(struct net_device *netdev); 913 void ixgbe_up(struct ixgbe_adapter *adapter); 914 void ixgbe_down(struct ixgbe_adapter *adapter); 915 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); 916 void ixgbe_reset(struct ixgbe_adapter *adapter); 917 void ixgbe_set_ethtool_ops(struct net_device *netdev); 918 int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); 919 int ixgbe_setup_tx_resources(struct ixgbe_ring *); 920 void ixgbe_free_rx_resources(struct ixgbe_ring *); 921 void ixgbe_free_tx_resources(struct ixgbe_ring *); 922 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 923 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 924 void ixgbe_disable_rx(struct ixgbe_adapter *adapter); 925 void ixgbe_disable_tx(struct ixgbe_adapter *adapter); 926 void ixgbe_update_stats(struct ixgbe_adapter *adapter); 927 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); 928 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 929 u16 subdevice_id); 930 #ifdef CONFIG_PCI_IOV 931 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter); 932 #endif 933 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 934 const u8 *addr, u16 queue); 935 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 936 const u8 *addr, u16 queue); 937 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid); 938 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); 939 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, 940 struct ixgbe_ring *); 941 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, 942 struct ixgbe_tx_buffer *); 943 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); 944 void ixgbe_write_eitr(struct ixgbe_q_vector *); 945 int ixgbe_poll(struct napi_struct *napi, int budget); 946 int ethtool_ioctl(struct ifreq *ifr); 947 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 948 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); 949 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); 950 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 951 union ixgbe_atr_hash_dword input, 952 union ixgbe_atr_hash_dword common, 953 u8 queue); 954 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 955 union ixgbe_atr_input *input_mask); 956 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 957 union ixgbe_atr_input *input, 958 u16 soft_id, u8 queue); 959 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 960 union ixgbe_atr_input *input, 961 u16 soft_id); 962 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 963 union ixgbe_atr_input *mask); 964 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 965 struct ixgbe_fdir_filter *input, 966 u16 sw_idx); 967 void ixgbe_set_rx_mode(struct net_device *netdev); 968 #ifdef CONFIG_IXGBE_DCB 969 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); 970 #endif 971 int ixgbe_setup_tc(struct net_device *dev, u8 tc); 972 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); 973 void ixgbe_do_reset(struct net_device *netdev); 974 #ifdef CONFIG_IXGBE_HWMON 975 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); 976 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); 977 #endif /* CONFIG_IXGBE_HWMON */ 978 #ifdef IXGBE_FCOE 979 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 980 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 981 u8 *hdr_len); 982 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, 983 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); 984 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, 985 struct scatterlist *sgl, unsigned int sgc); 986 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, 987 struct scatterlist *sgl, unsigned int sgc); 988 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); 989 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 990 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 991 int ixgbe_fcoe_enable(struct net_device *netdev); 992 int ixgbe_fcoe_disable(struct net_device *netdev); 993 #ifdef CONFIG_IXGBE_DCB 994 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); 995 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); 996 #endif /* CONFIG_IXGBE_DCB */ 997 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); 998 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, 999 struct netdev_fcoe_hbainfo *info); 1000 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); 1001 #endif /* IXGBE_FCOE */ 1002 #ifdef CONFIG_DEBUG_FS 1003 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); 1004 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); 1005 void ixgbe_dbg_init(void); 1006 void ixgbe_dbg_exit(void); 1007 #else 1008 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} 1009 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} 1010 static inline void ixgbe_dbg_init(void) {} 1011 static inline void ixgbe_dbg_exit(void) {} 1012 #endif /* CONFIG_DEBUG_FS */ 1013 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) 1014 { 1015 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 1016 } 1017 1018 void ixgbe_ptp_init(struct ixgbe_adapter *adapter); 1019 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter); 1020 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); 1021 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); 1022 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); 1023 void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter); 1024 void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *); 1025 void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb); 1026 static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring, 1027 union ixgbe_adv_rx_desc *rx_desc, 1028 struct sk_buff *skb) 1029 { 1030 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) { 1031 ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb); 1032 return; 1033 } 1034 1035 if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) 1036 return; 1037 1038 ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 1039 1040 /* Update the last_rx_timestamp timer in order to enable watchdog check 1041 * for error case of latched timestamp on a dropped packet. 1042 */ 1043 rx_ring->last_rx_timestamp = jiffies; 1044 } 1045 1046 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 1047 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 1048 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); 1049 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); 1050 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter); 1051 #ifdef CONFIG_PCI_IOV 1052 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); 1053 #endif 1054 1055 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 1056 struct ixgbe_adapter *adapter, 1057 struct ixgbe_ring *tx_ring); 1058 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter); 1059 void ixgbe_store_key(struct ixgbe_adapter *adapter); 1060 void ixgbe_store_reta(struct ixgbe_adapter *adapter); 1061 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 1062 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm); 1063 #ifdef CONFIG_IXGBE_IPSEC 1064 void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter); 1065 void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter); 1066 void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter); 1067 void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring, 1068 union ixgbe_adv_rx_desc *rx_desc, 1069 struct sk_buff *skb); 1070 int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 1071 struct ixgbe_ipsec_tx_data *itd); 1072 void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter, u32 vf); 1073 int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf); 1074 int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf); 1075 #else 1076 static inline void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter) { } 1077 static inline void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter) { } 1078 static inline void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter) { } 1079 static inline void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring, 1080 union ixgbe_adv_rx_desc *rx_desc, 1081 struct sk_buff *skb) { } 1082 static inline int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring, 1083 struct ixgbe_tx_buffer *first, 1084 struct ixgbe_ipsec_tx_data *itd) { return 0; } 1085 static inline void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter, 1086 u32 vf) { } 1087 static inline int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter, 1088 u32 *mbuf, u32 vf) { return -EACCES; } 1089 static inline int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter, 1090 u32 *mbuf, u32 vf) { return -EACCES; } 1091 #endif /* CONFIG_IXGBE_IPSEC */ 1092 1093 static inline bool ixgbe_enabled_xdp_adapter(struct ixgbe_adapter *adapter) 1094 { 1095 return !!adapter->xdp_prog; 1096 } 1097 1098 #endif /* _IXGBE_H_ */ 1099