1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #ifndef _IXGBE_H_ 30 #define _IXGBE_H_ 31 32 #include <linux/bitops.h> 33 #include <linux/types.h> 34 #include <linux/pci.h> 35 #include <linux/netdevice.h> 36 #include <linux/cpumask.h> 37 #include <linux/aer.h> 38 #include <linux/if_vlan.h> 39 #include <linux/jiffies.h> 40 41 #include <linux/clocksource.h> 42 #include <linux/net_tstamp.h> 43 #include <linux/ptp_clock_kernel.h> 44 45 #include "ixgbe_type.h" 46 #include "ixgbe_common.h" 47 #include "ixgbe_dcb.h" 48 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) 49 #define IXGBE_FCOE 50 #include "ixgbe_fcoe.h" 51 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ 52 #ifdef CONFIG_IXGBE_DCA 53 #include <linux/dca.h> 54 #endif 55 56 #include <net/busy_poll.h> 57 58 #ifdef CONFIG_NET_RX_BUSY_POLL 59 #define BP_EXTENDED_STATS 60 #endif 61 /* common prefix used by pr_<> macros */ 62 #undef pr_fmt 63 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 64 65 /* TX/RX descriptor defines */ 66 #define IXGBE_DEFAULT_TXD 512 67 #define IXGBE_DEFAULT_TX_WORK 256 68 #define IXGBE_MAX_TXD 4096 69 #define IXGBE_MIN_TXD 64 70 71 #if (PAGE_SIZE < 8192) 72 #define IXGBE_DEFAULT_RXD 512 73 #else 74 #define IXGBE_DEFAULT_RXD 128 75 #endif 76 #define IXGBE_MAX_RXD 4096 77 #define IXGBE_MIN_RXD 64 78 79 /* flow control */ 80 #define IXGBE_MIN_FCRTL 0x40 81 #define IXGBE_MAX_FCRTL 0x7FF80 82 #define IXGBE_MIN_FCRTH 0x600 83 #define IXGBE_MAX_FCRTH 0x7FFF0 84 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF 85 #define IXGBE_MIN_FCPAUSE 0 86 #define IXGBE_MAX_FCPAUSE 0xFFFF 87 88 /* Supported Rx Buffer Sizes */ 89 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ 90 #define IXGBE_RXBUFFER_2K 2048 91 #define IXGBE_RXBUFFER_3K 3072 92 #define IXGBE_RXBUFFER_4K 4096 93 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 94 95 /* 96 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 97 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, 98 * this adds up to 448 bytes of extra data. 99 * 100 * Since netdev_alloc_skb now allocates a page fragment we can use a value 101 * of 256 and the resultant skb will have a truesize of 960 or less. 102 */ 103 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 104 105 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 106 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 107 108 enum ixgbe_tx_flags { 109 /* cmd_type flags */ 110 IXGBE_TX_FLAGS_HW_VLAN = 0x01, 111 IXGBE_TX_FLAGS_TSO = 0x02, 112 IXGBE_TX_FLAGS_TSTAMP = 0x04, 113 114 /* olinfo flags */ 115 IXGBE_TX_FLAGS_CC = 0x08, 116 IXGBE_TX_FLAGS_IPV4 = 0x10, 117 IXGBE_TX_FLAGS_CSUM = 0x20, 118 119 /* software defined flags */ 120 IXGBE_TX_FLAGS_SW_VLAN = 0x40, 121 IXGBE_TX_FLAGS_FCOE = 0x80, 122 }; 123 124 /* VLAN info */ 125 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 126 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 127 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 128 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 129 130 #define IXGBE_MAX_VF_MC_ENTRIES 30 131 #define IXGBE_MAX_VF_FUNCTIONS 64 132 #define IXGBE_MAX_VFTA_ENTRIES 128 133 #define MAX_EMULATION_MAC_ADDRS 16 134 #define IXGBE_MAX_PF_MACVLANS 15 135 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) 136 #define IXGBE_82599_VF_DEVICE_ID 0x10ED 137 #define IXGBE_X540_VF_DEVICE_ID 0x1515 138 139 struct vf_data_storage { 140 unsigned char vf_mac_addresses[ETH_ALEN]; 141 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 142 u16 num_vf_mc_hashes; 143 u16 default_vf_vlan_id; 144 u16 vlans_enabled; 145 bool clear_to_send; 146 bool pf_set_mac; 147 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 148 u16 pf_qos; 149 u16 tx_rate; 150 u16 vlan_count; 151 u8 spoofchk_enabled; 152 unsigned int vf_api; 153 }; 154 155 struct vf_macvlans { 156 struct list_head l; 157 int vf; 158 int rar_entry; 159 bool free; 160 bool is_macvlan; 161 u8 vf_macvlan[ETH_ALEN]; 162 }; 163 164 #define IXGBE_MAX_TXD_PWR 14 165 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) 166 167 /* Tx Descriptors needed, worst case */ 168 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 169 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 170 171 /* wrapper around a pointer to a socket buffer, 172 * so a DMA handle can be stored along with the buffer */ 173 struct ixgbe_tx_buffer { 174 union ixgbe_adv_tx_desc *next_to_watch; 175 unsigned long time_stamp; 176 struct sk_buff *skb; 177 unsigned int bytecount; 178 unsigned short gso_segs; 179 __be16 protocol; 180 DEFINE_DMA_UNMAP_ADDR(dma); 181 DEFINE_DMA_UNMAP_LEN(len); 182 u32 tx_flags; 183 }; 184 185 struct ixgbe_rx_buffer { 186 struct sk_buff *skb; 187 dma_addr_t dma; 188 struct page *page; 189 unsigned int page_offset; 190 }; 191 192 struct ixgbe_queue_stats { 193 u64 packets; 194 u64 bytes; 195 #ifdef BP_EXTENDED_STATS 196 u64 yields; 197 u64 misses; 198 u64 cleaned; 199 #endif /* BP_EXTENDED_STATS */ 200 }; 201 202 struct ixgbe_tx_queue_stats { 203 u64 restart_queue; 204 u64 tx_busy; 205 u64 tx_done_old; 206 }; 207 208 struct ixgbe_rx_queue_stats { 209 u64 rsc_count; 210 u64 rsc_flush; 211 u64 non_eop_descs; 212 u64 alloc_rx_page_failed; 213 u64 alloc_rx_buff_failed; 214 u64 csum_err; 215 }; 216 217 enum ixgbe_ring_state_t { 218 __IXGBE_TX_FDIR_INIT_DONE, 219 __IXGBE_TX_XPS_INIT_DONE, 220 __IXGBE_TX_DETECT_HANG, 221 __IXGBE_HANG_CHECK_ARMED, 222 __IXGBE_RX_RSC_ENABLED, 223 __IXGBE_RX_CSUM_UDP_ZERO_ERR, 224 __IXGBE_RX_FCOE, 225 }; 226 227 struct ixgbe_fwd_adapter { 228 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 229 struct net_device *netdev; 230 struct ixgbe_adapter *real_adapter; 231 unsigned int tx_base_queue; 232 unsigned int rx_base_queue; 233 int pool; 234 }; 235 236 #define check_for_tx_hang(ring) \ 237 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 238 #define set_check_for_tx_hang(ring) \ 239 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 240 #define clear_check_for_tx_hang(ring) \ 241 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 242 #define ring_is_rsc_enabled(ring) \ 243 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 244 #define set_ring_rsc_enabled(ring) \ 245 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 246 #define clear_ring_rsc_enabled(ring) \ 247 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 248 struct ixgbe_ring { 249 struct ixgbe_ring *next; /* pointer to next ring in q_vector */ 250 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ 251 struct net_device *netdev; /* netdev ring belongs to */ 252 struct device *dev; /* device for DMA mapping */ 253 struct ixgbe_fwd_adapter *l2_accel_priv; 254 void *desc; /* descriptor ring memory */ 255 union { 256 struct ixgbe_tx_buffer *tx_buffer_info; 257 struct ixgbe_rx_buffer *rx_buffer_info; 258 }; 259 unsigned long state; 260 u8 __iomem *tail; 261 dma_addr_t dma; /* phys. address of descriptor ring */ 262 unsigned int size; /* length in bytes */ 263 264 u16 count; /* amount of descriptors */ 265 266 u8 queue_index; /* needed for multiqueue queue management */ 267 u8 reg_idx; /* holds the special value that gets 268 * the hardware register offset 269 * associated with this ring, which is 270 * different for DCB and RSS modes 271 */ 272 u16 next_to_use; 273 u16 next_to_clean; 274 275 union { 276 u16 next_to_alloc; 277 struct { 278 u8 atr_sample_rate; 279 u8 atr_count; 280 }; 281 }; 282 283 u8 dcb_tc; 284 struct ixgbe_queue_stats stats; 285 struct u64_stats_sync syncp; 286 union { 287 struct ixgbe_tx_queue_stats tx_stats; 288 struct ixgbe_rx_queue_stats rx_stats; 289 }; 290 } ____cacheline_internodealigned_in_smp; 291 292 enum ixgbe_ring_f_enum { 293 RING_F_NONE = 0, 294 RING_F_VMDQ, /* SR-IOV uses the same ring feature */ 295 RING_F_RSS, 296 RING_F_FDIR, 297 #ifdef IXGBE_FCOE 298 RING_F_FCOE, 299 #endif /* IXGBE_FCOE */ 300 301 RING_F_ARRAY_SIZE /* must be last in enum set */ 302 }; 303 304 #define IXGBE_MAX_RSS_INDICES 16 305 #define IXGBE_MAX_VMDQ_INDICES 64 306 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ 307 #define IXGBE_MAX_FCOE_INDICES 8 308 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 309 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 310 #define IXGBE_MAX_L2A_QUEUES 4 311 #define IXGBE_MAX_L2A_QUEUES 4 312 #define IXGBE_BAD_L2A_QUEUE 3 313 #define IXGBE_MAX_MACVLANS 31 314 #define IXGBE_MAX_DCBMACVLANS 8 315 316 struct ixgbe_ring_feature { 317 u16 limit; /* upper limit on feature indices */ 318 u16 indices; /* current value of indices */ 319 u16 mask; /* Mask used for feature to ring mapping */ 320 u16 offset; /* offset to start of feature */ 321 } ____cacheline_internodealigned_in_smp; 322 323 #define IXGBE_82599_VMDQ_8Q_MASK 0x78 324 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C 325 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E 326 327 /* 328 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since 329 * this is twice the size of a half page we need to double the page order 330 * for FCoE enabled Rx queues. 331 */ 332 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) 333 { 334 #ifdef IXGBE_FCOE 335 if (test_bit(__IXGBE_RX_FCOE, &ring->state)) 336 return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K : 337 IXGBE_RXBUFFER_3K; 338 #endif 339 return IXGBE_RXBUFFER_2K; 340 } 341 342 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) 343 { 344 #ifdef IXGBE_FCOE 345 if (test_bit(__IXGBE_RX_FCOE, &ring->state)) 346 return (PAGE_SIZE < 8192) ? 1 : 0; 347 #endif 348 return 0; 349 } 350 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) 351 352 struct ixgbe_ring_container { 353 struct ixgbe_ring *ring; /* pointer to linked list of rings */ 354 unsigned int total_bytes; /* total bytes processed this int */ 355 unsigned int total_packets; /* total packets processed this int */ 356 u16 work_limit; /* total work allowed per interrupt */ 357 u8 count; /* total number of rings in vector */ 358 u8 itr; /* current ITR setting for ring */ 359 }; 360 361 /* iterator for handling rings in ring container */ 362 #define ixgbe_for_each_ring(pos, head) \ 363 for (pos = (head).ring; pos != NULL; pos = pos->next) 364 365 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ 366 ? 8 : 1) 367 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS 368 369 /* MAX_Q_VECTORS of these are allocated, 370 * but we only use one per queue-specific vector. 371 */ 372 struct ixgbe_q_vector { 373 struct ixgbe_adapter *adapter; 374 #ifdef CONFIG_IXGBE_DCA 375 int cpu; /* CPU for DCA */ 376 #endif 377 u16 v_idx; /* index of q_vector within array, also used for 378 * finding the bit in EICR and friends that 379 * represents the vector for this ring */ 380 u16 itr; /* Interrupt throttle rate written to EITR */ 381 struct ixgbe_ring_container rx, tx; 382 383 struct napi_struct napi; 384 cpumask_t affinity_mask; 385 int numa_node; 386 struct rcu_head rcu; /* to avoid race with update stats on free */ 387 char name[IFNAMSIZ + 9]; 388 389 #ifdef CONFIG_NET_RX_BUSY_POLL 390 unsigned int state; 391 #define IXGBE_QV_STATE_IDLE 0 392 #define IXGBE_QV_STATE_NAPI 1 /* NAPI owns this QV */ 393 #define IXGBE_QV_STATE_POLL 2 /* poll owns this QV */ 394 #define IXGBE_QV_STATE_DISABLED 4 /* QV is disabled */ 395 #define IXGBE_QV_OWNED (IXGBE_QV_STATE_NAPI | IXGBE_QV_STATE_POLL) 396 #define IXGBE_QV_LOCKED (IXGBE_QV_OWNED | IXGBE_QV_STATE_DISABLED) 397 #define IXGBE_QV_STATE_NAPI_YIELD 8 /* NAPI yielded this QV */ 398 #define IXGBE_QV_STATE_POLL_YIELD 16 /* poll yielded this QV */ 399 #define IXGBE_QV_YIELD (IXGBE_QV_STATE_NAPI_YIELD | IXGBE_QV_STATE_POLL_YIELD) 400 #define IXGBE_QV_USER_PEND (IXGBE_QV_STATE_POLL | IXGBE_QV_STATE_POLL_YIELD) 401 spinlock_t lock; 402 #endif /* CONFIG_NET_RX_BUSY_POLL */ 403 404 /* for dynamic allocation of rings associated with this q_vector */ 405 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; 406 }; 407 #ifdef CONFIG_NET_RX_BUSY_POLL 408 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) 409 { 410 411 spin_lock_init(&q_vector->lock); 412 q_vector->state = IXGBE_QV_STATE_IDLE; 413 } 414 415 /* called from the device poll routine to get ownership of a q_vector */ 416 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) 417 { 418 int rc = true; 419 spin_lock_bh(&q_vector->lock); 420 if (q_vector->state & IXGBE_QV_LOCKED) { 421 WARN_ON(q_vector->state & IXGBE_QV_STATE_NAPI); 422 q_vector->state |= IXGBE_QV_STATE_NAPI_YIELD; 423 rc = false; 424 #ifdef BP_EXTENDED_STATS 425 q_vector->tx.ring->stats.yields++; 426 #endif 427 } else { 428 /* we don't care if someone yielded */ 429 q_vector->state = IXGBE_QV_STATE_NAPI; 430 } 431 spin_unlock_bh(&q_vector->lock); 432 return rc; 433 } 434 435 /* returns true is someone tried to get the qv while napi had it */ 436 static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) 437 { 438 int rc = false; 439 spin_lock_bh(&q_vector->lock); 440 WARN_ON(q_vector->state & (IXGBE_QV_STATE_POLL | 441 IXGBE_QV_STATE_NAPI_YIELD)); 442 443 if (q_vector->state & IXGBE_QV_STATE_POLL_YIELD) 444 rc = true; 445 /* will reset state to idle, unless QV is disabled */ 446 q_vector->state &= IXGBE_QV_STATE_DISABLED; 447 spin_unlock_bh(&q_vector->lock); 448 return rc; 449 } 450 451 /* called from ixgbe_low_latency_poll() */ 452 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) 453 { 454 int rc = true; 455 spin_lock_bh(&q_vector->lock); 456 if ((q_vector->state & IXGBE_QV_LOCKED)) { 457 q_vector->state |= IXGBE_QV_STATE_POLL_YIELD; 458 rc = false; 459 #ifdef BP_EXTENDED_STATS 460 q_vector->rx.ring->stats.yields++; 461 #endif 462 } else { 463 /* preserve yield marks */ 464 q_vector->state |= IXGBE_QV_STATE_POLL; 465 } 466 spin_unlock_bh(&q_vector->lock); 467 return rc; 468 } 469 470 /* returns true if someone tried to get the qv while it was locked */ 471 static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) 472 { 473 int rc = false; 474 spin_lock_bh(&q_vector->lock); 475 WARN_ON(q_vector->state & (IXGBE_QV_STATE_NAPI)); 476 477 if (q_vector->state & IXGBE_QV_STATE_POLL_YIELD) 478 rc = true; 479 /* will reset state to idle, unless QV is disabled */ 480 q_vector->state &= IXGBE_QV_STATE_DISABLED; 481 spin_unlock_bh(&q_vector->lock); 482 return rc; 483 } 484 485 /* true if a socket is polling, even if it did not get the lock */ 486 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) 487 { 488 WARN_ON(!(q_vector->state & IXGBE_QV_OWNED)); 489 return q_vector->state & IXGBE_QV_USER_PEND; 490 } 491 492 /* false if QV is currently owned */ 493 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) 494 { 495 int rc = true; 496 spin_lock_bh(&q_vector->lock); 497 if (q_vector->state & IXGBE_QV_OWNED) 498 rc = false; 499 q_vector->state |= IXGBE_QV_STATE_DISABLED; 500 spin_unlock_bh(&q_vector->lock); 501 502 return rc; 503 } 504 505 #else /* CONFIG_NET_RX_BUSY_POLL */ 506 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) 507 { 508 } 509 510 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) 511 { 512 return true; 513 } 514 515 static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) 516 { 517 return false; 518 } 519 520 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) 521 { 522 return false; 523 } 524 525 static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) 526 { 527 return false; 528 } 529 530 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) 531 { 532 return false; 533 } 534 535 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) 536 { 537 return true; 538 } 539 540 #endif /* CONFIG_NET_RX_BUSY_POLL */ 541 542 #ifdef CONFIG_IXGBE_HWMON 543 544 #define IXGBE_HWMON_TYPE_LOC 0 545 #define IXGBE_HWMON_TYPE_TEMP 1 546 #define IXGBE_HWMON_TYPE_CAUTION 2 547 #define IXGBE_HWMON_TYPE_MAX 3 548 549 struct hwmon_attr { 550 struct device_attribute dev_attr; 551 struct ixgbe_hw *hw; 552 struct ixgbe_thermal_diode_data *sensor; 553 char name[12]; 554 }; 555 556 struct hwmon_buff { 557 struct attribute_group group; 558 const struct attribute_group *groups[2]; 559 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; 560 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; 561 unsigned int n_hwmon; 562 }; 563 #endif /* CONFIG_IXGBE_HWMON */ 564 565 /* 566 * microsecond values for various ITR rates shifted by 2 to fit itr register 567 * with the first 3 bits reserved 0 568 */ 569 #define IXGBE_MIN_RSC_ITR 24 570 #define IXGBE_100K_ITR 40 571 #define IXGBE_20K_ITR 200 572 #define IXGBE_10K_ITR 400 573 #define IXGBE_8K_ITR 500 574 575 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ 576 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, 577 const u32 stat_err_bits) 578 { 579 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 580 } 581 582 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) 583 { 584 u16 ntc = ring->next_to_clean; 585 u16 ntu = ring->next_to_use; 586 587 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 588 } 589 590 static inline void ixgbe_write_tail(struct ixgbe_ring *ring, u32 value) 591 { 592 writel(value, ring->tail); 593 } 594 595 #define IXGBE_RX_DESC(R, i) \ 596 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 597 #define IXGBE_TX_DESC(R, i) \ 598 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 599 #define IXGBE_TX_CTXTDESC(R, i) \ 600 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 601 602 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ 603 #ifdef IXGBE_FCOE 604 /* Use 3K as the baby jumbo frame size for FCoE */ 605 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 606 #endif /* IXGBE_FCOE */ 607 608 #define OTHER_VECTOR 1 609 #define NON_Q_VECTORS (OTHER_VECTOR) 610 611 #define MAX_MSIX_VECTORS_82599 64 612 #define MAX_Q_VECTORS_82599 64 613 #define MAX_MSIX_VECTORS_82598 18 614 #define MAX_Q_VECTORS_82598 16 615 616 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 617 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 618 619 #define MIN_MSIX_Q_VECTORS 1 620 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 621 622 /* default to trying for four seconds */ 623 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 624 625 /* board specific private data structure */ 626 struct ixgbe_adapter { 627 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 628 /* OS defined structs */ 629 struct net_device *netdev; 630 struct pci_dev *pdev; 631 632 unsigned long state; 633 634 /* Some features need tri-state capability, 635 * thus the additional *_CAPABLE flags. 636 */ 637 u32 flags; 638 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 0) 639 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1) 640 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 2) 641 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3) 642 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4) 643 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5) 644 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6) 645 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 7) 646 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8) 647 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9) 648 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10) 649 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11) 650 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12) 651 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13) 652 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14) 653 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15) 654 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16) 655 #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17) 656 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18) 657 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19) 658 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20) 659 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21) 660 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22) 661 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23) 662 663 u32 flags2; 664 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0) 665 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) 666 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) 667 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3) 668 #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4) 669 #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5) 670 #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6) 671 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7) 672 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8) 673 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9) 674 #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10) 675 #define IXGBE_FLAG2_BRIDGE_MODE_VEB (u32)(1 << 11) 676 677 /* Tx fast path data */ 678 int num_tx_queues; 679 u16 tx_itr_setting; 680 u16 tx_work_limit; 681 682 /* Rx fast path data */ 683 int num_rx_queues; 684 u16 rx_itr_setting; 685 686 /* TX */ 687 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; 688 689 u64 restart_queue; 690 u64 lsc_int; 691 u32 tx_timeout_count; 692 693 /* RX */ 694 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; 695 int num_rx_pools; /* == num_rx_queues in 82598 */ 696 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ 697 u64 hw_csum_rx_error; 698 u64 hw_rx_no_dma_resources; 699 u64 rsc_total_count; 700 u64 rsc_total_flush; 701 u64 non_eop_descs; 702 u32 alloc_rx_page_failed; 703 u32 alloc_rx_buff_failed; 704 705 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; 706 707 /* DCB parameters */ 708 struct ieee_pfc *ixgbe_ieee_pfc; 709 struct ieee_ets *ixgbe_ieee_ets; 710 struct ixgbe_dcb_config dcb_cfg; 711 struct ixgbe_dcb_config temp_dcb_cfg; 712 u8 dcb_set_bitmap; 713 u8 dcbx_cap; 714 enum ixgbe_fc_mode last_lfc_mode; 715 716 int num_q_vectors; /* current number of q_vectors for device */ 717 int max_q_vectors; /* true count of q_vectors for device */ 718 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; 719 struct msix_entry *msix_entries; 720 721 u32 test_icr; 722 struct ixgbe_ring test_tx_ring; 723 struct ixgbe_ring test_rx_ring; 724 725 /* structs defined in ixgbe_hw.h */ 726 struct ixgbe_hw hw; 727 u16 msg_enable; 728 struct ixgbe_hw_stats stats; 729 730 u64 tx_busy; 731 unsigned int tx_ring_count; 732 unsigned int rx_ring_count; 733 734 u32 link_speed; 735 bool link_up; 736 unsigned long link_check_timeout; 737 738 struct timer_list service_timer; 739 struct work_struct service_task; 740 741 struct hlist_head fdir_filter_list; 742 unsigned long fdir_overflow; /* number of times ATR was backed off */ 743 union ixgbe_atr_input fdir_mask; 744 int fdir_filter_count; 745 u32 fdir_pballoc; 746 u32 atr_sample_rate; 747 spinlock_t fdir_perfect_lock; 748 749 #ifdef IXGBE_FCOE 750 struct ixgbe_fcoe fcoe; 751 #endif /* IXGBE_FCOE */ 752 u8 __iomem *io_addr; /* Mainly for iounmap use */ 753 u32 wol; 754 755 u16 bd_number; 756 757 u16 eeprom_verh; 758 u16 eeprom_verl; 759 u16 eeprom_cap; 760 761 u32 interrupt_event; 762 u32 led_reg; 763 764 struct ptp_clock *ptp_clock; 765 struct ptp_clock_info ptp_caps; 766 struct work_struct ptp_tx_work; 767 struct sk_buff *ptp_tx_skb; 768 struct hwtstamp_config tstamp_config; 769 unsigned long ptp_tx_start; 770 unsigned long last_overflow_check; 771 unsigned long last_rx_ptp_check; 772 unsigned long last_rx_timestamp; 773 spinlock_t tmreg_lock; 774 struct cyclecounter cc; 775 struct timecounter tc; 776 u32 base_incval; 777 778 /* SR-IOV */ 779 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 780 unsigned int num_vfs; 781 struct vf_data_storage *vfinfo; 782 int vf_rate_link_speed; 783 struct vf_macvlans vf_mvs; 784 struct vf_macvlans *mv_list; 785 786 u32 timer_event_accumulator; 787 u32 vferr_refcount; 788 struct kobject *info_kobj; 789 #ifdef CONFIG_IXGBE_HWMON 790 struct hwmon_buff *ixgbe_hwmon_buff; 791 #endif /* CONFIG_IXGBE_HWMON */ 792 #ifdef CONFIG_DEBUG_FS 793 struct dentry *ixgbe_dbg_adapter; 794 #endif /*CONFIG_DEBUG_FS*/ 795 796 u8 default_up; 797 unsigned long fwd_bitmask; /* Bitmask indicating in use pools */ 798 }; 799 800 struct ixgbe_fdir_filter { 801 struct hlist_node fdir_node; 802 union ixgbe_atr_input filter; 803 u16 sw_idx; 804 u16 action; 805 }; 806 807 enum ixgbe_state_t { 808 __IXGBE_TESTING, 809 __IXGBE_RESETTING, 810 __IXGBE_DOWN, 811 __IXGBE_DISABLED, 812 __IXGBE_REMOVING, 813 __IXGBE_SERVICE_SCHED, 814 __IXGBE_SERVICE_INITED, 815 __IXGBE_IN_SFP_INIT, 816 __IXGBE_PTP_RUNNING, 817 __IXGBE_PTP_TX_IN_PROGRESS, 818 }; 819 820 struct ixgbe_cb { 821 union { /* Union defining head/tail partner */ 822 struct sk_buff *head; 823 struct sk_buff *tail; 824 }; 825 dma_addr_t dma; 826 u16 append_cnt; 827 bool page_released; 828 }; 829 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) 830 831 enum ixgbe_boards { 832 board_82598, 833 board_82599, 834 board_X540, 835 }; 836 837 extern struct ixgbe_info ixgbe_82598_info; 838 extern struct ixgbe_info ixgbe_82599_info; 839 extern struct ixgbe_info ixgbe_X540_info; 840 #ifdef CONFIG_IXGBE_DCB 841 extern const struct dcbnl_rtnl_ops dcbnl_ops; 842 #endif 843 844 extern char ixgbe_driver_name[]; 845 extern const char ixgbe_driver_version[]; 846 #ifdef IXGBE_FCOE 847 extern char ixgbe_default_device_descr[]; 848 #endif /* IXGBE_FCOE */ 849 850 void ixgbe_up(struct ixgbe_adapter *adapter); 851 void ixgbe_down(struct ixgbe_adapter *adapter); 852 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); 853 void ixgbe_reset(struct ixgbe_adapter *adapter); 854 void ixgbe_set_ethtool_ops(struct net_device *netdev); 855 int ixgbe_setup_rx_resources(struct ixgbe_ring *); 856 int ixgbe_setup_tx_resources(struct ixgbe_ring *); 857 void ixgbe_free_rx_resources(struct ixgbe_ring *); 858 void ixgbe_free_tx_resources(struct ixgbe_ring *); 859 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 860 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 861 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *); 862 void ixgbe_update_stats(struct ixgbe_adapter *adapter); 863 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); 864 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 865 u16 subdevice_id); 866 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); 867 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, 868 struct ixgbe_ring *); 869 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, 870 struct ixgbe_tx_buffer *); 871 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); 872 void ixgbe_write_eitr(struct ixgbe_q_vector *); 873 int ixgbe_poll(struct napi_struct *napi, int budget); 874 int ethtool_ioctl(struct ifreq *ifr); 875 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 876 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); 877 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); 878 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 879 union ixgbe_atr_hash_dword input, 880 union ixgbe_atr_hash_dword common, 881 u8 queue); 882 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 883 union ixgbe_atr_input *input_mask); 884 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 885 union ixgbe_atr_input *input, 886 u16 soft_id, u8 queue); 887 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 888 union ixgbe_atr_input *input, 889 u16 soft_id); 890 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 891 union ixgbe_atr_input *mask); 892 void ixgbe_set_rx_mode(struct net_device *netdev); 893 #ifdef CONFIG_IXGBE_DCB 894 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); 895 #endif 896 int ixgbe_setup_tc(struct net_device *dev, u8 tc); 897 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); 898 void ixgbe_do_reset(struct net_device *netdev); 899 #ifdef CONFIG_IXGBE_HWMON 900 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); 901 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); 902 #endif /* CONFIG_IXGBE_HWMON */ 903 #ifdef IXGBE_FCOE 904 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 905 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 906 u8 *hdr_len); 907 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, 908 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); 909 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, 910 struct scatterlist *sgl, unsigned int sgc); 911 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, 912 struct scatterlist *sgl, unsigned int sgc); 913 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); 914 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 915 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 916 int ixgbe_fcoe_enable(struct net_device *netdev); 917 int ixgbe_fcoe_disable(struct net_device *netdev); 918 #ifdef CONFIG_IXGBE_DCB 919 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); 920 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); 921 #endif /* CONFIG_IXGBE_DCB */ 922 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); 923 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, 924 struct netdev_fcoe_hbainfo *info); 925 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); 926 #endif /* IXGBE_FCOE */ 927 #ifdef CONFIG_DEBUG_FS 928 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); 929 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); 930 void ixgbe_dbg_init(void); 931 void ixgbe_dbg_exit(void); 932 #else 933 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} 934 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} 935 static inline void ixgbe_dbg_init(void) {} 936 static inline void ixgbe_dbg_exit(void) {} 937 #endif /* CONFIG_DEBUG_FS */ 938 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) 939 { 940 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 941 } 942 943 void ixgbe_ptp_init(struct ixgbe_adapter *adapter); 944 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); 945 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); 946 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); 947 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_adapter *adapter, struct sk_buff *skb); 948 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 949 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 950 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); 951 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); 952 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr); 953 #ifdef CONFIG_PCI_IOV 954 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); 955 #endif 956 957 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 958 struct ixgbe_adapter *adapter, 959 struct ixgbe_ring *tx_ring); 960 #endif /* _IXGBE_H_ */ 961