1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #ifndef _IXGBE_H_ 30 #define _IXGBE_H_ 31 32 #include <linux/bitops.h> 33 #include <linux/types.h> 34 #include <linux/pci.h> 35 #include <linux/netdevice.h> 36 #include <linux/cpumask.h> 37 #include <linux/aer.h> 38 #include <linux/if_vlan.h> 39 #include <linux/jiffies.h> 40 41 #include <linux/timecounter.h> 42 #include <linux/net_tstamp.h> 43 #include <linux/ptp_clock_kernel.h> 44 45 #include "ixgbe_type.h" 46 #include "ixgbe_common.h" 47 #include "ixgbe_dcb.h" 48 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) 49 #define IXGBE_FCOE 50 #include "ixgbe_fcoe.h" 51 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ 52 #ifdef CONFIG_IXGBE_DCA 53 #include <linux/dca.h> 54 #endif 55 56 #include <net/busy_poll.h> 57 58 #ifdef CONFIG_NET_RX_BUSY_POLL 59 #define BP_EXTENDED_STATS 60 #endif 61 /* common prefix used by pr_<> macros */ 62 #undef pr_fmt 63 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 64 65 /* TX/RX descriptor defines */ 66 #define IXGBE_DEFAULT_TXD 512 67 #define IXGBE_DEFAULT_TX_WORK 256 68 #define IXGBE_MAX_TXD 4096 69 #define IXGBE_MIN_TXD 64 70 71 #if (PAGE_SIZE < 8192) 72 #define IXGBE_DEFAULT_RXD 512 73 #else 74 #define IXGBE_DEFAULT_RXD 128 75 #endif 76 #define IXGBE_MAX_RXD 4096 77 #define IXGBE_MIN_RXD 64 78 79 #define IXGBE_ETH_P_LLDP 0x88CC 80 81 /* flow control */ 82 #define IXGBE_MIN_FCRTL 0x40 83 #define IXGBE_MAX_FCRTL 0x7FF80 84 #define IXGBE_MIN_FCRTH 0x600 85 #define IXGBE_MAX_FCRTH 0x7FFF0 86 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF 87 #define IXGBE_MIN_FCPAUSE 0 88 #define IXGBE_MAX_FCPAUSE 0xFFFF 89 90 /* Supported Rx Buffer Sizes */ 91 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ 92 #define IXGBE_RXBUFFER_2K 2048 93 #define IXGBE_RXBUFFER_3K 3072 94 #define IXGBE_RXBUFFER_4K 4096 95 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 96 97 /* 98 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 99 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, 100 * this adds up to 448 bytes of extra data. 101 * 102 * Since netdev_alloc_skb now allocates a page fragment we can use a value 103 * of 256 and the resultant skb will have a truesize of 960 or less. 104 */ 105 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 106 107 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 108 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 109 110 enum ixgbe_tx_flags { 111 /* cmd_type flags */ 112 IXGBE_TX_FLAGS_HW_VLAN = 0x01, 113 IXGBE_TX_FLAGS_TSO = 0x02, 114 IXGBE_TX_FLAGS_TSTAMP = 0x04, 115 116 /* olinfo flags */ 117 IXGBE_TX_FLAGS_CC = 0x08, 118 IXGBE_TX_FLAGS_IPV4 = 0x10, 119 IXGBE_TX_FLAGS_CSUM = 0x20, 120 121 /* software defined flags */ 122 IXGBE_TX_FLAGS_SW_VLAN = 0x40, 123 IXGBE_TX_FLAGS_FCOE = 0x80, 124 }; 125 126 /* VLAN info */ 127 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 128 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 129 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 130 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 131 132 #define IXGBE_MAX_VF_MC_ENTRIES 30 133 #define IXGBE_MAX_VF_FUNCTIONS 64 134 #define IXGBE_MAX_VFTA_ENTRIES 128 135 #define MAX_EMULATION_MAC_ADDRS 16 136 #define IXGBE_MAX_PF_MACVLANS 15 137 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) 138 #define IXGBE_82599_VF_DEVICE_ID 0x10ED 139 #define IXGBE_X540_VF_DEVICE_ID 0x1515 140 141 struct vf_data_storage { 142 struct pci_dev *vfdev; 143 unsigned char vf_mac_addresses[ETH_ALEN]; 144 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 145 u16 num_vf_mc_hashes; 146 u16 default_vf_vlan_id; 147 u16 vlans_enabled; 148 bool clear_to_send; 149 bool pf_set_mac; 150 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 151 u16 pf_qos; 152 u16 tx_rate; 153 u16 vlan_count; 154 u8 spoofchk_enabled; 155 bool rss_query_enabled; 156 u8 trusted; 157 int xcast_mode; 158 unsigned int vf_api; 159 }; 160 161 enum ixgbevf_xcast_modes { 162 IXGBEVF_XCAST_MODE_NONE = 0, 163 IXGBEVF_XCAST_MODE_MULTI, 164 IXGBEVF_XCAST_MODE_ALLMULTI, 165 }; 166 167 struct vf_macvlans { 168 struct list_head l; 169 int vf; 170 bool free; 171 bool is_macvlan; 172 u8 vf_macvlan[ETH_ALEN]; 173 }; 174 175 #define IXGBE_MAX_TXD_PWR 14 176 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) 177 178 /* Tx Descriptors needed, worst case */ 179 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 180 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 181 182 /* wrapper around a pointer to a socket buffer, 183 * so a DMA handle can be stored along with the buffer */ 184 struct ixgbe_tx_buffer { 185 union ixgbe_adv_tx_desc *next_to_watch; 186 unsigned long time_stamp; 187 struct sk_buff *skb; 188 unsigned int bytecount; 189 unsigned short gso_segs; 190 __be16 protocol; 191 DEFINE_DMA_UNMAP_ADDR(dma); 192 DEFINE_DMA_UNMAP_LEN(len); 193 u32 tx_flags; 194 }; 195 196 struct ixgbe_rx_buffer { 197 struct sk_buff *skb; 198 dma_addr_t dma; 199 struct page *page; 200 unsigned int page_offset; 201 }; 202 203 struct ixgbe_queue_stats { 204 u64 packets; 205 u64 bytes; 206 #ifdef BP_EXTENDED_STATS 207 u64 yields; 208 u64 misses; 209 u64 cleaned; 210 #endif /* BP_EXTENDED_STATS */ 211 }; 212 213 struct ixgbe_tx_queue_stats { 214 u64 restart_queue; 215 u64 tx_busy; 216 u64 tx_done_old; 217 }; 218 219 struct ixgbe_rx_queue_stats { 220 u64 rsc_count; 221 u64 rsc_flush; 222 u64 non_eop_descs; 223 u64 alloc_rx_page_failed; 224 u64 alloc_rx_buff_failed; 225 u64 csum_err; 226 }; 227 228 #define IXGBE_TS_HDR_LEN 8 229 230 enum ixgbe_ring_state_t { 231 __IXGBE_TX_FDIR_INIT_DONE, 232 __IXGBE_TX_XPS_INIT_DONE, 233 __IXGBE_TX_DETECT_HANG, 234 __IXGBE_HANG_CHECK_ARMED, 235 __IXGBE_RX_RSC_ENABLED, 236 __IXGBE_RX_CSUM_UDP_ZERO_ERR, 237 __IXGBE_RX_FCOE, 238 }; 239 240 struct ixgbe_fwd_adapter { 241 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 242 struct net_device *netdev; 243 struct ixgbe_adapter *real_adapter; 244 unsigned int tx_base_queue; 245 unsigned int rx_base_queue; 246 int pool; 247 }; 248 249 #define check_for_tx_hang(ring) \ 250 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 251 #define set_check_for_tx_hang(ring) \ 252 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 253 #define clear_check_for_tx_hang(ring) \ 254 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 255 #define ring_is_rsc_enabled(ring) \ 256 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 257 #define set_ring_rsc_enabled(ring) \ 258 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 259 #define clear_ring_rsc_enabled(ring) \ 260 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 261 struct ixgbe_ring { 262 struct ixgbe_ring *next; /* pointer to next ring in q_vector */ 263 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ 264 struct net_device *netdev; /* netdev ring belongs to */ 265 struct device *dev; /* device for DMA mapping */ 266 struct ixgbe_fwd_adapter *l2_accel_priv; 267 void *desc; /* descriptor ring memory */ 268 union { 269 struct ixgbe_tx_buffer *tx_buffer_info; 270 struct ixgbe_rx_buffer *rx_buffer_info; 271 }; 272 unsigned long state; 273 u8 __iomem *tail; 274 dma_addr_t dma; /* phys. address of descriptor ring */ 275 unsigned int size; /* length in bytes */ 276 277 u16 count; /* amount of descriptors */ 278 279 u8 queue_index; /* needed for multiqueue queue management */ 280 u8 reg_idx; /* holds the special value that gets 281 * the hardware register offset 282 * associated with this ring, which is 283 * different for DCB and RSS modes 284 */ 285 u16 next_to_use; 286 u16 next_to_clean; 287 288 unsigned long last_rx_timestamp; 289 290 union { 291 u16 next_to_alloc; 292 struct { 293 u8 atr_sample_rate; 294 u8 atr_count; 295 }; 296 }; 297 298 u8 dcb_tc; 299 struct ixgbe_queue_stats stats; 300 struct u64_stats_sync syncp; 301 union { 302 struct ixgbe_tx_queue_stats tx_stats; 303 struct ixgbe_rx_queue_stats rx_stats; 304 }; 305 } ____cacheline_internodealigned_in_smp; 306 307 enum ixgbe_ring_f_enum { 308 RING_F_NONE = 0, 309 RING_F_VMDQ, /* SR-IOV uses the same ring feature */ 310 RING_F_RSS, 311 RING_F_FDIR, 312 #ifdef IXGBE_FCOE 313 RING_F_FCOE, 314 #endif /* IXGBE_FCOE */ 315 316 RING_F_ARRAY_SIZE /* must be last in enum set */ 317 }; 318 319 #define IXGBE_MAX_RSS_INDICES 16 320 #define IXGBE_MAX_RSS_INDICES_X550 63 321 #define IXGBE_MAX_VMDQ_INDICES 64 322 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ 323 #define IXGBE_MAX_FCOE_INDICES 8 324 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 325 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 326 #define IXGBE_MAX_L2A_QUEUES 4 327 #define IXGBE_BAD_L2A_QUEUE 3 328 #define IXGBE_MAX_MACVLANS 31 329 #define IXGBE_MAX_DCBMACVLANS 8 330 331 struct ixgbe_ring_feature { 332 u16 limit; /* upper limit on feature indices */ 333 u16 indices; /* current value of indices */ 334 u16 mask; /* Mask used for feature to ring mapping */ 335 u16 offset; /* offset to start of feature */ 336 } ____cacheline_internodealigned_in_smp; 337 338 #define IXGBE_82599_VMDQ_8Q_MASK 0x78 339 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C 340 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E 341 342 /* 343 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since 344 * this is twice the size of a half page we need to double the page order 345 * for FCoE enabled Rx queues. 346 */ 347 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) 348 { 349 #ifdef IXGBE_FCOE 350 if (test_bit(__IXGBE_RX_FCOE, &ring->state)) 351 return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K : 352 IXGBE_RXBUFFER_3K; 353 #endif 354 return IXGBE_RXBUFFER_2K; 355 } 356 357 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) 358 { 359 #ifdef IXGBE_FCOE 360 if (test_bit(__IXGBE_RX_FCOE, &ring->state)) 361 return (PAGE_SIZE < 8192) ? 1 : 0; 362 #endif 363 return 0; 364 } 365 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) 366 367 struct ixgbe_ring_container { 368 struct ixgbe_ring *ring; /* pointer to linked list of rings */ 369 unsigned int total_bytes; /* total bytes processed this int */ 370 unsigned int total_packets; /* total packets processed this int */ 371 u16 work_limit; /* total work allowed per interrupt */ 372 u8 count; /* total number of rings in vector */ 373 u8 itr; /* current ITR setting for ring */ 374 }; 375 376 /* iterator for handling rings in ring container */ 377 #define ixgbe_for_each_ring(pos, head) \ 378 for (pos = (head).ring; pos != NULL; pos = pos->next) 379 380 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ 381 ? 8 : 1) 382 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS 383 384 /* MAX_Q_VECTORS of these are allocated, 385 * but we only use one per queue-specific vector. 386 */ 387 struct ixgbe_q_vector { 388 struct ixgbe_adapter *adapter; 389 #ifdef CONFIG_IXGBE_DCA 390 int cpu; /* CPU for DCA */ 391 #endif 392 u16 v_idx; /* index of q_vector within array, also used for 393 * finding the bit in EICR and friends that 394 * represents the vector for this ring */ 395 u16 itr; /* Interrupt throttle rate written to EITR */ 396 struct ixgbe_ring_container rx, tx; 397 398 struct napi_struct napi; 399 cpumask_t affinity_mask; 400 int numa_node; 401 struct rcu_head rcu; /* to avoid race with update stats on free */ 402 char name[IFNAMSIZ + 9]; 403 404 #ifdef CONFIG_NET_RX_BUSY_POLL 405 atomic_t state; 406 #endif /* CONFIG_NET_RX_BUSY_POLL */ 407 408 /* for dynamic allocation of rings associated with this q_vector */ 409 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; 410 }; 411 412 #ifdef CONFIG_NET_RX_BUSY_POLL 413 enum ixgbe_qv_state_t { 414 IXGBE_QV_STATE_IDLE = 0, 415 IXGBE_QV_STATE_NAPI, 416 IXGBE_QV_STATE_POLL, 417 IXGBE_QV_STATE_DISABLE 418 }; 419 420 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) 421 { 422 /* reset state to idle */ 423 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); 424 } 425 426 /* called from the device poll routine to get ownership of a q_vector */ 427 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) 428 { 429 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, 430 IXGBE_QV_STATE_NAPI); 431 #ifdef BP_EXTENDED_STATS 432 if (rc != IXGBE_QV_STATE_IDLE) 433 q_vector->tx.ring->stats.yields++; 434 #endif 435 436 return rc == IXGBE_QV_STATE_IDLE; 437 } 438 439 /* returns true is someone tried to get the qv while napi had it */ 440 static inline void ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) 441 { 442 WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_NAPI); 443 444 /* flush any outstanding Rx frames */ 445 if (q_vector->napi.gro_list) 446 napi_gro_flush(&q_vector->napi, false); 447 448 /* reset state to idle */ 449 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); 450 } 451 452 /* called from ixgbe_low_latency_poll() */ 453 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) 454 { 455 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, 456 IXGBE_QV_STATE_POLL); 457 #ifdef BP_EXTENDED_STATS 458 if (rc != IXGBE_QV_STATE_IDLE) 459 q_vector->tx.ring->stats.yields++; 460 #endif 461 return rc == IXGBE_QV_STATE_IDLE; 462 } 463 464 /* returns true if someone tried to get the qv while it was locked */ 465 static inline void ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) 466 { 467 WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_POLL); 468 469 /* reset state to idle */ 470 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); 471 } 472 473 /* true if a socket is polling, even if it did not get the lock */ 474 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) 475 { 476 return atomic_read(&q_vector->state) == IXGBE_QV_STATE_POLL; 477 } 478 479 /* false if QV is currently owned */ 480 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) 481 { 482 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, 483 IXGBE_QV_STATE_DISABLE); 484 485 return rc == IXGBE_QV_STATE_IDLE; 486 } 487 488 #else /* CONFIG_NET_RX_BUSY_POLL */ 489 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) 490 { 491 } 492 493 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) 494 { 495 return true; 496 } 497 498 static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) 499 { 500 return false; 501 } 502 503 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) 504 { 505 return false; 506 } 507 508 static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) 509 { 510 return false; 511 } 512 513 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) 514 { 515 return false; 516 } 517 518 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) 519 { 520 return true; 521 } 522 523 #endif /* CONFIG_NET_RX_BUSY_POLL */ 524 525 #ifdef CONFIG_IXGBE_HWMON 526 527 #define IXGBE_HWMON_TYPE_LOC 0 528 #define IXGBE_HWMON_TYPE_TEMP 1 529 #define IXGBE_HWMON_TYPE_CAUTION 2 530 #define IXGBE_HWMON_TYPE_MAX 3 531 532 struct hwmon_attr { 533 struct device_attribute dev_attr; 534 struct ixgbe_hw *hw; 535 struct ixgbe_thermal_diode_data *sensor; 536 char name[12]; 537 }; 538 539 struct hwmon_buff { 540 struct attribute_group group; 541 const struct attribute_group *groups[2]; 542 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; 543 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; 544 unsigned int n_hwmon; 545 }; 546 #endif /* CONFIG_IXGBE_HWMON */ 547 548 /* 549 * microsecond values for various ITR rates shifted by 2 to fit itr register 550 * with the first 3 bits reserved 0 551 */ 552 #define IXGBE_MIN_RSC_ITR 24 553 #define IXGBE_100K_ITR 40 554 #define IXGBE_20K_ITR 200 555 #define IXGBE_12K_ITR 336 556 557 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ 558 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, 559 const u32 stat_err_bits) 560 { 561 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 562 } 563 564 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) 565 { 566 u16 ntc = ring->next_to_clean; 567 u16 ntu = ring->next_to_use; 568 569 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 570 } 571 572 #define IXGBE_RX_DESC(R, i) \ 573 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 574 #define IXGBE_TX_DESC(R, i) \ 575 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 576 #define IXGBE_TX_CTXTDESC(R, i) \ 577 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 578 579 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ 580 #ifdef IXGBE_FCOE 581 /* Use 3K as the baby jumbo frame size for FCoE */ 582 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 583 #endif /* IXGBE_FCOE */ 584 585 #define OTHER_VECTOR 1 586 #define NON_Q_VECTORS (OTHER_VECTOR) 587 588 #define MAX_MSIX_VECTORS_82599 64 589 #define MAX_Q_VECTORS_82599 64 590 #define MAX_MSIX_VECTORS_82598 18 591 #define MAX_Q_VECTORS_82598 16 592 593 struct ixgbe_mac_addr { 594 u8 addr[ETH_ALEN]; 595 u16 pool; 596 u16 state; /* bitmask */ 597 }; 598 599 #define IXGBE_MAC_STATE_DEFAULT 0x1 600 #define IXGBE_MAC_STATE_MODIFIED 0x2 601 #define IXGBE_MAC_STATE_IN_USE 0x4 602 603 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 604 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 605 606 #define MIN_MSIX_Q_VECTORS 1 607 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 608 609 /* default to trying for four seconds */ 610 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 611 #define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */ 612 613 /* board specific private data structure */ 614 struct ixgbe_adapter { 615 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 616 /* OS defined structs */ 617 struct net_device *netdev; 618 struct pci_dev *pdev; 619 620 unsigned long state; 621 622 /* Some features need tri-state capability, 623 * thus the additional *_CAPABLE flags. 624 */ 625 u32 flags; 626 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1) 627 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3) 628 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4) 629 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5) 630 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6) 631 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8) 632 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9) 633 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10) 634 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11) 635 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12) 636 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13) 637 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14) 638 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15) 639 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16) 640 #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17) 641 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18) 642 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19) 643 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20) 644 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21) 645 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22) 646 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23) 647 #define IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE BIT(24) 648 #define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25) 649 #define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26) 650 651 u32 flags2; 652 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0) 653 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) 654 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) 655 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3) 656 #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4) 657 #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5) 658 #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6) 659 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7) 660 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8) 661 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9) 662 #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10) 663 #define IXGBE_FLAG2_PHY_INTERRUPT (u32)(1 << 11) 664 #ifdef CONFIG_IXGBE_VXLAN 665 #define IXGBE_FLAG2_VXLAN_REREG_NEEDED BIT(12) 666 #endif 667 #define IXGBE_FLAG2_VLAN_PROMISC BIT(13) 668 669 /* Tx fast path data */ 670 int num_tx_queues; 671 u16 tx_itr_setting; 672 u16 tx_work_limit; 673 674 /* Rx fast path data */ 675 int num_rx_queues; 676 u16 rx_itr_setting; 677 678 /* TX */ 679 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; 680 681 u64 restart_queue; 682 u64 lsc_int; 683 u32 tx_timeout_count; 684 685 /* RX */ 686 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; 687 int num_rx_pools; /* == num_rx_queues in 82598 */ 688 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ 689 u64 hw_csum_rx_error; 690 u64 hw_rx_no_dma_resources; 691 u64 rsc_total_count; 692 u64 rsc_total_flush; 693 u64 non_eop_descs; 694 u32 alloc_rx_page_failed; 695 u32 alloc_rx_buff_failed; 696 697 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; 698 699 /* DCB parameters */ 700 struct ieee_pfc *ixgbe_ieee_pfc; 701 struct ieee_ets *ixgbe_ieee_ets; 702 struct ixgbe_dcb_config dcb_cfg; 703 struct ixgbe_dcb_config temp_dcb_cfg; 704 u8 dcb_set_bitmap; 705 u8 dcbx_cap; 706 enum ixgbe_fc_mode last_lfc_mode; 707 708 int num_q_vectors; /* current number of q_vectors for device */ 709 int max_q_vectors; /* true count of q_vectors for device */ 710 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; 711 struct msix_entry *msix_entries; 712 713 u32 test_icr; 714 struct ixgbe_ring test_tx_ring; 715 struct ixgbe_ring test_rx_ring; 716 717 /* structs defined in ixgbe_hw.h */ 718 struct ixgbe_hw hw; 719 u16 msg_enable; 720 struct ixgbe_hw_stats stats; 721 722 u64 tx_busy; 723 unsigned int tx_ring_count; 724 unsigned int rx_ring_count; 725 726 u32 link_speed; 727 bool link_up; 728 unsigned long sfp_poll_time; 729 unsigned long link_check_timeout; 730 731 struct timer_list service_timer; 732 struct work_struct service_task; 733 734 struct hlist_head fdir_filter_list; 735 unsigned long fdir_overflow; /* number of times ATR was backed off */ 736 union ixgbe_atr_input fdir_mask; 737 int fdir_filter_count; 738 u32 fdir_pballoc; 739 u32 atr_sample_rate; 740 spinlock_t fdir_perfect_lock; 741 742 #ifdef IXGBE_FCOE 743 struct ixgbe_fcoe fcoe; 744 #endif /* IXGBE_FCOE */ 745 u8 __iomem *io_addr; /* Mainly for iounmap use */ 746 u32 wol; 747 748 u16 bridge_mode; 749 750 u16 eeprom_verh; 751 u16 eeprom_verl; 752 u16 eeprom_cap; 753 754 u32 interrupt_event; 755 u32 led_reg; 756 757 struct ptp_clock *ptp_clock; 758 struct ptp_clock_info ptp_caps; 759 struct work_struct ptp_tx_work; 760 struct sk_buff *ptp_tx_skb; 761 struct hwtstamp_config tstamp_config; 762 unsigned long ptp_tx_start; 763 unsigned long last_overflow_check; 764 unsigned long last_rx_ptp_check; 765 unsigned long last_rx_timestamp; 766 spinlock_t tmreg_lock; 767 struct cyclecounter hw_cc; 768 struct timecounter hw_tc; 769 u32 base_incval; 770 u32 tx_hwtstamp_timeouts; 771 u32 rx_hwtstamp_cleared; 772 void (*ptp_setup_sdp)(struct ixgbe_adapter *); 773 774 /* SR-IOV */ 775 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 776 unsigned int num_vfs; 777 struct vf_data_storage *vfinfo; 778 int vf_rate_link_speed; 779 struct vf_macvlans vf_mvs; 780 struct vf_macvlans *mv_list; 781 782 u32 timer_event_accumulator; 783 u32 vferr_refcount; 784 struct ixgbe_mac_addr *mac_table; 785 #ifdef CONFIG_IXGBE_VXLAN 786 u16 vxlan_port; 787 #endif 788 struct kobject *info_kobj; 789 #ifdef CONFIG_IXGBE_HWMON 790 struct hwmon_buff *ixgbe_hwmon_buff; 791 #endif /* CONFIG_IXGBE_HWMON */ 792 #ifdef CONFIG_DEBUG_FS 793 struct dentry *ixgbe_dbg_adapter; 794 #endif /*CONFIG_DEBUG_FS*/ 795 796 u8 default_up; 797 unsigned long fwd_bitmask; /* Bitmask indicating in use pools */ 798 799 #define IXGBE_MAX_LINK_HANDLE 10 800 struct ixgbe_mat_field *jump_tables[IXGBE_MAX_LINK_HANDLE]; 801 unsigned long tables; 802 803 /* maximum number of RETA entries among all devices supported by ixgbe 804 * driver: currently it's x550 device in non-SRIOV mode 805 */ 806 #define IXGBE_MAX_RETA_ENTRIES 512 807 u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES]; 808 809 #define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */ 810 u32 rss_key[IXGBE_RSS_KEY_SIZE / sizeof(u32)]; 811 }; 812 813 static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter) 814 { 815 switch (adapter->hw.mac.type) { 816 case ixgbe_mac_82598EB: 817 case ixgbe_mac_82599EB: 818 case ixgbe_mac_X540: 819 return IXGBE_MAX_RSS_INDICES; 820 case ixgbe_mac_X550: 821 case ixgbe_mac_X550EM_x: 822 return IXGBE_MAX_RSS_INDICES_X550; 823 default: 824 return 0; 825 } 826 } 827 828 struct ixgbe_fdir_filter { 829 struct hlist_node fdir_node; 830 union ixgbe_atr_input filter; 831 u16 sw_idx; 832 u16 action; 833 }; 834 835 enum ixgbe_state_t { 836 __IXGBE_TESTING, 837 __IXGBE_RESETTING, 838 __IXGBE_DOWN, 839 __IXGBE_DISABLED, 840 __IXGBE_REMOVING, 841 __IXGBE_SERVICE_SCHED, 842 __IXGBE_SERVICE_INITED, 843 __IXGBE_IN_SFP_INIT, 844 __IXGBE_PTP_RUNNING, 845 __IXGBE_PTP_TX_IN_PROGRESS, 846 }; 847 848 struct ixgbe_cb { 849 union { /* Union defining head/tail partner */ 850 struct sk_buff *head; 851 struct sk_buff *tail; 852 }; 853 dma_addr_t dma; 854 u16 append_cnt; 855 bool page_released; 856 }; 857 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) 858 859 enum ixgbe_boards { 860 board_82598, 861 board_82599, 862 board_X540, 863 board_X550, 864 board_X550EM_x, 865 }; 866 867 extern struct ixgbe_info ixgbe_82598_info; 868 extern struct ixgbe_info ixgbe_82599_info; 869 extern struct ixgbe_info ixgbe_X540_info; 870 extern struct ixgbe_info ixgbe_X550_info; 871 extern struct ixgbe_info ixgbe_X550EM_x_info; 872 #ifdef CONFIG_IXGBE_DCB 873 extern const struct dcbnl_rtnl_ops dcbnl_ops; 874 #endif 875 876 extern char ixgbe_driver_name[]; 877 extern const char ixgbe_driver_version[]; 878 #ifdef IXGBE_FCOE 879 extern char ixgbe_default_device_descr[]; 880 #endif /* IXGBE_FCOE */ 881 882 void ixgbe_up(struct ixgbe_adapter *adapter); 883 void ixgbe_down(struct ixgbe_adapter *adapter); 884 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); 885 void ixgbe_reset(struct ixgbe_adapter *adapter); 886 void ixgbe_set_ethtool_ops(struct net_device *netdev); 887 int ixgbe_setup_rx_resources(struct ixgbe_ring *); 888 int ixgbe_setup_tx_resources(struct ixgbe_ring *); 889 void ixgbe_free_rx_resources(struct ixgbe_ring *); 890 void ixgbe_free_tx_resources(struct ixgbe_ring *); 891 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 892 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 893 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *); 894 void ixgbe_update_stats(struct ixgbe_adapter *adapter); 895 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); 896 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 897 u16 subdevice_id); 898 #ifdef CONFIG_PCI_IOV 899 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter); 900 #endif 901 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 902 const u8 *addr, u16 queue); 903 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 904 const u8 *addr, u16 queue); 905 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid); 906 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); 907 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, 908 struct ixgbe_ring *); 909 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, 910 struct ixgbe_tx_buffer *); 911 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); 912 void ixgbe_write_eitr(struct ixgbe_q_vector *); 913 int ixgbe_poll(struct napi_struct *napi, int budget); 914 int ethtool_ioctl(struct ifreq *ifr); 915 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 916 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); 917 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); 918 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 919 union ixgbe_atr_hash_dword input, 920 union ixgbe_atr_hash_dword common, 921 u8 queue); 922 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 923 union ixgbe_atr_input *input_mask); 924 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 925 union ixgbe_atr_input *input, 926 u16 soft_id, u8 queue); 927 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 928 union ixgbe_atr_input *input, 929 u16 soft_id); 930 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 931 union ixgbe_atr_input *mask); 932 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 933 struct ixgbe_fdir_filter *input, 934 u16 sw_idx); 935 void ixgbe_set_rx_mode(struct net_device *netdev); 936 #ifdef CONFIG_IXGBE_DCB 937 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); 938 #endif 939 int ixgbe_setup_tc(struct net_device *dev, u8 tc); 940 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); 941 void ixgbe_do_reset(struct net_device *netdev); 942 #ifdef CONFIG_IXGBE_HWMON 943 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); 944 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); 945 #endif /* CONFIG_IXGBE_HWMON */ 946 #ifdef IXGBE_FCOE 947 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 948 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 949 u8 *hdr_len); 950 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, 951 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); 952 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, 953 struct scatterlist *sgl, unsigned int sgc); 954 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, 955 struct scatterlist *sgl, unsigned int sgc); 956 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); 957 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 958 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 959 int ixgbe_fcoe_enable(struct net_device *netdev); 960 int ixgbe_fcoe_disable(struct net_device *netdev); 961 #ifdef CONFIG_IXGBE_DCB 962 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); 963 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); 964 #endif /* CONFIG_IXGBE_DCB */ 965 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); 966 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, 967 struct netdev_fcoe_hbainfo *info); 968 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); 969 #endif /* IXGBE_FCOE */ 970 #ifdef CONFIG_DEBUG_FS 971 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); 972 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); 973 void ixgbe_dbg_init(void); 974 void ixgbe_dbg_exit(void); 975 #else 976 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} 977 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} 978 static inline void ixgbe_dbg_init(void) {} 979 static inline void ixgbe_dbg_exit(void) {} 980 #endif /* CONFIG_DEBUG_FS */ 981 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) 982 { 983 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 984 } 985 986 void ixgbe_ptp_init(struct ixgbe_adapter *adapter); 987 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter); 988 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); 989 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); 990 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); 991 void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *); 992 void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb); 993 static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring, 994 union ixgbe_adv_rx_desc *rx_desc, 995 struct sk_buff *skb) 996 { 997 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) { 998 ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb); 999 return; 1000 } 1001 1002 if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) 1003 return; 1004 1005 ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 1006 1007 /* Update the last_rx_timestamp timer in order to enable watchdog check 1008 * for error case of latched timestamp on a dropped packet. 1009 */ 1010 rx_ring->last_rx_timestamp = jiffies; 1011 } 1012 1013 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 1014 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 1015 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); 1016 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); 1017 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter); 1018 #ifdef CONFIG_PCI_IOV 1019 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); 1020 #endif 1021 1022 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 1023 struct ixgbe_adapter *adapter, 1024 struct ixgbe_ring *tx_ring); 1025 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter); 1026 void ixgbe_store_reta(struct ixgbe_adapter *adapter); 1027 #endif /* _IXGBE_H_ */ 1028