1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #ifndef _IXGBE_H_ 5 #define _IXGBE_H_ 6 7 #include <linux/bitops.h> 8 #include <linux/types.h> 9 #include <linux/pci.h> 10 #include <linux/netdevice.h> 11 #include <linux/cpumask.h> 12 #include <linux/aer.h> 13 #include <linux/if_vlan.h> 14 #include <linux/jiffies.h> 15 16 #include <linux/timecounter.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/ptp_clock_kernel.h> 19 20 #include "ixgbe_type.h" 21 #include "ixgbe_common.h" 22 #include "ixgbe_dcb.h" 23 #if IS_ENABLED(CONFIG_FCOE) 24 #define IXGBE_FCOE 25 #include "ixgbe_fcoe.h" 26 #endif /* IS_ENABLED(CONFIG_FCOE) */ 27 #ifdef CONFIG_IXGBE_DCA 28 #include <linux/dca.h> 29 #endif 30 #include "ixgbe_ipsec.h" 31 32 #include <net/xdp.h> 33 #include <net/busy_poll.h> 34 35 /* common prefix used by pr_<> macros */ 36 #undef pr_fmt 37 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 38 39 /* TX/RX descriptor defines */ 40 #define IXGBE_DEFAULT_TXD 512 41 #define IXGBE_DEFAULT_TX_WORK 256 42 #define IXGBE_MAX_TXD 4096 43 #define IXGBE_MIN_TXD 64 44 45 #if (PAGE_SIZE < 8192) 46 #define IXGBE_DEFAULT_RXD 512 47 #else 48 #define IXGBE_DEFAULT_RXD 128 49 #endif 50 #define IXGBE_MAX_RXD 4096 51 #define IXGBE_MIN_RXD 64 52 53 #define IXGBE_ETH_P_LLDP 0x88CC 54 55 /* flow control */ 56 #define IXGBE_MIN_FCRTL 0x40 57 #define IXGBE_MAX_FCRTL 0x7FF80 58 #define IXGBE_MIN_FCRTH 0x600 59 #define IXGBE_MAX_FCRTH 0x7FFF0 60 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF 61 #define IXGBE_MIN_FCPAUSE 0 62 #define IXGBE_MAX_FCPAUSE 0xFFFF 63 64 /* Supported Rx Buffer Sizes */ 65 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ 66 #define IXGBE_RXBUFFER_1536 1536 67 #define IXGBE_RXBUFFER_2K 2048 68 #define IXGBE_RXBUFFER_3K 3072 69 #define IXGBE_RXBUFFER_4K 4096 70 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 71 72 /* Attempt to maximize the headroom available for incoming frames. We 73 * use a 2K buffer for receives and need 1536/1534 to store the data for 74 * the frame. This leaves us with 512 bytes of room. From that we need 75 * to deduct the space needed for the shared info and the padding needed 76 * to IP align the frame. 77 * 78 * Note: For cache line sizes 256 or larger this value is going to end 79 * up negative. In these cases we should fall back to the 3K 80 * buffers. 81 */ 82 #if (PAGE_SIZE < 8192) 83 #define IXGBE_MAX_2K_FRAME_BUILD_SKB (IXGBE_RXBUFFER_1536 - NET_IP_ALIGN) 84 #define IXGBE_2K_TOO_SMALL_WITH_PADDING \ 85 ((NET_SKB_PAD + IXGBE_RXBUFFER_1536) > SKB_WITH_OVERHEAD(IXGBE_RXBUFFER_2K)) 86 87 static inline int ixgbe_compute_pad(int rx_buf_len) 88 { 89 int page_size, pad_size; 90 91 page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2); 92 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len; 93 94 return pad_size; 95 } 96 97 static inline int ixgbe_skb_pad(void) 98 { 99 int rx_buf_len; 100 101 /* If a 2K buffer cannot handle a standard Ethernet frame then 102 * optimize padding for a 3K buffer instead of a 1.5K buffer. 103 * 104 * For a 3K buffer we need to add enough padding to allow for 105 * tailroom due to NET_IP_ALIGN possibly shifting us out of 106 * cache-line alignment. 107 */ 108 if (IXGBE_2K_TOO_SMALL_WITH_PADDING) 109 rx_buf_len = IXGBE_RXBUFFER_3K + SKB_DATA_ALIGN(NET_IP_ALIGN); 110 else 111 rx_buf_len = IXGBE_RXBUFFER_1536; 112 113 /* if needed make room for NET_IP_ALIGN */ 114 rx_buf_len -= NET_IP_ALIGN; 115 116 return ixgbe_compute_pad(rx_buf_len); 117 } 118 119 #define IXGBE_SKB_PAD ixgbe_skb_pad() 120 #else 121 #define IXGBE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 122 #endif 123 124 /* 125 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 126 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, 127 * this adds up to 448 bytes of extra data. 128 * 129 * Since netdev_alloc_skb now allocates a page fragment we can use a value 130 * of 256 and the resultant skb will have a truesize of 960 or less. 131 */ 132 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 133 134 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 135 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 136 137 #define IXGBE_RX_DMA_ATTR \ 138 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 139 140 enum ixgbe_tx_flags { 141 /* cmd_type flags */ 142 IXGBE_TX_FLAGS_HW_VLAN = 0x01, 143 IXGBE_TX_FLAGS_TSO = 0x02, 144 IXGBE_TX_FLAGS_TSTAMP = 0x04, 145 146 /* olinfo flags */ 147 IXGBE_TX_FLAGS_CC = 0x08, 148 IXGBE_TX_FLAGS_IPV4 = 0x10, 149 IXGBE_TX_FLAGS_CSUM = 0x20, 150 IXGBE_TX_FLAGS_IPSEC = 0x40, 151 152 /* software defined flags */ 153 IXGBE_TX_FLAGS_SW_VLAN = 0x80, 154 IXGBE_TX_FLAGS_FCOE = 0x100, 155 }; 156 157 /* VLAN info */ 158 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 159 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 160 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 161 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 162 163 #define IXGBE_MAX_VF_MC_ENTRIES 30 164 #define IXGBE_MAX_VF_FUNCTIONS 64 165 #define IXGBE_MAX_VFTA_ENTRIES 128 166 #define MAX_EMULATION_MAC_ADDRS 16 167 #define IXGBE_MAX_PF_MACVLANS 15 168 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) 169 #define IXGBE_82599_VF_DEVICE_ID 0x10ED 170 #define IXGBE_X540_VF_DEVICE_ID 0x1515 171 172 struct vf_data_storage { 173 struct pci_dev *vfdev; 174 unsigned char vf_mac_addresses[ETH_ALEN]; 175 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 176 u16 num_vf_mc_hashes; 177 bool clear_to_send; 178 bool pf_set_mac; 179 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 180 u16 pf_qos; 181 u16 tx_rate; 182 u8 spoofchk_enabled; 183 bool rss_query_enabled; 184 u8 trusted; 185 int xcast_mode; 186 unsigned int vf_api; 187 }; 188 189 enum ixgbevf_xcast_modes { 190 IXGBEVF_XCAST_MODE_NONE = 0, 191 IXGBEVF_XCAST_MODE_MULTI, 192 IXGBEVF_XCAST_MODE_ALLMULTI, 193 IXGBEVF_XCAST_MODE_PROMISC, 194 }; 195 196 struct vf_macvlans { 197 struct list_head l; 198 int vf; 199 bool free; 200 bool is_macvlan; 201 u8 vf_macvlan[ETH_ALEN]; 202 }; 203 204 #define IXGBE_MAX_TXD_PWR 14 205 #define IXGBE_MAX_DATA_PER_TXD (1u << IXGBE_MAX_TXD_PWR) 206 207 /* Tx Descriptors needed, worst case */ 208 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 209 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 210 211 /* wrapper around a pointer to a socket buffer, 212 * so a DMA handle can be stored along with the buffer */ 213 struct ixgbe_tx_buffer { 214 union ixgbe_adv_tx_desc *next_to_watch; 215 unsigned long time_stamp; 216 union { 217 struct sk_buff *skb; 218 struct xdp_frame *xdpf; 219 }; 220 unsigned int bytecount; 221 unsigned short gso_segs; 222 __be16 protocol; 223 DEFINE_DMA_UNMAP_ADDR(dma); 224 DEFINE_DMA_UNMAP_LEN(len); 225 u32 tx_flags; 226 }; 227 228 struct ixgbe_rx_buffer { 229 struct sk_buff *skb; 230 dma_addr_t dma; 231 struct page *page; 232 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 233 __u32 page_offset; 234 #else 235 __u16 page_offset; 236 #endif 237 __u16 pagecnt_bias; 238 }; 239 240 struct ixgbe_queue_stats { 241 u64 packets; 242 u64 bytes; 243 }; 244 245 struct ixgbe_tx_queue_stats { 246 u64 restart_queue; 247 u64 tx_busy; 248 u64 tx_done_old; 249 }; 250 251 struct ixgbe_rx_queue_stats { 252 u64 rsc_count; 253 u64 rsc_flush; 254 u64 non_eop_descs; 255 u64 alloc_rx_page; 256 u64 alloc_rx_page_failed; 257 u64 alloc_rx_buff_failed; 258 u64 csum_err; 259 }; 260 261 #define IXGBE_TS_HDR_LEN 8 262 263 enum ixgbe_ring_state_t { 264 __IXGBE_RX_3K_BUFFER, 265 __IXGBE_RX_BUILD_SKB_ENABLED, 266 __IXGBE_RX_RSC_ENABLED, 267 __IXGBE_RX_CSUM_UDP_ZERO_ERR, 268 __IXGBE_RX_FCOE, 269 __IXGBE_TX_FDIR_INIT_DONE, 270 __IXGBE_TX_XPS_INIT_DONE, 271 __IXGBE_TX_DETECT_HANG, 272 __IXGBE_HANG_CHECK_ARMED, 273 __IXGBE_TX_XDP_RING, 274 }; 275 276 #define ring_uses_build_skb(ring) \ 277 test_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &(ring)->state) 278 279 struct ixgbe_fwd_adapter { 280 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 281 struct net_device *netdev; 282 unsigned int tx_base_queue; 283 unsigned int rx_base_queue; 284 int pool; 285 }; 286 287 #define check_for_tx_hang(ring) \ 288 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 289 #define set_check_for_tx_hang(ring) \ 290 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 291 #define clear_check_for_tx_hang(ring) \ 292 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 293 #define ring_is_rsc_enabled(ring) \ 294 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 295 #define set_ring_rsc_enabled(ring) \ 296 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 297 #define clear_ring_rsc_enabled(ring) \ 298 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 299 #define ring_is_xdp(ring) \ 300 test_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 301 #define set_ring_xdp(ring) \ 302 set_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 303 #define clear_ring_xdp(ring) \ 304 clear_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 305 struct ixgbe_ring { 306 struct ixgbe_ring *next; /* pointer to next ring in q_vector */ 307 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ 308 struct net_device *netdev; /* netdev ring belongs to */ 309 struct bpf_prog *xdp_prog; 310 struct device *dev; /* device for DMA mapping */ 311 void *desc; /* descriptor ring memory */ 312 union { 313 struct ixgbe_tx_buffer *tx_buffer_info; 314 struct ixgbe_rx_buffer *rx_buffer_info; 315 }; 316 unsigned long state; 317 u8 __iomem *tail; 318 dma_addr_t dma; /* phys. address of descriptor ring */ 319 unsigned int size; /* length in bytes */ 320 321 u16 count; /* amount of descriptors */ 322 323 u8 queue_index; /* needed for multiqueue queue management */ 324 u8 reg_idx; /* holds the special value that gets 325 * the hardware register offset 326 * associated with this ring, which is 327 * different for DCB and RSS modes 328 */ 329 u16 next_to_use; 330 u16 next_to_clean; 331 332 unsigned long last_rx_timestamp; 333 334 union { 335 u16 next_to_alloc; 336 struct { 337 u8 atr_sample_rate; 338 u8 atr_count; 339 }; 340 }; 341 342 u8 dcb_tc; 343 struct ixgbe_queue_stats stats; 344 struct u64_stats_sync syncp; 345 union { 346 struct ixgbe_tx_queue_stats tx_stats; 347 struct ixgbe_rx_queue_stats rx_stats; 348 }; 349 struct xdp_rxq_info xdp_rxq; 350 } ____cacheline_internodealigned_in_smp; 351 352 enum ixgbe_ring_f_enum { 353 RING_F_NONE = 0, 354 RING_F_VMDQ, /* SR-IOV uses the same ring feature */ 355 RING_F_RSS, 356 RING_F_FDIR, 357 #ifdef IXGBE_FCOE 358 RING_F_FCOE, 359 #endif /* IXGBE_FCOE */ 360 361 RING_F_ARRAY_SIZE /* must be last in enum set */ 362 }; 363 364 #define IXGBE_MAX_RSS_INDICES 16 365 #define IXGBE_MAX_RSS_INDICES_X550 63 366 #define IXGBE_MAX_VMDQ_INDICES 64 367 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ 368 #define IXGBE_MAX_FCOE_INDICES 8 369 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 370 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 371 #define MAX_XDP_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 372 #define IXGBE_MAX_L2A_QUEUES 4 373 #define IXGBE_BAD_L2A_QUEUE 3 374 #define IXGBE_MAX_MACVLANS 63 375 376 struct ixgbe_ring_feature { 377 u16 limit; /* upper limit on feature indices */ 378 u16 indices; /* current value of indices */ 379 u16 mask; /* Mask used for feature to ring mapping */ 380 u16 offset; /* offset to start of feature */ 381 } ____cacheline_internodealigned_in_smp; 382 383 #define IXGBE_82599_VMDQ_8Q_MASK 0x78 384 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C 385 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E 386 387 /* 388 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since 389 * this is twice the size of a half page we need to double the page order 390 * for FCoE enabled Rx queues. 391 */ 392 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) 393 { 394 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 395 return IXGBE_RXBUFFER_3K; 396 #if (PAGE_SIZE < 8192) 397 if (ring_uses_build_skb(ring)) 398 return IXGBE_MAX_2K_FRAME_BUILD_SKB; 399 #endif 400 return IXGBE_RXBUFFER_2K; 401 } 402 403 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) 404 { 405 #if (PAGE_SIZE < 8192) 406 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 407 return 1; 408 #endif 409 return 0; 410 } 411 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) 412 413 #define IXGBE_ITR_ADAPTIVE_MIN_INC 2 414 #define IXGBE_ITR_ADAPTIVE_MIN_USECS 10 415 #define IXGBE_ITR_ADAPTIVE_MAX_USECS 126 416 #define IXGBE_ITR_ADAPTIVE_LATENCY 0x80 417 #define IXGBE_ITR_ADAPTIVE_BULK 0x00 418 419 struct ixgbe_ring_container { 420 struct ixgbe_ring *ring; /* pointer to linked list of rings */ 421 unsigned long next_update; /* jiffies value of last update */ 422 unsigned int total_bytes; /* total bytes processed this int */ 423 unsigned int total_packets; /* total packets processed this int */ 424 u16 work_limit; /* total work allowed per interrupt */ 425 u8 count; /* total number of rings in vector */ 426 u8 itr; /* current ITR setting for ring */ 427 }; 428 429 /* iterator for handling rings in ring container */ 430 #define ixgbe_for_each_ring(pos, head) \ 431 for (pos = (head).ring; pos != NULL; pos = pos->next) 432 433 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ 434 ? 8 : 1) 435 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS 436 437 /* MAX_Q_VECTORS of these are allocated, 438 * but we only use one per queue-specific vector. 439 */ 440 struct ixgbe_q_vector { 441 struct ixgbe_adapter *adapter; 442 #ifdef CONFIG_IXGBE_DCA 443 int cpu; /* CPU for DCA */ 444 #endif 445 u16 v_idx; /* index of q_vector within array, also used for 446 * finding the bit in EICR and friends that 447 * represents the vector for this ring */ 448 u16 itr; /* Interrupt throttle rate written to EITR */ 449 struct ixgbe_ring_container rx, tx; 450 451 struct napi_struct napi; 452 cpumask_t affinity_mask; 453 int numa_node; 454 struct rcu_head rcu; /* to avoid race with update stats on free */ 455 char name[IFNAMSIZ + 9]; 456 457 /* for dynamic allocation of rings associated with this q_vector */ 458 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; 459 }; 460 461 #ifdef CONFIG_IXGBE_HWMON 462 463 #define IXGBE_HWMON_TYPE_LOC 0 464 #define IXGBE_HWMON_TYPE_TEMP 1 465 #define IXGBE_HWMON_TYPE_CAUTION 2 466 #define IXGBE_HWMON_TYPE_MAX 3 467 468 struct hwmon_attr { 469 struct device_attribute dev_attr; 470 struct ixgbe_hw *hw; 471 struct ixgbe_thermal_diode_data *sensor; 472 char name[12]; 473 }; 474 475 struct hwmon_buff { 476 struct attribute_group group; 477 const struct attribute_group *groups[2]; 478 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; 479 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; 480 unsigned int n_hwmon; 481 }; 482 #endif /* CONFIG_IXGBE_HWMON */ 483 484 /* 485 * microsecond values for various ITR rates shifted by 2 to fit itr register 486 * with the first 3 bits reserved 0 487 */ 488 #define IXGBE_MIN_RSC_ITR 24 489 #define IXGBE_100K_ITR 40 490 #define IXGBE_20K_ITR 200 491 #define IXGBE_12K_ITR 336 492 493 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ 494 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, 495 const u32 stat_err_bits) 496 { 497 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 498 } 499 500 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) 501 { 502 u16 ntc = ring->next_to_clean; 503 u16 ntu = ring->next_to_use; 504 505 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 506 } 507 508 #define IXGBE_RX_DESC(R, i) \ 509 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 510 #define IXGBE_TX_DESC(R, i) \ 511 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 512 #define IXGBE_TX_CTXTDESC(R, i) \ 513 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 514 515 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ 516 #ifdef IXGBE_FCOE 517 /* Use 3K as the baby jumbo frame size for FCoE */ 518 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 519 #endif /* IXGBE_FCOE */ 520 521 #define OTHER_VECTOR 1 522 #define NON_Q_VECTORS (OTHER_VECTOR) 523 524 #define MAX_MSIX_VECTORS_82599 64 525 #define MAX_Q_VECTORS_82599 64 526 #define MAX_MSIX_VECTORS_82598 18 527 #define MAX_Q_VECTORS_82598 16 528 529 struct ixgbe_mac_addr { 530 u8 addr[ETH_ALEN]; 531 u16 pool; 532 u16 state; /* bitmask */ 533 }; 534 535 #define IXGBE_MAC_STATE_DEFAULT 0x1 536 #define IXGBE_MAC_STATE_MODIFIED 0x2 537 #define IXGBE_MAC_STATE_IN_USE 0x4 538 539 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 540 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 541 542 #define MIN_MSIX_Q_VECTORS 1 543 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 544 545 /* default to trying for four seconds */ 546 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 547 #define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */ 548 549 /* board specific private data structure */ 550 struct ixgbe_adapter { 551 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 552 /* OS defined structs */ 553 struct net_device *netdev; 554 struct bpf_prog *xdp_prog; 555 struct pci_dev *pdev; 556 557 unsigned long state; 558 559 /* Some features need tri-state capability, 560 * thus the additional *_CAPABLE flags. 561 */ 562 u32 flags; 563 #define IXGBE_FLAG_MSI_ENABLED BIT(1) 564 #define IXGBE_FLAG_MSIX_ENABLED BIT(3) 565 #define IXGBE_FLAG_RX_1BUF_CAPABLE BIT(4) 566 #define IXGBE_FLAG_RX_PS_CAPABLE BIT(5) 567 #define IXGBE_FLAG_RX_PS_ENABLED BIT(6) 568 #define IXGBE_FLAG_DCA_ENABLED BIT(8) 569 #define IXGBE_FLAG_DCA_CAPABLE BIT(9) 570 #define IXGBE_FLAG_IMIR_ENABLED BIT(10) 571 #define IXGBE_FLAG_MQ_CAPABLE BIT(11) 572 #define IXGBE_FLAG_DCB_ENABLED BIT(12) 573 #define IXGBE_FLAG_VMDQ_CAPABLE BIT(13) 574 #define IXGBE_FLAG_VMDQ_ENABLED BIT(14) 575 #define IXGBE_FLAG_FAN_FAIL_CAPABLE BIT(15) 576 #define IXGBE_FLAG_NEED_LINK_UPDATE BIT(16) 577 #define IXGBE_FLAG_NEED_LINK_CONFIG BIT(17) 578 #define IXGBE_FLAG_FDIR_HASH_CAPABLE BIT(18) 579 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE BIT(19) 580 #define IXGBE_FLAG_FCOE_CAPABLE BIT(20) 581 #define IXGBE_FLAG_FCOE_ENABLED BIT(21) 582 #define IXGBE_FLAG_SRIOV_CAPABLE BIT(22) 583 #define IXGBE_FLAG_SRIOV_ENABLED BIT(23) 584 #define IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE BIT(24) 585 #define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25) 586 #define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26) 587 #define IXGBE_FLAG_DCB_CAPABLE BIT(27) 588 #define IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE BIT(28) 589 590 u32 flags2; 591 #define IXGBE_FLAG2_RSC_CAPABLE BIT(0) 592 #define IXGBE_FLAG2_RSC_ENABLED BIT(1) 593 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE BIT(2) 594 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT BIT(3) 595 #define IXGBE_FLAG2_SEARCH_FOR_SFP BIT(4) 596 #define IXGBE_FLAG2_SFP_NEEDS_RESET BIT(5) 597 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT BIT(7) 598 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP BIT(8) 599 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP BIT(9) 600 #define IXGBE_FLAG2_PTP_PPS_ENABLED BIT(10) 601 #define IXGBE_FLAG2_PHY_INTERRUPT BIT(11) 602 #define IXGBE_FLAG2_UDP_TUN_REREG_NEEDED BIT(12) 603 #define IXGBE_FLAG2_VLAN_PROMISC BIT(13) 604 #define IXGBE_FLAG2_EEE_CAPABLE BIT(14) 605 #define IXGBE_FLAG2_EEE_ENABLED BIT(15) 606 #define IXGBE_FLAG2_RX_LEGACY BIT(16) 607 #define IXGBE_FLAG2_IPSEC_ENABLED BIT(17) 608 609 /* Tx fast path data */ 610 int num_tx_queues; 611 u16 tx_itr_setting; 612 u16 tx_work_limit; 613 u64 tx_ipsec; 614 615 /* Rx fast path data */ 616 int num_rx_queues; 617 u16 rx_itr_setting; 618 u64 rx_ipsec; 619 620 /* Port number used to identify VXLAN traffic */ 621 __be16 vxlan_port; 622 __be16 geneve_port; 623 624 /* XDP */ 625 int num_xdp_queues; 626 struct ixgbe_ring *xdp_ring[MAX_XDP_QUEUES]; 627 628 /* TX */ 629 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; 630 631 u64 restart_queue; 632 u64 lsc_int; 633 u32 tx_timeout_count; 634 635 /* RX */ 636 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; 637 int num_rx_pools; /* == num_rx_queues in 82598 */ 638 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ 639 u64 hw_csum_rx_error; 640 u64 hw_rx_no_dma_resources; 641 u64 rsc_total_count; 642 u64 rsc_total_flush; 643 u64 non_eop_descs; 644 u32 alloc_rx_page; 645 u32 alloc_rx_page_failed; 646 u32 alloc_rx_buff_failed; 647 648 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; 649 650 /* DCB parameters */ 651 struct ieee_pfc *ixgbe_ieee_pfc; 652 struct ieee_ets *ixgbe_ieee_ets; 653 struct ixgbe_dcb_config dcb_cfg; 654 struct ixgbe_dcb_config temp_dcb_cfg; 655 u8 hw_tcs; 656 u8 dcb_set_bitmap; 657 u8 dcbx_cap; 658 enum ixgbe_fc_mode last_lfc_mode; 659 660 int num_q_vectors; /* current number of q_vectors for device */ 661 int max_q_vectors; /* true count of q_vectors for device */ 662 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; 663 struct msix_entry *msix_entries; 664 665 u32 test_icr; 666 struct ixgbe_ring test_tx_ring; 667 struct ixgbe_ring test_rx_ring; 668 669 /* structs defined in ixgbe_hw.h */ 670 struct ixgbe_hw hw; 671 u16 msg_enable; 672 struct ixgbe_hw_stats stats; 673 674 u64 tx_busy; 675 unsigned int tx_ring_count; 676 unsigned int xdp_ring_count; 677 unsigned int rx_ring_count; 678 679 u32 link_speed; 680 bool link_up; 681 unsigned long sfp_poll_time; 682 unsigned long link_check_timeout; 683 684 struct timer_list service_timer; 685 struct work_struct service_task; 686 687 struct hlist_head fdir_filter_list; 688 unsigned long fdir_overflow; /* number of times ATR was backed off */ 689 union ixgbe_atr_input fdir_mask; 690 int fdir_filter_count; 691 u32 fdir_pballoc; 692 u32 atr_sample_rate; 693 spinlock_t fdir_perfect_lock; 694 695 #ifdef IXGBE_FCOE 696 struct ixgbe_fcoe fcoe; 697 #endif /* IXGBE_FCOE */ 698 u8 __iomem *io_addr; /* Mainly for iounmap use */ 699 u32 wol; 700 701 u16 bridge_mode; 702 703 char eeprom_id[NVM_VER_SIZE]; 704 u16 eeprom_cap; 705 706 u32 interrupt_event; 707 u32 led_reg; 708 709 struct ptp_clock *ptp_clock; 710 struct ptp_clock_info ptp_caps; 711 struct work_struct ptp_tx_work; 712 struct sk_buff *ptp_tx_skb; 713 struct hwtstamp_config tstamp_config; 714 unsigned long ptp_tx_start; 715 unsigned long last_overflow_check; 716 unsigned long last_rx_ptp_check; 717 unsigned long last_rx_timestamp; 718 spinlock_t tmreg_lock; 719 struct cyclecounter hw_cc; 720 struct timecounter hw_tc; 721 u32 base_incval; 722 u32 tx_hwtstamp_timeouts; 723 u32 tx_hwtstamp_skipped; 724 u32 rx_hwtstamp_cleared; 725 void (*ptp_setup_sdp)(struct ixgbe_adapter *); 726 727 /* SR-IOV */ 728 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 729 unsigned int num_vfs; 730 struct vf_data_storage *vfinfo; 731 int vf_rate_link_speed; 732 struct vf_macvlans vf_mvs; 733 struct vf_macvlans *mv_list; 734 735 u32 timer_event_accumulator; 736 u32 vferr_refcount; 737 struct ixgbe_mac_addr *mac_table; 738 struct kobject *info_kobj; 739 #ifdef CONFIG_IXGBE_HWMON 740 struct hwmon_buff *ixgbe_hwmon_buff; 741 #endif /* CONFIG_IXGBE_HWMON */ 742 #ifdef CONFIG_DEBUG_FS 743 struct dentry *ixgbe_dbg_adapter; 744 #endif /*CONFIG_DEBUG_FS*/ 745 746 u8 default_up; 747 /* Bitmask indicating in use pools */ 748 DECLARE_BITMAP(fwd_bitmask, IXGBE_MAX_MACVLANS + 1); 749 750 #define IXGBE_MAX_LINK_HANDLE 10 751 struct ixgbe_jump_table *jump_tables[IXGBE_MAX_LINK_HANDLE]; 752 unsigned long tables; 753 754 /* maximum number of RETA entries among all devices supported by ixgbe 755 * driver: currently it's x550 device in non-SRIOV mode 756 */ 757 #define IXGBE_MAX_RETA_ENTRIES 512 758 u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES]; 759 760 #define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */ 761 u32 *rss_key; 762 763 #ifdef CONFIG_XFRM_OFFLOAD 764 struct ixgbe_ipsec *ipsec; 765 #endif /* CONFIG_XFRM_OFFLOAD */ 766 }; 767 768 static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter) 769 { 770 switch (adapter->hw.mac.type) { 771 case ixgbe_mac_82598EB: 772 case ixgbe_mac_82599EB: 773 case ixgbe_mac_X540: 774 return IXGBE_MAX_RSS_INDICES; 775 case ixgbe_mac_X550: 776 case ixgbe_mac_X550EM_x: 777 case ixgbe_mac_x550em_a: 778 return IXGBE_MAX_RSS_INDICES_X550; 779 default: 780 return 0; 781 } 782 } 783 784 struct ixgbe_fdir_filter { 785 struct hlist_node fdir_node; 786 union ixgbe_atr_input filter; 787 u16 sw_idx; 788 u64 action; 789 }; 790 791 enum ixgbe_state_t { 792 __IXGBE_TESTING, 793 __IXGBE_RESETTING, 794 __IXGBE_DOWN, 795 __IXGBE_DISABLED, 796 __IXGBE_REMOVING, 797 __IXGBE_SERVICE_SCHED, 798 __IXGBE_SERVICE_INITED, 799 __IXGBE_IN_SFP_INIT, 800 __IXGBE_PTP_RUNNING, 801 __IXGBE_PTP_TX_IN_PROGRESS, 802 __IXGBE_RESET_REQUESTED, 803 }; 804 805 struct ixgbe_cb { 806 union { /* Union defining head/tail partner */ 807 struct sk_buff *head; 808 struct sk_buff *tail; 809 }; 810 dma_addr_t dma; 811 u16 append_cnt; 812 bool page_released; 813 }; 814 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) 815 816 enum ixgbe_boards { 817 board_82598, 818 board_82599, 819 board_X540, 820 board_X550, 821 board_X550EM_x, 822 board_x550em_x_fw, 823 board_x550em_a, 824 board_x550em_a_fw, 825 }; 826 827 extern const struct ixgbe_info ixgbe_82598_info; 828 extern const struct ixgbe_info ixgbe_82599_info; 829 extern const struct ixgbe_info ixgbe_X540_info; 830 extern const struct ixgbe_info ixgbe_X550_info; 831 extern const struct ixgbe_info ixgbe_X550EM_x_info; 832 extern const struct ixgbe_info ixgbe_x550em_x_fw_info; 833 extern const struct ixgbe_info ixgbe_x550em_a_info; 834 extern const struct ixgbe_info ixgbe_x550em_a_fw_info; 835 #ifdef CONFIG_IXGBE_DCB 836 extern const struct dcbnl_rtnl_ops ixgbe_dcbnl_ops; 837 #endif 838 839 extern char ixgbe_driver_name[]; 840 extern const char ixgbe_driver_version[]; 841 #ifdef IXGBE_FCOE 842 extern char ixgbe_default_device_descr[]; 843 #endif /* IXGBE_FCOE */ 844 845 int ixgbe_open(struct net_device *netdev); 846 int ixgbe_close(struct net_device *netdev); 847 void ixgbe_up(struct ixgbe_adapter *adapter); 848 void ixgbe_down(struct ixgbe_adapter *adapter); 849 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); 850 void ixgbe_reset(struct ixgbe_adapter *adapter); 851 void ixgbe_set_ethtool_ops(struct net_device *netdev); 852 int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); 853 int ixgbe_setup_tx_resources(struct ixgbe_ring *); 854 void ixgbe_free_rx_resources(struct ixgbe_ring *); 855 void ixgbe_free_tx_resources(struct ixgbe_ring *); 856 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 857 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 858 void ixgbe_disable_rx(struct ixgbe_adapter *adapter); 859 void ixgbe_disable_tx(struct ixgbe_adapter *adapter); 860 void ixgbe_update_stats(struct ixgbe_adapter *adapter); 861 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); 862 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 863 u16 subdevice_id); 864 #ifdef CONFIG_PCI_IOV 865 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter); 866 #endif 867 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 868 const u8 *addr, u16 queue); 869 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 870 const u8 *addr, u16 queue); 871 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid); 872 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); 873 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, 874 struct ixgbe_ring *); 875 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, 876 struct ixgbe_tx_buffer *); 877 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); 878 void ixgbe_write_eitr(struct ixgbe_q_vector *); 879 int ixgbe_poll(struct napi_struct *napi, int budget); 880 int ethtool_ioctl(struct ifreq *ifr); 881 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 882 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); 883 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); 884 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 885 union ixgbe_atr_hash_dword input, 886 union ixgbe_atr_hash_dword common, 887 u8 queue); 888 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 889 union ixgbe_atr_input *input_mask); 890 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 891 union ixgbe_atr_input *input, 892 u16 soft_id, u8 queue); 893 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 894 union ixgbe_atr_input *input, 895 u16 soft_id); 896 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 897 union ixgbe_atr_input *mask); 898 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 899 struct ixgbe_fdir_filter *input, 900 u16 sw_idx); 901 void ixgbe_set_rx_mode(struct net_device *netdev); 902 #ifdef CONFIG_IXGBE_DCB 903 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); 904 #endif 905 int ixgbe_setup_tc(struct net_device *dev, u8 tc); 906 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); 907 void ixgbe_do_reset(struct net_device *netdev); 908 #ifdef CONFIG_IXGBE_HWMON 909 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); 910 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); 911 #endif /* CONFIG_IXGBE_HWMON */ 912 #ifdef IXGBE_FCOE 913 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 914 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 915 u8 *hdr_len); 916 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, 917 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); 918 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, 919 struct scatterlist *sgl, unsigned int sgc); 920 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, 921 struct scatterlist *sgl, unsigned int sgc); 922 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); 923 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 924 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 925 int ixgbe_fcoe_enable(struct net_device *netdev); 926 int ixgbe_fcoe_disable(struct net_device *netdev); 927 #ifdef CONFIG_IXGBE_DCB 928 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); 929 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); 930 #endif /* CONFIG_IXGBE_DCB */ 931 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); 932 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, 933 struct netdev_fcoe_hbainfo *info); 934 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); 935 #endif /* IXGBE_FCOE */ 936 #ifdef CONFIG_DEBUG_FS 937 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); 938 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); 939 void ixgbe_dbg_init(void); 940 void ixgbe_dbg_exit(void); 941 #else 942 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} 943 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} 944 static inline void ixgbe_dbg_init(void) {} 945 static inline void ixgbe_dbg_exit(void) {} 946 #endif /* CONFIG_DEBUG_FS */ 947 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) 948 { 949 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 950 } 951 952 void ixgbe_ptp_init(struct ixgbe_adapter *adapter); 953 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter); 954 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); 955 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); 956 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); 957 void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter); 958 void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *); 959 void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb); 960 static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring, 961 union ixgbe_adv_rx_desc *rx_desc, 962 struct sk_buff *skb) 963 { 964 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) { 965 ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb); 966 return; 967 } 968 969 if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) 970 return; 971 972 ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 973 974 /* Update the last_rx_timestamp timer in order to enable watchdog check 975 * for error case of latched timestamp on a dropped packet. 976 */ 977 rx_ring->last_rx_timestamp = jiffies; 978 } 979 980 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 981 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 982 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); 983 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); 984 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter); 985 #ifdef CONFIG_PCI_IOV 986 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); 987 #endif 988 989 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 990 struct ixgbe_adapter *adapter, 991 struct ixgbe_ring *tx_ring); 992 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter); 993 void ixgbe_store_key(struct ixgbe_adapter *adapter); 994 void ixgbe_store_reta(struct ixgbe_adapter *adapter); 995 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 996 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm); 997 #ifdef CONFIG_XFRM_OFFLOAD 998 void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter); 999 void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter); 1000 void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter); 1001 void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring, 1002 union ixgbe_adv_rx_desc *rx_desc, 1003 struct sk_buff *skb); 1004 int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 1005 struct ixgbe_ipsec_tx_data *itd); 1006 #else 1007 static inline void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter) { }; 1008 static inline void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter) { }; 1009 static inline void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter) { }; 1010 static inline void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring, 1011 union ixgbe_adv_rx_desc *rx_desc, 1012 struct sk_buff *skb) { }; 1013 static inline int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring, 1014 struct ixgbe_tx_buffer *first, 1015 struct ixgbe_ipsec_tx_data *itd) { return 0; }; 1016 #endif /* CONFIG_XFRM_OFFLOAD */ 1017 #endif /* _IXGBE_H_ */ 1018