1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #ifndef _IXGBE_H_ 5 #define _IXGBE_H_ 6 7 #include <linux/bitops.h> 8 #include <linux/types.h> 9 #include <linux/pci.h> 10 #include <linux/netdevice.h> 11 #include <linux/cpumask.h> 12 #include <linux/aer.h> 13 #include <linux/if_vlan.h> 14 #include <linux/jiffies.h> 15 #include <linux/phy.h> 16 17 #include <linux/timecounter.h> 18 #include <linux/net_tstamp.h> 19 #include <linux/ptp_clock_kernel.h> 20 21 #include "ixgbe_type.h" 22 #include "ixgbe_common.h" 23 #include "ixgbe_dcb.h" 24 #if IS_ENABLED(CONFIG_FCOE) 25 #define IXGBE_FCOE 26 #include "ixgbe_fcoe.h" 27 #endif /* IS_ENABLED(CONFIG_FCOE) */ 28 #ifdef CONFIG_IXGBE_DCA 29 #include <linux/dca.h> 30 #endif 31 #include "ixgbe_ipsec.h" 32 33 #include <net/xdp.h> 34 35 /* common prefix used by pr_<> macros */ 36 #undef pr_fmt 37 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 38 39 /* TX/RX descriptor defines */ 40 #define IXGBE_DEFAULT_TXD 512 41 #define IXGBE_DEFAULT_TX_WORK 256 42 #define IXGBE_MAX_TXD_82598 4096 43 #define IXGBE_MAX_TXD_82599 8192 44 #define IXGBE_MAX_TXD_X540 8192 45 #define IXGBE_MAX_TXD_X550 32768 46 #define IXGBE_MIN_TXD 64 47 48 #if (PAGE_SIZE < 8192) 49 #define IXGBE_DEFAULT_RXD 512 50 #else 51 #define IXGBE_DEFAULT_RXD 128 52 #endif 53 #define IXGBE_MAX_RXD_82598 4096 54 #define IXGBE_MAX_RXD_82599 8192 55 #define IXGBE_MAX_RXD_X540 8192 56 #define IXGBE_MAX_RXD_X550 32768 57 #define IXGBE_MIN_RXD 64 58 59 /* flow control */ 60 #define IXGBE_MIN_FCRTL 0x40 61 #define IXGBE_MAX_FCRTL 0x7FF80 62 #define IXGBE_MIN_FCRTH 0x600 63 #define IXGBE_MAX_FCRTH 0x7FFF0 64 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF 65 #define IXGBE_MIN_FCPAUSE 0 66 #define IXGBE_MAX_FCPAUSE 0xFFFF 67 68 /* Supported Rx Buffer Sizes */ 69 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ 70 #define IXGBE_RXBUFFER_1536 1536 71 #define IXGBE_RXBUFFER_2K 2048 72 #define IXGBE_RXBUFFER_3K 3072 73 #define IXGBE_RXBUFFER_4K 4096 74 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 75 76 /* Attempt to maximize the headroom available for incoming frames. We 77 * use a 2K buffer for receives and need 1536/1534 to store the data for 78 * the frame. This leaves us with 512 bytes of room. From that we need 79 * to deduct the space needed for the shared info and the padding needed 80 * to IP align the frame. 81 * 82 * Note: For cache line sizes 256 or larger this value is going to end 83 * up negative. In these cases we should fall back to the 3K 84 * buffers. 85 */ 86 #if (PAGE_SIZE < 8192) 87 #define IXGBE_MAX_2K_FRAME_BUILD_SKB (IXGBE_RXBUFFER_1536 - NET_IP_ALIGN) 88 #define IXGBE_2K_TOO_SMALL_WITH_PADDING \ 89 ((NET_SKB_PAD + IXGBE_RXBUFFER_1536) > SKB_WITH_OVERHEAD(IXGBE_RXBUFFER_2K)) 90 91 static inline int ixgbe_compute_pad(int rx_buf_len) 92 { 93 int page_size, pad_size; 94 95 page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2); 96 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len; 97 98 return pad_size; 99 } 100 101 static inline int ixgbe_skb_pad(void) 102 { 103 int rx_buf_len; 104 105 /* If a 2K buffer cannot handle a standard Ethernet frame then 106 * optimize padding for a 3K buffer instead of a 1.5K buffer. 107 * 108 * For a 3K buffer we need to add enough padding to allow for 109 * tailroom due to NET_IP_ALIGN possibly shifting us out of 110 * cache-line alignment. 111 */ 112 if (IXGBE_2K_TOO_SMALL_WITH_PADDING) 113 rx_buf_len = IXGBE_RXBUFFER_3K + SKB_DATA_ALIGN(NET_IP_ALIGN); 114 else 115 rx_buf_len = IXGBE_RXBUFFER_1536; 116 117 /* if needed make room for NET_IP_ALIGN */ 118 rx_buf_len -= NET_IP_ALIGN; 119 120 return ixgbe_compute_pad(rx_buf_len); 121 } 122 123 #define IXGBE_SKB_PAD ixgbe_skb_pad() 124 #else 125 #define IXGBE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 126 #endif 127 128 /* 129 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 130 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, 131 * this adds up to 448 bytes of extra data. 132 * 133 * Since netdev_alloc_skb now allocates a page fragment we can use a value 134 * of 256 and the resultant skb will have a truesize of 960 or less. 135 */ 136 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 137 138 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 139 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 140 141 #define IXGBE_RX_DMA_ATTR \ 142 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 143 144 enum ixgbe_tx_flags { 145 /* cmd_type flags */ 146 IXGBE_TX_FLAGS_HW_VLAN = 0x01, 147 IXGBE_TX_FLAGS_TSO = 0x02, 148 IXGBE_TX_FLAGS_TSTAMP = 0x04, 149 150 /* olinfo flags */ 151 IXGBE_TX_FLAGS_CC = 0x08, 152 IXGBE_TX_FLAGS_IPV4 = 0x10, 153 IXGBE_TX_FLAGS_CSUM = 0x20, 154 IXGBE_TX_FLAGS_IPSEC = 0x40, 155 156 /* software defined flags */ 157 IXGBE_TX_FLAGS_SW_VLAN = 0x80, 158 IXGBE_TX_FLAGS_FCOE = 0x100, 159 }; 160 161 /* VLAN info */ 162 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 163 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 164 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 165 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 166 167 #define IXGBE_MAX_VF_MC_ENTRIES 30 168 #define IXGBE_MAX_VF_FUNCTIONS 64 169 #define IXGBE_MAX_VFTA_ENTRIES 128 170 #define MAX_EMULATION_MAC_ADDRS 16 171 #define IXGBE_MAX_PF_MACVLANS 15 172 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) 173 #define IXGBE_82599_VF_DEVICE_ID 0x10ED 174 #define IXGBE_X540_VF_DEVICE_ID 0x1515 175 176 #define UPDATE_VF_COUNTER_32bit(reg, last_counter, counter) \ 177 { \ 178 u32 current_counter = IXGBE_READ_REG(hw, reg); \ 179 if (current_counter < last_counter) \ 180 counter += 0x100000000LL; \ 181 last_counter = current_counter; \ 182 counter &= 0xFFFFFFFF00000000LL; \ 183 counter |= current_counter; \ 184 } 185 186 #define UPDATE_VF_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \ 187 { \ 188 u64 current_counter_lsb = IXGBE_READ_REG(hw, reg_lsb); \ 189 u64 current_counter_msb = IXGBE_READ_REG(hw, reg_msb); \ 190 u64 current_counter = (current_counter_msb << 32) | \ 191 current_counter_lsb; \ 192 if (current_counter < last_counter) \ 193 counter += 0x1000000000LL; \ 194 last_counter = current_counter; \ 195 counter &= 0xFFFFFFF000000000LL; \ 196 counter |= current_counter; \ 197 } 198 199 struct vf_stats { 200 u64 gprc; 201 u64 gorc; 202 u64 gptc; 203 u64 gotc; 204 u64 mprc; 205 }; 206 207 struct vf_data_storage { 208 struct pci_dev *vfdev; 209 unsigned char vf_mac_addresses[ETH_ALEN]; 210 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 211 u16 num_vf_mc_hashes; 212 bool clear_to_send; 213 struct vf_stats vfstats; 214 struct vf_stats last_vfstats; 215 struct vf_stats saved_rst_vfstats; 216 bool pf_set_mac; 217 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 218 u16 pf_qos; 219 u16 tx_rate; 220 int link_enable; 221 int link_state; 222 u8 spoofchk_enabled; 223 bool rss_query_enabled; 224 u8 trusted; 225 int xcast_mode; 226 unsigned int vf_api; 227 u8 primary_abort_count; 228 }; 229 230 enum ixgbevf_xcast_modes { 231 IXGBEVF_XCAST_MODE_NONE = 0, 232 IXGBEVF_XCAST_MODE_MULTI, 233 IXGBEVF_XCAST_MODE_ALLMULTI, 234 IXGBEVF_XCAST_MODE_PROMISC, 235 }; 236 237 struct vf_macvlans { 238 struct list_head l; 239 int vf; 240 bool free; 241 bool is_macvlan; 242 u8 vf_macvlan[ETH_ALEN]; 243 }; 244 245 #define IXGBE_MAX_TXD_PWR 14 246 #define IXGBE_MAX_DATA_PER_TXD (1u << IXGBE_MAX_TXD_PWR) 247 248 /* Tx Descriptors needed, worst case */ 249 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 250 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 251 252 /* wrapper around a pointer to a socket buffer, 253 * so a DMA handle can be stored along with the buffer */ 254 struct ixgbe_tx_buffer { 255 union ixgbe_adv_tx_desc *next_to_watch; 256 unsigned long time_stamp; 257 union { 258 struct sk_buff *skb; 259 struct xdp_frame *xdpf; 260 }; 261 unsigned int bytecount; 262 unsigned short gso_segs; 263 __be16 protocol; 264 DEFINE_DMA_UNMAP_ADDR(dma); 265 DEFINE_DMA_UNMAP_LEN(len); 266 u32 tx_flags; 267 }; 268 269 struct ixgbe_rx_buffer { 270 union { 271 struct { 272 struct sk_buff *skb; 273 dma_addr_t dma; 274 struct page *page; 275 __u32 page_offset; 276 __u16 pagecnt_bias; 277 }; 278 struct { 279 bool discard; 280 struct xdp_buff *xdp; 281 }; 282 }; 283 }; 284 285 struct ixgbe_queue_stats { 286 u64 packets; 287 u64 bytes; 288 }; 289 290 struct ixgbe_tx_queue_stats { 291 u64 restart_queue; 292 u64 tx_busy; 293 u64 tx_done_old; 294 }; 295 296 struct ixgbe_rx_queue_stats { 297 u64 rsc_count; 298 u64 rsc_flush; 299 u64 non_eop_descs; 300 u64 alloc_rx_page; 301 u64 alloc_rx_page_failed; 302 u64 alloc_rx_buff_failed; 303 u64 csum_err; 304 }; 305 306 #define IXGBE_TS_HDR_LEN 8 307 308 enum ixgbe_ring_state_t { 309 __IXGBE_RX_3K_BUFFER, 310 __IXGBE_RX_BUILD_SKB_ENABLED, 311 __IXGBE_RX_RSC_ENABLED, 312 __IXGBE_RX_CSUM_UDP_ZERO_ERR, 313 __IXGBE_RX_FCOE, 314 __IXGBE_TX_FDIR_INIT_DONE, 315 __IXGBE_TX_XPS_INIT_DONE, 316 __IXGBE_TX_DETECT_HANG, 317 __IXGBE_HANG_CHECK_ARMED, 318 __IXGBE_TX_XDP_RING, 319 __IXGBE_TX_DISABLED, 320 }; 321 322 #define ring_uses_build_skb(ring) \ 323 test_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &(ring)->state) 324 325 struct ixgbe_fwd_adapter { 326 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 327 struct net_device *netdev; 328 unsigned int tx_base_queue; 329 unsigned int rx_base_queue; 330 int pool; 331 }; 332 333 #define check_for_tx_hang(ring) \ 334 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 335 #define set_check_for_tx_hang(ring) \ 336 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 337 #define clear_check_for_tx_hang(ring) \ 338 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 339 #define ring_is_rsc_enabled(ring) \ 340 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 341 #define set_ring_rsc_enabled(ring) \ 342 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 343 #define clear_ring_rsc_enabled(ring) \ 344 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 345 #define ring_is_xdp(ring) \ 346 test_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 347 #define set_ring_xdp(ring) \ 348 set_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 349 #define clear_ring_xdp(ring) \ 350 clear_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 351 struct ixgbe_ring { 352 struct ixgbe_ring *next; /* pointer to next ring in q_vector */ 353 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ 354 struct net_device *netdev; /* netdev ring belongs to */ 355 struct bpf_prog *xdp_prog; 356 struct device *dev; /* device for DMA mapping */ 357 void *desc; /* descriptor ring memory */ 358 union { 359 struct ixgbe_tx_buffer *tx_buffer_info; 360 struct ixgbe_rx_buffer *rx_buffer_info; 361 }; 362 unsigned long state; 363 u8 __iomem *tail; 364 dma_addr_t dma; /* phys. address of descriptor ring */ 365 unsigned int size; /* length in bytes */ 366 367 u16 count; /* amount of descriptors */ 368 369 u8 queue_index; /* needed for multiqueue queue management */ 370 u8 reg_idx; /* holds the special value that gets 371 * the hardware register offset 372 * associated with this ring, which is 373 * different for DCB and RSS modes 374 */ 375 u16 next_to_use; 376 u16 next_to_clean; 377 378 unsigned long last_rx_timestamp; 379 380 union { 381 u16 next_to_alloc; 382 struct { 383 u8 atr_sample_rate; 384 u8 atr_count; 385 }; 386 }; 387 388 u8 dcb_tc; 389 struct ixgbe_queue_stats stats; 390 struct u64_stats_sync syncp; 391 union { 392 struct ixgbe_tx_queue_stats tx_stats; 393 struct ixgbe_rx_queue_stats rx_stats; 394 }; 395 u16 rx_offset; 396 struct xdp_rxq_info xdp_rxq; 397 spinlock_t tx_lock; /* used in XDP mode */ 398 struct xsk_buff_pool *xsk_pool; 399 u16 ring_idx; /* {rx,tx,xdp}_ring back reference idx */ 400 u16 rx_buf_len; 401 } ____cacheline_internodealigned_in_smp; 402 403 enum ixgbe_ring_f_enum { 404 RING_F_NONE = 0, 405 RING_F_VMDQ, /* SR-IOV uses the same ring feature */ 406 RING_F_RSS, 407 RING_F_FDIR, 408 #ifdef IXGBE_FCOE 409 RING_F_FCOE, 410 #endif /* IXGBE_FCOE */ 411 412 RING_F_ARRAY_SIZE /* must be last in enum set */ 413 }; 414 415 #define IXGBE_MAX_RSS_INDICES 16 416 #define IXGBE_MAX_RSS_INDICES_X550 63 417 #define IXGBE_MAX_VMDQ_INDICES 64 418 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ 419 #define IXGBE_MAX_FCOE_INDICES 8 420 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 421 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 422 #define IXGBE_MAX_XDP_QS (IXGBE_MAX_FDIR_INDICES + 1) 423 #define IXGBE_MAX_L2A_QUEUES 4 424 #define IXGBE_BAD_L2A_QUEUE 3 425 #define IXGBE_MAX_MACVLANS 63 426 427 DECLARE_STATIC_KEY_FALSE(ixgbe_xdp_locking_key); 428 429 struct ixgbe_ring_feature { 430 u16 limit; /* upper limit on feature indices */ 431 u16 indices; /* current value of indices */ 432 u16 mask; /* Mask used for feature to ring mapping */ 433 u16 offset; /* offset to start of feature */ 434 } ____cacheline_internodealigned_in_smp; 435 436 #define IXGBE_82599_VMDQ_8Q_MASK 0x78 437 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C 438 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E 439 440 /* 441 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since 442 * this is twice the size of a half page we need to double the page order 443 * for FCoE enabled Rx queues. 444 */ 445 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) 446 { 447 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 448 return IXGBE_RXBUFFER_3K; 449 #if (PAGE_SIZE < 8192) 450 if (ring_uses_build_skb(ring)) 451 return IXGBE_MAX_2K_FRAME_BUILD_SKB; 452 #endif 453 return IXGBE_RXBUFFER_2K; 454 } 455 456 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) 457 { 458 #if (PAGE_SIZE < 8192) 459 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 460 return 1; 461 #endif 462 return 0; 463 } 464 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) 465 466 #define IXGBE_ITR_ADAPTIVE_MIN_INC 2 467 #define IXGBE_ITR_ADAPTIVE_MIN_USECS 10 468 #define IXGBE_ITR_ADAPTIVE_MAX_USECS 126 469 #define IXGBE_ITR_ADAPTIVE_LATENCY 0x80 470 #define IXGBE_ITR_ADAPTIVE_BULK 0x00 471 472 struct ixgbe_ring_container { 473 struct ixgbe_ring *ring; /* pointer to linked list of rings */ 474 unsigned long next_update; /* jiffies value of last update */ 475 unsigned int total_bytes; /* total bytes processed this int */ 476 unsigned int total_packets; /* total packets processed this int */ 477 u16 work_limit; /* total work allowed per interrupt */ 478 u8 count; /* total number of rings in vector */ 479 u8 itr; /* current ITR setting for ring */ 480 }; 481 482 /* iterator for handling rings in ring container */ 483 #define ixgbe_for_each_ring(pos, head) \ 484 for (pos = (head).ring; pos != NULL; pos = pos->next) 485 486 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ 487 ? 8 : 1) 488 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS 489 490 /* MAX_Q_VECTORS of these are allocated, 491 * but we only use one per queue-specific vector. 492 */ 493 struct ixgbe_q_vector { 494 struct ixgbe_adapter *adapter; 495 #ifdef CONFIG_IXGBE_DCA 496 int cpu; /* CPU for DCA */ 497 #endif 498 u16 v_idx; /* index of q_vector within array, also used for 499 * finding the bit in EICR and friends that 500 * represents the vector for this ring */ 501 u16 itr; /* Interrupt throttle rate written to EITR */ 502 struct ixgbe_ring_container rx, tx; 503 504 struct napi_struct napi; 505 cpumask_t affinity_mask; 506 int numa_node; 507 struct rcu_head rcu; /* to avoid race with update stats on free */ 508 char name[IFNAMSIZ + 9]; 509 510 /* for dynamic allocation of rings associated with this q_vector */ 511 struct ixgbe_ring ring[] ____cacheline_internodealigned_in_smp; 512 }; 513 514 #ifdef CONFIG_IXGBE_HWMON 515 516 #define IXGBE_HWMON_TYPE_LOC 0 517 #define IXGBE_HWMON_TYPE_TEMP 1 518 #define IXGBE_HWMON_TYPE_CAUTION 2 519 #define IXGBE_HWMON_TYPE_MAX 3 520 521 struct hwmon_attr { 522 struct device_attribute dev_attr; 523 struct ixgbe_hw *hw; 524 struct ixgbe_thermal_diode_data *sensor; 525 char name[12]; 526 }; 527 528 struct hwmon_buff { 529 struct attribute_group group; 530 const struct attribute_group *groups[2]; 531 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; 532 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; 533 unsigned int n_hwmon; 534 }; 535 #endif /* CONFIG_IXGBE_HWMON */ 536 537 /* 538 * microsecond values for various ITR rates shifted by 2 to fit itr register 539 * with the first 3 bits reserved 0 540 */ 541 #define IXGBE_MIN_RSC_ITR 24 542 #define IXGBE_100K_ITR 40 543 #define IXGBE_20K_ITR 200 544 #define IXGBE_12K_ITR 336 545 546 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ 547 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, 548 const u32 stat_err_bits) 549 { 550 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 551 } 552 553 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) 554 { 555 u16 ntc = ring->next_to_clean; 556 u16 ntu = ring->next_to_use; 557 558 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 559 } 560 561 #define IXGBE_RX_DESC(R, i) \ 562 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 563 #define IXGBE_TX_DESC(R, i) \ 564 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 565 #define IXGBE_TX_CTXTDESC(R, i) \ 566 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 567 568 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ 569 #ifdef IXGBE_FCOE 570 /* Use 3K as the baby jumbo frame size for FCoE */ 571 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 572 #endif /* IXGBE_FCOE */ 573 574 #define OTHER_VECTOR 1 575 #define NON_Q_VECTORS (OTHER_VECTOR) 576 577 #define MAX_MSIX_VECTORS_82599 64 578 #define MAX_Q_VECTORS_82599 64 579 #define MAX_MSIX_VECTORS_82598 18 580 #define MAX_Q_VECTORS_82598 16 581 582 struct ixgbe_mac_addr { 583 u8 addr[ETH_ALEN]; 584 u16 pool; 585 u16 state; /* bitmask */ 586 }; 587 588 #define IXGBE_MAC_STATE_DEFAULT 0x1 589 #define IXGBE_MAC_STATE_MODIFIED 0x2 590 #define IXGBE_MAC_STATE_IN_USE 0x4 591 592 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 593 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 594 595 #define MIN_MSIX_Q_VECTORS 1 596 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 597 598 /* default to trying for four seconds */ 599 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 600 #define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */ 601 602 #define IXGBE_PRIMARY_ABORT_LIMIT 5 603 604 /* board specific private data structure */ 605 struct ixgbe_adapter { 606 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 607 /* OS defined structs */ 608 struct net_device *netdev; 609 struct bpf_prog *xdp_prog; 610 struct pci_dev *pdev; 611 struct mii_bus *mii_bus; 612 613 unsigned long state; 614 615 /* Some features need tri-state capability, 616 * thus the additional *_CAPABLE flags. 617 */ 618 u32 flags; 619 #define IXGBE_FLAG_MSI_ENABLED BIT(1) 620 #define IXGBE_FLAG_MSIX_ENABLED BIT(3) 621 #define IXGBE_FLAG_RX_1BUF_CAPABLE BIT(4) 622 #define IXGBE_FLAG_RX_PS_CAPABLE BIT(5) 623 #define IXGBE_FLAG_RX_PS_ENABLED BIT(6) 624 #define IXGBE_FLAG_DCA_ENABLED BIT(8) 625 #define IXGBE_FLAG_DCA_CAPABLE BIT(9) 626 #define IXGBE_FLAG_IMIR_ENABLED BIT(10) 627 #define IXGBE_FLAG_MQ_CAPABLE BIT(11) 628 #define IXGBE_FLAG_DCB_ENABLED BIT(12) 629 #define IXGBE_FLAG_VMDQ_CAPABLE BIT(13) 630 #define IXGBE_FLAG_VMDQ_ENABLED BIT(14) 631 #define IXGBE_FLAG_FAN_FAIL_CAPABLE BIT(15) 632 #define IXGBE_FLAG_NEED_LINK_UPDATE BIT(16) 633 #define IXGBE_FLAG_NEED_LINK_CONFIG BIT(17) 634 #define IXGBE_FLAG_FDIR_HASH_CAPABLE BIT(18) 635 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE BIT(19) 636 #define IXGBE_FLAG_FCOE_CAPABLE BIT(20) 637 #define IXGBE_FLAG_FCOE_ENABLED BIT(21) 638 #define IXGBE_FLAG_SRIOV_CAPABLE BIT(22) 639 #define IXGBE_FLAG_SRIOV_ENABLED BIT(23) 640 #define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25) 641 #define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26) 642 #define IXGBE_FLAG_DCB_CAPABLE BIT(27) 643 644 u32 flags2; 645 #define IXGBE_FLAG2_RSC_CAPABLE BIT(0) 646 #define IXGBE_FLAG2_RSC_ENABLED BIT(1) 647 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE BIT(2) 648 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT BIT(3) 649 #define IXGBE_FLAG2_SEARCH_FOR_SFP BIT(4) 650 #define IXGBE_FLAG2_SFP_NEEDS_RESET BIT(5) 651 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT BIT(7) 652 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP BIT(8) 653 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP BIT(9) 654 #define IXGBE_FLAG2_PTP_PPS_ENABLED BIT(10) 655 #define IXGBE_FLAG2_PHY_INTERRUPT BIT(11) 656 #define IXGBE_FLAG2_VLAN_PROMISC BIT(13) 657 #define IXGBE_FLAG2_EEE_CAPABLE BIT(14) 658 #define IXGBE_FLAG2_EEE_ENABLED BIT(15) 659 #define IXGBE_FLAG2_RX_LEGACY BIT(16) 660 #define IXGBE_FLAG2_IPSEC_ENABLED BIT(17) 661 #define IXGBE_FLAG2_VF_IPSEC_ENABLED BIT(18) 662 #define IXGBE_FLAG2_AUTO_DISABLE_VF BIT(19) 663 664 /* Tx fast path data */ 665 int num_tx_queues; 666 u16 tx_itr_setting; 667 u16 tx_work_limit; 668 u64 tx_ipsec; 669 670 /* Rx fast path data */ 671 int num_rx_queues; 672 u16 rx_itr_setting; 673 u64 rx_ipsec; 674 675 /* Port number used to identify VXLAN traffic */ 676 __be16 vxlan_port; 677 __be16 geneve_port; 678 679 /* XDP */ 680 int num_xdp_queues; 681 struct ixgbe_ring *xdp_ring[IXGBE_MAX_XDP_QS]; 682 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled rings */ 683 684 /* TX */ 685 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; 686 687 u64 restart_queue; 688 u64 lsc_int; 689 u32 tx_timeout_count; 690 691 /* RX */ 692 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; 693 int num_rx_pools; /* == num_rx_queues in 82598 */ 694 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ 695 u64 hw_csum_rx_error; 696 u64 hw_rx_no_dma_resources; 697 u64 rsc_total_count; 698 u64 rsc_total_flush; 699 u64 non_eop_descs; 700 u32 alloc_rx_page; 701 u32 alloc_rx_page_failed; 702 u32 alloc_rx_buff_failed; 703 704 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; 705 706 /* DCB parameters */ 707 struct ieee_pfc *ixgbe_ieee_pfc; 708 struct ieee_ets *ixgbe_ieee_ets; 709 struct ixgbe_dcb_config dcb_cfg; 710 struct ixgbe_dcb_config temp_dcb_cfg; 711 u8 hw_tcs; 712 u8 dcb_set_bitmap; 713 u8 dcbx_cap; 714 enum ixgbe_fc_mode last_lfc_mode; 715 716 int num_q_vectors; /* current number of q_vectors for device */ 717 int max_q_vectors; /* true count of q_vectors for device */ 718 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; 719 struct msix_entry *msix_entries; 720 721 u32 test_icr; 722 struct ixgbe_ring test_tx_ring; 723 struct ixgbe_ring test_rx_ring; 724 725 /* structs defined in ixgbe_hw.h */ 726 struct ixgbe_hw hw; 727 u16 msg_enable; 728 struct ixgbe_hw_stats stats; 729 730 u64 tx_busy; 731 unsigned int tx_ring_count; 732 unsigned int xdp_ring_count; 733 unsigned int rx_ring_count; 734 735 u32 link_speed; 736 bool link_up; 737 unsigned long sfp_poll_time; 738 unsigned long link_check_timeout; 739 740 struct timer_list service_timer; 741 struct work_struct service_task; 742 743 struct hlist_head fdir_filter_list; 744 unsigned long fdir_overflow; /* number of times ATR was backed off */ 745 union ixgbe_atr_input fdir_mask; 746 int fdir_filter_count; 747 u32 fdir_pballoc; 748 u32 atr_sample_rate; 749 spinlock_t fdir_perfect_lock; 750 751 #ifdef IXGBE_FCOE 752 struct ixgbe_fcoe fcoe; 753 #endif /* IXGBE_FCOE */ 754 u8 __iomem *io_addr; /* Mainly for iounmap use */ 755 u32 wol; 756 757 u16 bridge_mode; 758 759 char eeprom_id[NVM_VER_SIZE]; 760 u16 eeprom_cap; 761 762 u32 interrupt_event; 763 u32 led_reg; 764 765 struct ptp_clock *ptp_clock; 766 struct ptp_clock_info ptp_caps; 767 struct work_struct ptp_tx_work; 768 struct sk_buff *ptp_tx_skb; 769 struct hwtstamp_config tstamp_config; 770 unsigned long ptp_tx_start; 771 unsigned long last_overflow_check; 772 unsigned long last_rx_ptp_check; 773 unsigned long last_rx_timestamp; 774 spinlock_t tmreg_lock; 775 struct cyclecounter hw_cc; 776 struct timecounter hw_tc; 777 u32 base_incval; 778 u32 tx_hwtstamp_timeouts; 779 u32 tx_hwtstamp_skipped; 780 u32 rx_hwtstamp_cleared; 781 void (*ptp_setup_sdp)(struct ixgbe_adapter *); 782 783 /* SR-IOV */ 784 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 785 unsigned int num_vfs; 786 struct vf_data_storage *vfinfo; 787 int vf_rate_link_speed; 788 struct vf_macvlans vf_mvs; 789 struct vf_macvlans *mv_list; 790 791 u32 timer_event_accumulator; 792 u32 vferr_refcount; 793 struct ixgbe_mac_addr *mac_table; 794 struct kobject *info_kobj; 795 #ifdef CONFIG_IXGBE_HWMON 796 struct hwmon_buff *ixgbe_hwmon_buff; 797 #endif /* CONFIG_IXGBE_HWMON */ 798 #ifdef CONFIG_DEBUG_FS 799 struct dentry *ixgbe_dbg_adapter; 800 #endif /*CONFIG_DEBUG_FS*/ 801 802 u8 default_up; 803 /* Bitmask indicating in use pools */ 804 DECLARE_BITMAP(fwd_bitmask, IXGBE_MAX_MACVLANS + 1); 805 806 #define IXGBE_MAX_LINK_HANDLE 10 807 struct ixgbe_jump_table *jump_tables[IXGBE_MAX_LINK_HANDLE]; 808 unsigned long tables; 809 810 /* maximum number of RETA entries among all devices supported by ixgbe 811 * driver: currently it's x550 device in non-SRIOV mode 812 */ 813 #define IXGBE_MAX_RETA_ENTRIES 512 814 u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES]; 815 816 #define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */ 817 u32 *rss_key; 818 819 #ifdef CONFIG_IXGBE_IPSEC 820 struct ixgbe_ipsec *ipsec; 821 #endif /* CONFIG_IXGBE_IPSEC */ 822 spinlock_t vfs_lock; 823 }; 824 825 static inline int ixgbe_determine_xdp_q_idx(int cpu) 826 { 827 if (static_key_enabled(&ixgbe_xdp_locking_key)) 828 return cpu % IXGBE_MAX_XDP_QS; 829 else 830 return cpu; 831 } 832 833 static inline 834 struct ixgbe_ring *ixgbe_determine_xdp_ring(struct ixgbe_adapter *adapter) 835 { 836 int index = ixgbe_determine_xdp_q_idx(smp_processor_id()); 837 838 return adapter->xdp_ring[index]; 839 } 840 841 static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter) 842 { 843 switch (adapter->hw.mac.type) { 844 case ixgbe_mac_82598EB: 845 case ixgbe_mac_82599EB: 846 case ixgbe_mac_X540: 847 return IXGBE_MAX_RSS_INDICES; 848 case ixgbe_mac_X550: 849 case ixgbe_mac_X550EM_x: 850 case ixgbe_mac_x550em_a: 851 return IXGBE_MAX_RSS_INDICES_X550; 852 default: 853 return 0; 854 } 855 } 856 857 struct ixgbe_fdir_filter { 858 struct hlist_node fdir_node; 859 union ixgbe_atr_input filter; 860 u16 sw_idx; 861 u64 action; 862 }; 863 864 enum ixgbe_state_t { 865 __IXGBE_TESTING, 866 __IXGBE_RESETTING, 867 __IXGBE_DOWN, 868 __IXGBE_DISABLED, 869 __IXGBE_REMOVING, 870 __IXGBE_SERVICE_SCHED, 871 __IXGBE_SERVICE_INITED, 872 __IXGBE_IN_SFP_INIT, 873 __IXGBE_PTP_RUNNING, 874 __IXGBE_PTP_TX_IN_PROGRESS, 875 __IXGBE_RESET_REQUESTED, 876 }; 877 878 struct ixgbe_cb { 879 union { /* Union defining head/tail partner */ 880 struct sk_buff *head; 881 struct sk_buff *tail; 882 }; 883 dma_addr_t dma; 884 u16 append_cnt; 885 bool page_released; 886 }; 887 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) 888 889 enum ixgbe_boards { 890 board_82598, 891 board_82599, 892 board_X540, 893 board_X550, 894 board_X550EM_x, 895 board_x550em_x_fw, 896 board_x550em_a, 897 board_x550em_a_fw, 898 }; 899 900 extern const struct ixgbe_info ixgbe_82598_info; 901 extern const struct ixgbe_info ixgbe_82599_info; 902 extern const struct ixgbe_info ixgbe_X540_info; 903 extern const struct ixgbe_info ixgbe_X550_info; 904 extern const struct ixgbe_info ixgbe_X550EM_x_info; 905 extern const struct ixgbe_info ixgbe_x550em_x_fw_info; 906 extern const struct ixgbe_info ixgbe_x550em_a_info; 907 extern const struct ixgbe_info ixgbe_x550em_a_fw_info; 908 #ifdef CONFIG_IXGBE_DCB 909 extern const struct dcbnl_rtnl_ops ixgbe_dcbnl_ops; 910 #endif 911 912 extern char ixgbe_driver_name[]; 913 #ifdef IXGBE_FCOE 914 extern char ixgbe_default_device_descr[]; 915 #endif /* IXGBE_FCOE */ 916 917 int ixgbe_open(struct net_device *netdev); 918 int ixgbe_close(struct net_device *netdev); 919 void ixgbe_up(struct ixgbe_adapter *adapter); 920 void ixgbe_down(struct ixgbe_adapter *adapter); 921 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); 922 void ixgbe_reset(struct ixgbe_adapter *adapter); 923 void ixgbe_set_ethtool_ops(struct net_device *netdev); 924 int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); 925 int ixgbe_setup_tx_resources(struct ixgbe_ring *); 926 void ixgbe_free_rx_resources(struct ixgbe_ring *); 927 void ixgbe_free_tx_resources(struct ixgbe_ring *); 928 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 929 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 930 void ixgbe_disable_rx(struct ixgbe_adapter *adapter); 931 void ixgbe_disable_tx(struct ixgbe_adapter *adapter); 932 void ixgbe_update_stats(struct ixgbe_adapter *adapter); 933 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); 934 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 935 u16 subdevice_id); 936 #ifdef CONFIG_PCI_IOV 937 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter); 938 #endif 939 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 940 const u8 *addr, u16 queue); 941 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 942 const u8 *addr, u16 queue); 943 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid); 944 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); 945 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, 946 struct ixgbe_ring *); 947 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, 948 struct ixgbe_tx_buffer *); 949 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); 950 void ixgbe_write_eitr(struct ixgbe_q_vector *); 951 int ixgbe_poll(struct napi_struct *napi, int budget); 952 int ethtool_ioctl(struct ifreq *ifr); 953 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 954 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); 955 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); 956 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 957 union ixgbe_atr_hash_dword input, 958 union ixgbe_atr_hash_dword common, 959 u8 queue); 960 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 961 union ixgbe_atr_input *input_mask); 962 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 963 union ixgbe_atr_input *input, 964 u16 soft_id, u8 queue); 965 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 966 union ixgbe_atr_input *input, 967 u16 soft_id); 968 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 969 union ixgbe_atr_input *mask); 970 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 971 struct ixgbe_fdir_filter *input, 972 u16 sw_idx); 973 void ixgbe_set_rx_mode(struct net_device *netdev); 974 #ifdef CONFIG_IXGBE_DCB 975 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); 976 #endif 977 int ixgbe_setup_tc(struct net_device *dev, u8 tc); 978 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); 979 void ixgbe_do_reset(struct net_device *netdev); 980 #ifdef CONFIG_IXGBE_HWMON 981 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); 982 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); 983 #endif /* CONFIG_IXGBE_HWMON */ 984 #ifdef IXGBE_FCOE 985 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 986 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 987 u8 *hdr_len); 988 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, 989 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); 990 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, 991 struct scatterlist *sgl, unsigned int sgc); 992 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, 993 struct scatterlist *sgl, unsigned int sgc); 994 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); 995 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 996 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 997 int ixgbe_fcoe_enable(struct net_device *netdev); 998 int ixgbe_fcoe_disable(struct net_device *netdev); 999 #ifdef CONFIG_IXGBE_DCB 1000 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); 1001 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); 1002 #endif /* CONFIG_IXGBE_DCB */ 1003 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); 1004 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, 1005 struct netdev_fcoe_hbainfo *info); 1006 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); 1007 #endif /* IXGBE_FCOE */ 1008 #ifdef CONFIG_DEBUG_FS 1009 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); 1010 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); 1011 void ixgbe_dbg_init(void); 1012 void ixgbe_dbg_exit(void); 1013 #else 1014 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} 1015 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} 1016 static inline void ixgbe_dbg_init(void) {} 1017 static inline void ixgbe_dbg_exit(void) {} 1018 #endif /* CONFIG_DEBUG_FS */ 1019 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) 1020 { 1021 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 1022 } 1023 1024 void ixgbe_ptp_init(struct ixgbe_adapter *adapter); 1025 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter); 1026 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); 1027 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); 1028 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); 1029 void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter); 1030 void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *); 1031 void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb); 1032 static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring, 1033 union ixgbe_adv_rx_desc *rx_desc, 1034 struct sk_buff *skb) 1035 { 1036 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) { 1037 ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb); 1038 return; 1039 } 1040 1041 if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) 1042 return; 1043 1044 ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 1045 1046 /* Update the last_rx_timestamp timer in order to enable watchdog check 1047 * for error case of latched timestamp on a dropped packet. 1048 */ 1049 rx_ring->last_rx_timestamp = jiffies; 1050 } 1051 1052 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 1053 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 1054 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); 1055 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); 1056 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter); 1057 #ifdef CONFIG_PCI_IOV 1058 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); 1059 #endif 1060 1061 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 1062 struct ixgbe_adapter *adapter, 1063 struct ixgbe_ring *tx_ring); 1064 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter); 1065 void ixgbe_store_key(struct ixgbe_adapter *adapter); 1066 void ixgbe_store_reta(struct ixgbe_adapter *adapter); 1067 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 1068 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm); 1069 #ifdef CONFIG_IXGBE_IPSEC 1070 void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter); 1071 void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter); 1072 void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter); 1073 void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring, 1074 union ixgbe_adv_rx_desc *rx_desc, 1075 struct sk_buff *skb); 1076 int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 1077 struct ixgbe_ipsec_tx_data *itd); 1078 void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter, u32 vf); 1079 int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf); 1080 int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf); 1081 #else 1082 static inline void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter) { } 1083 static inline void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter) { } 1084 static inline void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter) { } 1085 static inline void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring, 1086 union ixgbe_adv_rx_desc *rx_desc, 1087 struct sk_buff *skb) { } 1088 static inline int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring, 1089 struct ixgbe_tx_buffer *first, 1090 struct ixgbe_ipsec_tx_data *itd) { return 0; } 1091 static inline void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter, 1092 u32 vf) { } 1093 static inline int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter, 1094 u32 *mbuf, u32 vf) { return -EACCES; } 1095 static inline int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter, 1096 u32 *mbuf, u32 vf) { return -EACCES; } 1097 #endif /* CONFIG_IXGBE_IPSEC */ 1098 1099 static inline bool ixgbe_enabled_xdp_adapter(struct ixgbe_adapter *adapter) 1100 { 1101 return !!adapter->xdp_prog; 1102 } 1103 1104 #endif /* _IXGBE_H_ */ 1105