1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c)  2018 Intel Corporation */
3 
4 #ifndef _IGC_REGS_H_
5 #define _IGC_REGS_H_
6 
7 /* General Register Descriptions */
8 #define IGC_CTRL		0x00000  /* Device Control - RW */
9 #define IGC_STATUS		0x00008  /* Device Status - RO */
10 #define IGC_EECD		0x00010  /* EEPROM/Flash Control - RW */
11 #define IGC_CTRL_EXT		0x00018  /* Extended Device Control - RW */
12 #define IGC_MDIC		0x00020  /* MDI Control - RW */
13 #define IGC_MDICNFG		0x00E04  /* MDC/MDIO Configuration - RW */
14 #define IGC_CONNSW		0x00034  /* Copper/Fiber switch control - RW */
15 
16 /* Internal Packet Buffer Size Registers */
17 #define IGC_RXPBS		0x02404  /* Rx Packet Buffer Size - RW */
18 #define IGC_TXPBS		0x03404  /* Tx Packet Buffer Size - RW */
19 
20 /* NVM  Register Descriptions */
21 #define IGC_EERD		0x12014  /* EEprom mode read - RW */
22 #define IGC_EEWR		0x12018  /* EEprom mode write - RW */
23 
24 /* Flow Control Register Descriptions */
25 #define IGC_FCAL		0x00028  /* FC Address Low - RW */
26 #define IGC_FCAH		0x0002C  /* FC Address High - RW */
27 #define IGC_FCT			0x00030  /* FC Type - RW */
28 #define IGC_FCTTV		0x00170  /* FC Transmit Timer - RW */
29 #define IGC_FCRTL		0x02160  /* FC Receive Threshold Low - RW */
30 #define IGC_FCRTH		0x02168  /* FC Receive Threshold High - RW */
31 #define IGC_FCRTV		0x02460  /* FC Refresh Timer Value - RW */
32 #define IGC_FCSTS		0x02464  /* FC Status - RO */
33 
34 /* PCIe Register Description */
35 #define IGC_GCR			0x05B00  /* PCIe control- RW */
36 
37 /* Semaphore registers */
38 #define IGC_SW_FW_SYNC		0x05B5C  /* SW-FW Synchronization - RW */
39 #define IGC_SWSM		0x05B50  /* SW Semaphore */
40 #define IGC_FWSM		0x05B54  /* FW Semaphore */
41 
42 /* Function Active and Power State to MNG */
43 #define IGC_FACTPS		0x05B30
44 
45 /* Interrupt Register Description */
46 #define IGC_EICS		0x01520  /* Ext. Interrupt Cause Set - W0 */
47 #define IGC_EIMS		0x01524  /* Ext. Interrupt Mask Set/Read - RW */
48 #define IGC_EIMC		0x01528  /* Ext. Interrupt Mask Clear - WO */
49 #define IGC_EIAC		0x0152C  /* Ext. Interrupt Auto Clear - RW */
50 #define IGC_EIAM		0x01530  /* Ext. Interrupt Auto Mask - RW */
51 #define IGC_ICR			0x01500  /* Intr Cause Read - RC/W1C */
52 #define IGC_ICS			0x01504  /* Intr Cause Set - WO */
53 #define IGC_IMS			0x01508  /* Intr Mask Set/Read - RW */
54 #define IGC_IMC			0x0150C  /* Intr Mask Clear - WO */
55 #define IGC_IAM			0x01510  /* Intr Ack Auto Mask- RW */
56 /* Intr Throttle - RW */
57 #define IGC_EITR(_n)		(0x01680 + (0x4 * (_n)))
58 /* Interrupt Vector Allocation - RW */
59 #define IGC_IVAR0		0x01700
60 #define IGC_IVAR_MISC		0x01740  /* IVAR for "other" causes - RW */
61 #define IGC_GPIE		0x01514  /* General Purpose Intr Enable - RW */
62 
63 /* Interrupt Cause */
64 #define IGC_ICRXPTC		0x04104  /* Rx Packet Timer Expire Count */
65 #define IGC_ICRXATC		0x04108  /* Rx Absolute Timer Expire Count */
66 #define IGC_ICTXPTC		0x0410C  /* Tx Packet Timer Expire Count */
67 #define IGC_ICTXATC		0x04110  /* Tx Absolute Timer Expire Count */
68 #define IGC_ICTXQEC		0x04118  /* Tx Queue Empty Count */
69 #define IGC_ICTXQMTC		0x0411C  /* Tx Queue Min Threshold Count */
70 #define IGC_ICRXDMTC		0x04120  /* Rx Descriptor Min Threshold Count */
71 #define IGC_ICRXOC		0x04124  /* Receiver Overrun Count */
72 
73 #define IGC_CBTMPC		0x0402C  /* Circuit Breaker TX Packet Count */
74 #define IGC_HTDPMC		0x0403C  /* Host Transmit Discarded Packets */
75 #define IGC_CBRMPC		0x040FC  /* Circuit Breaker RX Packet Count */
76 #define IGC_RPTHC		0x04104  /* Rx Packets To Host */
77 #define IGC_HGPTC		0x04118  /* Host Good Packets TX Count */
78 #define IGC_HTCBDPC		0x04124  /* Host TX Circ.Breaker Drop Count */
79 
80 /* MSI-X Table Register Descriptions */
81 #define IGC_PBACL		0x05B68  /* MSIx PBA Clear - R/W 1 to clear */
82 
83 /* RSS registers */
84 #define IGC_MRQC		0x05818 /* Multiple Receive Control - RW */
85 
86 /* Filtering Registers */
87 #define IGC_ETQF(_n)		(0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
88 
89 /* ETQF register bit definitions */
90 #define IGC_ETQF_FILTER_ENABLE	BIT(26)
91 #define IGC_ETQF_QUEUE_ENABLE	BIT(31)
92 #define IGC_ETQF_QUEUE_SHIFT	16
93 #define IGC_ETQF_QUEUE_MASK	0x00070000
94 #define IGC_ETQF_ETYPE_MASK	0x0000FFFF
95 
96 /* Redirection Table - RW Array */
97 #define IGC_RETA(_i)		(0x05C00 + ((_i) * 4))
98 /* RSS Random Key - RW Array */
99 #define IGC_RSSRK(_i)		(0x05C80 + ((_i) * 4))
100 
101 /* Receive Register Descriptions */
102 #define IGC_RCTL		0x00100  /* Rx Control - RW */
103 #define IGC_SRRCTL(_n)		(0x0C00C + ((_n) * 0x40))
104 #define IGC_PSRTYPE(_i)		(0x05480 + ((_i) * 4))
105 #define IGC_RDBAL(_n)		(0x0C000 + ((_n) * 0x40))
106 #define IGC_RDBAH(_n)		(0x0C004 + ((_n) * 0x40))
107 #define IGC_RDLEN(_n)		(0x0C008 + ((_n) * 0x40))
108 #define IGC_RDH(_n)		(0x0C010 + ((_n) * 0x40))
109 #define IGC_RDT(_n)		(0x0C018 + ((_n) * 0x40))
110 #define IGC_RXDCTL(_n)		(0x0C028 + ((_n) * 0x40))
111 #define IGC_RQDPC(_n)		(0x0C030 + ((_n) * 0x40))
112 #define IGC_RXCSUM		0x05000  /* Rx Checksum Control - RW */
113 #define IGC_RLPML		0x05004  /* Rx Long Packet Max Length */
114 #define IGC_RFCTL		0x05008  /* Receive Filter Control*/
115 #define IGC_MTA			0x05200  /* Multicast Table Array - RW Array */
116 #define IGC_UTA			0x0A000  /* Unicast Table Array - RW */
117 #define IGC_RAL(_n)		(0x05400 + ((_n) * 0x08))
118 #define IGC_RAH(_n)		(0x05404 + ((_n) * 0x08))
119 #define IGC_VLAPQF		0x055B0  /* VLAN Priority Queue Filter VLAPQF */
120 
121 /* Transmit Register Descriptions */
122 #define IGC_TCTL		0x00400  /* Tx Control - RW */
123 #define IGC_TIPG		0x00410  /* Tx Inter-packet gap - RW */
124 #define IGC_TDBAL(_n)		(0x0E000 + ((_n) * 0x40))
125 #define IGC_TDBAH(_n)		(0x0E004 + ((_n) * 0x40))
126 #define IGC_TDLEN(_n)		(0x0E008 + ((_n) * 0x40))
127 #define IGC_TDH(_n)		(0x0E010 + ((_n) * 0x40))
128 #define IGC_TDT(_n)		(0x0E018 + ((_n) * 0x40))
129 #define IGC_TXDCTL(_n)		(0x0E028 + ((_n) * 0x40))
130 
131 /* MMD Register Descriptions */
132 #define IGC_MMDAC		13 /* MMD Access Control */
133 #define IGC_MMDAAD		14 /* MMD Access Address/Data */
134 
135 /* Good transmitted packets counter registers */
136 #define IGC_PQGPTC(_n)		(0x010014 + (0x100 * (_n)))
137 
138 /* Statistics Register Descriptions */
139 #define IGC_CRCERRS	0x04000  /* CRC Error Count - R/clr */
140 #define IGC_ALGNERRC	0x04004  /* Alignment Error Count - R/clr */
141 #define IGC_SYMERRS	0x04008  /* Symbol Error Count - R/clr */
142 #define IGC_RXERRC	0x0400C  /* Receive Error Count - R/clr */
143 #define IGC_MPC		0x04010  /* Missed Packet Count - R/clr */
144 #define IGC_SCC		0x04014  /* Single Collision Count - R/clr */
145 #define IGC_ECOL	0x04018  /* Excessive Collision Count - R/clr */
146 #define IGC_MCC		0x0401C  /* Multiple Collision Count - R/clr */
147 #define IGC_LATECOL	0x04020  /* Late Collision Count - R/clr */
148 #define IGC_COLC	0x04028  /* Collision Count - R/clr */
149 #define IGC_DC		0x04030  /* Defer Count - R/clr */
150 #define IGC_TNCRS	0x04034  /* Tx-No CRS - R/clr */
151 #define IGC_SEC		0x04038  /* Sequence Error Count - R/clr */
152 #define IGC_CEXTERR	0x0403C  /* Carrier Extension Error Count - R/clr */
153 #define IGC_RLEC	0x04040  /* Receive Length Error Count - R/clr */
154 #define IGC_XONRXC	0x04048  /* XON Rx Count - R/clr */
155 #define IGC_XONTXC	0x0404C  /* XON Tx Count - R/clr */
156 #define IGC_XOFFRXC	0x04050  /* XOFF Rx Count - R/clr */
157 #define IGC_XOFFTXC	0x04054  /* XOFF Tx Count - R/clr */
158 #define IGC_FCRUC	0x04058  /* Flow Control Rx Unsupported Count- R/clr */
159 #define IGC_PRC64	0x0405C  /* Packets Rx (64 bytes) - R/clr */
160 #define IGC_PRC127	0x04060  /* Packets Rx (65-127 bytes) - R/clr */
161 #define IGC_PRC255	0x04064  /* Packets Rx (128-255 bytes) - R/clr */
162 #define IGC_PRC511	0x04068  /* Packets Rx (255-511 bytes) - R/clr */
163 #define IGC_PRC1023	0x0406C  /* Packets Rx (512-1023 bytes) - R/clr */
164 #define IGC_PRC1522	0x04070  /* Packets Rx (1024-1522 bytes) - R/clr */
165 #define IGC_GPRC	0x04074  /* Good Packets Rx Count - R/clr */
166 #define IGC_BPRC	0x04078  /* Broadcast Packets Rx Count - R/clr */
167 #define IGC_MPRC	0x0407C  /* Multicast Packets Rx Count - R/clr */
168 #define IGC_GPTC	0x04080  /* Good Packets Tx Count - R/clr */
169 #define IGC_GORCL	0x04088  /* Good Octets Rx Count Low - R/clr */
170 #define IGC_GORCH	0x0408C  /* Good Octets Rx Count High - R/clr */
171 #define IGC_GOTCL	0x04090  /* Good Octets Tx Count Low - R/clr */
172 #define IGC_GOTCH	0x04094  /* Good Octets Tx Count High - R/clr */
173 #define IGC_RNBC	0x040A0  /* Rx No Buffers Count - R/clr */
174 #define IGC_RUC		0x040A4  /* Rx Undersize Count - R/clr */
175 #define IGC_RFC		0x040A8  /* Rx Fragment Count - R/clr */
176 #define IGC_ROC		0x040AC  /* Rx Oversize Count - R/clr */
177 #define IGC_RJC		0x040B0  /* Rx Jabber Count - R/clr */
178 #define IGC_MGTPRC	0x040B4  /* Management Packets Rx Count - R/clr */
179 #define IGC_MGTPDC	0x040B8  /* Management Packets Dropped Count - R/clr */
180 #define IGC_MGTPTC	0x040BC  /* Management Packets Tx Count - R/clr */
181 #define IGC_TORL	0x040C0  /* Total Octets Rx Low - R/clr */
182 #define IGC_TORH	0x040C4  /* Total Octets Rx High - R/clr */
183 #define IGC_TOTL	0x040C8  /* Total Octets Tx Low - R/clr */
184 #define IGC_TOTH	0x040CC  /* Total Octets Tx High - R/clr */
185 #define IGC_TPR		0x040D0  /* Total Packets Rx - R/clr */
186 #define IGC_TPT		0x040D4  /* Total Packets Tx - R/clr */
187 #define IGC_PTC64	0x040D8  /* Packets Tx (64 bytes) - R/clr */
188 #define IGC_PTC127	0x040DC  /* Packets Tx (65-127 bytes) - R/clr */
189 #define IGC_PTC255	0x040E0  /* Packets Tx (128-255 bytes) - R/clr */
190 #define IGC_PTC511	0x040E4  /* Packets Tx (256-511 bytes) - R/clr */
191 #define IGC_PTC1023	0x040E8  /* Packets Tx (512-1023 bytes) - R/clr */
192 #define IGC_PTC1522	0x040EC  /* Packets Tx (1024-1522 Bytes) - R/clr */
193 #define IGC_MPTC	0x040F0  /* Multicast Packets Tx Count - R/clr */
194 #define IGC_BPTC	0x040F4  /* Broadcast Packets Tx Count - R/clr */
195 #define IGC_TSCTC	0x040F8  /* TCP Segmentation Context Tx - R/clr */
196 #define IGC_TSCTFC	0x040FC  /* TCP Segmentation Context Tx Fail - R/clr */
197 #define IGC_IAC		0x04100  /* Interrupt Assertion Count */
198 #define IGC_ICTXPTC	0x0410C  /* Interrupt Cause Tx Pkt Timer Expire Count */
199 #define IGC_ICTXATC	0x04110  /* Interrupt Cause Tx Abs Timer Expire Count */
200 #define IGC_ICTXQEC	0x04118  /* Interrupt Cause Tx Queue Empty Count */
201 #define IGC_ICTXQMTC	0x0411C  /* Interrupt Cause Tx Queue Min Thresh Count */
202 #define IGC_RPTHC	0x04104  /* Rx Packets To Host */
203 #define IGC_HGPTC	0x04118  /* Host Good Packets Tx Count */
204 #define IGC_RXDMTC	0x04120  /* Rx Descriptor Minimum Threshold Count */
205 #define IGC_HGORCL	0x04128  /* Host Good Octets Received Count Low */
206 #define IGC_HGORCH	0x0412C  /* Host Good Octets Received Count High */
207 #define IGC_HGOTCL	0x04130  /* Host Good Octets Transmit Count Low */
208 #define IGC_HGOTCH	0x04134  /* Host Good Octets Transmit Count High */
209 #define IGC_LENERRS	0x04138  /* Length Errors Count */
210 #define IGC_HRMPC	0x0A018  /* Header Redirection Missed Packet Count */
211 
212 /* Management registers */
213 #define IGC_MANC	0x05820  /* Management Control - RW */
214 
215 /* Shadow Ram Write Register - RW */
216 #define IGC_SRWR	0x12018
217 
218 /* forward declaration */
219 struct igc_hw;
220 u32 igc_rd32(struct igc_hw *hw, u32 reg);
221 
222 /* write operations, indexed using DWORDS */
223 #define wr32(reg, val) \
224 do { \
225 	u8 __iomem *hw_addr = READ_ONCE((hw)->hw_addr); \
226 	if (!IGC_REMOVED(hw_addr)) \
227 		writel((val), &hw_addr[(reg)]); \
228 } while (0)
229 
230 #define rd32(reg) (igc_rd32(hw, reg))
231 
232 #define wrfl() ((void)rd32(IGC_STATUS))
233 
234 #define array_wr32(reg, offset, value) \
235 	wr32((reg) + ((offset) << 2), (value))
236 
237 #define array_rd32(reg, offset) (igc_rd32(hw, (reg) + ((offset) << 2)))
238 
239 #endif
240