1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c)  2018 Intel Corporation */
3 
4 #ifndef _IGC_REGS_H_
5 #define _IGC_REGS_H_
6 
7 /* General Register Descriptions */
8 #define IGC_CTRL		0x00000  /* Device Control - RW */
9 #define IGC_STATUS		0x00008  /* Device Status - RO */
10 #define IGC_EECD		0x00010  /* EEPROM/Flash Control - RW */
11 #define IGC_CTRL_EXT		0x00018  /* Extended Device Control - RW */
12 #define IGC_MDIC		0x00020  /* MDI Control - RW */
13 #define IGC_CONNSW		0x00034  /* Copper/Fiber switch control - RW */
14 #define IGC_VET			0x00038  /* VLAN Ether Type - RW */
15 #define IGC_I225_PHPM		0x00E14  /* I225 PHY Power Management */
16 #define IGC_GPHY_VERSION	0x0001E  /* I225 gPHY Firmware Version */
17 
18 /* Internal Packet Buffer Size Registers */
19 #define IGC_RXPBS		0x02404  /* Rx Packet Buffer Size - RW */
20 #define IGC_TXPBS		0x03404  /* Tx Packet Buffer Size - RW */
21 
22 /* NVM  Register Descriptions */
23 #define IGC_EERD		0x12014  /* EEprom mode read - RW */
24 #define IGC_EEWR		0x12018  /* EEprom mode write - RW */
25 
26 /* Flow Control Register Descriptions */
27 #define IGC_FCAL		0x00028  /* FC Address Low - RW */
28 #define IGC_FCAH		0x0002C  /* FC Address High - RW */
29 #define IGC_FCT			0x00030  /* FC Type - RW */
30 #define IGC_FCTTV		0x00170  /* FC Transmit Timer - RW */
31 #define IGC_FCRTL		0x02160  /* FC Receive Threshold Low - RW */
32 #define IGC_FCRTH		0x02168  /* FC Receive Threshold High - RW */
33 #define IGC_FCRTV		0x02460  /* FC Refresh Timer Value - RW */
34 
35 /* Semaphore registers */
36 #define IGC_SW_FW_SYNC		0x05B5C  /* SW-FW Synchronization - RW */
37 #define IGC_SWSM		0x05B50  /* SW Semaphore */
38 #define IGC_FWSM		0x05B54  /* FW Semaphore */
39 
40 /* Function Active and Power State to MNG */
41 #define IGC_FACTPS		0x05B30
42 
43 /* Interrupt Register Description */
44 #define IGC_EICR		0x01580  /* Ext. Interrupt Cause read - W0 */
45 #define IGC_EICS		0x01520  /* Ext. Interrupt Cause Set - W0 */
46 #define IGC_EIMS		0x01524  /* Ext. Interrupt Mask Set/Read - RW */
47 #define IGC_EIMC		0x01528  /* Ext. Interrupt Mask Clear - WO */
48 #define IGC_EIAC		0x0152C  /* Ext. Interrupt Auto Clear - RW */
49 #define IGC_EIAM		0x01530  /* Ext. Interrupt Auto Mask - RW */
50 #define IGC_ICR			0x01500  /* Intr Cause Read - RC/W1C */
51 #define IGC_ICS			0x01504  /* Intr Cause Set - WO */
52 #define IGC_IMS			0x01508  /* Intr Mask Set/Read - RW */
53 #define IGC_IMC			0x0150C  /* Intr Mask Clear - WO */
54 #define IGC_IAM			0x01510  /* Intr Ack Auto Mask- RW */
55 /* Intr Throttle - RW */
56 #define IGC_EITR(_n)		(0x01680 + (0x4 * (_n)))
57 /* Interrupt Vector Allocation - RW */
58 #define IGC_IVAR0		0x01700
59 #define IGC_IVAR_MISC		0x01740  /* IVAR for "other" causes - RW */
60 #define IGC_GPIE		0x01514  /* General Purpose Intr Enable - RW */
61 
62 /* MSI-X Table Register Descriptions */
63 #define IGC_PBACL		0x05B68  /* MSIx PBA Clear - R/W 1 to clear */
64 
65 /* RSS registers */
66 #define IGC_MRQC		0x05818 /* Multiple Receive Control - RW */
67 
68 /* Filtering Registers */
69 #define IGC_ETQF(_n)		(0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
70 
71 /* ETQF register bit definitions */
72 #define IGC_ETQF_FILTER_ENABLE	BIT(26)
73 #define IGC_ETQF_QUEUE_ENABLE	BIT(31)
74 #define IGC_ETQF_QUEUE_SHIFT	16
75 #define IGC_ETQF_QUEUE_MASK	0x00070000
76 #define IGC_ETQF_ETYPE_MASK	0x0000FFFF
77 
78 /* Redirection Table - RW Array */
79 #define IGC_RETA(_i)		(0x05C00 + ((_i) * 4))
80 /* RSS Random Key - RW Array */
81 #define IGC_RSSRK(_i)		(0x05C80 + ((_i) * 4))
82 
83 /* Receive Register Descriptions */
84 #define IGC_RCTL		0x00100  /* Rx Control - RW */
85 #define IGC_SRRCTL(_n)		(0x0C00C + ((_n) * 0x40))
86 #define IGC_PSRTYPE(_i)		(0x05480 + ((_i) * 4))
87 #define IGC_RDBAL(_n)		(0x0C000 + ((_n) * 0x40))
88 #define IGC_RDBAH(_n)		(0x0C004 + ((_n) * 0x40))
89 #define IGC_RDLEN(_n)		(0x0C008 + ((_n) * 0x40))
90 #define IGC_RDH(_n)		(0x0C010 + ((_n) * 0x40))
91 #define IGC_RDT(_n)		(0x0C018 + ((_n) * 0x40))
92 #define IGC_RXDCTL(_n)		(0x0C028 + ((_n) * 0x40))
93 #define IGC_RQDPC(_n)		(0x0C030 + ((_n) * 0x40))
94 #define IGC_RXCSUM		0x05000  /* Rx Checksum Control - RW */
95 #define IGC_RLPML		0x05004  /* Rx Long Packet Max Length */
96 #define IGC_RFCTL		0x05008  /* Receive Filter Control*/
97 #define IGC_MTA			0x05200  /* Multicast Table Array - RW Array */
98 #define IGC_RA			0x05400  /* Receive Address - RW Array */
99 #define IGC_UTA			0x0A000  /* Unicast Table Array - RW */
100 #define IGC_RAL(_n)		(0x05400 + ((_n) * 0x08))
101 #define IGC_RAH(_n)		(0x05404 + ((_n) * 0x08))
102 #define IGC_VLANPQF		0x055B0  /* VLAN Priority Queue Filter - RW */
103 
104 /* Transmit Register Descriptions */
105 #define IGC_TCTL		0x00400  /* Tx Control - RW */
106 #define IGC_TIPG		0x00410  /* Tx Inter-packet gap - RW */
107 #define IGC_TDBAL(_n)		(0x0E000 + ((_n) * 0x40))
108 #define IGC_TDBAH(_n)		(0x0E004 + ((_n) * 0x40))
109 #define IGC_TDLEN(_n)		(0x0E008 + ((_n) * 0x40))
110 #define IGC_TDH(_n)		(0x0E010 + ((_n) * 0x40))
111 #define IGC_TDT(_n)		(0x0E018 + ((_n) * 0x40))
112 #define IGC_TXDCTL(_n)		(0x0E028 + ((_n) * 0x40))
113 
114 /* MMD Register Descriptions */
115 #define IGC_MMDAC		13 /* MMD Access Control */
116 #define IGC_MMDAAD		14 /* MMD Access Address/Data */
117 
118 /* Statistics Register Descriptions */
119 #define IGC_CRCERRS	0x04000  /* CRC Error Count - R/clr */
120 #define IGC_ALGNERRC	0x04004  /* Alignment Error Count - R/clr */
121 #define IGC_RXERRC	0x0400C  /* Receive Error Count - R/clr */
122 #define IGC_MPC		0x04010  /* Missed Packet Count - R/clr */
123 #define IGC_SCC		0x04014  /* Single Collision Count - R/clr */
124 #define IGC_ECOL	0x04018  /* Excessive Collision Count - R/clr */
125 #define IGC_MCC		0x0401C  /* Multiple Collision Count - R/clr */
126 #define IGC_LATECOL	0x04020  /* Late Collision Count - R/clr */
127 #define IGC_COLC	0x04028  /* Collision Count - R/clr */
128 #define IGC_RERC	0x0402C  /* Receive Error Count - R/clr */
129 #define IGC_DC		0x04030  /* Defer Count - R/clr */
130 #define IGC_TNCRS	0x04034  /* Tx-No CRS - R/clr */
131 #define IGC_HTDPMC	0x0403C  /* Host Transmit Discarded by MAC - R/clr */
132 #define IGC_RLEC	0x04040  /* Receive Length Error Count - R/clr */
133 #define IGC_XONRXC	0x04048  /* XON Rx Count - R/clr */
134 #define IGC_XONTXC	0x0404C  /* XON Tx Count - R/clr */
135 #define IGC_XOFFRXC	0x04050  /* XOFF Rx Count - R/clr */
136 #define IGC_XOFFTXC	0x04054  /* XOFF Tx Count - R/clr */
137 #define IGC_FCRUC	0x04058  /* Flow Control Rx Unsupported Count- R/clr */
138 #define IGC_PRC64	0x0405C  /* Packets Rx (64 bytes) - R/clr */
139 #define IGC_PRC127	0x04060  /* Packets Rx (65-127 bytes) - R/clr */
140 #define IGC_PRC255	0x04064  /* Packets Rx (128-255 bytes) - R/clr */
141 #define IGC_PRC511	0x04068  /* Packets Rx (255-511 bytes) - R/clr */
142 #define IGC_PRC1023	0x0406C  /* Packets Rx (512-1023 bytes) - R/clr */
143 #define IGC_PRC1522	0x04070  /* Packets Rx (1024-1522 bytes) - R/clr */
144 #define IGC_GPRC	0x04074  /* Good Packets Rx Count - R/clr */
145 #define IGC_BPRC	0x04078  /* Broadcast Packets Rx Count - R/clr */
146 #define IGC_MPRC	0x0407C  /* Multicast Packets Rx Count - R/clr */
147 #define IGC_GPTC	0x04080  /* Good Packets Tx Count - R/clr */
148 #define IGC_GORCL	0x04088  /* Good Octets Rx Count Low - R/clr */
149 #define IGC_GORCH	0x0408C  /* Good Octets Rx Count High - R/clr */
150 #define IGC_GOTCL	0x04090  /* Good Octets Tx Count Low - R/clr */
151 #define IGC_GOTCH	0x04094  /* Good Octets Tx Count High - R/clr */
152 #define IGC_RNBC	0x040A0  /* Rx No Buffers Count - R/clr */
153 #define IGC_RUC		0x040A4  /* Rx Undersize Count - R/clr */
154 #define IGC_RFC		0x040A8  /* Rx Fragment Count - R/clr */
155 #define IGC_ROC		0x040AC  /* Rx Oversize Count - R/clr */
156 #define IGC_RJC		0x040B0  /* Rx Jabber Count - R/clr */
157 #define IGC_MGTPRC	0x040B4  /* Management Packets Rx Count - R/clr */
158 #define IGC_MGTPDC	0x040B8  /* Management Packets Dropped Count - R/clr */
159 #define IGC_MGTPTC	0x040BC  /* Management Packets Tx Count - R/clr */
160 #define IGC_TORL	0x040C0  /* Total Octets Rx Low - R/clr */
161 #define IGC_TORH	0x040C4  /* Total Octets Rx High - R/clr */
162 #define IGC_TOTL	0x040C8  /* Total Octets Tx Low - R/clr */
163 #define IGC_TOTH	0x040CC  /* Total Octets Tx High - R/clr */
164 #define IGC_TPR		0x040D0  /* Total Packets Rx - R/clr */
165 #define IGC_TPT		0x040D4  /* Total Packets Tx - R/clr */
166 #define IGC_PTC64	0x040D8  /* Packets Tx (64 bytes) - R/clr */
167 #define IGC_PTC127	0x040DC  /* Packets Tx (65-127 bytes) - R/clr */
168 #define IGC_PTC255	0x040E0  /* Packets Tx (128-255 bytes) - R/clr */
169 #define IGC_PTC511	0x040E4  /* Packets Tx (256-511 bytes) - R/clr */
170 #define IGC_PTC1023	0x040E8  /* Packets Tx (512-1023 bytes) - R/clr */
171 #define IGC_PTC1522	0x040EC  /* Packets Tx (1024-1522 Bytes) - R/clr */
172 #define IGC_MPTC	0x040F0  /* Multicast Packets Tx Count - R/clr */
173 #define IGC_BPTC	0x040F4  /* Broadcast Packets Tx Count - R/clr */
174 #define IGC_TSCTC	0x040F8  /* TCP Segmentation Context Tx - R/clr */
175 #define IGC_IAC		0x04100  /* Interrupt Assertion Count */
176 #define IGC_RPTHC	0x04104  /* Rx Packets To Host */
177 #define IGC_TLPIC	0x04148  /* EEE Tx LPI Count */
178 #define IGC_RLPIC	0x0414C  /* EEE Rx LPI Count */
179 #define IGC_HGPTC	0x04118  /* Host Good Packets Tx Count */
180 #define IGC_RXDMTC	0x04120  /* Rx Descriptor Minimum Threshold Count */
181 #define IGC_HGORCL	0x04128  /* Host Good Octets Received Count Low */
182 #define IGC_HGORCH	0x0412C  /* Host Good Octets Received Count High */
183 #define IGC_HGOTCL	0x04130  /* Host Good Octets Transmit Count Low */
184 #define IGC_HGOTCH	0x04134  /* Host Good Octets Transmit Count High */
185 #define IGC_LENERRS	0x04138  /* Length Errors Count */
186 
187 /* Time sync registers */
188 #define IGC_TSICR	0x0B66C  /* Time Sync Interrupt Cause */
189 #define IGC_TSIM	0x0B674  /* Time Sync Interrupt Mask Register */
190 #define IGC_TSAUXC	0x0B640  /* Timesync Auxiliary Control register */
191 #define IGC_TSYNCRXCTL	0x0B620  /* Rx Time Sync Control register - RW */
192 #define IGC_TSYNCTXCTL	0x0B614  /* Tx Time Sync Control register - RW */
193 #define IGC_TSYNCRXCFG	0x05F50  /* Time Sync Rx Configuration - RW */
194 #define IGC_TSSDP	0x0003C  /* Time Sync SDP Configuration Register - RW */
195 #define IGC_TRGTTIML0	0x0B644 /* Target Time Register 0 Low  - RW */
196 #define IGC_TRGTTIMH0	0x0B648 /* Target Time Register 0 High - RW */
197 #define IGC_TRGTTIML1	0x0B64C /* Target Time Register 1 Low  - RW */
198 #define IGC_TRGTTIMH1	0x0B650 /* Target Time Register 1 High - RW */
199 #define IGC_FREQOUT0	0x0B654 /* Frequency Out 0 Control Register - RW */
200 #define IGC_FREQOUT1	0x0B658 /* Frequency Out 1 Control Register - RW */
201 #define IGC_AUXSTMPL0	0x0B65C /* Auxiliary Time Stamp 0 Register Low  - RO */
202 #define IGC_AUXSTMPH0	0x0B660 /* Auxiliary Time Stamp 0 Register High - RO */
203 #define IGC_AUXSTMPL1	0x0B664 /* Auxiliary Time Stamp 1 Register Low  - RO */
204 #define IGC_AUXSTMPH1	0x0B668 /* Auxiliary Time Stamp 1 Register High - RO */
205 
206 #define IGC_IMIR(_i)	(0x05A80 + ((_i) * 4))  /* Immediate Interrupt */
207 #define IGC_IMIREXT(_i)	(0x05AA0 + ((_i) * 4))  /* Immediate INTR Ext*/
208 
209 #define IGC_FTQF(_n)	(0x059E0 + (4 * (_n)))  /* 5-tuple Queue Fltr */
210 
211 /* Transmit Scheduling Registers */
212 #define IGC_TQAVCTRL		0x3570
213 #define IGC_TXQCTL(_n)		(0x3344 + 0x4 * (_n))
214 #define IGC_BASET_L		0x3314
215 #define IGC_BASET_H		0x3318
216 #define IGC_QBVCYCLET		0x331C
217 #define IGC_QBVCYCLET_S		0x3320
218 
219 #define IGC_STQT(_n)		(0x3324 + 0x4 * (_n))
220 #define IGC_ENDQT(_n)		(0x3334 + 0x4 * (_n))
221 #define IGC_DTXMXPKTSZ		0x355C
222 
223 /* System Time Registers */
224 #define IGC_SYSTIML	0x0B600  /* System time register Low - RO */
225 #define IGC_SYSTIMH	0x0B604  /* System time register High - RO */
226 #define IGC_SYSTIMR	0x0B6F8  /* System time register Residue */
227 #define IGC_TIMINCA	0x0B608  /* Increment attributes register - RW */
228 
229 #define IGC_TXSTMPL	0x0B618  /* Tx timestamp value Low - RO */
230 #define IGC_TXSTMPH	0x0B61C  /* Tx timestamp value High - RO */
231 
232 /* Management registers */
233 #define IGC_MANC	0x05820  /* Management Control - RW */
234 
235 /* Shadow Ram Write Register - RW */
236 #define IGC_SRWR	0x12018
237 
238 /* Wake Up registers */
239 #define IGC_WUC		0x05800  /* Wakeup Control - RW */
240 #define IGC_WUFC	0x05808  /* Wakeup Filter Control - RW */
241 #define IGC_WUS		0x05810  /* Wakeup Status - R/W1C */
242 #define IGC_WUPL	0x05900  /* Wakeup Packet Length - RW */
243 
244 /* Wake Up packet memory */
245 #define IGC_WUPM_REG(_i)	(0x05A00 + ((_i) * 4))
246 
247 /* Energy Efficient Ethernet "EEE" registers */
248 #define IGC_EEER	0x0E30 /* Energy Efficient Ethernet "EEE"*/
249 #define IGC_IPCNFG	0x0E38 /* Internal PHY Configuration */
250 #define IGC_EEE_SU	0x0E34 /* EEE Setup */
251 
252 /* LTR registers */
253 #define IGC_LTRC	0x01A0 /* Latency Tolerance Reporting Control */
254 #define IGC_DMACR	0x02508 /* DMA Coalescing Control Register */
255 #define IGC_LTRMINV	0x5BB0 /* LTR Minimum Value */
256 #define IGC_LTRMAXV	0x5BB4 /* LTR Maximum Value */
257 
258 /* forward declaration */
259 struct igc_hw;
260 u32 igc_rd32(struct igc_hw *hw, u32 reg);
261 
262 /* write operations, indexed using DWORDS */
263 #define wr32(reg, val) \
264 do { \
265 	u8 __iomem *hw_addr = READ_ONCE((hw)->hw_addr); \
266 	writel((val), &hw_addr[(reg)]); \
267 } while (0)
268 
269 #define rd32(reg) (igc_rd32(hw, reg))
270 
271 #define wrfl() ((void)rd32(IGC_STATUS))
272 
273 #define array_wr32(reg, offset, value) \
274 	wr32((reg) + ((offset) << 2), (value))
275 
276 #define array_rd32(reg, offset) (igc_rd32(hw, (reg) + ((offset) << 2)))
277 
278 #endif
279