1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c)  2019 Intel Corporation */
3 
4 #include "igc.h"
5 
6 #include <linux/module.h>
7 #include <linux/device.h>
8 #include <linux/pci.h>
9 #include <linux/ptp_classify.h>
10 #include <linux/clocksource.h>
11 #include <linux/ktime.h>
12 #include <linux/delay.h>
13 #include <linux/iopoll.h>
14 
15 #define INCVALUE_MASK		0x7fffffff
16 #define ISGN			0x80000000
17 
18 #define IGC_SYSTIM_OVERFLOW_PERIOD	(HZ * 60 * 9)
19 #define IGC_PTP_TX_TIMEOUT		(HZ * 15)
20 
21 #define IGC_PTM_STAT_SLEEP		2
22 #define IGC_PTM_STAT_TIMEOUT		100
23 
24 /* SYSTIM read access for I225 */
25 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts)
26 {
27 	struct igc_hw *hw = &adapter->hw;
28 	u32 sec, nsec;
29 
30 	/* The timestamp is latched when SYSTIML is read. */
31 	nsec = rd32(IGC_SYSTIML);
32 	sec = rd32(IGC_SYSTIMH);
33 
34 	ts->tv_sec = sec;
35 	ts->tv_nsec = nsec;
36 }
37 
38 static void igc_ptp_write_i225(struct igc_adapter *adapter,
39 			       const struct timespec64 *ts)
40 {
41 	struct igc_hw *hw = &adapter->hw;
42 
43 	wr32(IGC_SYSTIML, ts->tv_nsec);
44 	wr32(IGC_SYSTIMH, ts->tv_sec);
45 }
46 
47 static int igc_ptp_adjfine_i225(struct ptp_clock_info *ptp, long scaled_ppm)
48 {
49 	struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
50 					       ptp_caps);
51 	struct igc_hw *hw = &igc->hw;
52 	int neg_adj = 0;
53 	u64 rate;
54 	u32 inca;
55 
56 	if (scaled_ppm < 0) {
57 		neg_adj = 1;
58 		scaled_ppm = -scaled_ppm;
59 	}
60 	rate = scaled_ppm;
61 	rate <<= 14;
62 	rate = div_u64(rate, 78125);
63 
64 	inca = rate & INCVALUE_MASK;
65 	if (neg_adj)
66 		inca |= ISGN;
67 
68 	wr32(IGC_TIMINCA, inca);
69 
70 	return 0;
71 }
72 
73 static int igc_ptp_adjtime_i225(struct ptp_clock_info *ptp, s64 delta)
74 {
75 	struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
76 					       ptp_caps);
77 	struct timespec64 now, then = ns_to_timespec64(delta);
78 	unsigned long flags;
79 
80 	spin_lock_irqsave(&igc->tmreg_lock, flags);
81 
82 	igc_ptp_read(igc, &now);
83 	now = timespec64_add(now, then);
84 	igc_ptp_write_i225(igc, (const struct timespec64 *)&now);
85 
86 	spin_unlock_irqrestore(&igc->tmreg_lock, flags);
87 
88 	return 0;
89 }
90 
91 static int igc_ptp_gettimex64_i225(struct ptp_clock_info *ptp,
92 				   struct timespec64 *ts,
93 				   struct ptp_system_timestamp *sts)
94 {
95 	struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
96 					       ptp_caps);
97 	struct igc_hw *hw = &igc->hw;
98 	unsigned long flags;
99 
100 	spin_lock_irqsave(&igc->tmreg_lock, flags);
101 
102 	ptp_read_system_prets(sts);
103 	ts->tv_nsec = rd32(IGC_SYSTIML);
104 	ts->tv_sec = rd32(IGC_SYSTIMH);
105 	ptp_read_system_postts(sts);
106 
107 	spin_unlock_irqrestore(&igc->tmreg_lock, flags);
108 
109 	return 0;
110 }
111 
112 static int igc_ptp_settime_i225(struct ptp_clock_info *ptp,
113 				const struct timespec64 *ts)
114 {
115 	struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
116 					       ptp_caps);
117 	unsigned long flags;
118 
119 	spin_lock_irqsave(&igc->tmreg_lock, flags);
120 
121 	igc_ptp_write_i225(igc, ts);
122 
123 	spin_unlock_irqrestore(&igc->tmreg_lock, flags);
124 
125 	return 0;
126 }
127 
128 static void igc_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
129 {
130 	u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
131 	static const u32 mask[IGC_N_SDP] = {
132 		IGC_CTRL_SDP0_DIR,
133 		IGC_CTRL_SDP1_DIR,
134 		IGC_CTRL_EXT_SDP2_DIR,
135 		IGC_CTRL_EXT_SDP3_DIR,
136 	};
137 
138 	if (input)
139 		*ptr &= ~mask[pin];
140 	else
141 		*ptr |= mask[pin];
142 }
143 
144 static void igc_pin_perout(struct igc_adapter *igc, int chan, int pin, int freq)
145 {
146 	static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
147 		IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
148 	};
149 	static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
150 		IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
151 	};
152 	static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
153 		IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
154 	};
155 	static const u32 igc_ts_sdp_sel_tt0[IGC_N_SDP] = {
156 		IGC_TS_SDP0_SEL_TT0, IGC_TS_SDP1_SEL_TT0,
157 		IGC_TS_SDP2_SEL_TT0, IGC_TS_SDP3_SEL_TT0,
158 	};
159 	static const u32 igc_ts_sdp_sel_tt1[IGC_N_SDP] = {
160 		IGC_TS_SDP0_SEL_TT1, IGC_TS_SDP1_SEL_TT1,
161 		IGC_TS_SDP2_SEL_TT1, IGC_TS_SDP3_SEL_TT1,
162 	};
163 	static const u32 igc_ts_sdp_sel_fc0[IGC_N_SDP] = {
164 		IGC_TS_SDP0_SEL_FC0, IGC_TS_SDP1_SEL_FC0,
165 		IGC_TS_SDP2_SEL_FC0, IGC_TS_SDP3_SEL_FC0,
166 	};
167 	static const u32 igc_ts_sdp_sel_fc1[IGC_N_SDP] = {
168 		IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
169 		IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
170 	};
171 	static const u32 igc_ts_sdp_sel_clr[IGC_N_SDP] = {
172 		IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
173 		IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
174 	};
175 	struct igc_hw *hw = &igc->hw;
176 	u32 ctrl, ctrl_ext, tssdp = 0;
177 
178 	ctrl = rd32(IGC_CTRL);
179 	ctrl_ext = rd32(IGC_CTRL_EXT);
180 	tssdp = rd32(IGC_TSSDP);
181 
182 	igc_pin_direction(pin, 0, &ctrl, &ctrl_ext);
183 
184 	/* Make sure this pin is not enabled as an input. */
185 	if ((tssdp & IGC_AUX0_SEL_SDP3) == igc_aux0_sel_sdp[pin])
186 		tssdp &= ~IGC_AUX0_TS_SDP_EN;
187 
188 	if ((tssdp & IGC_AUX1_SEL_SDP3) == igc_aux1_sel_sdp[pin])
189 		tssdp &= ~IGC_AUX1_TS_SDP_EN;
190 
191 	tssdp &= ~igc_ts_sdp_sel_clr[pin];
192 	if (freq) {
193 		if (chan == 1)
194 			tssdp |= igc_ts_sdp_sel_fc1[pin];
195 		else
196 			tssdp |= igc_ts_sdp_sel_fc0[pin];
197 	} else {
198 		if (chan == 1)
199 			tssdp |= igc_ts_sdp_sel_tt1[pin];
200 		else
201 			tssdp |= igc_ts_sdp_sel_tt0[pin];
202 	}
203 	tssdp |= igc_ts_sdp_en[pin];
204 
205 	wr32(IGC_TSSDP, tssdp);
206 	wr32(IGC_CTRL, ctrl);
207 	wr32(IGC_CTRL_EXT, ctrl_ext);
208 }
209 
210 static void igc_pin_extts(struct igc_adapter *igc, int chan, int pin)
211 {
212 	static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
213 		IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
214 	};
215 	static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
216 		IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
217 	};
218 	static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
219 		IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
220 	};
221 	struct igc_hw *hw = &igc->hw;
222 	u32 ctrl, ctrl_ext, tssdp = 0;
223 
224 	ctrl = rd32(IGC_CTRL);
225 	ctrl_ext = rd32(IGC_CTRL_EXT);
226 	tssdp = rd32(IGC_TSSDP);
227 
228 	igc_pin_direction(pin, 1, &ctrl, &ctrl_ext);
229 
230 	/* Make sure this pin is not enabled as an output. */
231 	tssdp &= ~igc_ts_sdp_en[pin];
232 
233 	if (chan == 1) {
234 		tssdp &= ~IGC_AUX1_SEL_SDP3;
235 		tssdp |= igc_aux1_sel_sdp[pin] | IGC_AUX1_TS_SDP_EN;
236 	} else {
237 		tssdp &= ~IGC_AUX0_SEL_SDP3;
238 		tssdp |= igc_aux0_sel_sdp[pin] | IGC_AUX0_TS_SDP_EN;
239 	}
240 
241 	wr32(IGC_TSSDP, tssdp);
242 	wr32(IGC_CTRL, ctrl);
243 	wr32(IGC_CTRL_EXT, ctrl_ext);
244 }
245 
246 static int igc_ptp_feature_enable_i225(struct ptp_clock_info *ptp,
247 				       struct ptp_clock_request *rq, int on)
248 {
249 	struct igc_adapter *igc =
250 		container_of(ptp, struct igc_adapter, ptp_caps);
251 	struct igc_hw *hw = &igc->hw;
252 	unsigned long flags;
253 	struct timespec64 ts;
254 	int use_freq = 0, pin = -1;
255 	u32 tsim, tsauxc, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
256 	s64 ns;
257 
258 	switch (rq->type) {
259 	case PTP_CLK_REQ_EXTTS:
260 		/* Reject requests with unsupported flags */
261 		if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
262 					PTP_RISING_EDGE |
263 					PTP_FALLING_EDGE |
264 					PTP_STRICT_FLAGS))
265 			return -EOPNOTSUPP;
266 
267 		/* Reject requests failing to enable both edges. */
268 		if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
269 		    (rq->extts.flags & PTP_ENABLE_FEATURE) &&
270 		    (rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES)
271 			return -EOPNOTSUPP;
272 
273 		if (on) {
274 			pin = ptp_find_pin(igc->ptp_clock, PTP_PF_EXTTS,
275 					   rq->extts.index);
276 			if (pin < 0)
277 				return -EBUSY;
278 		}
279 		if (rq->extts.index == 1) {
280 			tsauxc_mask = IGC_TSAUXC_EN_TS1;
281 			tsim_mask = IGC_TSICR_AUTT1;
282 		} else {
283 			tsauxc_mask = IGC_TSAUXC_EN_TS0;
284 			tsim_mask = IGC_TSICR_AUTT0;
285 		}
286 		spin_lock_irqsave(&igc->tmreg_lock, flags);
287 		tsauxc = rd32(IGC_TSAUXC);
288 		tsim = rd32(IGC_TSIM);
289 		if (on) {
290 			igc_pin_extts(igc, rq->extts.index, pin);
291 			tsauxc |= tsauxc_mask;
292 			tsim |= tsim_mask;
293 		} else {
294 			tsauxc &= ~tsauxc_mask;
295 			tsim &= ~tsim_mask;
296 		}
297 		wr32(IGC_TSAUXC, tsauxc);
298 		wr32(IGC_TSIM, tsim);
299 		spin_unlock_irqrestore(&igc->tmreg_lock, flags);
300 		return 0;
301 
302 	case PTP_CLK_REQ_PEROUT:
303 		/* Reject requests with unsupported flags */
304 		if (rq->perout.flags)
305 			return -EOPNOTSUPP;
306 
307 		if (on) {
308 			pin = ptp_find_pin(igc->ptp_clock, PTP_PF_PEROUT,
309 					   rq->perout.index);
310 			if (pin < 0)
311 				return -EBUSY;
312 		}
313 		ts.tv_sec = rq->perout.period.sec;
314 		ts.tv_nsec = rq->perout.period.nsec;
315 		ns = timespec64_to_ns(&ts);
316 		ns = ns >> 1;
317 		if (on && (ns <= 70000000LL || ns == 125000000LL ||
318 			   ns == 250000000LL || ns == 500000000LL)) {
319 			if (ns < 8LL)
320 				return -EINVAL;
321 			use_freq = 1;
322 		}
323 		ts = ns_to_timespec64(ns);
324 		if (rq->perout.index == 1) {
325 			if (use_freq) {
326 				tsauxc_mask = IGC_TSAUXC_EN_CLK1;
327 				tsim_mask = 0;
328 			} else {
329 				tsauxc_mask = IGC_TSAUXC_EN_TT1;
330 				tsim_mask = IGC_TSICR_TT1;
331 			}
332 			trgttiml = IGC_TRGTTIML1;
333 			trgttimh = IGC_TRGTTIMH1;
334 			freqout = IGC_FREQOUT1;
335 		} else {
336 			if (use_freq) {
337 				tsauxc_mask = IGC_TSAUXC_EN_CLK0;
338 				tsim_mask = 0;
339 			} else {
340 				tsauxc_mask = IGC_TSAUXC_EN_TT0;
341 				tsim_mask = IGC_TSICR_TT0;
342 			}
343 			trgttiml = IGC_TRGTTIML0;
344 			trgttimh = IGC_TRGTTIMH0;
345 			freqout = IGC_FREQOUT0;
346 		}
347 		spin_lock_irqsave(&igc->tmreg_lock, flags);
348 		tsauxc = rd32(IGC_TSAUXC);
349 		tsim = rd32(IGC_TSIM);
350 		if (rq->perout.index == 1) {
351 			tsauxc &= ~(IGC_TSAUXC_EN_TT1 | IGC_TSAUXC_EN_CLK1);
352 			tsim &= ~IGC_TSICR_TT1;
353 		} else {
354 			tsauxc &= ~(IGC_TSAUXC_EN_TT0 | IGC_TSAUXC_EN_CLK0);
355 			tsim &= ~IGC_TSICR_TT0;
356 		}
357 		if (on) {
358 			int i = rq->perout.index;
359 
360 			igc_pin_perout(igc, i, pin, use_freq);
361 			igc->perout[i].start.tv_sec = rq->perout.start.sec;
362 			igc->perout[i].start.tv_nsec = rq->perout.start.nsec;
363 			igc->perout[i].period.tv_sec = ts.tv_sec;
364 			igc->perout[i].period.tv_nsec = ts.tv_nsec;
365 			wr32(trgttimh, rq->perout.start.sec);
366 			/* For now, always select timer 0 as source. */
367 			wr32(trgttiml, rq->perout.start.nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0);
368 			if (use_freq)
369 				wr32(freqout, ns);
370 			tsauxc |= tsauxc_mask;
371 			tsim |= tsim_mask;
372 		}
373 		wr32(IGC_TSAUXC, tsauxc);
374 		wr32(IGC_TSIM, tsim);
375 		spin_unlock_irqrestore(&igc->tmreg_lock, flags);
376 		return 0;
377 
378 	case PTP_CLK_REQ_PPS:
379 		spin_lock_irqsave(&igc->tmreg_lock, flags);
380 		tsim = rd32(IGC_TSIM);
381 		if (on)
382 			tsim |= IGC_TSICR_SYS_WRAP;
383 		else
384 			tsim &= ~IGC_TSICR_SYS_WRAP;
385 		igc->pps_sys_wrap_on = on;
386 		wr32(IGC_TSIM, tsim);
387 		spin_unlock_irqrestore(&igc->tmreg_lock, flags);
388 		return 0;
389 
390 	default:
391 		break;
392 	}
393 
394 	return -EOPNOTSUPP;
395 }
396 
397 static int igc_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
398 			      enum ptp_pin_function func, unsigned int chan)
399 {
400 	switch (func) {
401 	case PTP_PF_NONE:
402 	case PTP_PF_EXTTS:
403 	case PTP_PF_PEROUT:
404 		break;
405 	case PTP_PF_PHYSYNC:
406 		return -1;
407 	}
408 	return 0;
409 }
410 
411 /**
412  * igc_ptp_systim_to_hwtstamp - convert system time value to HW timestamp
413  * @adapter: board private structure
414  * @hwtstamps: timestamp structure to update
415  * @systim: unsigned 64bit system time value
416  *
417  * We need to convert the system time value stored in the RX/TXSTMP registers
418  * into a hwtstamp which can be used by the upper level timestamping functions.
419  **/
420 static void igc_ptp_systim_to_hwtstamp(struct igc_adapter *adapter,
421 				       struct skb_shared_hwtstamps *hwtstamps,
422 				       u64 systim)
423 {
424 	switch (adapter->hw.mac.type) {
425 	case igc_i225:
426 		memset(hwtstamps, 0, sizeof(*hwtstamps));
427 		/* Upper 32 bits contain s, lower 32 bits contain ns. */
428 		hwtstamps->hwtstamp = ktime_set(systim >> 32,
429 						systim & 0xFFFFFFFF);
430 		break;
431 	default:
432 		break;
433 	}
434 }
435 
436 /**
437  * igc_ptp_rx_pktstamp - Retrieve timestamp from Rx packet buffer
438  * @adapter: Pointer to adapter the packet buffer belongs to
439  * @buf: Pointer to packet buffer
440  *
441  * This function retrieves the timestamp saved in the beginning of packet
442  * buffer. While two timestamps are available, one in timer0 reference and the
443  * other in timer1 reference, this function considers only the timestamp in
444  * timer0 reference.
445  *
446  * Returns timestamp value.
447  */
448 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf)
449 {
450 	ktime_t timestamp;
451 	u32 secs, nsecs;
452 	int adjust;
453 
454 	/* Timestamps are saved in little endian at the beginning of the packet
455 	 * buffer following the layout:
456 	 *
457 	 * DWORD: | 0              | 1              | 2              | 3              |
458 	 * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH |
459 	 *
460 	 * SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds
461 	 * part of the timestamp.
462 	 */
463 	nsecs = le32_to_cpu(buf[2]);
464 	secs = le32_to_cpu(buf[3]);
465 
466 	timestamp = ktime_set(secs, nsecs);
467 
468 	/* Adjust timestamp for the RX latency based on link speed */
469 	switch (adapter->link_speed) {
470 	case SPEED_10:
471 		adjust = IGC_I225_RX_LATENCY_10;
472 		break;
473 	case SPEED_100:
474 		adjust = IGC_I225_RX_LATENCY_100;
475 		break;
476 	case SPEED_1000:
477 		adjust = IGC_I225_RX_LATENCY_1000;
478 		break;
479 	case SPEED_2500:
480 		adjust = IGC_I225_RX_LATENCY_2500;
481 		break;
482 	default:
483 		adjust = 0;
484 		netdev_warn_once(adapter->netdev, "Imprecise timestamp\n");
485 		break;
486 	}
487 
488 	return ktime_sub_ns(timestamp, adjust);
489 }
490 
491 static void igc_ptp_disable_rx_timestamp(struct igc_adapter *adapter)
492 {
493 	struct igc_hw *hw = &adapter->hw;
494 	u32 val;
495 	int i;
496 
497 	wr32(IGC_TSYNCRXCTL, 0);
498 
499 	for (i = 0; i < adapter->num_rx_queues; i++) {
500 		val = rd32(IGC_SRRCTL(i));
501 		val &= ~IGC_SRRCTL_TIMESTAMP;
502 		wr32(IGC_SRRCTL(i), val);
503 	}
504 
505 	val = rd32(IGC_RXPBS);
506 	val &= ~IGC_RXPBS_CFG_TS_EN;
507 	wr32(IGC_RXPBS, val);
508 }
509 
510 static void igc_ptp_enable_rx_timestamp(struct igc_adapter *adapter)
511 {
512 	struct igc_hw *hw = &adapter->hw;
513 	u32 val;
514 	int i;
515 
516 	val = rd32(IGC_RXPBS);
517 	val |= IGC_RXPBS_CFG_TS_EN;
518 	wr32(IGC_RXPBS, val);
519 
520 	for (i = 0; i < adapter->num_rx_queues; i++) {
521 		val = rd32(IGC_SRRCTL(i));
522 		/* FIXME: For now, only support retrieving RX timestamps from
523 		 * timer 0.
524 		 */
525 		val |= IGC_SRRCTL_TIMER1SEL(0) | IGC_SRRCTL_TIMER0SEL(0) |
526 		       IGC_SRRCTL_TIMESTAMP;
527 		wr32(IGC_SRRCTL(i), val);
528 	}
529 
530 	val = IGC_TSYNCRXCTL_ENABLED | IGC_TSYNCRXCTL_TYPE_ALL |
531 	      IGC_TSYNCRXCTL_RXSYNSIG;
532 	wr32(IGC_TSYNCRXCTL, val);
533 }
534 
535 static void igc_ptp_disable_tx_timestamp(struct igc_adapter *adapter)
536 {
537 	struct igc_hw *hw = &adapter->hw;
538 
539 	wr32(IGC_TSYNCTXCTL, 0);
540 }
541 
542 static void igc_ptp_enable_tx_timestamp(struct igc_adapter *adapter)
543 {
544 	struct igc_hw *hw = &adapter->hw;
545 
546 	wr32(IGC_TSYNCTXCTL, IGC_TSYNCTXCTL_ENABLED | IGC_TSYNCTXCTL_TXSYNSIG);
547 
548 	/* Read TXSTMP registers to discard any timestamp previously stored. */
549 	rd32(IGC_TXSTMPL);
550 	rd32(IGC_TXSTMPH);
551 }
552 
553 /**
554  * igc_ptp_set_timestamp_mode - setup hardware for timestamping
555  * @adapter: networking device structure
556  * @config: hwtstamp configuration
557  *
558  * Return: 0 in case of success, negative errno code otherwise.
559  */
560 static int igc_ptp_set_timestamp_mode(struct igc_adapter *adapter,
561 				      struct hwtstamp_config *config)
562 {
563 	switch (config->tx_type) {
564 	case HWTSTAMP_TX_OFF:
565 		igc_ptp_disable_tx_timestamp(adapter);
566 		break;
567 	case HWTSTAMP_TX_ON:
568 		igc_ptp_enable_tx_timestamp(adapter);
569 		break;
570 	default:
571 		return -ERANGE;
572 	}
573 
574 	switch (config->rx_filter) {
575 	case HWTSTAMP_FILTER_NONE:
576 		igc_ptp_disable_rx_timestamp(adapter);
577 		break;
578 	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
579 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
580 	case HWTSTAMP_FILTER_PTP_V2_EVENT:
581 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
582 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
583 	case HWTSTAMP_FILTER_PTP_V2_SYNC:
584 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
585 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
586 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
587 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
588 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
589 	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
590 	case HWTSTAMP_FILTER_NTP_ALL:
591 	case HWTSTAMP_FILTER_ALL:
592 		igc_ptp_enable_rx_timestamp(adapter);
593 		config->rx_filter = HWTSTAMP_FILTER_ALL;
594 		break;
595 	default:
596 		return -ERANGE;
597 	}
598 
599 	return 0;
600 }
601 
602 static void igc_ptp_tx_timeout(struct igc_adapter *adapter)
603 {
604 	struct igc_hw *hw = &adapter->hw;
605 
606 	dev_kfree_skb_any(adapter->ptp_tx_skb);
607 	adapter->ptp_tx_skb = NULL;
608 	adapter->tx_hwtstamp_timeouts++;
609 	clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state);
610 	/* Clear the tx valid bit in TSYNCTXCTL register to enable interrupt. */
611 	rd32(IGC_TXSTMPH);
612 	netdev_warn(adapter->netdev, "Tx timestamp timeout\n");
613 }
614 
615 void igc_ptp_tx_hang(struct igc_adapter *adapter)
616 {
617 	bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
618 					      IGC_PTP_TX_TIMEOUT);
619 
620 	if (!test_bit(__IGC_PTP_TX_IN_PROGRESS, &adapter->state))
621 		return;
622 
623 	/* If we haven't received a timestamp within the timeout, it is
624 	 * reasonable to assume that it will never occur, so we can unlock the
625 	 * timestamp bit when this occurs.
626 	 */
627 	if (timeout) {
628 		cancel_work_sync(&adapter->ptp_tx_work);
629 		igc_ptp_tx_timeout(adapter);
630 	}
631 }
632 
633 /**
634  * igc_ptp_tx_hwtstamp - utility function which checks for TX time stamp
635  * @adapter: Board private structure
636  *
637  * If we were asked to do hardware stamping and such a time stamp is
638  * available, then it must have been for this skb here because we only
639  * allow only one such packet into the queue.
640  */
641 static void igc_ptp_tx_hwtstamp(struct igc_adapter *adapter)
642 {
643 	struct sk_buff *skb = adapter->ptp_tx_skb;
644 	struct skb_shared_hwtstamps shhwtstamps;
645 	struct igc_hw *hw = &adapter->hw;
646 	int adjust = 0;
647 	u64 regval;
648 
649 	if (WARN_ON_ONCE(!skb))
650 		return;
651 
652 	regval = rd32(IGC_TXSTMPL);
653 	regval |= (u64)rd32(IGC_TXSTMPH) << 32;
654 	igc_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
655 
656 	switch (adapter->link_speed) {
657 	case SPEED_10:
658 		adjust = IGC_I225_TX_LATENCY_10;
659 		break;
660 	case SPEED_100:
661 		adjust = IGC_I225_TX_LATENCY_100;
662 		break;
663 	case SPEED_1000:
664 		adjust = IGC_I225_TX_LATENCY_1000;
665 		break;
666 	case SPEED_2500:
667 		adjust = IGC_I225_TX_LATENCY_2500;
668 		break;
669 	}
670 
671 	shhwtstamps.hwtstamp =
672 		ktime_add_ns(shhwtstamps.hwtstamp, adjust);
673 
674 	/* Clear the lock early before calling skb_tstamp_tx so that
675 	 * applications are not woken up before the lock bit is clear. We use
676 	 * a copy of the skb pointer to ensure other threads can't change it
677 	 * while we're notifying the stack.
678 	 */
679 	adapter->ptp_tx_skb = NULL;
680 	clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state);
681 
682 	/* Notify the stack and free the skb after we've unlocked */
683 	skb_tstamp_tx(skb, &shhwtstamps);
684 	dev_kfree_skb_any(skb);
685 }
686 
687 /**
688  * igc_ptp_tx_work
689  * @work: pointer to work struct
690  *
691  * This work function polls the TSYNCTXCTL valid bit to determine when a
692  * timestamp has been taken for the current stored skb.
693  */
694 static void igc_ptp_tx_work(struct work_struct *work)
695 {
696 	struct igc_adapter *adapter = container_of(work, struct igc_adapter,
697 						   ptp_tx_work);
698 	struct igc_hw *hw = &adapter->hw;
699 	u32 tsynctxctl;
700 
701 	if (!test_bit(__IGC_PTP_TX_IN_PROGRESS, &adapter->state))
702 		return;
703 
704 	tsynctxctl = rd32(IGC_TSYNCTXCTL);
705 	if (WARN_ON_ONCE(!(tsynctxctl & IGC_TSYNCTXCTL_TXTT_0)))
706 		return;
707 
708 	igc_ptp_tx_hwtstamp(adapter);
709 }
710 
711 /**
712  * igc_ptp_set_ts_config - set hardware time stamping config
713  * @netdev: network interface device structure
714  * @ifr: interface request data
715  *
716  **/
717 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
718 {
719 	struct igc_adapter *adapter = netdev_priv(netdev);
720 	struct hwtstamp_config config;
721 	int err;
722 
723 	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
724 		return -EFAULT;
725 
726 	err = igc_ptp_set_timestamp_mode(adapter, &config);
727 	if (err)
728 		return err;
729 
730 	/* save these settings for future reference */
731 	memcpy(&adapter->tstamp_config, &config,
732 	       sizeof(adapter->tstamp_config));
733 
734 	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
735 		-EFAULT : 0;
736 }
737 
738 /**
739  * igc_ptp_get_ts_config - get hardware time stamping config
740  * @netdev: network interface device structure
741  * @ifr: interface request data
742  *
743  * Get the hwtstamp_config settings to return to the user. Rather than attempt
744  * to deconstruct the settings from the registers, just return a shadow copy
745  * of the last known settings.
746  **/
747 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
748 {
749 	struct igc_adapter *adapter = netdev_priv(netdev);
750 	struct hwtstamp_config *config = &adapter->tstamp_config;
751 
752 	return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
753 		-EFAULT : 0;
754 }
755 
756 /* The two conditions below must be met for cross timestamping via
757  * PCIe PTM:
758  *
759  * 1. We have an way to convert the timestamps in the PTM messages
760  *    to something related to the system clocks (right now, only
761  *    X86 systems with support for the Always Running Timer allow that);
762  *
763  * 2. We have PTM enabled in the path from the device to the PCIe root port.
764  */
765 static bool igc_is_crosststamp_supported(struct igc_adapter *adapter)
766 {
767 	if (!IS_ENABLED(CONFIG_X86_TSC))
768 		return false;
769 
770 	/* FIXME: it was noticed that enabling support for PCIe PTM in
771 	 * some i225-V models could cause lockups when bringing the
772 	 * interface up/down. There should be no downsides to
773 	 * disabling crosstimestamping support for i225-V, as it
774 	 * doesn't have any PTP support. That way we gain some time
775 	 * while root causing the issue.
776 	 */
777 	if (adapter->pdev->device == IGC_DEV_ID_I225_V)
778 		return false;
779 
780 	return pcie_ptm_enabled(adapter->pdev);
781 }
782 
783 static struct system_counterval_t igc_device_tstamp_to_system(u64 tstamp)
784 {
785 #if IS_ENABLED(CONFIG_X86_TSC) && !defined(CONFIG_UML)
786 	return convert_art_ns_to_tsc(tstamp);
787 #else
788 	return (struct system_counterval_t) { };
789 #endif
790 }
791 
792 static void igc_ptm_log_error(struct igc_adapter *adapter, u32 ptm_stat)
793 {
794 	struct net_device *netdev = adapter->netdev;
795 
796 	switch (ptm_stat) {
797 	case IGC_PTM_STAT_RET_ERR:
798 		netdev_err(netdev, "PTM Error: Root port timeout\n");
799 		break;
800 	case IGC_PTM_STAT_BAD_PTM_RES:
801 		netdev_err(netdev, "PTM Error: Bad response, PTM Response Data expected\n");
802 		break;
803 	case IGC_PTM_STAT_T4M1_OVFL:
804 		netdev_err(netdev, "PTM Error: T4 minus T1 overflow\n");
805 		break;
806 	case IGC_PTM_STAT_ADJUST_1ST:
807 		netdev_err(netdev, "PTM Error: 1588 timer adjusted during first PTM cycle\n");
808 		break;
809 	case IGC_PTM_STAT_ADJUST_CYC:
810 		netdev_err(netdev, "PTM Error: 1588 timer adjusted during non-first PTM cycle\n");
811 		break;
812 	default:
813 		netdev_err(netdev, "PTM Error: Unknown error (%#x)\n", ptm_stat);
814 		break;
815 	}
816 }
817 
818 static int igc_phc_get_syncdevicetime(ktime_t *device,
819 				      struct system_counterval_t *system,
820 				      void *ctx)
821 {
822 	u32 stat, t2_curr_h, t2_curr_l, ctrl;
823 	struct igc_adapter *adapter = ctx;
824 	struct igc_hw *hw = &adapter->hw;
825 	int err, count = 100;
826 	ktime_t t1, t2_curr;
827 
828 	/* Get a snapshot of system clocks to use as historic value. */
829 	ktime_get_snapshot(&adapter->snapshot);
830 
831 	do {
832 		/* Doing this in a loop because in the event of a
833 		 * badly timed (ha!) system clock adjustment, we may
834 		 * get PTM errors from the PCI root, but these errors
835 		 * are transitory. Repeating the process returns valid
836 		 * data eventually.
837 		 */
838 
839 		/* To "manually" start the PTM cycle we need to clear and
840 		 * then set again the TRIG bit.
841 		 */
842 		ctrl = rd32(IGC_PTM_CTRL);
843 		ctrl &= ~IGC_PTM_CTRL_TRIG;
844 		wr32(IGC_PTM_CTRL, ctrl);
845 		ctrl |= IGC_PTM_CTRL_TRIG;
846 		wr32(IGC_PTM_CTRL, ctrl);
847 
848 		/* The cycle only starts "for real" when software notifies
849 		 * that it has read the registers, this is done by setting
850 		 * VALID bit.
851 		 */
852 		wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID);
853 
854 		err = readx_poll_timeout(rd32, IGC_PTM_STAT, stat,
855 					 stat, IGC_PTM_STAT_SLEEP,
856 					 IGC_PTM_STAT_TIMEOUT);
857 		if (err < 0) {
858 			netdev_err(adapter->netdev, "Timeout reading IGC_PTM_STAT register\n");
859 			return err;
860 		}
861 
862 		if ((stat & IGC_PTM_STAT_VALID) == IGC_PTM_STAT_VALID)
863 			break;
864 
865 		if (stat & ~IGC_PTM_STAT_VALID) {
866 			/* An error occurred, log it. */
867 			igc_ptm_log_error(adapter, stat);
868 			/* The STAT register is write-1-to-clear (W1C),
869 			 * so write the previous error status to clear it.
870 			 */
871 			wr32(IGC_PTM_STAT, stat);
872 			continue;
873 		}
874 	} while (--count);
875 
876 	if (!count) {
877 		netdev_err(adapter->netdev, "Exceeded number of tries for PTM cycle\n");
878 		return -ETIMEDOUT;
879 	}
880 
881 	t1 = ktime_set(rd32(IGC_PTM_T1_TIM0_H), rd32(IGC_PTM_T1_TIM0_L));
882 
883 	t2_curr_l = rd32(IGC_PTM_CURR_T2_L);
884 	t2_curr_h = rd32(IGC_PTM_CURR_T2_H);
885 
886 	/* FIXME: When the register that tells the endianness of the
887 	 * PTM registers are implemented, check them here and add the
888 	 * appropriate conversion.
889 	 */
890 	t2_curr_h = swab32(t2_curr_h);
891 
892 	t2_curr = ((s64)t2_curr_h << 32 | t2_curr_l);
893 
894 	*device = t1;
895 	*system = igc_device_tstamp_to_system(t2_curr);
896 
897 	return 0;
898 }
899 
900 static int igc_ptp_getcrosststamp(struct ptp_clock_info *ptp,
901 				  struct system_device_crosststamp *cts)
902 {
903 	struct igc_adapter *adapter = container_of(ptp, struct igc_adapter,
904 						   ptp_caps);
905 
906 	return get_device_system_crosststamp(igc_phc_get_syncdevicetime,
907 					     adapter, &adapter->snapshot, cts);
908 }
909 
910 /**
911  * igc_ptp_init - Initialize PTP functionality
912  * @adapter: Board private structure
913  *
914  * This function is called at device probe to initialize the PTP
915  * functionality.
916  */
917 void igc_ptp_init(struct igc_adapter *adapter)
918 {
919 	struct net_device *netdev = adapter->netdev;
920 	struct igc_hw *hw = &adapter->hw;
921 	int i;
922 
923 	switch (hw->mac.type) {
924 	case igc_i225:
925 		for (i = 0; i < IGC_N_SDP; i++) {
926 			struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
927 
928 			snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
929 			ppd->index = i;
930 			ppd->func = PTP_PF_NONE;
931 		}
932 		snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
933 		adapter->ptp_caps.owner = THIS_MODULE;
934 		adapter->ptp_caps.max_adj = 62499999;
935 		adapter->ptp_caps.adjfine = igc_ptp_adjfine_i225;
936 		adapter->ptp_caps.adjtime = igc_ptp_adjtime_i225;
937 		adapter->ptp_caps.gettimex64 = igc_ptp_gettimex64_i225;
938 		adapter->ptp_caps.settime64 = igc_ptp_settime_i225;
939 		adapter->ptp_caps.enable = igc_ptp_feature_enable_i225;
940 		adapter->ptp_caps.pps = 1;
941 		adapter->ptp_caps.pin_config = adapter->sdp_config;
942 		adapter->ptp_caps.n_ext_ts = IGC_N_EXTTS;
943 		adapter->ptp_caps.n_per_out = IGC_N_PEROUT;
944 		adapter->ptp_caps.n_pins = IGC_N_SDP;
945 		adapter->ptp_caps.verify = igc_ptp_verify_pin;
946 
947 		if (!igc_is_crosststamp_supported(adapter))
948 			break;
949 
950 		adapter->ptp_caps.getcrosststamp = igc_ptp_getcrosststamp;
951 		break;
952 	default:
953 		adapter->ptp_clock = NULL;
954 		return;
955 	}
956 
957 	spin_lock_init(&adapter->tmreg_lock);
958 	INIT_WORK(&adapter->ptp_tx_work, igc_ptp_tx_work);
959 
960 	adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
961 	adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
962 
963 	adapter->prev_ptp_time = ktime_to_timespec64(ktime_get_real());
964 	adapter->ptp_reset_start = ktime_get();
965 
966 	adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
967 						&adapter->pdev->dev);
968 	if (IS_ERR(adapter->ptp_clock)) {
969 		adapter->ptp_clock = NULL;
970 		netdev_err(netdev, "ptp_clock_register failed\n");
971 	} else if (adapter->ptp_clock) {
972 		netdev_info(netdev, "PHC added\n");
973 		adapter->ptp_flags |= IGC_PTP_ENABLED;
974 	}
975 }
976 
977 static void igc_ptp_time_save(struct igc_adapter *adapter)
978 {
979 	igc_ptp_read(adapter, &adapter->prev_ptp_time);
980 	adapter->ptp_reset_start = ktime_get();
981 }
982 
983 static void igc_ptp_time_restore(struct igc_adapter *adapter)
984 {
985 	struct timespec64 ts = adapter->prev_ptp_time;
986 	ktime_t delta;
987 
988 	delta = ktime_sub(ktime_get(), adapter->ptp_reset_start);
989 
990 	timespec64_add_ns(&ts, ktime_to_ns(delta));
991 
992 	igc_ptp_write_i225(adapter, &ts);
993 }
994 
995 /**
996  * igc_ptp_suspend - Disable PTP work items and prepare for suspend
997  * @adapter: Board private structure
998  *
999  * This function stops the overflow check work and PTP Tx timestamp work, and
1000  * will prepare the device for OS suspend.
1001  */
1002 void igc_ptp_suspend(struct igc_adapter *adapter)
1003 {
1004 	if (!(adapter->ptp_flags & IGC_PTP_ENABLED))
1005 		return;
1006 
1007 	cancel_work_sync(&adapter->ptp_tx_work);
1008 	dev_kfree_skb_any(adapter->ptp_tx_skb);
1009 	adapter->ptp_tx_skb = NULL;
1010 	clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state);
1011 
1012 	if (pci_device_is_present(adapter->pdev))
1013 		igc_ptp_time_save(adapter);
1014 }
1015 
1016 /**
1017  * igc_ptp_stop - Disable PTP device and stop the overflow check.
1018  * @adapter: Board private structure.
1019  *
1020  * This function stops the PTP support and cancels the delayed work.
1021  **/
1022 void igc_ptp_stop(struct igc_adapter *adapter)
1023 {
1024 	igc_ptp_suspend(adapter);
1025 
1026 	if (adapter->ptp_clock) {
1027 		ptp_clock_unregister(adapter->ptp_clock);
1028 		netdev_info(adapter->netdev, "PHC removed\n");
1029 		adapter->ptp_flags &= ~IGC_PTP_ENABLED;
1030 	}
1031 }
1032 
1033 /**
1034  * igc_ptp_reset - Re-enable the adapter for PTP following a reset.
1035  * @adapter: Board private structure.
1036  *
1037  * This function handles the reset work required to re-enable the PTP device.
1038  **/
1039 void igc_ptp_reset(struct igc_adapter *adapter)
1040 {
1041 	struct igc_hw *hw = &adapter->hw;
1042 	u32 cycle_ctrl, ctrl;
1043 	unsigned long flags;
1044 	u32 timadj;
1045 
1046 	/* reset the tstamp_config */
1047 	igc_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1048 
1049 	spin_lock_irqsave(&adapter->tmreg_lock, flags);
1050 
1051 	switch (adapter->hw.mac.type) {
1052 	case igc_i225:
1053 		timadj = rd32(IGC_TIMADJ);
1054 		timadj |= IGC_TIMADJ_ADJUST_METH;
1055 		wr32(IGC_TIMADJ, timadj);
1056 
1057 		wr32(IGC_TSAUXC, 0x0);
1058 		wr32(IGC_TSSDP, 0x0);
1059 		wr32(IGC_TSIM,
1060 		     IGC_TSICR_INTERRUPTS |
1061 		     (adapter->pps_sys_wrap_on ? IGC_TSICR_SYS_WRAP : 0));
1062 		wr32(IGC_IMS, IGC_IMS_TS);
1063 
1064 		if (!igc_is_crosststamp_supported(adapter))
1065 			break;
1066 
1067 		wr32(IGC_PCIE_DIG_DELAY, IGC_PCIE_DIG_DELAY_DEFAULT);
1068 		wr32(IGC_PCIE_PHY_DELAY, IGC_PCIE_PHY_DELAY_DEFAULT);
1069 
1070 		cycle_ctrl = IGC_PTM_CYCLE_CTRL_CYC_TIME(IGC_PTM_CYC_TIME_DEFAULT);
1071 
1072 		wr32(IGC_PTM_CYCLE_CTRL, cycle_ctrl);
1073 
1074 		ctrl = IGC_PTM_CTRL_EN |
1075 			IGC_PTM_CTRL_START_NOW |
1076 			IGC_PTM_CTRL_SHRT_CYC(IGC_PTM_SHORT_CYC_DEFAULT) |
1077 			IGC_PTM_CTRL_PTM_TO(IGC_PTM_TIMEOUT_DEFAULT) |
1078 			IGC_PTM_CTRL_TRIG;
1079 
1080 		wr32(IGC_PTM_CTRL, ctrl);
1081 
1082 		/* Force the first cycle to run. */
1083 		wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID);
1084 
1085 		break;
1086 	default:
1087 		/* No work to do. */
1088 		goto out;
1089 	}
1090 
1091 	/* Re-initialize the timer. */
1092 	if (hw->mac.type == igc_i225) {
1093 		igc_ptp_time_restore(adapter);
1094 	} else {
1095 		timecounter_init(&adapter->tc, &adapter->cc,
1096 				 ktime_to_ns(ktime_get_real()));
1097 	}
1098 out:
1099 	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1100 
1101 	wrfl();
1102 }
1103