1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 Intel Corporation */ 3 4 #include "igc.h" 5 6 #include <linux/module.h> 7 #include <linux/device.h> 8 #include <linux/pci.h> 9 #include <linux/ptp_classify.h> 10 #include <linux/clocksource.h> 11 #include <linux/ktime.h> 12 #include <linux/delay.h> 13 #include <linux/iopoll.h> 14 15 #define INCVALUE_MASK 0x7fffffff 16 #define ISGN 0x80000000 17 18 #define IGC_PTP_TX_TIMEOUT (HZ * 15) 19 20 #define IGC_PTM_STAT_SLEEP 2 21 #define IGC_PTM_STAT_TIMEOUT 100 22 23 /* SYSTIM read access for I225 */ 24 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts) 25 { 26 struct igc_hw *hw = &adapter->hw; 27 u32 sec, nsec; 28 29 /* The timestamp is latched when SYSTIML is read. */ 30 nsec = rd32(IGC_SYSTIML); 31 sec = rd32(IGC_SYSTIMH); 32 33 ts->tv_sec = sec; 34 ts->tv_nsec = nsec; 35 } 36 37 static void igc_ptp_write_i225(struct igc_adapter *adapter, 38 const struct timespec64 *ts) 39 { 40 struct igc_hw *hw = &adapter->hw; 41 42 wr32(IGC_SYSTIML, ts->tv_nsec); 43 wr32(IGC_SYSTIMH, ts->tv_sec); 44 } 45 46 static int igc_ptp_adjfine_i225(struct ptp_clock_info *ptp, long scaled_ppm) 47 { 48 struct igc_adapter *igc = container_of(ptp, struct igc_adapter, 49 ptp_caps); 50 struct igc_hw *hw = &igc->hw; 51 int neg_adj = 0; 52 u64 rate; 53 u32 inca; 54 55 if (scaled_ppm < 0) { 56 neg_adj = 1; 57 scaled_ppm = -scaled_ppm; 58 } 59 rate = scaled_ppm; 60 rate <<= 14; 61 rate = div_u64(rate, 78125); 62 63 inca = rate & INCVALUE_MASK; 64 if (neg_adj) 65 inca |= ISGN; 66 67 wr32(IGC_TIMINCA, inca); 68 69 return 0; 70 } 71 72 static int igc_ptp_adjtime_i225(struct ptp_clock_info *ptp, s64 delta) 73 { 74 struct igc_adapter *igc = container_of(ptp, struct igc_adapter, 75 ptp_caps); 76 struct timespec64 now, then = ns_to_timespec64(delta); 77 unsigned long flags; 78 79 spin_lock_irqsave(&igc->tmreg_lock, flags); 80 81 igc_ptp_read(igc, &now); 82 now = timespec64_add(now, then); 83 igc_ptp_write_i225(igc, (const struct timespec64 *)&now); 84 85 spin_unlock_irqrestore(&igc->tmreg_lock, flags); 86 87 return 0; 88 } 89 90 static int igc_ptp_gettimex64_i225(struct ptp_clock_info *ptp, 91 struct timespec64 *ts, 92 struct ptp_system_timestamp *sts) 93 { 94 struct igc_adapter *igc = container_of(ptp, struct igc_adapter, 95 ptp_caps); 96 struct igc_hw *hw = &igc->hw; 97 unsigned long flags; 98 99 spin_lock_irqsave(&igc->tmreg_lock, flags); 100 101 ptp_read_system_prets(sts); 102 ts->tv_nsec = rd32(IGC_SYSTIML); 103 ts->tv_sec = rd32(IGC_SYSTIMH); 104 ptp_read_system_postts(sts); 105 106 spin_unlock_irqrestore(&igc->tmreg_lock, flags); 107 108 return 0; 109 } 110 111 static int igc_ptp_settime_i225(struct ptp_clock_info *ptp, 112 const struct timespec64 *ts) 113 { 114 struct igc_adapter *igc = container_of(ptp, struct igc_adapter, 115 ptp_caps); 116 unsigned long flags; 117 118 spin_lock_irqsave(&igc->tmreg_lock, flags); 119 120 igc_ptp_write_i225(igc, ts); 121 122 spin_unlock_irqrestore(&igc->tmreg_lock, flags); 123 124 return 0; 125 } 126 127 static void igc_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext) 128 { 129 u32 *ptr = pin < 2 ? ctrl : ctrl_ext; 130 static const u32 mask[IGC_N_SDP] = { 131 IGC_CTRL_SDP0_DIR, 132 IGC_CTRL_SDP1_DIR, 133 IGC_CTRL_EXT_SDP2_DIR, 134 IGC_CTRL_EXT_SDP3_DIR, 135 }; 136 137 if (input) 138 *ptr &= ~mask[pin]; 139 else 140 *ptr |= mask[pin]; 141 } 142 143 static void igc_pin_perout(struct igc_adapter *igc, int chan, int pin, int freq) 144 { 145 static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = { 146 IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3, 147 }; 148 static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = { 149 IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3, 150 }; 151 static const u32 igc_ts_sdp_en[IGC_N_SDP] = { 152 IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN, 153 }; 154 static const u32 igc_ts_sdp_sel_tt0[IGC_N_SDP] = { 155 IGC_TS_SDP0_SEL_TT0, IGC_TS_SDP1_SEL_TT0, 156 IGC_TS_SDP2_SEL_TT0, IGC_TS_SDP3_SEL_TT0, 157 }; 158 static const u32 igc_ts_sdp_sel_tt1[IGC_N_SDP] = { 159 IGC_TS_SDP0_SEL_TT1, IGC_TS_SDP1_SEL_TT1, 160 IGC_TS_SDP2_SEL_TT1, IGC_TS_SDP3_SEL_TT1, 161 }; 162 static const u32 igc_ts_sdp_sel_fc0[IGC_N_SDP] = { 163 IGC_TS_SDP0_SEL_FC0, IGC_TS_SDP1_SEL_FC0, 164 IGC_TS_SDP2_SEL_FC0, IGC_TS_SDP3_SEL_FC0, 165 }; 166 static const u32 igc_ts_sdp_sel_fc1[IGC_N_SDP] = { 167 IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1, 168 IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1, 169 }; 170 static const u32 igc_ts_sdp_sel_clr[IGC_N_SDP] = { 171 IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1, 172 IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1, 173 }; 174 struct igc_hw *hw = &igc->hw; 175 u32 ctrl, ctrl_ext, tssdp = 0; 176 177 ctrl = rd32(IGC_CTRL); 178 ctrl_ext = rd32(IGC_CTRL_EXT); 179 tssdp = rd32(IGC_TSSDP); 180 181 igc_pin_direction(pin, 0, &ctrl, &ctrl_ext); 182 183 /* Make sure this pin is not enabled as an input. */ 184 if ((tssdp & IGC_AUX0_SEL_SDP3) == igc_aux0_sel_sdp[pin]) 185 tssdp &= ~IGC_AUX0_TS_SDP_EN; 186 187 if ((tssdp & IGC_AUX1_SEL_SDP3) == igc_aux1_sel_sdp[pin]) 188 tssdp &= ~IGC_AUX1_TS_SDP_EN; 189 190 tssdp &= ~igc_ts_sdp_sel_clr[pin]; 191 if (freq) { 192 if (chan == 1) 193 tssdp |= igc_ts_sdp_sel_fc1[pin]; 194 else 195 tssdp |= igc_ts_sdp_sel_fc0[pin]; 196 } else { 197 if (chan == 1) 198 tssdp |= igc_ts_sdp_sel_tt1[pin]; 199 else 200 tssdp |= igc_ts_sdp_sel_tt0[pin]; 201 } 202 tssdp |= igc_ts_sdp_en[pin]; 203 204 wr32(IGC_TSSDP, tssdp); 205 wr32(IGC_CTRL, ctrl); 206 wr32(IGC_CTRL_EXT, ctrl_ext); 207 } 208 209 static void igc_pin_extts(struct igc_adapter *igc, int chan, int pin) 210 { 211 static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = { 212 IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3, 213 }; 214 static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = { 215 IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3, 216 }; 217 static const u32 igc_ts_sdp_en[IGC_N_SDP] = { 218 IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN, 219 }; 220 struct igc_hw *hw = &igc->hw; 221 u32 ctrl, ctrl_ext, tssdp = 0; 222 223 ctrl = rd32(IGC_CTRL); 224 ctrl_ext = rd32(IGC_CTRL_EXT); 225 tssdp = rd32(IGC_TSSDP); 226 227 igc_pin_direction(pin, 1, &ctrl, &ctrl_ext); 228 229 /* Make sure this pin is not enabled as an output. */ 230 tssdp &= ~igc_ts_sdp_en[pin]; 231 232 if (chan == 1) { 233 tssdp &= ~IGC_AUX1_SEL_SDP3; 234 tssdp |= igc_aux1_sel_sdp[pin] | IGC_AUX1_TS_SDP_EN; 235 } else { 236 tssdp &= ~IGC_AUX0_SEL_SDP3; 237 tssdp |= igc_aux0_sel_sdp[pin] | IGC_AUX0_TS_SDP_EN; 238 } 239 240 wr32(IGC_TSSDP, tssdp); 241 wr32(IGC_CTRL, ctrl); 242 wr32(IGC_CTRL_EXT, ctrl_ext); 243 } 244 245 static int igc_ptp_feature_enable_i225(struct ptp_clock_info *ptp, 246 struct ptp_clock_request *rq, int on) 247 { 248 struct igc_adapter *igc = 249 container_of(ptp, struct igc_adapter, ptp_caps); 250 struct igc_hw *hw = &igc->hw; 251 unsigned long flags; 252 struct timespec64 ts; 253 int use_freq = 0, pin = -1; 254 u32 tsim, tsauxc, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout; 255 s64 ns; 256 257 switch (rq->type) { 258 case PTP_CLK_REQ_EXTTS: 259 /* Reject requests with unsupported flags */ 260 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | 261 PTP_RISING_EDGE | 262 PTP_FALLING_EDGE | 263 PTP_STRICT_FLAGS)) 264 return -EOPNOTSUPP; 265 266 /* Reject requests failing to enable both edges. */ 267 if ((rq->extts.flags & PTP_STRICT_FLAGS) && 268 (rq->extts.flags & PTP_ENABLE_FEATURE) && 269 (rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES) 270 return -EOPNOTSUPP; 271 272 if (on) { 273 pin = ptp_find_pin(igc->ptp_clock, PTP_PF_EXTTS, 274 rq->extts.index); 275 if (pin < 0) 276 return -EBUSY; 277 } 278 if (rq->extts.index == 1) { 279 tsauxc_mask = IGC_TSAUXC_EN_TS1; 280 tsim_mask = IGC_TSICR_AUTT1; 281 } else { 282 tsauxc_mask = IGC_TSAUXC_EN_TS0; 283 tsim_mask = IGC_TSICR_AUTT0; 284 } 285 spin_lock_irqsave(&igc->tmreg_lock, flags); 286 tsauxc = rd32(IGC_TSAUXC); 287 tsim = rd32(IGC_TSIM); 288 if (on) { 289 igc_pin_extts(igc, rq->extts.index, pin); 290 tsauxc |= tsauxc_mask; 291 tsim |= tsim_mask; 292 } else { 293 tsauxc &= ~tsauxc_mask; 294 tsim &= ~tsim_mask; 295 } 296 wr32(IGC_TSAUXC, tsauxc); 297 wr32(IGC_TSIM, tsim); 298 spin_unlock_irqrestore(&igc->tmreg_lock, flags); 299 return 0; 300 301 case PTP_CLK_REQ_PEROUT: 302 /* Reject requests with unsupported flags */ 303 if (rq->perout.flags) 304 return -EOPNOTSUPP; 305 306 if (on) { 307 pin = ptp_find_pin(igc->ptp_clock, PTP_PF_PEROUT, 308 rq->perout.index); 309 if (pin < 0) 310 return -EBUSY; 311 } 312 ts.tv_sec = rq->perout.period.sec; 313 ts.tv_nsec = rq->perout.period.nsec; 314 ns = timespec64_to_ns(&ts); 315 ns = ns >> 1; 316 if (on && (ns <= 70000000LL || ns == 125000000LL || 317 ns == 250000000LL || ns == 500000000LL)) { 318 if (ns < 8LL) 319 return -EINVAL; 320 use_freq = 1; 321 } 322 ts = ns_to_timespec64(ns); 323 if (rq->perout.index == 1) { 324 if (use_freq) { 325 tsauxc_mask = IGC_TSAUXC_EN_CLK1; 326 tsim_mask = 0; 327 } else { 328 tsauxc_mask = IGC_TSAUXC_EN_TT1; 329 tsim_mask = IGC_TSICR_TT1; 330 } 331 trgttiml = IGC_TRGTTIML1; 332 trgttimh = IGC_TRGTTIMH1; 333 freqout = IGC_FREQOUT1; 334 } else { 335 if (use_freq) { 336 tsauxc_mask = IGC_TSAUXC_EN_CLK0; 337 tsim_mask = 0; 338 } else { 339 tsauxc_mask = IGC_TSAUXC_EN_TT0; 340 tsim_mask = IGC_TSICR_TT0; 341 } 342 trgttiml = IGC_TRGTTIML0; 343 trgttimh = IGC_TRGTTIMH0; 344 freqout = IGC_FREQOUT0; 345 } 346 spin_lock_irqsave(&igc->tmreg_lock, flags); 347 tsauxc = rd32(IGC_TSAUXC); 348 tsim = rd32(IGC_TSIM); 349 if (rq->perout.index == 1) { 350 tsauxc &= ~(IGC_TSAUXC_EN_TT1 | IGC_TSAUXC_EN_CLK1); 351 tsim &= ~IGC_TSICR_TT1; 352 } else { 353 tsauxc &= ~(IGC_TSAUXC_EN_TT0 | IGC_TSAUXC_EN_CLK0); 354 tsim &= ~IGC_TSICR_TT0; 355 } 356 if (on) { 357 int i = rq->perout.index; 358 359 igc_pin_perout(igc, i, pin, use_freq); 360 igc->perout[i].start.tv_sec = rq->perout.start.sec; 361 igc->perout[i].start.tv_nsec = rq->perout.start.nsec; 362 igc->perout[i].period.tv_sec = ts.tv_sec; 363 igc->perout[i].period.tv_nsec = ts.tv_nsec; 364 wr32(trgttimh, rq->perout.start.sec); 365 /* For now, always select timer 0 as source. */ 366 wr32(trgttiml, rq->perout.start.nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0); 367 if (use_freq) 368 wr32(freqout, ns); 369 tsauxc |= tsauxc_mask; 370 tsim |= tsim_mask; 371 } 372 wr32(IGC_TSAUXC, tsauxc); 373 wr32(IGC_TSIM, tsim); 374 spin_unlock_irqrestore(&igc->tmreg_lock, flags); 375 return 0; 376 377 case PTP_CLK_REQ_PPS: 378 spin_lock_irqsave(&igc->tmreg_lock, flags); 379 tsim = rd32(IGC_TSIM); 380 if (on) 381 tsim |= IGC_TSICR_SYS_WRAP; 382 else 383 tsim &= ~IGC_TSICR_SYS_WRAP; 384 igc->pps_sys_wrap_on = on; 385 wr32(IGC_TSIM, tsim); 386 spin_unlock_irqrestore(&igc->tmreg_lock, flags); 387 return 0; 388 389 default: 390 break; 391 } 392 393 return -EOPNOTSUPP; 394 } 395 396 static int igc_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin, 397 enum ptp_pin_function func, unsigned int chan) 398 { 399 switch (func) { 400 case PTP_PF_NONE: 401 case PTP_PF_EXTTS: 402 case PTP_PF_PEROUT: 403 break; 404 case PTP_PF_PHYSYNC: 405 return -1; 406 } 407 return 0; 408 } 409 410 /** 411 * igc_ptp_systim_to_hwtstamp - convert system time value to HW timestamp 412 * @adapter: board private structure 413 * @hwtstamps: timestamp structure to update 414 * @systim: unsigned 64bit system time value 415 * 416 * We need to convert the system time value stored in the RX/TXSTMP registers 417 * into a hwtstamp which can be used by the upper level timestamping functions. 418 **/ 419 static void igc_ptp_systim_to_hwtstamp(struct igc_adapter *adapter, 420 struct skb_shared_hwtstamps *hwtstamps, 421 u64 systim) 422 { 423 switch (adapter->hw.mac.type) { 424 case igc_i225: 425 memset(hwtstamps, 0, sizeof(*hwtstamps)); 426 /* Upper 32 bits contain s, lower 32 bits contain ns. */ 427 hwtstamps->hwtstamp = ktime_set(systim >> 32, 428 systim & 0xFFFFFFFF); 429 break; 430 default: 431 break; 432 } 433 } 434 435 /** 436 * igc_ptp_rx_pktstamp - Retrieve timestamp from Rx packet buffer 437 * @adapter: Pointer to adapter the packet buffer belongs to 438 * @buf: Pointer to packet buffer 439 * 440 * This function retrieves the timestamp saved in the beginning of packet 441 * buffer. While two timestamps are available, one in timer0 reference and the 442 * other in timer1 reference, this function considers only the timestamp in 443 * timer0 reference. 444 * 445 * Returns timestamp value. 446 */ 447 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf) 448 { 449 ktime_t timestamp; 450 u32 secs, nsecs; 451 int adjust; 452 453 /* Timestamps are saved in little endian at the beginning of the packet 454 * buffer following the layout: 455 * 456 * DWORD: | 0 | 1 | 2 | 3 | 457 * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH | 458 * 459 * SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds 460 * part of the timestamp. 461 */ 462 nsecs = le32_to_cpu(buf[2]); 463 secs = le32_to_cpu(buf[3]); 464 465 timestamp = ktime_set(secs, nsecs); 466 467 /* Adjust timestamp for the RX latency based on link speed */ 468 switch (adapter->link_speed) { 469 case SPEED_10: 470 adjust = IGC_I225_RX_LATENCY_10; 471 break; 472 case SPEED_100: 473 adjust = IGC_I225_RX_LATENCY_100; 474 break; 475 case SPEED_1000: 476 adjust = IGC_I225_RX_LATENCY_1000; 477 break; 478 case SPEED_2500: 479 adjust = IGC_I225_RX_LATENCY_2500; 480 break; 481 default: 482 adjust = 0; 483 netdev_warn_once(adapter->netdev, "Imprecise timestamp\n"); 484 break; 485 } 486 487 return ktime_sub_ns(timestamp, adjust); 488 } 489 490 static void igc_ptp_disable_rx_timestamp(struct igc_adapter *adapter) 491 { 492 struct igc_hw *hw = &adapter->hw; 493 u32 val; 494 int i; 495 496 wr32(IGC_TSYNCRXCTL, 0); 497 498 for (i = 0; i < adapter->num_rx_queues; i++) { 499 val = rd32(IGC_SRRCTL(i)); 500 val &= ~IGC_SRRCTL_TIMESTAMP; 501 wr32(IGC_SRRCTL(i), val); 502 } 503 504 val = rd32(IGC_RXPBS); 505 val &= ~IGC_RXPBS_CFG_TS_EN; 506 wr32(IGC_RXPBS, val); 507 } 508 509 static void igc_ptp_enable_rx_timestamp(struct igc_adapter *adapter) 510 { 511 struct igc_hw *hw = &adapter->hw; 512 u32 val; 513 int i; 514 515 val = rd32(IGC_RXPBS); 516 val |= IGC_RXPBS_CFG_TS_EN; 517 wr32(IGC_RXPBS, val); 518 519 for (i = 0; i < adapter->num_rx_queues; i++) { 520 val = rd32(IGC_SRRCTL(i)); 521 /* FIXME: For now, only support retrieving RX timestamps from 522 * timer 0. 523 */ 524 val |= IGC_SRRCTL_TIMER1SEL(0) | IGC_SRRCTL_TIMER0SEL(0) | 525 IGC_SRRCTL_TIMESTAMP; 526 wr32(IGC_SRRCTL(i), val); 527 } 528 529 val = IGC_TSYNCRXCTL_ENABLED | IGC_TSYNCRXCTL_TYPE_ALL | 530 IGC_TSYNCRXCTL_RXSYNSIG; 531 wr32(IGC_TSYNCRXCTL, val); 532 } 533 534 static void igc_ptp_disable_tx_timestamp(struct igc_adapter *adapter) 535 { 536 struct igc_hw *hw = &adapter->hw; 537 538 wr32(IGC_TSYNCTXCTL, 0); 539 } 540 541 static void igc_ptp_enable_tx_timestamp(struct igc_adapter *adapter) 542 { 543 struct igc_hw *hw = &adapter->hw; 544 545 wr32(IGC_TSYNCTXCTL, IGC_TSYNCTXCTL_ENABLED | IGC_TSYNCTXCTL_TXSYNSIG); 546 547 /* Read TXSTMP registers to discard any timestamp previously stored. */ 548 rd32(IGC_TXSTMPL); 549 rd32(IGC_TXSTMPH); 550 } 551 552 /** 553 * igc_ptp_set_timestamp_mode - setup hardware for timestamping 554 * @adapter: networking device structure 555 * @config: hwtstamp configuration 556 * 557 * Return: 0 in case of success, negative errno code otherwise. 558 */ 559 static int igc_ptp_set_timestamp_mode(struct igc_adapter *adapter, 560 struct hwtstamp_config *config) 561 { 562 switch (config->tx_type) { 563 case HWTSTAMP_TX_OFF: 564 igc_ptp_disable_tx_timestamp(adapter); 565 break; 566 case HWTSTAMP_TX_ON: 567 igc_ptp_enable_tx_timestamp(adapter); 568 break; 569 default: 570 return -ERANGE; 571 } 572 573 switch (config->rx_filter) { 574 case HWTSTAMP_FILTER_NONE: 575 igc_ptp_disable_rx_timestamp(adapter); 576 break; 577 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 578 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 579 case HWTSTAMP_FILTER_PTP_V2_EVENT: 580 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 581 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 582 case HWTSTAMP_FILTER_PTP_V2_SYNC: 583 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 584 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 585 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 586 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 587 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 588 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 589 case HWTSTAMP_FILTER_NTP_ALL: 590 case HWTSTAMP_FILTER_ALL: 591 igc_ptp_enable_rx_timestamp(adapter); 592 config->rx_filter = HWTSTAMP_FILTER_ALL; 593 break; 594 default: 595 return -ERANGE; 596 } 597 598 return 0; 599 } 600 601 static void igc_ptp_tx_timeout(struct igc_adapter *adapter) 602 { 603 struct igc_hw *hw = &adapter->hw; 604 605 dev_kfree_skb_any(adapter->ptp_tx_skb); 606 adapter->ptp_tx_skb = NULL; 607 adapter->tx_hwtstamp_timeouts++; 608 clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state); 609 /* Clear the tx valid bit in TSYNCTXCTL register to enable interrupt. */ 610 rd32(IGC_TXSTMPH); 611 netdev_warn(adapter->netdev, "Tx timestamp timeout\n"); 612 } 613 614 void igc_ptp_tx_hang(struct igc_adapter *adapter) 615 { 616 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start + 617 IGC_PTP_TX_TIMEOUT); 618 619 if (!test_bit(__IGC_PTP_TX_IN_PROGRESS, &adapter->state)) 620 return; 621 622 /* If we haven't received a timestamp within the timeout, it is 623 * reasonable to assume that it will never occur, so we can unlock the 624 * timestamp bit when this occurs. 625 */ 626 if (timeout) { 627 cancel_work_sync(&adapter->ptp_tx_work); 628 igc_ptp_tx_timeout(adapter); 629 } 630 } 631 632 /** 633 * igc_ptp_tx_hwtstamp - utility function which checks for TX time stamp 634 * @adapter: Board private structure 635 * 636 * If we were asked to do hardware stamping and such a time stamp is 637 * available, then it must have been for this skb here because we only 638 * allow only one such packet into the queue. 639 */ 640 static void igc_ptp_tx_hwtstamp(struct igc_adapter *adapter) 641 { 642 struct sk_buff *skb = adapter->ptp_tx_skb; 643 struct skb_shared_hwtstamps shhwtstamps; 644 struct igc_hw *hw = &adapter->hw; 645 int adjust = 0; 646 u64 regval; 647 648 if (WARN_ON_ONCE(!skb)) 649 return; 650 651 regval = rd32(IGC_TXSTMPL); 652 regval |= (u64)rd32(IGC_TXSTMPH) << 32; 653 igc_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); 654 655 switch (adapter->link_speed) { 656 case SPEED_10: 657 adjust = IGC_I225_TX_LATENCY_10; 658 break; 659 case SPEED_100: 660 adjust = IGC_I225_TX_LATENCY_100; 661 break; 662 case SPEED_1000: 663 adjust = IGC_I225_TX_LATENCY_1000; 664 break; 665 case SPEED_2500: 666 adjust = IGC_I225_TX_LATENCY_2500; 667 break; 668 } 669 670 shhwtstamps.hwtstamp = 671 ktime_add_ns(shhwtstamps.hwtstamp, adjust); 672 673 /* Clear the lock early before calling skb_tstamp_tx so that 674 * applications are not woken up before the lock bit is clear. We use 675 * a copy of the skb pointer to ensure other threads can't change it 676 * while we're notifying the stack. 677 */ 678 adapter->ptp_tx_skb = NULL; 679 clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state); 680 681 /* Notify the stack and free the skb after we've unlocked */ 682 skb_tstamp_tx(skb, &shhwtstamps); 683 dev_kfree_skb_any(skb); 684 } 685 686 /** 687 * igc_ptp_tx_work 688 * @work: pointer to work struct 689 * 690 * This work function polls the TSYNCTXCTL valid bit to determine when a 691 * timestamp has been taken for the current stored skb. 692 */ 693 static void igc_ptp_tx_work(struct work_struct *work) 694 { 695 struct igc_adapter *adapter = container_of(work, struct igc_adapter, 696 ptp_tx_work); 697 struct igc_hw *hw = &adapter->hw; 698 u32 tsynctxctl; 699 700 if (!test_bit(__IGC_PTP_TX_IN_PROGRESS, &adapter->state)) 701 return; 702 703 tsynctxctl = rd32(IGC_TSYNCTXCTL); 704 if (WARN_ON_ONCE(!(tsynctxctl & IGC_TSYNCTXCTL_TXTT_0))) 705 return; 706 707 igc_ptp_tx_hwtstamp(adapter); 708 } 709 710 /** 711 * igc_ptp_set_ts_config - set hardware time stamping config 712 * @netdev: network interface device structure 713 * @ifr: interface request data 714 * 715 **/ 716 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr) 717 { 718 struct igc_adapter *adapter = netdev_priv(netdev); 719 struct hwtstamp_config config; 720 int err; 721 722 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 723 return -EFAULT; 724 725 err = igc_ptp_set_timestamp_mode(adapter, &config); 726 if (err) 727 return err; 728 729 /* save these settings for future reference */ 730 memcpy(&adapter->tstamp_config, &config, 731 sizeof(adapter->tstamp_config)); 732 733 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 734 -EFAULT : 0; 735 } 736 737 /** 738 * igc_ptp_get_ts_config - get hardware time stamping config 739 * @netdev: network interface device structure 740 * @ifr: interface request data 741 * 742 * Get the hwtstamp_config settings to return to the user. Rather than attempt 743 * to deconstruct the settings from the registers, just return a shadow copy 744 * of the last known settings. 745 **/ 746 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr) 747 { 748 struct igc_adapter *adapter = netdev_priv(netdev); 749 struct hwtstamp_config *config = &adapter->tstamp_config; 750 751 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 752 -EFAULT : 0; 753 } 754 755 /* The two conditions below must be met for cross timestamping via 756 * PCIe PTM: 757 * 758 * 1. We have an way to convert the timestamps in the PTM messages 759 * to something related to the system clocks (right now, only 760 * X86 systems with support for the Always Running Timer allow that); 761 * 762 * 2. We have PTM enabled in the path from the device to the PCIe root port. 763 */ 764 static bool igc_is_crosststamp_supported(struct igc_adapter *adapter) 765 { 766 if (!IS_ENABLED(CONFIG_X86_TSC)) 767 return false; 768 769 /* FIXME: it was noticed that enabling support for PCIe PTM in 770 * some i225-V models could cause lockups when bringing the 771 * interface up/down. There should be no downsides to 772 * disabling crosstimestamping support for i225-V, as it 773 * doesn't have any PTP support. That way we gain some time 774 * while root causing the issue. 775 */ 776 if (adapter->pdev->device == IGC_DEV_ID_I225_V) 777 return false; 778 779 return pcie_ptm_enabled(adapter->pdev); 780 } 781 782 static struct system_counterval_t igc_device_tstamp_to_system(u64 tstamp) 783 { 784 #if IS_ENABLED(CONFIG_X86_TSC) && !defined(CONFIG_UML) 785 return convert_art_ns_to_tsc(tstamp); 786 #else 787 return (struct system_counterval_t) { }; 788 #endif 789 } 790 791 static void igc_ptm_log_error(struct igc_adapter *adapter, u32 ptm_stat) 792 { 793 struct net_device *netdev = adapter->netdev; 794 795 switch (ptm_stat) { 796 case IGC_PTM_STAT_RET_ERR: 797 netdev_err(netdev, "PTM Error: Root port timeout\n"); 798 break; 799 case IGC_PTM_STAT_BAD_PTM_RES: 800 netdev_err(netdev, "PTM Error: Bad response, PTM Response Data expected\n"); 801 break; 802 case IGC_PTM_STAT_T4M1_OVFL: 803 netdev_err(netdev, "PTM Error: T4 minus T1 overflow\n"); 804 break; 805 case IGC_PTM_STAT_ADJUST_1ST: 806 netdev_err(netdev, "PTM Error: 1588 timer adjusted during first PTM cycle\n"); 807 break; 808 case IGC_PTM_STAT_ADJUST_CYC: 809 netdev_err(netdev, "PTM Error: 1588 timer adjusted during non-first PTM cycle\n"); 810 break; 811 default: 812 netdev_err(netdev, "PTM Error: Unknown error (%#x)\n", ptm_stat); 813 break; 814 } 815 } 816 817 static int igc_phc_get_syncdevicetime(ktime_t *device, 818 struct system_counterval_t *system, 819 void *ctx) 820 { 821 u32 stat, t2_curr_h, t2_curr_l, ctrl; 822 struct igc_adapter *adapter = ctx; 823 struct igc_hw *hw = &adapter->hw; 824 int err, count = 100; 825 ktime_t t1, t2_curr; 826 827 /* Get a snapshot of system clocks to use as historic value. */ 828 ktime_get_snapshot(&adapter->snapshot); 829 830 do { 831 /* Doing this in a loop because in the event of a 832 * badly timed (ha!) system clock adjustment, we may 833 * get PTM errors from the PCI root, but these errors 834 * are transitory. Repeating the process returns valid 835 * data eventually. 836 */ 837 838 /* To "manually" start the PTM cycle we need to clear and 839 * then set again the TRIG bit. 840 */ 841 ctrl = rd32(IGC_PTM_CTRL); 842 ctrl &= ~IGC_PTM_CTRL_TRIG; 843 wr32(IGC_PTM_CTRL, ctrl); 844 ctrl |= IGC_PTM_CTRL_TRIG; 845 wr32(IGC_PTM_CTRL, ctrl); 846 847 /* The cycle only starts "for real" when software notifies 848 * that it has read the registers, this is done by setting 849 * VALID bit. 850 */ 851 wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID); 852 853 err = readx_poll_timeout(rd32, IGC_PTM_STAT, stat, 854 stat, IGC_PTM_STAT_SLEEP, 855 IGC_PTM_STAT_TIMEOUT); 856 if (err < 0) { 857 netdev_err(adapter->netdev, "Timeout reading IGC_PTM_STAT register\n"); 858 return err; 859 } 860 861 if ((stat & IGC_PTM_STAT_VALID) == IGC_PTM_STAT_VALID) 862 break; 863 864 if (stat & ~IGC_PTM_STAT_VALID) { 865 /* An error occurred, log it. */ 866 igc_ptm_log_error(adapter, stat); 867 /* The STAT register is write-1-to-clear (W1C), 868 * so write the previous error status to clear it. 869 */ 870 wr32(IGC_PTM_STAT, stat); 871 continue; 872 } 873 } while (--count); 874 875 if (!count) { 876 netdev_err(adapter->netdev, "Exceeded number of tries for PTM cycle\n"); 877 return -ETIMEDOUT; 878 } 879 880 t1 = ktime_set(rd32(IGC_PTM_T1_TIM0_H), rd32(IGC_PTM_T1_TIM0_L)); 881 882 t2_curr_l = rd32(IGC_PTM_CURR_T2_L); 883 t2_curr_h = rd32(IGC_PTM_CURR_T2_H); 884 885 /* FIXME: When the register that tells the endianness of the 886 * PTM registers are implemented, check them here and add the 887 * appropriate conversion. 888 */ 889 t2_curr_h = swab32(t2_curr_h); 890 891 t2_curr = ((s64)t2_curr_h << 32 | t2_curr_l); 892 893 *device = t1; 894 *system = igc_device_tstamp_to_system(t2_curr); 895 896 return 0; 897 } 898 899 static int igc_ptp_getcrosststamp(struct ptp_clock_info *ptp, 900 struct system_device_crosststamp *cts) 901 { 902 struct igc_adapter *adapter = container_of(ptp, struct igc_adapter, 903 ptp_caps); 904 905 return get_device_system_crosststamp(igc_phc_get_syncdevicetime, 906 adapter, &adapter->snapshot, cts); 907 } 908 909 /** 910 * igc_ptp_init - Initialize PTP functionality 911 * @adapter: Board private structure 912 * 913 * This function is called at device probe to initialize the PTP 914 * functionality. 915 */ 916 void igc_ptp_init(struct igc_adapter *adapter) 917 { 918 struct net_device *netdev = adapter->netdev; 919 struct igc_hw *hw = &adapter->hw; 920 int i; 921 922 switch (hw->mac.type) { 923 case igc_i225: 924 for (i = 0; i < IGC_N_SDP; i++) { 925 struct ptp_pin_desc *ppd = &adapter->sdp_config[i]; 926 927 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i); 928 ppd->index = i; 929 ppd->func = PTP_PF_NONE; 930 } 931 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 932 adapter->ptp_caps.owner = THIS_MODULE; 933 adapter->ptp_caps.max_adj = 62499999; 934 adapter->ptp_caps.adjfine = igc_ptp_adjfine_i225; 935 adapter->ptp_caps.adjtime = igc_ptp_adjtime_i225; 936 adapter->ptp_caps.gettimex64 = igc_ptp_gettimex64_i225; 937 adapter->ptp_caps.settime64 = igc_ptp_settime_i225; 938 adapter->ptp_caps.enable = igc_ptp_feature_enable_i225; 939 adapter->ptp_caps.pps = 1; 940 adapter->ptp_caps.pin_config = adapter->sdp_config; 941 adapter->ptp_caps.n_ext_ts = IGC_N_EXTTS; 942 adapter->ptp_caps.n_per_out = IGC_N_PEROUT; 943 adapter->ptp_caps.n_pins = IGC_N_SDP; 944 adapter->ptp_caps.verify = igc_ptp_verify_pin; 945 946 if (!igc_is_crosststamp_supported(adapter)) 947 break; 948 949 adapter->ptp_caps.getcrosststamp = igc_ptp_getcrosststamp; 950 break; 951 default: 952 adapter->ptp_clock = NULL; 953 return; 954 } 955 956 spin_lock_init(&adapter->tmreg_lock); 957 INIT_WORK(&adapter->ptp_tx_work, igc_ptp_tx_work); 958 959 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 960 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 961 962 adapter->prev_ptp_time = ktime_to_timespec64(ktime_get_real()); 963 adapter->ptp_reset_start = ktime_get(); 964 965 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, 966 &adapter->pdev->dev); 967 if (IS_ERR(adapter->ptp_clock)) { 968 adapter->ptp_clock = NULL; 969 netdev_err(netdev, "ptp_clock_register failed\n"); 970 } else if (adapter->ptp_clock) { 971 netdev_info(netdev, "PHC added\n"); 972 adapter->ptp_flags |= IGC_PTP_ENABLED; 973 } 974 } 975 976 static void igc_ptp_time_save(struct igc_adapter *adapter) 977 { 978 igc_ptp_read(adapter, &adapter->prev_ptp_time); 979 adapter->ptp_reset_start = ktime_get(); 980 } 981 982 static void igc_ptp_time_restore(struct igc_adapter *adapter) 983 { 984 struct timespec64 ts = adapter->prev_ptp_time; 985 ktime_t delta; 986 987 delta = ktime_sub(ktime_get(), adapter->ptp_reset_start); 988 989 timespec64_add_ns(&ts, ktime_to_ns(delta)); 990 991 igc_ptp_write_i225(adapter, &ts); 992 } 993 994 static void igc_ptm_stop(struct igc_adapter *adapter) 995 { 996 struct igc_hw *hw = &adapter->hw; 997 u32 ctrl; 998 999 ctrl = rd32(IGC_PTM_CTRL); 1000 ctrl &= ~IGC_PTM_CTRL_EN; 1001 1002 wr32(IGC_PTM_CTRL, ctrl); 1003 } 1004 1005 /** 1006 * igc_ptp_suspend - Disable PTP work items and prepare for suspend 1007 * @adapter: Board private structure 1008 * 1009 * This function stops the overflow check work and PTP Tx timestamp work, and 1010 * will prepare the device for OS suspend. 1011 */ 1012 void igc_ptp_suspend(struct igc_adapter *adapter) 1013 { 1014 if (!(adapter->ptp_flags & IGC_PTP_ENABLED)) 1015 return; 1016 1017 cancel_work_sync(&adapter->ptp_tx_work); 1018 dev_kfree_skb_any(adapter->ptp_tx_skb); 1019 adapter->ptp_tx_skb = NULL; 1020 clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state); 1021 1022 if (pci_device_is_present(adapter->pdev)) { 1023 igc_ptp_time_save(adapter); 1024 igc_ptm_stop(adapter); 1025 } 1026 } 1027 1028 /** 1029 * igc_ptp_stop - Disable PTP device and stop the overflow check. 1030 * @adapter: Board private structure. 1031 * 1032 * This function stops the PTP support and cancels the delayed work. 1033 **/ 1034 void igc_ptp_stop(struct igc_adapter *adapter) 1035 { 1036 igc_ptp_suspend(adapter); 1037 1038 if (adapter->ptp_clock) { 1039 ptp_clock_unregister(adapter->ptp_clock); 1040 netdev_info(adapter->netdev, "PHC removed\n"); 1041 adapter->ptp_flags &= ~IGC_PTP_ENABLED; 1042 } 1043 } 1044 1045 /** 1046 * igc_ptp_reset - Re-enable the adapter for PTP following a reset. 1047 * @adapter: Board private structure. 1048 * 1049 * This function handles the reset work required to re-enable the PTP device. 1050 **/ 1051 void igc_ptp_reset(struct igc_adapter *adapter) 1052 { 1053 struct igc_hw *hw = &adapter->hw; 1054 u32 cycle_ctrl, ctrl; 1055 unsigned long flags; 1056 u32 timadj; 1057 1058 /* reset the tstamp_config */ 1059 igc_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config); 1060 1061 spin_lock_irqsave(&adapter->tmreg_lock, flags); 1062 1063 switch (adapter->hw.mac.type) { 1064 case igc_i225: 1065 timadj = rd32(IGC_TIMADJ); 1066 timadj |= IGC_TIMADJ_ADJUST_METH; 1067 wr32(IGC_TIMADJ, timadj); 1068 1069 wr32(IGC_TSAUXC, 0x0); 1070 wr32(IGC_TSSDP, 0x0); 1071 wr32(IGC_TSIM, 1072 IGC_TSICR_INTERRUPTS | 1073 (adapter->pps_sys_wrap_on ? IGC_TSICR_SYS_WRAP : 0)); 1074 wr32(IGC_IMS, IGC_IMS_TS); 1075 1076 if (!igc_is_crosststamp_supported(adapter)) 1077 break; 1078 1079 wr32(IGC_PCIE_DIG_DELAY, IGC_PCIE_DIG_DELAY_DEFAULT); 1080 wr32(IGC_PCIE_PHY_DELAY, IGC_PCIE_PHY_DELAY_DEFAULT); 1081 1082 cycle_ctrl = IGC_PTM_CYCLE_CTRL_CYC_TIME(IGC_PTM_CYC_TIME_DEFAULT); 1083 1084 wr32(IGC_PTM_CYCLE_CTRL, cycle_ctrl); 1085 1086 ctrl = IGC_PTM_CTRL_EN | 1087 IGC_PTM_CTRL_START_NOW | 1088 IGC_PTM_CTRL_SHRT_CYC(IGC_PTM_SHORT_CYC_DEFAULT) | 1089 IGC_PTM_CTRL_PTM_TO(IGC_PTM_TIMEOUT_DEFAULT) | 1090 IGC_PTM_CTRL_TRIG; 1091 1092 wr32(IGC_PTM_CTRL, ctrl); 1093 1094 /* Force the first cycle to run. */ 1095 wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID); 1096 1097 break; 1098 default: 1099 /* No work to do. */ 1100 goto out; 1101 } 1102 1103 /* Re-initialize the timer. */ 1104 if (hw->mac.type == igc_i225) { 1105 igc_ptp_time_restore(adapter); 1106 } else { 1107 timecounter_init(&adapter->tc, &adapter->cc, 1108 ktime_to_ns(ktime_get_real())); 1109 } 1110 out: 1111 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 1112 1113 wrfl(); 1114 } 1115