1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 Intel Corporation */ 3 4 #include "igc.h" 5 6 #include <linux/module.h> 7 #include <linux/device.h> 8 #include <linux/pci.h> 9 #include <linux/ptp_classify.h> 10 #include <linux/clocksource.h> 11 #include <linux/ktime.h> 12 #include <linux/delay.h> 13 #include <linux/iopoll.h> 14 15 #define INCVALUE_MASK 0x7fffffff 16 #define ISGN 0x80000000 17 18 #define IGC_PTP_TX_TIMEOUT (HZ * 15) 19 20 #define IGC_PTM_STAT_SLEEP 2 21 #define IGC_PTM_STAT_TIMEOUT 100 22 23 /* SYSTIM read access for I225 */ 24 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts) 25 { 26 struct igc_hw *hw = &adapter->hw; 27 u32 sec, nsec; 28 29 /* The timestamp is latched when SYSTIML is read. */ 30 nsec = rd32(IGC_SYSTIML); 31 sec = rd32(IGC_SYSTIMH); 32 33 ts->tv_sec = sec; 34 ts->tv_nsec = nsec; 35 } 36 37 static void igc_ptp_write_i225(struct igc_adapter *adapter, 38 const struct timespec64 *ts) 39 { 40 struct igc_hw *hw = &adapter->hw; 41 42 wr32(IGC_SYSTIML, ts->tv_nsec); 43 wr32(IGC_SYSTIMH, ts->tv_sec); 44 } 45 46 static int igc_ptp_adjfine_i225(struct ptp_clock_info *ptp, long scaled_ppm) 47 { 48 struct igc_adapter *igc = container_of(ptp, struct igc_adapter, 49 ptp_caps); 50 struct igc_hw *hw = &igc->hw; 51 int neg_adj = 0; 52 u64 rate; 53 u32 inca; 54 55 if (scaled_ppm < 0) { 56 neg_adj = 1; 57 scaled_ppm = -scaled_ppm; 58 } 59 rate = scaled_ppm; 60 rate <<= 14; 61 rate = div_u64(rate, 78125); 62 63 inca = rate & INCVALUE_MASK; 64 if (neg_adj) 65 inca |= ISGN; 66 67 wr32(IGC_TIMINCA, inca); 68 69 return 0; 70 } 71 72 static int igc_ptp_adjtime_i225(struct ptp_clock_info *ptp, s64 delta) 73 { 74 struct igc_adapter *igc = container_of(ptp, struct igc_adapter, 75 ptp_caps); 76 struct timespec64 now, then = ns_to_timespec64(delta); 77 unsigned long flags; 78 79 spin_lock_irqsave(&igc->tmreg_lock, flags); 80 81 igc_ptp_read(igc, &now); 82 now = timespec64_add(now, then); 83 igc_ptp_write_i225(igc, (const struct timespec64 *)&now); 84 85 spin_unlock_irqrestore(&igc->tmreg_lock, flags); 86 87 return 0; 88 } 89 90 static int igc_ptp_gettimex64_i225(struct ptp_clock_info *ptp, 91 struct timespec64 *ts, 92 struct ptp_system_timestamp *sts) 93 { 94 struct igc_adapter *igc = container_of(ptp, struct igc_adapter, 95 ptp_caps); 96 struct igc_hw *hw = &igc->hw; 97 unsigned long flags; 98 99 spin_lock_irqsave(&igc->tmreg_lock, flags); 100 101 ptp_read_system_prets(sts); 102 ts->tv_nsec = rd32(IGC_SYSTIML); 103 ts->tv_sec = rd32(IGC_SYSTIMH); 104 ptp_read_system_postts(sts); 105 106 spin_unlock_irqrestore(&igc->tmreg_lock, flags); 107 108 return 0; 109 } 110 111 static int igc_ptp_settime_i225(struct ptp_clock_info *ptp, 112 const struct timespec64 *ts) 113 { 114 struct igc_adapter *igc = container_of(ptp, struct igc_adapter, 115 ptp_caps); 116 unsigned long flags; 117 118 spin_lock_irqsave(&igc->tmreg_lock, flags); 119 120 igc_ptp_write_i225(igc, ts); 121 122 spin_unlock_irqrestore(&igc->tmreg_lock, flags); 123 124 return 0; 125 } 126 127 static void igc_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext) 128 { 129 u32 *ptr = pin < 2 ? ctrl : ctrl_ext; 130 static const u32 mask[IGC_N_SDP] = { 131 IGC_CTRL_SDP0_DIR, 132 IGC_CTRL_SDP1_DIR, 133 IGC_CTRL_EXT_SDP2_DIR, 134 IGC_CTRL_EXT_SDP3_DIR, 135 }; 136 137 if (input) 138 *ptr &= ~mask[pin]; 139 else 140 *ptr |= mask[pin]; 141 } 142 143 static void igc_pin_perout(struct igc_adapter *igc, int chan, int pin, int freq) 144 { 145 static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = { 146 IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3, 147 }; 148 static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = { 149 IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3, 150 }; 151 static const u32 igc_ts_sdp_en[IGC_N_SDP] = { 152 IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN, 153 }; 154 static const u32 igc_ts_sdp_sel_tt0[IGC_N_SDP] = { 155 IGC_TS_SDP0_SEL_TT0, IGC_TS_SDP1_SEL_TT0, 156 IGC_TS_SDP2_SEL_TT0, IGC_TS_SDP3_SEL_TT0, 157 }; 158 static const u32 igc_ts_sdp_sel_tt1[IGC_N_SDP] = { 159 IGC_TS_SDP0_SEL_TT1, IGC_TS_SDP1_SEL_TT1, 160 IGC_TS_SDP2_SEL_TT1, IGC_TS_SDP3_SEL_TT1, 161 }; 162 static const u32 igc_ts_sdp_sel_fc0[IGC_N_SDP] = { 163 IGC_TS_SDP0_SEL_FC0, IGC_TS_SDP1_SEL_FC0, 164 IGC_TS_SDP2_SEL_FC0, IGC_TS_SDP3_SEL_FC0, 165 }; 166 static const u32 igc_ts_sdp_sel_fc1[IGC_N_SDP] = { 167 IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1, 168 IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1, 169 }; 170 static const u32 igc_ts_sdp_sel_clr[IGC_N_SDP] = { 171 IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1, 172 IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1, 173 }; 174 struct igc_hw *hw = &igc->hw; 175 u32 ctrl, ctrl_ext, tssdp = 0; 176 177 ctrl = rd32(IGC_CTRL); 178 ctrl_ext = rd32(IGC_CTRL_EXT); 179 tssdp = rd32(IGC_TSSDP); 180 181 igc_pin_direction(pin, 0, &ctrl, &ctrl_ext); 182 183 /* Make sure this pin is not enabled as an input. */ 184 if ((tssdp & IGC_AUX0_SEL_SDP3) == igc_aux0_sel_sdp[pin]) 185 tssdp &= ~IGC_AUX0_TS_SDP_EN; 186 187 if ((tssdp & IGC_AUX1_SEL_SDP3) == igc_aux1_sel_sdp[pin]) 188 tssdp &= ~IGC_AUX1_TS_SDP_EN; 189 190 tssdp &= ~igc_ts_sdp_sel_clr[pin]; 191 if (freq) { 192 if (chan == 1) 193 tssdp |= igc_ts_sdp_sel_fc1[pin]; 194 else 195 tssdp |= igc_ts_sdp_sel_fc0[pin]; 196 } else { 197 if (chan == 1) 198 tssdp |= igc_ts_sdp_sel_tt1[pin]; 199 else 200 tssdp |= igc_ts_sdp_sel_tt0[pin]; 201 } 202 tssdp |= igc_ts_sdp_en[pin]; 203 204 wr32(IGC_TSSDP, tssdp); 205 wr32(IGC_CTRL, ctrl); 206 wr32(IGC_CTRL_EXT, ctrl_ext); 207 } 208 209 static void igc_pin_extts(struct igc_adapter *igc, int chan, int pin) 210 { 211 static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = { 212 IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3, 213 }; 214 static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = { 215 IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3, 216 }; 217 static const u32 igc_ts_sdp_en[IGC_N_SDP] = { 218 IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN, 219 }; 220 struct igc_hw *hw = &igc->hw; 221 u32 ctrl, ctrl_ext, tssdp = 0; 222 223 ctrl = rd32(IGC_CTRL); 224 ctrl_ext = rd32(IGC_CTRL_EXT); 225 tssdp = rd32(IGC_TSSDP); 226 227 igc_pin_direction(pin, 1, &ctrl, &ctrl_ext); 228 229 /* Make sure this pin is not enabled as an output. */ 230 tssdp &= ~igc_ts_sdp_en[pin]; 231 232 if (chan == 1) { 233 tssdp &= ~IGC_AUX1_SEL_SDP3; 234 tssdp |= igc_aux1_sel_sdp[pin] | IGC_AUX1_TS_SDP_EN; 235 } else { 236 tssdp &= ~IGC_AUX0_SEL_SDP3; 237 tssdp |= igc_aux0_sel_sdp[pin] | IGC_AUX0_TS_SDP_EN; 238 } 239 240 wr32(IGC_TSSDP, tssdp); 241 wr32(IGC_CTRL, ctrl); 242 wr32(IGC_CTRL_EXT, ctrl_ext); 243 } 244 245 static int igc_ptp_feature_enable_i225(struct ptp_clock_info *ptp, 246 struct ptp_clock_request *rq, int on) 247 { 248 struct igc_adapter *igc = 249 container_of(ptp, struct igc_adapter, ptp_caps); 250 struct igc_hw *hw = &igc->hw; 251 unsigned long flags; 252 struct timespec64 ts; 253 int use_freq = 0, pin = -1; 254 u32 tsim, tsauxc, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout; 255 s64 ns; 256 257 switch (rq->type) { 258 case PTP_CLK_REQ_EXTTS: 259 /* Reject requests with unsupported flags */ 260 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | 261 PTP_RISING_EDGE | 262 PTP_FALLING_EDGE | 263 PTP_STRICT_FLAGS)) 264 return -EOPNOTSUPP; 265 266 /* Reject requests failing to enable both edges. */ 267 if ((rq->extts.flags & PTP_STRICT_FLAGS) && 268 (rq->extts.flags & PTP_ENABLE_FEATURE) && 269 (rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES) 270 return -EOPNOTSUPP; 271 272 if (on) { 273 pin = ptp_find_pin(igc->ptp_clock, PTP_PF_EXTTS, 274 rq->extts.index); 275 if (pin < 0) 276 return -EBUSY; 277 } 278 if (rq->extts.index == 1) { 279 tsauxc_mask = IGC_TSAUXC_EN_TS1; 280 tsim_mask = IGC_TSICR_AUTT1; 281 } else { 282 tsauxc_mask = IGC_TSAUXC_EN_TS0; 283 tsim_mask = IGC_TSICR_AUTT0; 284 } 285 spin_lock_irqsave(&igc->tmreg_lock, flags); 286 tsauxc = rd32(IGC_TSAUXC); 287 tsim = rd32(IGC_TSIM); 288 if (on) { 289 igc_pin_extts(igc, rq->extts.index, pin); 290 tsauxc |= tsauxc_mask; 291 tsim |= tsim_mask; 292 } else { 293 tsauxc &= ~tsauxc_mask; 294 tsim &= ~tsim_mask; 295 } 296 wr32(IGC_TSAUXC, tsauxc); 297 wr32(IGC_TSIM, tsim); 298 spin_unlock_irqrestore(&igc->tmreg_lock, flags); 299 return 0; 300 301 case PTP_CLK_REQ_PEROUT: 302 /* Reject requests with unsupported flags */ 303 if (rq->perout.flags) 304 return -EOPNOTSUPP; 305 306 if (on) { 307 pin = ptp_find_pin(igc->ptp_clock, PTP_PF_PEROUT, 308 rq->perout.index); 309 if (pin < 0) 310 return -EBUSY; 311 } 312 ts.tv_sec = rq->perout.period.sec; 313 ts.tv_nsec = rq->perout.period.nsec; 314 ns = timespec64_to_ns(&ts); 315 ns = ns >> 1; 316 if (on && (ns <= 70000000LL || ns == 125000000LL || 317 ns == 250000000LL || ns == 500000000LL)) { 318 if (ns < 8LL) 319 return -EINVAL; 320 use_freq = 1; 321 } 322 ts = ns_to_timespec64(ns); 323 if (rq->perout.index == 1) { 324 if (use_freq) { 325 tsauxc_mask = IGC_TSAUXC_EN_CLK1 | IGC_TSAUXC_ST1; 326 tsim_mask = 0; 327 } else { 328 tsauxc_mask = IGC_TSAUXC_EN_TT1; 329 tsim_mask = IGC_TSICR_TT1; 330 } 331 trgttiml = IGC_TRGTTIML1; 332 trgttimh = IGC_TRGTTIMH1; 333 freqout = IGC_FREQOUT1; 334 } else { 335 if (use_freq) { 336 tsauxc_mask = IGC_TSAUXC_EN_CLK0 | IGC_TSAUXC_ST0; 337 tsim_mask = 0; 338 } else { 339 tsauxc_mask = IGC_TSAUXC_EN_TT0; 340 tsim_mask = IGC_TSICR_TT0; 341 } 342 trgttiml = IGC_TRGTTIML0; 343 trgttimh = IGC_TRGTTIMH0; 344 freqout = IGC_FREQOUT0; 345 } 346 spin_lock_irqsave(&igc->tmreg_lock, flags); 347 tsauxc = rd32(IGC_TSAUXC); 348 tsim = rd32(IGC_TSIM); 349 if (rq->perout.index == 1) { 350 tsauxc &= ~(IGC_TSAUXC_EN_TT1 | IGC_TSAUXC_EN_CLK1 | 351 IGC_TSAUXC_ST1); 352 tsim &= ~IGC_TSICR_TT1; 353 } else { 354 tsauxc &= ~(IGC_TSAUXC_EN_TT0 | IGC_TSAUXC_EN_CLK0 | 355 IGC_TSAUXC_ST0); 356 tsim &= ~IGC_TSICR_TT0; 357 } 358 if (on) { 359 struct timespec64 safe_start; 360 int i = rq->perout.index; 361 362 igc_pin_perout(igc, i, pin, use_freq); 363 igc_ptp_read(igc, &safe_start); 364 365 /* PPS output start time is triggered by Target time(TT) 366 * register. Programming any past time value into TT 367 * register will cause PPS to never start. Need to make 368 * sure we program the TT register a time ahead in 369 * future. There isn't a stringent need to fire PPS out 370 * right away. Adding +2 seconds should take care of 371 * corner cases. Let's say if the SYSTIML is close to 372 * wrap up and the timer keeps ticking as we program the 373 * register, adding +2seconds is safe bet. 374 */ 375 safe_start.tv_sec += 2; 376 377 if (rq->perout.start.sec < safe_start.tv_sec) 378 igc->perout[i].start.tv_sec = safe_start.tv_sec; 379 else 380 igc->perout[i].start.tv_sec = rq->perout.start.sec; 381 igc->perout[i].start.tv_nsec = rq->perout.start.nsec; 382 igc->perout[i].period.tv_sec = ts.tv_sec; 383 igc->perout[i].period.tv_nsec = ts.tv_nsec; 384 wr32(trgttimh, (u32)igc->perout[i].start.tv_sec); 385 /* For now, always select timer 0 as source. */ 386 wr32(trgttiml, (u32)(igc->perout[i].start.tv_nsec | 387 IGC_TT_IO_TIMER_SEL_SYSTIM0)); 388 if (use_freq) 389 wr32(freqout, ns); 390 tsauxc |= tsauxc_mask; 391 tsim |= tsim_mask; 392 } 393 wr32(IGC_TSAUXC, tsauxc); 394 wr32(IGC_TSIM, tsim); 395 spin_unlock_irqrestore(&igc->tmreg_lock, flags); 396 return 0; 397 398 case PTP_CLK_REQ_PPS: 399 spin_lock_irqsave(&igc->tmreg_lock, flags); 400 tsim = rd32(IGC_TSIM); 401 if (on) 402 tsim |= IGC_TSICR_SYS_WRAP; 403 else 404 tsim &= ~IGC_TSICR_SYS_WRAP; 405 igc->pps_sys_wrap_on = on; 406 wr32(IGC_TSIM, tsim); 407 spin_unlock_irqrestore(&igc->tmreg_lock, flags); 408 return 0; 409 410 default: 411 break; 412 } 413 414 return -EOPNOTSUPP; 415 } 416 417 static int igc_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin, 418 enum ptp_pin_function func, unsigned int chan) 419 { 420 switch (func) { 421 case PTP_PF_NONE: 422 case PTP_PF_EXTTS: 423 case PTP_PF_PEROUT: 424 break; 425 case PTP_PF_PHYSYNC: 426 return -1; 427 } 428 return 0; 429 } 430 431 /** 432 * igc_ptp_systim_to_hwtstamp - convert system time value to HW timestamp 433 * @adapter: board private structure 434 * @hwtstamps: timestamp structure to update 435 * @systim: unsigned 64bit system time value 436 * 437 * We need to convert the system time value stored in the RX/TXSTMP registers 438 * into a hwtstamp which can be used by the upper level timestamping functions. 439 * 440 * Returns 0 on success. 441 **/ 442 static int igc_ptp_systim_to_hwtstamp(struct igc_adapter *adapter, 443 struct skb_shared_hwtstamps *hwtstamps, 444 u64 systim) 445 { 446 switch (adapter->hw.mac.type) { 447 case igc_i225: 448 memset(hwtstamps, 0, sizeof(*hwtstamps)); 449 /* Upper 32 bits contain s, lower 32 bits contain ns. */ 450 hwtstamps->hwtstamp = ktime_set(systim >> 32, 451 systim & 0xFFFFFFFF); 452 break; 453 default: 454 return -EINVAL; 455 } 456 return 0; 457 } 458 459 /** 460 * igc_ptp_rx_pktstamp - Retrieve timestamp from Rx packet buffer 461 * @adapter: Pointer to adapter the packet buffer belongs to 462 * @buf: Pointer to packet buffer 463 * 464 * This function retrieves the timestamp saved in the beginning of packet 465 * buffer. While two timestamps are available, one in timer0 reference and the 466 * other in timer1 reference, this function considers only the timestamp in 467 * timer0 reference. 468 * 469 * Returns timestamp value. 470 */ 471 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf) 472 { 473 ktime_t timestamp; 474 u32 secs, nsecs; 475 int adjust; 476 477 /* Timestamps are saved in little endian at the beginning of the packet 478 * buffer following the layout: 479 * 480 * DWORD: | 0 | 1 | 2 | 3 | 481 * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH | 482 * 483 * SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds 484 * part of the timestamp. 485 */ 486 nsecs = le32_to_cpu(buf[2]); 487 secs = le32_to_cpu(buf[3]); 488 489 timestamp = ktime_set(secs, nsecs); 490 491 /* Adjust timestamp for the RX latency based on link speed */ 492 switch (adapter->link_speed) { 493 case SPEED_10: 494 adjust = IGC_I225_RX_LATENCY_10; 495 break; 496 case SPEED_100: 497 adjust = IGC_I225_RX_LATENCY_100; 498 break; 499 case SPEED_1000: 500 adjust = IGC_I225_RX_LATENCY_1000; 501 break; 502 case SPEED_2500: 503 adjust = IGC_I225_RX_LATENCY_2500; 504 break; 505 default: 506 adjust = 0; 507 netdev_warn_once(adapter->netdev, "Imprecise timestamp\n"); 508 break; 509 } 510 511 return ktime_sub_ns(timestamp, adjust); 512 } 513 514 static void igc_ptp_disable_rx_timestamp(struct igc_adapter *adapter) 515 { 516 struct igc_hw *hw = &adapter->hw; 517 u32 val; 518 int i; 519 520 wr32(IGC_TSYNCRXCTL, 0); 521 522 for (i = 0; i < adapter->num_rx_queues; i++) { 523 val = rd32(IGC_SRRCTL(i)); 524 val &= ~IGC_SRRCTL_TIMESTAMP; 525 wr32(IGC_SRRCTL(i), val); 526 } 527 528 val = rd32(IGC_RXPBS); 529 val &= ~IGC_RXPBS_CFG_TS_EN; 530 wr32(IGC_RXPBS, val); 531 } 532 533 static void igc_ptp_enable_rx_timestamp(struct igc_adapter *adapter) 534 { 535 struct igc_hw *hw = &adapter->hw; 536 u32 val; 537 int i; 538 539 val = rd32(IGC_RXPBS); 540 val |= IGC_RXPBS_CFG_TS_EN; 541 wr32(IGC_RXPBS, val); 542 543 for (i = 0; i < adapter->num_rx_queues; i++) { 544 val = rd32(IGC_SRRCTL(i)); 545 /* FIXME: For now, only support retrieving RX timestamps from 546 * timer 0. 547 */ 548 val |= IGC_SRRCTL_TIMER1SEL(0) | IGC_SRRCTL_TIMER0SEL(0) | 549 IGC_SRRCTL_TIMESTAMP; 550 wr32(IGC_SRRCTL(i), val); 551 } 552 553 val = IGC_TSYNCRXCTL_ENABLED | IGC_TSYNCRXCTL_TYPE_ALL | 554 IGC_TSYNCRXCTL_RXSYNSIG; 555 wr32(IGC_TSYNCRXCTL, val); 556 } 557 558 static void igc_ptp_clear_tx_tstamp(struct igc_adapter *adapter) 559 { 560 unsigned long flags; 561 562 spin_lock_irqsave(&adapter->ptp_tx_lock, flags); 563 564 dev_kfree_skb_any(adapter->ptp_tx_skb); 565 adapter->ptp_tx_skb = NULL; 566 567 spin_unlock_irqrestore(&adapter->ptp_tx_lock, flags); 568 } 569 570 static void igc_ptp_disable_tx_timestamp(struct igc_adapter *adapter) 571 { 572 struct igc_hw *hw = &adapter->hw; 573 int i; 574 575 /* Clear the flags first to avoid new packets to be enqueued 576 * for TX timestamping. 577 */ 578 for (i = 0; i < adapter->num_tx_queues; i++) { 579 struct igc_ring *tx_ring = adapter->tx_ring[i]; 580 581 clear_bit(IGC_RING_FLAG_TX_HWTSTAMP, &tx_ring->flags); 582 } 583 584 /* Now we can clean the pending TX timestamp requests. */ 585 igc_ptp_clear_tx_tstamp(adapter); 586 587 wr32(IGC_TSYNCTXCTL, 0); 588 } 589 590 static void igc_ptp_enable_tx_timestamp(struct igc_adapter *adapter) 591 { 592 struct igc_hw *hw = &adapter->hw; 593 int i; 594 595 wr32(IGC_TSYNCTXCTL, IGC_TSYNCTXCTL_ENABLED | IGC_TSYNCTXCTL_TXSYNSIG); 596 597 /* Read TXSTMP registers to discard any timestamp previously stored. */ 598 rd32(IGC_TXSTMPL); 599 rd32(IGC_TXSTMPH); 600 601 /* The hardware is ready to accept TX timestamp requests, 602 * notify the transmit path. 603 */ 604 for (i = 0; i < adapter->num_tx_queues; i++) { 605 struct igc_ring *tx_ring = adapter->tx_ring[i]; 606 607 set_bit(IGC_RING_FLAG_TX_HWTSTAMP, &tx_ring->flags); 608 } 609 610 } 611 612 /** 613 * igc_ptp_set_timestamp_mode - setup hardware for timestamping 614 * @adapter: networking device structure 615 * @config: hwtstamp configuration 616 * 617 * Return: 0 in case of success, negative errno code otherwise. 618 */ 619 static int igc_ptp_set_timestamp_mode(struct igc_adapter *adapter, 620 struct hwtstamp_config *config) 621 { 622 switch (config->tx_type) { 623 case HWTSTAMP_TX_OFF: 624 igc_ptp_disable_tx_timestamp(adapter); 625 break; 626 case HWTSTAMP_TX_ON: 627 igc_ptp_enable_tx_timestamp(adapter); 628 break; 629 default: 630 return -ERANGE; 631 } 632 633 switch (config->rx_filter) { 634 case HWTSTAMP_FILTER_NONE: 635 igc_ptp_disable_rx_timestamp(adapter); 636 break; 637 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 638 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 639 case HWTSTAMP_FILTER_PTP_V2_EVENT: 640 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 641 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 642 case HWTSTAMP_FILTER_PTP_V2_SYNC: 643 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 644 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 645 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 646 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 647 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 648 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 649 case HWTSTAMP_FILTER_NTP_ALL: 650 case HWTSTAMP_FILTER_ALL: 651 igc_ptp_enable_rx_timestamp(adapter); 652 config->rx_filter = HWTSTAMP_FILTER_ALL; 653 break; 654 default: 655 return -ERANGE; 656 } 657 658 return 0; 659 } 660 661 /* Requires adapter->ptp_tx_lock held by caller. */ 662 static void igc_ptp_tx_timeout(struct igc_adapter *adapter) 663 { 664 struct igc_hw *hw = &adapter->hw; 665 666 dev_kfree_skb_any(adapter->ptp_tx_skb); 667 adapter->ptp_tx_skb = NULL; 668 adapter->tx_hwtstamp_timeouts++; 669 /* Clear the tx valid bit in TSYNCTXCTL register to enable interrupt. */ 670 rd32(IGC_TXSTMPH); 671 netdev_warn(adapter->netdev, "Tx timestamp timeout\n"); 672 } 673 674 void igc_ptp_tx_hang(struct igc_adapter *adapter) 675 { 676 unsigned long flags; 677 678 spin_lock_irqsave(&adapter->ptp_tx_lock, flags); 679 680 if (!adapter->ptp_tx_skb) 681 goto unlock; 682 683 if (time_is_after_jiffies(adapter->ptp_tx_start + IGC_PTP_TX_TIMEOUT)) 684 goto unlock; 685 686 igc_ptp_tx_timeout(adapter); 687 688 unlock: 689 spin_unlock_irqrestore(&adapter->ptp_tx_lock, flags); 690 } 691 692 /** 693 * igc_ptp_tx_hwtstamp - utility function which checks for TX time stamp 694 * @adapter: Board private structure 695 * 696 * If we were asked to do hardware stamping and such a time stamp is 697 * available, then it must have been for this skb here because we only 698 * allow only one such packet into the queue. 699 * 700 * Context: Expects adapter->ptp_tx_lock to be held by caller. 701 */ 702 static void igc_ptp_tx_hwtstamp(struct igc_adapter *adapter) 703 { 704 struct sk_buff *skb = adapter->ptp_tx_skb; 705 struct skb_shared_hwtstamps shhwtstamps; 706 struct igc_hw *hw = &adapter->hw; 707 u32 tsynctxctl; 708 int adjust = 0; 709 u64 regval; 710 711 if (WARN_ON_ONCE(!skb)) 712 return; 713 714 tsynctxctl = rd32(IGC_TSYNCTXCTL); 715 tsynctxctl &= IGC_TSYNCTXCTL_TXTT_0; 716 if (tsynctxctl) { 717 regval = rd32(IGC_TXSTMPL); 718 regval |= (u64)rd32(IGC_TXSTMPH) << 32; 719 } else { 720 /* There's a bug in the hardware that could cause 721 * missing interrupts for TX timestamping. The issue 722 * is that for new interrupts to be triggered, the 723 * IGC_TXSTMPH_0 register must be read. 724 * 725 * To avoid discarding a valid timestamp that just 726 * happened at the "wrong" time, we need to confirm 727 * that there was no timestamp captured, we do that by 728 * assuming that no two timestamps in sequence have 729 * the same nanosecond value. 730 * 731 * So, we read the "low" register, read the "high" 732 * register (to latch a new timestamp) and read the 733 * "low" register again, if "old" and "new" versions 734 * of the "low" register are different, a valid 735 * timestamp was captured, we can read the "high" 736 * register again. 737 */ 738 u32 txstmpl_old, txstmpl_new; 739 740 txstmpl_old = rd32(IGC_TXSTMPL); 741 rd32(IGC_TXSTMPH); 742 txstmpl_new = rd32(IGC_TXSTMPL); 743 744 if (txstmpl_old == txstmpl_new) 745 return; 746 747 regval = txstmpl_new; 748 regval |= (u64)rd32(IGC_TXSTMPH) << 32; 749 } 750 if (igc_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval)) 751 return; 752 753 switch (adapter->link_speed) { 754 case SPEED_10: 755 adjust = IGC_I225_TX_LATENCY_10; 756 break; 757 case SPEED_100: 758 adjust = IGC_I225_TX_LATENCY_100; 759 break; 760 case SPEED_1000: 761 adjust = IGC_I225_TX_LATENCY_1000; 762 break; 763 case SPEED_2500: 764 adjust = IGC_I225_TX_LATENCY_2500; 765 break; 766 } 767 768 shhwtstamps.hwtstamp = 769 ktime_add_ns(shhwtstamps.hwtstamp, adjust); 770 771 adapter->ptp_tx_skb = NULL; 772 773 /* Notify the stack and free the skb after we've unlocked */ 774 skb_tstamp_tx(skb, &shhwtstamps); 775 dev_kfree_skb_any(skb); 776 } 777 778 /** 779 * igc_ptp_tx_tstamp_event 780 * @adapter: board private structure 781 * 782 * Called when a TX timestamp interrupt happens to retrieve the 783 * timestamp and send it up to the socket. 784 */ 785 void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter) 786 { 787 unsigned long flags; 788 789 spin_lock_irqsave(&adapter->ptp_tx_lock, flags); 790 791 if (!adapter->ptp_tx_skb) 792 goto unlock; 793 794 igc_ptp_tx_hwtstamp(adapter); 795 796 unlock: 797 spin_unlock_irqrestore(&adapter->ptp_tx_lock, flags); 798 } 799 800 /** 801 * igc_ptp_set_ts_config - set hardware time stamping config 802 * @netdev: network interface device structure 803 * @ifr: interface request data 804 * 805 **/ 806 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr) 807 { 808 struct igc_adapter *adapter = netdev_priv(netdev); 809 struct hwtstamp_config config; 810 int err; 811 812 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 813 return -EFAULT; 814 815 err = igc_ptp_set_timestamp_mode(adapter, &config); 816 if (err) 817 return err; 818 819 /* save these settings for future reference */ 820 memcpy(&adapter->tstamp_config, &config, 821 sizeof(adapter->tstamp_config)); 822 823 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 824 -EFAULT : 0; 825 } 826 827 /** 828 * igc_ptp_get_ts_config - get hardware time stamping config 829 * @netdev: network interface device structure 830 * @ifr: interface request data 831 * 832 * Get the hwtstamp_config settings to return to the user. Rather than attempt 833 * to deconstruct the settings from the registers, just return a shadow copy 834 * of the last known settings. 835 **/ 836 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr) 837 { 838 struct igc_adapter *adapter = netdev_priv(netdev); 839 struct hwtstamp_config *config = &adapter->tstamp_config; 840 841 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 842 -EFAULT : 0; 843 } 844 845 /* The two conditions below must be met for cross timestamping via 846 * PCIe PTM: 847 * 848 * 1. We have an way to convert the timestamps in the PTM messages 849 * to something related to the system clocks (right now, only 850 * X86 systems with support for the Always Running Timer allow that); 851 * 852 * 2. We have PTM enabled in the path from the device to the PCIe root port. 853 */ 854 static bool igc_is_crosststamp_supported(struct igc_adapter *adapter) 855 { 856 if (!IS_ENABLED(CONFIG_X86_TSC)) 857 return false; 858 859 /* FIXME: it was noticed that enabling support for PCIe PTM in 860 * some i225-V models could cause lockups when bringing the 861 * interface up/down. There should be no downsides to 862 * disabling crosstimestamping support for i225-V, as it 863 * doesn't have any PTP support. That way we gain some time 864 * while root causing the issue. 865 */ 866 if (adapter->pdev->device == IGC_DEV_ID_I225_V) 867 return false; 868 869 return pcie_ptm_enabled(adapter->pdev); 870 } 871 872 static struct system_counterval_t igc_device_tstamp_to_system(u64 tstamp) 873 { 874 #if IS_ENABLED(CONFIG_X86_TSC) && !defined(CONFIG_UML) 875 return convert_art_ns_to_tsc(tstamp); 876 #else 877 return (struct system_counterval_t) { }; 878 #endif 879 } 880 881 static void igc_ptm_log_error(struct igc_adapter *adapter, u32 ptm_stat) 882 { 883 struct net_device *netdev = adapter->netdev; 884 885 switch (ptm_stat) { 886 case IGC_PTM_STAT_RET_ERR: 887 netdev_err(netdev, "PTM Error: Root port timeout\n"); 888 break; 889 case IGC_PTM_STAT_BAD_PTM_RES: 890 netdev_err(netdev, "PTM Error: Bad response, PTM Response Data expected\n"); 891 break; 892 case IGC_PTM_STAT_T4M1_OVFL: 893 netdev_err(netdev, "PTM Error: T4 minus T1 overflow\n"); 894 break; 895 case IGC_PTM_STAT_ADJUST_1ST: 896 netdev_err(netdev, "PTM Error: 1588 timer adjusted during first PTM cycle\n"); 897 break; 898 case IGC_PTM_STAT_ADJUST_CYC: 899 netdev_err(netdev, "PTM Error: 1588 timer adjusted during non-first PTM cycle\n"); 900 break; 901 default: 902 netdev_err(netdev, "PTM Error: Unknown error (%#x)\n", ptm_stat); 903 break; 904 } 905 } 906 907 static int igc_phc_get_syncdevicetime(ktime_t *device, 908 struct system_counterval_t *system, 909 void *ctx) 910 { 911 u32 stat, t2_curr_h, t2_curr_l, ctrl; 912 struct igc_adapter *adapter = ctx; 913 struct igc_hw *hw = &adapter->hw; 914 int err, count = 100; 915 ktime_t t1, t2_curr; 916 917 /* Get a snapshot of system clocks to use as historic value. */ 918 ktime_get_snapshot(&adapter->snapshot); 919 920 do { 921 /* Doing this in a loop because in the event of a 922 * badly timed (ha!) system clock adjustment, we may 923 * get PTM errors from the PCI root, but these errors 924 * are transitory. Repeating the process returns valid 925 * data eventually. 926 */ 927 928 /* To "manually" start the PTM cycle we need to clear and 929 * then set again the TRIG bit. 930 */ 931 ctrl = rd32(IGC_PTM_CTRL); 932 ctrl &= ~IGC_PTM_CTRL_TRIG; 933 wr32(IGC_PTM_CTRL, ctrl); 934 ctrl |= IGC_PTM_CTRL_TRIG; 935 wr32(IGC_PTM_CTRL, ctrl); 936 937 /* The cycle only starts "for real" when software notifies 938 * that it has read the registers, this is done by setting 939 * VALID bit. 940 */ 941 wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID); 942 943 err = readx_poll_timeout(rd32, IGC_PTM_STAT, stat, 944 stat, IGC_PTM_STAT_SLEEP, 945 IGC_PTM_STAT_TIMEOUT); 946 if (err < 0) { 947 netdev_err(adapter->netdev, "Timeout reading IGC_PTM_STAT register\n"); 948 return err; 949 } 950 951 if ((stat & IGC_PTM_STAT_VALID) == IGC_PTM_STAT_VALID) 952 break; 953 954 if (stat & ~IGC_PTM_STAT_VALID) { 955 /* An error occurred, log it. */ 956 igc_ptm_log_error(adapter, stat); 957 /* The STAT register is write-1-to-clear (W1C), 958 * so write the previous error status to clear it. 959 */ 960 wr32(IGC_PTM_STAT, stat); 961 continue; 962 } 963 } while (--count); 964 965 if (!count) { 966 netdev_err(adapter->netdev, "Exceeded number of tries for PTM cycle\n"); 967 return -ETIMEDOUT; 968 } 969 970 t1 = ktime_set(rd32(IGC_PTM_T1_TIM0_H), rd32(IGC_PTM_T1_TIM0_L)); 971 972 t2_curr_l = rd32(IGC_PTM_CURR_T2_L); 973 t2_curr_h = rd32(IGC_PTM_CURR_T2_H); 974 975 /* FIXME: When the register that tells the endianness of the 976 * PTM registers are implemented, check them here and add the 977 * appropriate conversion. 978 */ 979 t2_curr_h = swab32(t2_curr_h); 980 981 t2_curr = ((s64)t2_curr_h << 32 | t2_curr_l); 982 983 *device = t1; 984 *system = igc_device_tstamp_to_system(t2_curr); 985 986 return 0; 987 } 988 989 static int igc_ptp_getcrosststamp(struct ptp_clock_info *ptp, 990 struct system_device_crosststamp *cts) 991 { 992 struct igc_adapter *adapter = container_of(ptp, struct igc_adapter, 993 ptp_caps); 994 995 return get_device_system_crosststamp(igc_phc_get_syncdevicetime, 996 adapter, &adapter->snapshot, cts); 997 } 998 999 /** 1000 * igc_ptp_init - Initialize PTP functionality 1001 * @adapter: Board private structure 1002 * 1003 * This function is called at device probe to initialize the PTP 1004 * functionality. 1005 */ 1006 void igc_ptp_init(struct igc_adapter *adapter) 1007 { 1008 struct net_device *netdev = adapter->netdev; 1009 struct igc_hw *hw = &adapter->hw; 1010 int i; 1011 1012 switch (hw->mac.type) { 1013 case igc_i225: 1014 for (i = 0; i < IGC_N_SDP; i++) { 1015 struct ptp_pin_desc *ppd = &adapter->sdp_config[i]; 1016 1017 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i); 1018 ppd->index = i; 1019 ppd->func = PTP_PF_NONE; 1020 } 1021 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 1022 adapter->ptp_caps.owner = THIS_MODULE; 1023 adapter->ptp_caps.max_adj = 62499999; 1024 adapter->ptp_caps.adjfine = igc_ptp_adjfine_i225; 1025 adapter->ptp_caps.adjtime = igc_ptp_adjtime_i225; 1026 adapter->ptp_caps.gettimex64 = igc_ptp_gettimex64_i225; 1027 adapter->ptp_caps.settime64 = igc_ptp_settime_i225; 1028 adapter->ptp_caps.enable = igc_ptp_feature_enable_i225; 1029 adapter->ptp_caps.pps = 1; 1030 adapter->ptp_caps.pin_config = adapter->sdp_config; 1031 adapter->ptp_caps.n_ext_ts = IGC_N_EXTTS; 1032 adapter->ptp_caps.n_per_out = IGC_N_PEROUT; 1033 adapter->ptp_caps.n_pins = IGC_N_SDP; 1034 adapter->ptp_caps.verify = igc_ptp_verify_pin; 1035 1036 if (!igc_is_crosststamp_supported(adapter)) 1037 break; 1038 1039 adapter->ptp_caps.getcrosststamp = igc_ptp_getcrosststamp; 1040 break; 1041 default: 1042 adapter->ptp_clock = NULL; 1043 return; 1044 } 1045 1046 spin_lock_init(&adapter->ptp_tx_lock); 1047 spin_lock_init(&adapter->tmreg_lock); 1048 1049 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 1050 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 1051 1052 adapter->prev_ptp_time = ktime_to_timespec64(ktime_get_real()); 1053 adapter->ptp_reset_start = ktime_get(); 1054 1055 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, 1056 &adapter->pdev->dev); 1057 if (IS_ERR(adapter->ptp_clock)) { 1058 adapter->ptp_clock = NULL; 1059 netdev_err(netdev, "ptp_clock_register failed\n"); 1060 } else if (adapter->ptp_clock) { 1061 netdev_info(netdev, "PHC added\n"); 1062 adapter->ptp_flags |= IGC_PTP_ENABLED; 1063 } 1064 } 1065 1066 static void igc_ptp_time_save(struct igc_adapter *adapter) 1067 { 1068 igc_ptp_read(adapter, &adapter->prev_ptp_time); 1069 adapter->ptp_reset_start = ktime_get(); 1070 } 1071 1072 static void igc_ptp_time_restore(struct igc_adapter *adapter) 1073 { 1074 struct timespec64 ts = adapter->prev_ptp_time; 1075 ktime_t delta; 1076 1077 delta = ktime_sub(ktime_get(), adapter->ptp_reset_start); 1078 1079 timespec64_add_ns(&ts, ktime_to_ns(delta)); 1080 1081 igc_ptp_write_i225(adapter, &ts); 1082 } 1083 1084 static void igc_ptm_stop(struct igc_adapter *adapter) 1085 { 1086 struct igc_hw *hw = &adapter->hw; 1087 u32 ctrl; 1088 1089 ctrl = rd32(IGC_PTM_CTRL); 1090 ctrl &= ~IGC_PTM_CTRL_EN; 1091 1092 wr32(IGC_PTM_CTRL, ctrl); 1093 } 1094 1095 /** 1096 * igc_ptp_suspend - Disable PTP work items and prepare for suspend 1097 * @adapter: Board private structure 1098 * 1099 * This function stops the overflow check work and PTP Tx timestamp work, and 1100 * will prepare the device for OS suspend. 1101 */ 1102 void igc_ptp_suspend(struct igc_adapter *adapter) 1103 { 1104 if (!(adapter->ptp_flags & IGC_PTP_ENABLED)) 1105 return; 1106 1107 igc_ptp_clear_tx_tstamp(adapter); 1108 1109 if (pci_device_is_present(adapter->pdev)) { 1110 igc_ptp_time_save(adapter); 1111 igc_ptm_stop(adapter); 1112 } 1113 } 1114 1115 /** 1116 * igc_ptp_stop - Disable PTP device and stop the overflow check. 1117 * @adapter: Board private structure. 1118 * 1119 * This function stops the PTP support and cancels the delayed work. 1120 **/ 1121 void igc_ptp_stop(struct igc_adapter *adapter) 1122 { 1123 igc_ptp_suspend(adapter); 1124 1125 if (adapter->ptp_clock) { 1126 ptp_clock_unregister(adapter->ptp_clock); 1127 netdev_info(adapter->netdev, "PHC removed\n"); 1128 adapter->ptp_flags &= ~IGC_PTP_ENABLED; 1129 } 1130 } 1131 1132 /** 1133 * igc_ptp_reset - Re-enable the adapter for PTP following a reset. 1134 * @adapter: Board private structure. 1135 * 1136 * This function handles the reset work required to re-enable the PTP device. 1137 **/ 1138 void igc_ptp_reset(struct igc_adapter *adapter) 1139 { 1140 struct igc_hw *hw = &adapter->hw; 1141 u32 cycle_ctrl, ctrl; 1142 unsigned long flags; 1143 u32 timadj; 1144 1145 /* reset the tstamp_config */ 1146 igc_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config); 1147 1148 spin_lock_irqsave(&adapter->tmreg_lock, flags); 1149 1150 switch (adapter->hw.mac.type) { 1151 case igc_i225: 1152 timadj = rd32(IGC_TIMADJ); 1153 timadj |= IGC_TIMADJ_ADJUST_METH; 1154 wr32(IGC_TIMADJ, timadj); 1155 1156 wr32(IGC_TSAUXC, 0x0); 1157 wr32(IGC_TSSDP, 0x0); 1158 wr32(IGC_TSIM, 1159 IGC_TSICR_INTERRUPTS | 1160 (adapter->pps_sys_wrap_on ? IGC_TSICR_SYS_WRAP : 0)); 1161 wr32(IGC_IMS, IGC_IMS_TS); 1162 1163 if (!igc_is_crosststamp_supported(adapter)) 1164 break; 1165 1166 wr32(IGC_PCIE_DIG_DELAY, IGC_PCIE_DIG_DELAY_DEFAULT); 1167 wr32(IGC_PCIE_PHY_DELAY, IGC_PCIE_PHY_DELAY_DEFAULT); 1168 1169 cycle_ctrl = IGC_PTM_CYCLE_CTRL_CYC_TIME(IGC_PTM_CYC_TIME_DEFAULT); 1170 1171 wr32(IGC_PTM_CYCLE_CTRL, cycle_ctrl); 1172 1173 ctrl = IGC_PTM_CTRL_EN | 1174 IGC_PTM_CTRL_START_NOW | 1175 IGC_PTM_CTRL_SHRT_CYC(IGC_PTM_SHORT_CYC_DEFAULT) | 1176 IGC_PTM_CTRL_PTM_TO(IGC_PTM_TIMEOUT_DEFAULT) | 1177 IGC_PTM_CTRL_TRIG; 1178 1179 wr32(IGC_PTM_CTRL, ctrl); 1180 1181 /* Force the first cycle to run. */ 1182 wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID); 1183 1184 break; 1185 default: 1186 /* No work to do. */ 1187 goto out; 1188 } 1189 1190 /* Re-initialize the timer. */ 1191 if (hw->mac.type == igc_i225) { 1192 igc_ptp_time_restore(adapter); 1193 } else { 1194 timecounter_init(&adapter->tc, &adapter->cc, 1195 ktime_to_ns(ktime_get_real())); 1196 } 1197 out: 1198 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 1199 1200 wrfl(); 1201 } 1202