1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #include "igc_phy.h" 5 6 /** 7 * igc_check_reset_block - Check if PHY reset is blocked 8 * @hw: pointer to the HW structure 9 * 10 * Read the PHY management control register and check whether a PHY reset 11 * is blocked. If a reset is not blocked return 0, otherwise 12 * return IGC_ERR_BLK_PHY_RESET (12). 13 */ 14 s32 igc_check_reset_block(struct igc_hw *hw) 15 { 16 u32 manc; 17 18 manc = rd32(IGC_MANC); 19 20 return (manc & IGC_MANC_BLK_PHY_RST_ON_IDE) ? 21 IGC_ERR_BLK_PHY_RESET : 0; 22 } 23 24 /** 25 * igc_get_phy_id - Retrieve the PHY ID and revision 26 * @hw: pointer to the HW structure 27 * 28 * Reads the PHY registers and stores the PHY ID and possibly the PHY 29 * revision in the hardware structure. 30 */ 31 s32 igc_get_phy_id(struct igc_hw *hw) 32 { 33 struct igc_phy_info *phy = &hw->phy; 34 s32 ret_val = 0; 35 u16 phy_id; 36 37 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 38 if (ret_val) 39 goto out; 40 41 phy->id = (u32)(phy_id << 16); 42 usleep_range(200, 500); 43 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 44 if (ret_val) 45 goto out; 46 47 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 48 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 49 50 out: 51 return ret_val; 52 } 53 54 /** 55 * igc_phy_has_link - Polls PHY for link 56 * @hw: pointer to the HW structure 57 * @iterations: number of times to poll for link 58 * @usec_interval: delay between polling attempts 59 * @success: pointer to whether polling was successful or not 60 * 61 * Polls the PHY status register for link, 'iterations' number of times. 62 */ 63 s32 igc_phy_has_link(struct igc_hw *hw, u32 iterations, 64 u32 usec_interval, bool *success) 65 { 66 u16 i, phy_status; 67 s32 ret_val = 0; 68 69 for (i = 0; i < iterations; i++) { 70 /* Some PHYs require the PHY_STATUS register to be read 71 * twice due to the link bit being sticky. No harm doing 72 * it across the board. 73 */ 74 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 75 if (ret_val && usec_interval > 0) { 76 /* If the first read fails, another entity may have 77 * ownership of the resources, wait and try again to 78 * see if they have relinquished the resources yet. 79 */ 80 if (usec_interval >= 1000) 81 mdelay(usec_interval / 1000); 82 else 83 udelay(usec_interval); 84 } 85 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 86 if (ret_val) 87 break; 88 if (phy_status & MII_SR_LINK_STATUS) 89 break; 90 if (usec_interval >= 1000) 91 mdelay(usec_interval / 1000); 92 else 93 udelay(usec_interval); 94 } 95 96 *success = (i < iterations) ? true : false; 97 98 return ret_val; 99 } 100 101 /** 102 * igc_power_up_phy_copper - Restore copper link in case of PHY power down 103 * @hw: pointer to the HW structure 104 * 105 * In the case of a PHY power down to save power, or to turn off link during a 106 * driver unload, restore the link to previous settings. 107 */ 108 void igc_power_up_phy_copper(struct igc_hw *hw) 109 { 110 u16 mii_reg = 0; 111 112 /* The PHY will retain its settings across a power down/up cycle */ 113 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 114 mii_reg &= ~MII_CR_POWER_DOWN; 115 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 116 } 117 118 /** 119 * igc_power_down_phy_copper - Power down copper PHY 120 * @hw: pointer to the HW structure 121 * 122 * Power down PHY to save power when interface is down and wake on lan 123 * is not enabled. 124 */ 125 void igc_power_down_phy_copper(struct igc_hw *hw) 126 { 127 u16 mii_reg = 0; 128 129 /* The PHY will retain its settings across a power down/up cycle */ 130 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 131 mii_reg |= MII_CR_POWER_DOWN; 132 133 /* Temporary workaround - should be removed when PHY will implement 134 * IEEE registers as properly 135 */ 136 /* hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);*/ 137 usleep_range(1000, 2000); 138 } 139 140 /** 141 * igc_check_downshift - Checks whether a downshift in speed occurred 142 * @hw: pointer to the HW structure 143 * 144 * Success returns 0, Failure returns 1 145 * 146 * A downshift is detected by querying the PHY link health. 147 */ 148 s32 igc_check_downshift(struct igc_hw *hw) 149 { 150 struct igc_phy_info *phy = &hw->phy; 151 s32 ret_val; 152 153 switch (phy->type) { 154 case igc_phy_i225: 155 default: 156 /* speed downshift not supported */ 157 phy->speed_downgraded = false; 158 ret_val = 0; 159 } 160 161 return ret_val; 162 } 163 164 /** 165 * igc_phy_hw_reset - PHY hardware reset 166 * @hw: pointer to the HW structure 167 * 168 * Verify the reset block is not blocking us from resetting. Acquire 169 * semaphore (if necessary) and read/set/write the device control reset 170 * bit in the PHY. Wait the appropriate delay time for the device to 171 * reset and release the semaphore (if necessary). 172 */ 173 s32 igc_phy_hw_reset(struct igc_hw *hw) 174 { 175 struct igc_phy_info *phy = &hw->phy; 176 u32 phpm = 0, timeout = 10000; 177 s32 ret_val; 178 u32 ctrl; 179 180 ret_val = igc_check_reset_block(hw); 181 if (ret_val) { 182 ret_val = 0; 183 goto out; 184 } 185 186 ret_val = phy->ops.acquire(hw); 187 if (ret_val) 188 goto out; 189 190 phpm = rd32(IGC_I225_PHPM); 191 192 ctrl = rd32(IGC_CTRL); 193 wr32(IGC_CTRL, ctrl | IGC_CTRL_PHY_RST); 194 wrfl(); 195 196 udelay(phy->reset_delay_us); 197 198 wr32(IGC_CTRL, ctrl); 199 wrfl(); 200 201 /* SW should guarantee 100us for the completion of the PHY reset */ 202 usleep_range(100, 150); 203 do { 204 phpm = rd32(IGC_I225_PHPM); 205 timeout--; 206 udelay(1); 207 } while (!(phpm & IGC_PHY_RST_COMP) && timeout); 208 209 if (!timeout) 210 hw_dbg("Timeout is expired after a phy reset\n"); 211 212 usleep_range(100, 150); 213 214 phy->ops.release(hw); 215 216 out: 217 return ret_val; 218 } 219 220 /** 221 * igc_phy_setup_autoneg - Configure PHY for auto-negotiation 222 * @hw: pointer to the HW structure 223 * 224 * Reads the MII auto-neg advertisement register and/or the 1000T control 225 * register and if the PHY is already setup for auto-negotiation, then 226 * return successful. Otherwise, setup advertisement and flow control to 227 * the appropriate values for the wanted auto-negotiation. 228 */ 229 static s32 igc_phy_setup_autoneg(struct igc_hw *hw) 230 { 231 struct igc_phy_info *phy = &hw->phy; 232 u16 aneg_multigbt_an_ctrl = 0; 233 u16 mii_1000t_ctrl_reg = 0; 234 u16 mii_autoneg_adv_reg; 235 s32 ret_val; 236 237 phy->autoneg_advertised &= phy->autoneg_mask; 238 239 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 240 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 241 if (ret_val) 242 return ret_val; 243 244 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 245 /* Read the MII 1000Base-T Control Register (Address 9). */ 246 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 247 &mii_1000t_ctrl_reg); 248 if (ret_val) 249 return ret_val; 250 } 251 252 if (phy->autoneg_mask & ADVERTISE_2500_FULL) { 253 /* Read the MULTI GBT AN Control Register - reg 7.32 */ 254 ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK << 255 MMD_DEVADDR_SHIFT) | 256 ANEG_MULTIGBT_AN_CTRL, 257 &aneg_multigbt_an_ctrl); 258 259 if (ret_val) 260 return ret_val; 261 } 262 263 /* Need to parse both autoneg_advertised and fc and set up 264 * the appropriate PHY registers. First we will parse for 265 * autoneg_advertised software override. Since we can advertise 266 * a plethora of combinations, we need to check each bit 267 * individually. 268 */ 269 270 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 271 * Advertisement Register (Address 4) and the 1000 mb speed bits in 272 * the 1000Base-T Control Register (Address 9). 273 */ 274 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 275 NWAY_AR_100TX_HD_CAPS | 276 NWAY_AR_10T_FD_CAPS | 277 NWAY_AR_10T_HD_CAPS); 278 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 279 280 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); 281 282 /* Do we want to advertise 10 Mb Half Duplex? */ 283 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 284 hw_dbg("Advertise 10mb Half duplex\n"); 285 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 286 } 287 288 /* Do we want to advertise 10 Mb Full Duplex? */ 289 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 290 hw_dbg("Advertise 10mb Full duplex\n"); 291 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 292 } 293 294 /* Do we want to advertise 100 Mb Half Duplex? */ 295 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 296 hw_dbg("Advertise 100mb Half duplex\n"); 297 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 298 } 299 300 /* Do we want to advertise 100 Mb Full Duplex? */ 301 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 302 hw_dbg("Advertise 100mb Full duplex\n"); 303 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 304 } 305 306 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 307 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 308 hw_dbg("Advertise 1000mb Half duplex request denied!\n"); 309 310 /* Do we want to advertise 1000 Mb Full Duplex? */ 311 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 312 hw_dbg("Advertise 1000mb Full duplex\n"); 313 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 314 } 315 316 /* We do not allow the Phy to advertise 2500 Mb Half Duplex */ 317 if (phy->autoneg_advertised & ADVERTISE_2500_HALF) 318 hw_dbg("Advertise 2500mb Half duplex request denied!\n"); 319 320 /* Do we want to advertise 2500 Mb Full Duplex? */ 321 if (phy->autoneg_advertised & ADVERTISE_2500_FULL) { 322 hw_dbg("Advertise 2500mb Full duplex\n"); 323 aneg_multigbt_an_ctrl |= CR_2500T_FD_CAPS; 324 } else { 325 aneg_multigbt_an_ctrl &= ~CR_2500T_FD_CAPS; 326 } 327 328 /* Check for a software override of the flow control settings, and 329 * setup the PHY advertisement registers accordingly. If 330 * auto-negotiation is enabled, then software will have to set the 331 * "PAUSE" bits to the correct value in the Auto-Negotiation 332 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 333 * negotiation. 334 * 335 * The possible values of the "fc" parameter are: 336 * 0: Flow control is completely disabled 337 * 1: Rx flow control is enabled (we can receive pause frames 338 * but not send pause frames). 339 * 2: Tx flow control is enabled (we can send pause frames 340 * but we do not support receiving pause frames). 341 * 3: Both Rx and Tx flow control (symmetric) are enabled. 342 * other: No software override. The flow control configuration 343 * in the EEPROM is used. 344 */ 345 switch (hw->fc.current_mode) { 346 case igc_fc_none: 347 /* Flow control (Rx & Tx) is completely disabled by a 348 * software over-ride. 349 */ 350 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 351 break; 352 case igc_fc_rx_pause: 353 /* Rx Flow control is enabled, and Tx Flow control is 354 * disabled, by a software over-ride. 355 * 356 * Since there really isn't a way to advertise that we are 357 * capable of Rx Pause ONLY, we will advertise that we 358 * support both symmetric and asymmetric Rx PAUSE. Later 359 * (in igc_config_fc_after_link_up) we will disable the 360 * hw's ability to send PAUSE frames. 361 */ 362 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 363 break; 364 case igc_fc_tx_pause: 365 /* Tx Flow control is enabled, and Rx Flow control is 366 * disabled, by a software over-ride. 367 */ 368 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 369 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 370 break; 371 case igc_fc_full: 372 /* Flow control (both Rx and Tx) is enabled by a software 373 * over-ride. 374 */ 375 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 376 break; 377 default: 378 hw_dbg("Flow control param set incorrectly\n"); 379 return -IGC_ERR_CONFIG; 380 } 381 382 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 383 if (ret_val) 384 return ret_val; 385 386 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 387 388 if (phy->autoneg_mask & ADVERTISE_1000_FULL) 389 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, 390 mii_1000t_ctrl_reg); 391 392 if (phy->autoneg_mask & ADVERTISE_2500_FULL) 393 ret_val = phy->ops.write_reg(hw, 394 (STANDARD_AN_REG_MASK << 395 MMD_DEVADDR_SHIFT) | 396 ANEG_MULTIGBT_AN_CTRL, 397 aneg_multigbt_an_ctrl); 398 399 return ret_val; 400 } 401 402 /** 403 * igc_wait_autoneg - Wait for auto-neg completion 404 * @hw: pointer to the HW structure 405 * 406 * Waits for auto-negotiation to complete or for the auto-negotiation time 407 * limit to expire, which ever happens first. 408 */ 409 static s32 igc_wait_autoneg(struct igc_hw *hw) 410 { 411 u16 i, phy_status; 412 s32 ret_val = 0; 413 414 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 415 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 416 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 417 if (ret_val) 418 break; 419 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 420 if (ret_val) 421 break; 422 if (phy_status & MII_SR_AUTONEG_COMPLETE) 423 break; 424 msleep(100); 425 } 426 427 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 428 * has completed. 429 */ 430 return ret_val; 431 } 432 433 /** 434 * igc_copper_link_autoneg - Setup/Enable autoneg for copper link 435 * @hw: pointer to the HW structure 436 * 437 * Performs initial bounds checking on autoneg advertisement parameter, then 438 * configure to advertise the full capability. Setup the PHY to autoneg 439 * and restart the negotiation process between the link partner. If 440 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 441 */ 442 static s32 igc_copper_link_autoneg(struct igc_hw *hw) 443 { 444 struct igc_phy_info *phy = &hw->phy; 445 u16 phy_ctrl; 446 s32 ret_val; 447 448 /* Perform some bounds checking on the autoneg advertisement 449 * parameter. 450 */ 451 phy->autoneg_advertised &= phy->autoneg_mask; 452 453 /* If autoneg_advertised is zero, we assume it was not defaulted 454 * by the calling code so we set to advertise full capability. 455 */ 456 if (phy->autoneg_advertised == 0) 457 phy->autoneg_advertised = phy->autoneg_mask; 458 459 hw_dbg("Reconfiguring auto-neg advertisement params\n"); 460 ret_val = igc_phy_setup_autoneg(hw); 461 if (ret_val) { 462 hw_dbg("Error Setting up Auto-Negotiation\n"); 463 goto out; 464 } 465 hw_dbg("Restarting Auto-Neg\n"); 466 467 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 468 * the Auto Neg Restart bit in the PHY control register. 469 */ 470 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 471 if (ret_val) 472 goto out; 473 474 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 475 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 476 if (ret_val) 477 goto out; 478 479 /* Does the user want to wait for Auto-Neg to complete here, or 480 * check at a later time (for example, callback routine). 481 */ 482 if (phy->autoneg_wait_to_complete) { 483 ret_val = igc_wait_autoneg(hw); 484 if (ret_val) { 485 hw_dbg("Error while waiting for autoneg to complete\n"); 486 goto out; 487 } 488 } 489 490 hw->mac.get_link_status = true; 491 492 out: 493 return ret_val; 494 } 495 496 /** 497 * igc_setup_copper_link - Configure copper link settings 498 * @hw: pointer to the HW structure 499 * 500 * Calls the appropriate function to configure the link for auto-neg or forced 501 * speed and duplex. Then we check for link, once link is established calls 502 * to configure collision distance and flow control are called. If link is 503 * not established, we return -IGC_ERR_PHY (-2). 504 */ 505 s32 igc_setup_copper_link(struct igc_hw *hw) 506 { 507 s32 ret_val = 0; 508 bool link; 509 510 if (hw->mac.autoneg) { 511 /* Setup autoneg and flow control advertisement and perform 512 * autonegotiation. 513 */ 514 ret_val = igc_copper_link_autoneg(hw); 515 if (ret_val) 516 goto out; 517 } else { 518 /* PHY will be set to 10H, 10F, 100H or 100F 519 * depending on user settings. 520 */ 521 hw_dbg("Forcing Speed and Duplex\n"); 522 ret_val = hw->phy.ops.force_speed_duplex(hw); 523 if (ret_val) { 524 hw_dbg("Error Forcing Speed and Duplex\n"); 525 goto out; 526 } 527 } 528 529 /* Check link status. Wait up to 100 microseconds for link to become 530 * valid. 531 */ 532 ret_val = igc_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link); 533 if (ret_val) 534 goto out; 535 536 if (link) { 537 hw_dbg("Valid link established!!!\n"); 538 igc_config_collision_dist(hw); 539 ret_val = igc_config_fc_after_link_up(hw); 540 } else { 541 hw_dbg("Unable to establish link!!!\n"); 542 } 543 544 out: 545 return ret_val; 546 } 547 548 /** 549 * igc_read_phy_reg_mdic - Read MDI control register 550 * @hw: pointer to the HW structure 551 * @offset: register offset to be read 552 * @data: pointer to the read data 553 * 554 * Reads the MDI control register in the PHY at offset and stores the 555 * information read to data. 556 */ 557 static s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data) 558 { 559 struct igc_phy_info *phy = &hw->phy; 560 u32 i, mdic = 0; 561 s32 ret_val = 0; 562 563 if (offset > MAX_PHY_REG_ADDRESS) { 564 hw_dbg("PHY Address %d is out of range\n", offset); 565 ret_val = -IGC_ERR_PARAM; 566 goto out; 567 } 568 569 /* Set up Op-code, Phy Address, and register offset in the MDI 570 * Control register. The MAC will take care of interfacing with the 571 * PHY to retrieve the desired data. 572 */ 573 mdic = ((offset << IGC_MDIC_REG_SHIFT) | 574 (phy->addr << IGC_MDIC_PHY_SHIFT) | 575 (IGC_MDIC_OP_READ)); 576 577 wr32(IGC_MDIC, mdic); 578 579 /* Poll the ready bit to see if the MDI read completed 580 * Increasing the time out as testing showed failures with 581 * the lower time out 582 */ 583 for (i = 0; i < IGC_GEN_POLL_TIMEOUT; i++) { 584 usleep_range(500, 1000); 585 mdic = rd32(IGC_MDIC); 586 if (mdic & IGC_MDIC_READY) 587 break; 588 } 589 if (!(mdic & IGC_MDIC_READY)) { 590 hw_dbg("MDI Read did not complete\n"); 591 ret_val = -IGC_ERR_PHY; 592 goto out; 593 } 594 if (mdic & IGC_MDIC_ERROR) { 595 hw_dbg("MDI Error\n"); 596 ret_val = -IGC_ERR_PHY; 597 goto out; 598 } 599 *data = (u16)mdic; 600 601 out: 602 return ret_val; 603 } 604 605 /** 606 * igc_write_phy_reg_mdic - Write MDI control register 607 * @hw: pointer to the HW structure 608 * @offset: register offset to write to 609 * @data: data to write to register at offset 610 * 611 * Writes data to MDI control register in the PHY at offset. 612 */ 613 static s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data) 614 { 615 struct igc_phy_info *phy = &hw->phy; 616 u32 i, mdic = 0; 617 s32 ret_val = 0; 618 619 if (offset > MAX_PHY_REG_ADDRESS) { 620 hw_dbg("PHY Address %d is out of range\n", offset); 621 ret_val = -IGC_ERR_PARAM; 622 goto out; 623 } 624 625 /* Set up Op-code, Phy Address, and register offset in the MDI 626 * Control register. The MAC will take care of interfacing with the 627 * PHY to write the desired data. 628 */ 629 mdic = (((u32)data) | 630 (offset << IGC_MDIC_REG_SHIFT) | 631 (phy->addr << IGC_MDIC_PHY_SHIFT) | 632 (IGC_MDIC_OP_WRITE)); 633 634 wr32(IGC_MDIC, mdic); 635 636 /* Poll the ready bit to see if the MDI read completed 637 * Increasing the time out as testing showed failures with 638 * the lower time out 639 */ 640 for (i = 0; i < IGC_GEN_POLL_TIMEOUT; i++) { 641 usleep_range(500, 1000); 642 mdic = rd32(IGC_MDIC); 643 if (mdic & IGC_MDIC_READY) 644 break; 645 } 646 if (!(mdic & IGC_MDIC_READY)) { 647 hw_dbg("MDI Write did not complete\n"); 648 ret_val = -IGC_ERR_PHY; 649 goto out; 650 } 651 if (mdic & IGC_MDIC_ERROR) { 652 hw_dbg("MDI Error\n"); 653 ret_val = -IGC_ERR_PHY; 654 goto out; 655 } 656 657 out: 658 return ret_val; 659 } 660 661 /** 662 * __igc_access_xmdio_reg - Read/write XMDIO register 663 * @hw: pointer to the HW structure 664 * @address: XMDIO address to program 665 * @dev_addr: device address to program 666 * @data: pointer to value to read/write from/to the XMDIO address 667 * @read: boolean flag to indicate read or write 668 */ 669 static s32 __igc_access_xmdio_reg(struct igc_hw *hw, u16 address, 670 u8 dev_addr, u16 *data, bool read) 671 { 672 s32 ret_val; 673 674 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr); 675 if (ret_val) 676 return ret_val; 677 678 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address); 679 if (ret_val) 680 return ret_val; 681 682 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA | 683 dev_addr); 684 if (ret_val) 685 return ret_val; 686 687 if (read) 688 ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data); 689 else 690 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data); 691 if (ret_val) 692 return ret_val; 693 694 /* Recalibrate the device back to 0 */ 695 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0); 696 if (ret_val) 697 return ret_val; 698 699 return ret_val; 700 } 701 702 /** 703 * igc_read_xmdio_reg - Read XMDIO register 704 * @hw: pointer to the HW structure 705 * @addr: XMDIO address to program 706 * @dev_addr: device address to program 707 * @data: value to be read from the EMI address 708 */ 709 static s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, 710 u8 dev_addr, u16 *data) 711 { 712 return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true); 713 } 714 715 /** 716 * igc_write_xmdio_reg - Write XMDIO register 717 * @hw: pointer to the HW structure 718 * @addr: XMDIO address to program 719 * @dev_addr: device address to program 720 * @data: value to be written to the XMDIO address 721 */ 722 static s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, 723 u8 dev_addr, u16 data) 724 { 725 return __igc_access_xmdio_reg(hw, addr, dev_addr, &data, false); 726 } 727 728 /** 729 * igc_write_phy_reg_gpy - Write GPY PHY register 730 * @hw: pointer to the HW structure 731 * @offset: register offset to write to 732 * @data: data to write at register offset 733 * 734 * Acquires semaphore, if necessary, then writes the data to PHY register 735 * at the offset. Release any acquired semaphores before exiting. 736 */ 737 s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data) 738 { 739 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT; 740 s32 ret_val; 741 742 offset = offset & GPY_REG_MASK; 743 744 if (!dev_addr) { 745 ret_val = hw->phy.ops.acquire(hw); 746 if (ret_val) 747 return ret_val; 748 ret_val = igc_write_phy_reg_mdic(hw, offset, data); 749 if (ret_val) 750 return ret_val; 751 hw->phy.ops.release(hw); 752 } else { 753 ret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr, 754 data); 755 } 756 757 return ret_val; 758 } 759 760 /** 761 * igc_read_phy_reg_gpy - Read GPY PHY register 762 * @hw: pointer to the HW structure 763 * @offset: lower half is register offset to read to 764 * upper half is MMD to use. 765 * @data: data to read at register offset 766 * 767 * Acquires semaphore, if necessary, then reads the data in the PHY register 768 * at the offset. Release any acquired semaphores before exiting. 769 */ 770 s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data) 771 { 772 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT; 773 s32 ret_val; 774 775 offset = offset & GPY_REG_MASK; 776 777 if (!dev_addr) { 778 ret_val = hw->phy.ops.acquire(hw); 779 if (ret_val) 780 return ret_val; 781 ret_val = igc_read_phy_reg_mdic(hw, offset, data); 782 if (ret_val) 783 return ret_val; 784 hw->phy.ops.release(hw); 785 } else { 786 ret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr, 787 data); 788 } 789 790 return ret_val; 791 } 792 793 /** 794 * igc_read_phy_fw_version - Read gPHY firmware version 795 * @hw: pointer to the HW structure 796 */ 797 u16 igc_read_phy_fw_version(struct igc_hw *hw) 798 { 799 struct igc_phy_info *phy = &hw->phy; 800 u16 gphy_version = 0; 801 u16 ret_val; 802 803 /* NVM image version is reported as firmware version for i225 device */ 804 ret_val = phy->ops.read_reg(hw, IGC_GPHY_VERSION, &gphy_version); 805 if (ret_val) 806 hw_dbg("igc_phy: read wrong gphy version\n"); 807 808 return gphy_version; 809 } 810