1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #include <linux/bitfield.h> 5 #include "igc_phy.h" 6 7 /** 8 * igc_check_reset_block - Check if PHY reset is blocked 9 * @hw: pointer to the HW structure 10 * 11 * Read the PHY management control register and check whether a PHY reset 12 * is blocked. If a reset is not blocked return 0, otherwise 13 * return IGC_ERR_BLK_PHY_RESET (12). 14 */ 15 s32 igc_check_reset_block(struct igc_hw *hw) 16 { 17 u32 manc; 18 19 manc = rd32(IGC_MANC); 20 21 return (manc & IGC_MANC_BLK_PHY_RST_ON_IDE) ? 22 IGC_ERR_BLK_PHY_RESET : 0; 23 } 24 25 /** 26 * igc_get_phy_id - Retrieve the PHY ID and revision 27 * @hw: pointer to the HW structure 28 * 29 * Reads the PHY registers and stores the PHY ID and possibly the PHY 30 * revision in the hardware structure. 31 */ 32 s32 igc_get_phy_id(struct igc_hw *hw) 33 { 34 struct igc_phy_info *phy = &hw->phy; 35 s32 ret_val = 0; 36 u16 phy_id; 37 38 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 39 if (ret_val) 40 goto out; 41 42 phy->id = (u32)(phy_id << 16); 43 usleep_range(200, 500); 44 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 45 if (ret_val) 46 goto out; 47 48 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 49 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 50 51 out: 52 return ret_val; 53 } 54 55 /** 56 * igc_phy_has_link - Polls PHY for link 57 * @hw: pointer to the HW structure 58 * @iterations: number of times to poll for link 59 * @usec_interval: delay between polling attempts 60 * @success: pointer to whether polling was successful or not 61 * 62 * Polls the PHY status register for link, 'iterations' number of times. 63 */ 64 s32 igc_phy_has_link(struct igc_hw *hw, u32 iterations, 65 u32 usec_interval, bool *success) 66 { 67 u16 i, phy_status; 68 s32 ret_val = 0; 69 70 for (i = 0; i < iterations; i++) { 71 /* Some PHYs require the PHY_STATUS register to be read 72 * twice due to the link bit being sticky. No harm doing 73 * it across the board. 74 */ 75 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 76 if (ret_val && usec_interval > 0) { 77 /* If the first read fails, another entity may have 78 * ownership of the resources, wait and try again to 79 * see if they have relinquished the resources yet. 80 */ 81 if (usec_interval >= 1000) 82 mdelay(usec_interval / 1000); 83 else 84 udelay(usec_interval); 85 } 86 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 87 if (ret_val) 88 break; 89 if (phy_status & MII_SR_LINK_STATUS) 90 break; 91 if (usec_interval >= 1000) 92 mdelay(usec_interval / 1000); 93 else 94 udelay(usec_interval); 95 } 96 97 *success = (i < iterations) ? true : false; 98 99 return ret_val; 100 } 101 102 /** 103 * igc_power_up_phy_copper - Restore copper link in case of PHY power down 104 * @hw: pointer to the HW structure 105 * 106 * In the case of a PHY power down to save power, or to turn off link during a 107 * driver unload, restore the link to previous settings. 108 */ 109 void igc_power_up_phy_copper(struct igc_hw *hw) 110 { 111 u16 mii_reg = 0; 112 113 /* The PHY will retain its settings across a power down/up cycle */ 114 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 115 mii_reg &= ~MII_CR_POWER_DOWN; 116 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 117 } 118 119 /** 120 * igc_power_down_phy_copper - Power down copper PHY 121 * @hw: pointer to the HW structure 122 * 123 * Power down PHY to save power when interface is down and wake on lan 124 * is not enabled. 125 */ 126 void igc_power_down_phy_copper(struct igc_hw *hw) 127 { 128 u16 mii_reg = 0; 129 130 /* The PHY will retain its settings across a power down/up cycle */ 131 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 132 mii_reg |= MII_CR_POWER_DOWN; 133 134 /* Temporary workaround - should be removed when PHY will implement 135 * IEEE registers as properly 136 */ 137 /* hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);*/ 138 usleep_range(1000, 2000); 139 } 140 141 /** 142 * igc_check_downshift - Checks whether a downshift in speed occurred 143 * @hw: pointer to the HW structure 144 * 145 * A downshift is detected by querying the PHY link health. 146 */ 147 void igc_check_downshift(struct igc_hw *hw) 148 { 149 struct igc_phy_info *phy = &hw->phy; 150 151 /* speed downshift not supported */ 152 phy->speed_downgraded = false; 153 } 154 155 /** 156 * igc_phy_hw_reset - PHY hardware reset 157 * @hw: pointer to the HW structure 158 * 159 * Verify the reset block is not blocking us from resetting. Acquire 160 * semaphore (if necessary) and read/set/write the device control reset 161 * bit in the PHY. Wait the appropriate delay time for the device to 162 * reset and release the semaphore (if necessary). 163 */ 164 s32 igc_phy_hw_reset(struct igc_hw *hw) 165 { 166 struct igc_phy_info *phy = &hw->phy; 167 u32 phpm = 0, timeout = 10000; 168 s32 ret_val; 169 u32 ctrl; 170 171 ret_val = igc_check_reset_block(hw); 172 if (ret_val) { 173 ret_val = 0; 174 goto out; 175 } 176 177 ret_val = phy->ops.acquire(hw); 178 if (ret_val) 179 goto out; 180 181 phpm = rd32(IGC_I225_PHPM); 182 183 ctrl = rd32(IGC_CTRL); 184 wr32(IGC_CTRL, ctrl | IGC_CTRL_PHY_RST); 185 wrfl(); 186 187 udelay(phy->reset_delay_us); 188 189 wr32(IGC_CTRL, ctrl); 190 wrfl(); 191 192 /* SW should guarantee 100us for the completion of the PHY reset */ 193 usleep_range(100, 150); 194 do { 195 phpm = rd32(IGC_I225_PHPM); 196 timeout--; 197 udelay(1); 198 } while (!(phpm & IGC_PHY_RST_COMP) && timeout); 199 200 if (!timeout) 201 hw_dbg("Timeout is expired after a phy reset\n"); 202 203 usleep_range(100, 150); 204 205 phy->ops.release(hw); 206 207 out: 208 return ret_val; 209 } 210 211 /** 212 * igc_phy_setup_autoneg - Configure PHY for auto-negotiation 213 * @hw: pointer to the HW structure 214 * 215 * Reads the MII auto-neg advertisement register and/or the 1000T control 216 * register and if the PHY is already setup for auto-negotiation, then 217 * return successful. Otherwise, setup advertisement and flow control to 218 * the appropriate values for the wanted auto-negotiation. 219 */ 220 static s32 igc_phy_setup_autoneg(struct igc_hw *hw) 221 { 222 struct igc_phy_info *phy = &hw->phy; 223 u16 aneg_multigbt_an_ctrl = 0; 224 u16 mii_1000t_ctrl_reg = 0; 225 u16 mii_autoneg_adv_reg; 226 s32 ret_val; 227 228 phy->autoneg_advertised &= phy->autoneg_mask; 229 230 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 231 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 232 if (ret_val) 233 return ret_val; 234 235 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 236 /* Read the MII 1000Base-T Control Register (Address 9). */ 237 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 238 &mii_1000t_ctrl_reg); 239 if (ret_val) 240 return ret_val; 241 } 242 243 if (phy->autoneg_mask & ADVERTISE_2500_FULL) { 244 /* Read the MULTI GBT AN Control Register - reg 7.32 */ 245 ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK << 246 MMD_DEVADDR_SHIFT) | 247 ANEG_MULTIGBT_AN_CTRL, 248 &aneg_multigbt_an_ctrl); 249 250 if (ret_val) 251 return ret_val; 252 } 253 254 /* Need to parse both autoneg_advertised and fc and set up 255 * the appropriate PHY registers. First we will parse for 256 * autoneg_advertised software override. Since we can advertise 257 * a plethora of combinations, we need to check each bit 258 * individually. 259 */ 260 261 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 262 * Advertisement Register (Address 4) and the 1000 mb speed bits in 263 * the 1000Base-T Control Register (Address 9). 264 */ 265 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 266 NWAY_AR_100TX_HD_CAPS | 267 NWAY_AR_10T_FD_CAPS | 268 NWAY_AR_10T_HD_CAPS); 269 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 270 271 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); 272 273 /* Do we want to advertise 10 Mb Half Duplex? */ 274 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 275 hw_dbg("Advertise 10mb Half duplex\n"); 276 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 277 } 278 279 /* Do we want to advertise 10 Mb Full Duplex? */ 280 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 281 hw_dbg("Advertise 10mb Full duplex\n"); 282 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 283 } 284 285 /* Do we want to advertise 100 Mb Half Duplex? */ 286 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 287 hw_dbg("Advertise 100mb Half duplex\n"); 288 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 289 } 290 291 /* Do we want to advertise 100 Mb Full Duplex? */ 292 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 293 hw_dbg("Advertise 100mb Full duplex\n"); 294 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 295 } 296 297 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 298 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 299 hw_dbg("Advertise 1000mb Half duplex request denied!\n"); 300 301 /* Do we want to advertise 1000 Mb Full Duplex? */ 302 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 303 hw_dbg("Advertise 1000mb Full duplex\n"); 304 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 305 } 306 307 /* We do not allow the Phy to advertise 2500 Mb Half Duplex */ 308 if (phy->autoneg_advertised & ADVERTISE_2500_HALF) 309 hw_dbg("Advertise 2500mb Half duplex request denied!\n"); 310 311 /* Do we want to advertise 2500 Mb Full Duplex? */ 312 if (phy->autoneg_advertised & ADVERTISE_2500_FULL) { 313 hw_dbg("Advertise 2500mb Full duplex\n"); 314 aneg_multigbt_an_ctrl |= CR_2500T_FD_CAPS; 315 } else { 316 aneg_multigbt_an_ctrl &= ~CR_2500T_FD_CAPS; 317 } 318 319 /* Check for a software override of the flow control settings, and 320 * setup the PHY advertisement registers accordingly. If 321 * auto-negotiation is enabled, then software will have to set the 322 * "PAUSE" bits to the correct value in the Auto-Negotiation 323 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 324 * negotiation. 325 * 326 * The possible values of the "fc" parameter are: 327 * 0: Flow control is completely disabled 328 * 1: Rx flow control is enabled (we can receive pause frames 329 * but not send pause frames). 330 * 2: Tx flow control is enabled (we can send pause frames 331 * but we do not support receiving pause frames). 332 * 3: Both Rx and Tx flow control (symmetric) are enabled. 333 * other: No software override. The flow control configuration 334 * in the EEPROM is used. 335 */ 336 switch (hw->fc.current_mode) { 337 case igc_fc_none: 338 /* Flow control (Rx & Tx) is completely disabled by a 339 * software over-ride. 340 */ 341 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 342 break; 343 case igc_fc_rx_pause: 344 /* Rx Flow control is enabled, and Tx Flow control is 345 * disabled, by a software over-ride. 346 * 347 * Since there really isn't a way to advertise that we are 348 * capable of Rx Pause ONLY, we will advertise that we 349 * support both symmetric and asymmetric Rx PAUSE. Later 350 * (in igc_config_fc_after_link_up) we will disable the 351 * hw's ability to send PAUSE frames. 352 */ 353 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 354 break; 355 case igc_fc_tx_pause: 356 /* Tx Flow control is enabled, and Rx Flow control is 357 * disabled, by a software over-ride. 358 */ 359 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 360 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 361 break; 362 case igc_fc_full: 363 /* Flow control (both Rx and Tx) is enabled by a software 364 * over-ride. 365 */ 366 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 367 break; 368 default: 369 hw_dbg("Flow control param set incorrectly\n"); 370 return -IGC_ERR_CONFIG; 371 } 372 373 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 374 if (ret_val) 375 return ret_val; 376 377 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 378 379 if (phy->autoneg_mask & ADVERTISE_1000_FULL) 380 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, 381 mii_1000t_ctrl_reg); 382 383 if (phy->autoneg_mask & ADVERTISE_2500_FULL) 384 ret_val = phy->ops.write_reg(hw, 385 (STANDARD_AN_REG_MASK << 386 MMD_DEVADDR_SHIFT) | 387 ANEG_MULTIGBT_AN_CTRL, 388 aneg_multigbt_an_ctrl); 389 390 return ret_val; 391 } 392 393 /** 394 * igc_wait_autoneg - Wait for auto-neg completion 395 * @hw: pointer to the HW structure 396 * 397 * Waits for auto-negotiation to complete or for the auto-negotiation time 398 * limit to expire, which ever happens first. 399 */ 400 static s32 igc_wait_autoneg(struct igc_hw *hw) 401 { 402 u16 i, phy_status; 403 s32 ret_val = 0; 404 405 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 406 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 407 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 408 if (ret_val) 409 break; 410 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 411 if (ret_val) 412 break; 413 if (phy_status & MII_SR_AUTONEG_COMPLETE) 414 break; 415 msleep(100); 416 } 417 418 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 419 * has completed. 420 */ 421 return ret_val; 422 } 423 424 /** 425 * igc_copper_link_autoneg - Setup/Enable autoneg for copper link 426 * @hw: pointer to the HW structure 427 * 428 * Performs initial bounds checking on autoneg advertisement parameter, then 429 * configure to advertise the full capability. Setup the PHY to autoneg 430 * and restart the negotiation process between the link partner. If 431 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 432 */ 433 static s32 igc_copper_link_autoneg(struct igc_hw *hw) 434 { 435 struct igc_phy_info *phy = &hw->phy; 436 u16 phy_ctrl; 437 s32 ret_val; 438 439 /* Perform some bounds checking on the autoneg advertisement 440 * parameter. 441 */ 442 phy->autoneg_advertised &= phy->autoneg_mask; 443 444 /* If autoneg_advertised is zero, we assume it was not defaulted 445 * by the calling code so we set to advertise full capability. 446 */ 447 if (phy->autoneg_advertised == 0) 448 phy->autoneg_advertised = phy->autoneg_mask; 449 450 hw_dbg("Reconfiguring auto-neg advertisement params\n"); 451 ret_val = igc_phy_setup_autoneg(hw); 452 if (ret_val) { 453 hw_dbg("Error Setting up Auto-Negotiation\n"); 454 goto out; 455 } 456 hw_dbg("Restarting Auto-Neg\n"); 457 458 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 459 * the Auto Neg Restart bit in the PHY control register. 460 */ 461 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 462 if (ret_val) 463 goto out; 464 465 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 466 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 467 if (ret_val) 468 goto out; 469 470 /* Does the user want to wait for Auto-Neg to complete here, or 471 * check at a later time (for example, callback routine). 472 */ 473 if (phy->autoneg_wait_to_complete) { 474 ret_val = igc_wait_autoneg(hw); 475 if (ret_val) { 476 hw_dbg("Error while waiting for autoneg to complete\n"); 477 goto out; 478 } 479 } 480 481 hw->mac.get_link_status = true; 482 483 out: 484 return ret_val; 485 } 486 487 /** 488 * igc_setup_copper_link - Configure copper link settings 489 * @hw: pointer to the HW structure 490 * 491 * Calls the appropriate function to configure the link for auto-neg or forced 492 * speed and duplex. Then we check for link, once link is established calls 493 * to configure collision distance and flow control are called. If link is 494 * not established, we return -IGC_ERR_PHY (-2). 495 */ 496 s32 igc_setup_copper_link(struct igc_hw *hw) 497 { 498 s32 ret_val = 0; 499 bool link; 500 501 if (hw->mac.autoneg) { 502 /* Setup autoneg and flow control advertisement and perform 503 * autonegotiation. 504 */ 505 ret_val = igc_copper_link_autoneg(hw); 506 if (ret_val) 507 goto out; 508 } else { 509 /* PHY will be set to 10H, 10F, 100H or 100F 510 * depending on user settings. 511 */ 512 hw_dbg("Forcing Speed and Duplex\n"); 513 ret_val = hw->phy.ops.force_speed_duplex(hw); 514 if (ret_val) { 515 hw_dbg("Error Forcing Speed and Duplex\n"); 516 goto out; 517 } 518 } 519 520 /* Check link status. Wait up to 100 microseconds for link to become 521 * valid. 522 */ 523 ret_val = igc_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link); 524 if (ret_val) 525 goto out; 526 527 if (link) { 528 hw_dbg("Valid link established!!!\n"); 529 igc_config_collision_dist(hw); 530 ret_val = igc_config_fc_after_link_up(hw); 531 } else { 532 hw_dbg("Unable to establish link!!!\n"); 533 } 534 535 out: 536 return ret_val; 537 } 538 539 /** 540 * igc_read_phy_reg_mdic - Read MDI control register 541 * @hw: pointer to the HW structure 542 * @offset: register offset to be read 543 * @data: pointer to the read data 544 * 545 * Reads the MDI control register in the PHY at offset and stores the 546 * information read to data. 547 */ 548 static s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data) 549 { 550 struct igc_phy_info *phy = &hw->phy; 551 u32 i, mdic = 0; 552 s32 ret_val = 0; 553 554 if (offset > MAX_PHY_REG_ADDRESS) { 555 hw_dbg("PHY Address %d is out of range\n", offset); 556 ret_val = -IGC_ERR_PARAM; 557 goto out; 558 } 559 560 /* Set up Op-code, Phy Address, and register offset in the MDI 561 * Control register. The MAC will take care of interfacing with the 562 * PHY to retrieve the desired data. 563 */ 564 mdic = ((offset << IGC_MDIC_REG_SHIFT) | 565 (phy->addr << IGC_MDIC_PHY_SHIFT) | 566 (IGC_MDIC_OP_READ)); 567 568 wr32(IGC_MDIC, mdic); 569 570 /* Poll the ready bit to see if the MDI read completed 571 * Increasing the time out as testing showed failures with 572 * the lower time out 573 */ 574 for (i = 0; i < IGC_GEN_POLL_TIMEOUT; i++) { 575 udelay(50); 576 mdic = rd32(IGC_MDIC); 577 if (mdic & IGC_MDIC_READY) 578 break; 579 } 580 if (!(mdic & IGC_MDIC_READY)) { 581 hw_dbg("MDI Read did not complete\n"); 582 ret_val = -IGC_ERR_PHY; 583 goto out; 584 } 585 if (mdic & IGC_MDIC_ERROR) { 586 hw_dbg("MDI Error\n"); 587 ret_val = -IGC_ERR_PHY; 588 goto out; 589 } 590 *data = (u16)mdic; 591 592 out: 593 return ret_val; 594 } 595 596 /** 597 * igc_write_phy_reg_mdic - Write MDI control register 598 * @hw: pointer to the HW structure 599 * @offset: register offset to write to 600 * @data: data to write to register at offset 601 * 602 * Writes data to MDI control register in the PHY at offset. 603 */ 604 static s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data) 605 { 606 struct igc_phy_info *phy = &hw->phy; 607 u32 i, mdic = 0; 608 s32 ret_val = 0; 609 610 if (offset > MAX_PHY_REG_ADDRESS) { 611 hw_dbg("PHY Address %d is out of range\n", offset); 612 ret_val = -IGC_ERR_PARAM; 613 goto out; 614 } 615 616 /* Set up Op-code, Phy Address, and register offset in the MDI 617 * Control register. The MAC will take care of interfacing with the 618 * PHY to write the desired data. 619 */ 620 mdic = (((u32)data) | 621 (offset << IGC_MDIC_REG_SHIFT) | 622 (phy->addr << IGC_MDIC_PHY_SHIFT) | 623 (IGC_MDIC_OP_WRITE)); 624 625 wr32(IGC_MDIC, mdic); 626 627 /* Poll the ready bit to see if the MDI read completed 628 * Increasing the time out as testing showed failures with 629 * the lower time out 630 */ 631 for (i = 0; i < IGC_GEN_POLL_TIMEOUT; i++) { 632 udelay(50); 633 mdic = rd32(IGC_MDIC); 634 if (mdic & IGC_MDIC_READY) 635 break; 636 } 637 if (!(mdic & IGC_MDIC_READY)) { 638 hw_dbg("MDI Write did not complete\n"); 639 ret_val = -IGC_ERR_PHY; 640 goto out; 641 } 642 if (mdic & IGC_MDIC_ERROR) { 643 hw_dbg("MDI Error\n"); 644 ret_val = -IGC_ERR_PHY; 645 goto out; 646 } 647 648 out: 649 return ret_val; 650 } 651 652 /** 653 * __igc_access_xmdio_reg - Read/write XMDIO register 654 * @hw: pointer to the HW structure 655 * @address: XMDIO address to program 656 * @dev_addr: device address to program 657 * @data: pointer to value to read/write from/to the XMDIO address 658 * @read: boolean flag to indicate read or write 659 */ 660 static s32 __igc_access_xmdio_reg(struct igc_hw *hw, u16 address, 661 u8 dev_addr, u16 *data, bool read) 662 { 663 s32 ret_val; 664 665 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr); 666 if (ret_val) 667 return ret_val; 668 669 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address); 670 if (ret_val) 671 return ret_val; 672 673 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA | 674 dev_addr); 675 if (ret_val) 676 return ret_val; 677 678 if (read) 679 ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data); 680 else 681 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data); 682 if (ret_val) 683 return ret_val; 684 685 /* Recalibrate the device back to 0 */ 686 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0); 687 if (ret_val) 688 return ret_val; 689 690 return ret_val; 691 } 692 693 /** 694 * igc_read_xmdio_reg - Read XMDIO register 695 * @hw: pointer to the HW structure 696 * @addr: XMDIO address to program 697 * @dev_addr: device address to program 698 * @data: value to be read from the EMI address 699 */ 700 static s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, 701 u8 dev_addr, u16 *data) 702 { 703 return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true); 704 } 705 706 /** 707 * igc_write_xmdio_reg - Write XMDIO register 708 * @hw: pointer to the HW structure 709 * @addr: XMDIO address to program 710 * @dev_addr: device address to program 711 * @data: value to be written to the XMDIO address 712 */ 713 static s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, 714 u8 dev_addr, u16 data) 715 { 716 return __igc_access_xmdio_reg(hw, addr, dev_addr, &data, false); 717 } 718 719 /** 720 * igc_write_phy_reg_gpy - Write GPY PHY register 721 * @hw: pointer to the HW structure 722 * @offset: register offset to write to 723 * @data: data to write at register offset 724 * 725 * Acquires semaphore, if necessary, then writes the data to PHY register 726 * at the offset. Release any acquired semaphores before exiting. 727 */ 728 s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data) 729 { 730 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT; 731 s32 ret_val; 732 733 offset = offset & GPY_REG_MASK; 734 735 if (!dev_addr) { 736 ret_val = hw->phy.ops.acquire(hw); 737 if (ret_val) 738 return ret_val; 739 ret_val = igc_write_phy_reg_mdic(hw, offset, data); 740 hw->phy.ops.release(hw); 741 } else { 742 ret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr, 743 data); 744 } 745 746 return ret_val; 747 } 748 749 /** 750 * igc_read_phy_reg_gpy - Read GPY PHY register 751 * @hw: pointer to the HW structure 752 * @offset: lower half is register offset to read to 753 * upper half is MMD to use. 754 * @data: data to read at register offset 755 * 756 * Acquires semaphore, if necessary, then reads the data in the PHY register 757 * at the offset. Release any acquired semaphores before exiting. 758 */ 759 s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data) 760 { 761 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT; 762 s32 ret_val; 763 764 offset = offset & GPY_REG_MASK; 765 766 if (!dev_addr) { 767 ret_val = hw->phy.ops.acquire(hw); 768 if (ret_val) 769 return ret_val; 770 ret_val = igc_read_phy_reg_mdic(hw, offset, data); 771 hw->phy.ops.release(hw); 772 } else { 773 ret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr, 774 data); 775 } 776 777 return ret_val; 778 } 779 780 /** 781 * igc_read_phy_fw_version - Read gPHY firmware version 782 * @hw: pointer to the HW structure 783 */ 784 u16 igc_read_phy_fw_version(struct igc_hw *hw) 785 { 786 struct igc_phy_info *phy = &hw->phy; 787 u16 gphy_version = 0; 788 u16 ret_val; 789 790 /* NVM image version is reported as firmware version for i225 device */ 791 ret_val = phy->ops.read_reg(hw, IGC_GPHY_VERSION, &gphy_version); 792 if (ret_val) 793 hw_dbg("igc_phy: read wrong gphy version\n"); 794 795 return gphy_version; 796 } 797