1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #include "igc_phy.h" 5 6 /* forward declaration */ 7 static s32 igc_phy_setup_autoneg(struct igc_hw *hw); 8 static s32 igc_wait_autoneg(struct igc_hw *hw); 9 10 /** 11 * igc_check_reset_block - Check if PHY reset is blocked 12 * @hw: pointer to the HW structure 13 * 14 * Read the PHY management control register and check whether a PHY reset 15 * is blocked. If a reset is not blocked return 0, otherwise 16 * return IGC_ERR_BLK_PHY_RESET (12). 17 */ 18 s32 igc_check_reset_block(struct igc_hw *hw) 19 { 20 u32 manc; 21 22 manc = rd32(IGC_MANC); 23 24 return (manc & IGC_MANC_BLK_PHY_RST_ON_IDE) ? 25 IGC_ERR_BLK_PHY_RESET : 0; 26 } 27 28 /** 29 * igc_get_phy_id - Retrieve the PHY ID and revision 30 * @hw: pointer to the HW structure 31 * 32 * Reads the PHY registers and stores the PHY ID and possibly the PHY 33 * revision in the hardware structure. 34 */ 35 s32 igc_get_phy_id(struct igc_hw *hw) 36 { 37 struct igc_phy_info *phy = &hw->phy; 38 s32 ret_val = 0; 39 u16 phy_id; 40 41 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 42 if (ret_val) 43 goto out; 44 45 phy->id = (u32)(phy_id << 16); 46 usleep_range(200, 500); 47 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 48 if (ret_val) 49 goto out; 50 51 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 52 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 53 54 out: 55 return ret_val; 56 } 57 58 /** 59 * igc_phy_has_link - Polls PHY for link 60 * @hw: pointer to the HW structure 61 * @iterations: number of times to poll for link 62 * @usec_interval: delay between polling attempts 63 * @success: pointer to whether polling was successful or not 64 * 65 * Polls the PHY status register for link, 'iterations' number of times. 66 */ 67 s32 igc_phy_has_link(struct igc_hw *hw, u32 iterations, 68 u32 usec_interval, bool *success) 69 { 70 u16 i, phy_status; 71 s32 ret_val = 0; 72 73 for (i = 0; i < iterations; i++) { 74 /* Some PHYs require the PHY_STATUS register to be read 75 * twice due to the link bit being sticky. No harm doing 76 * it across the board. 77 */ 78 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 79 if (ret_val && usec_interval > 0) { 80 /* If the first read fails, another entity may have 81 * ownership of the resources, wait and try again to 82 * see if they have relinquished the resources yet. 83 */ 84 if (usec_interval >= 1000) 85 mdelay(usec_interval / 1000); 86 else 87 udelay(usec_interval); 88 } 89 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 90 if (ret_val) 91 break; 92 if (phy_status & MII_SR_LINK_STATUS) 93 break; 94 if (usec_interval >= 1000) 95 mdelay(usec_interval / 1000); 96 else 97 udelay(usec_interval); 98 } 99 100 *success = (i < iterations) ? true : false; 101 102 return ret_val; 103 } 104 105 /** 106 * igc_power_up_phy_copper - Restore copper link in case of PHY power down 107 * @hw: pointer to the HW structure 108 * 109 * In the case of a PHY power down to save power, or to turn off link during a 110 * driver unload, restore the link to previous settings. 111 */ 112 void igc_power_up_phy_copper(struct igc_hw *hw) 113 { 114 u16 mii_reg = 0; 115 116 /* The PHY will retain its settings across a power down/up cycle */ 117 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 118 mii_reg &= ~MII_CR_POWER_DOWN; 119 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 120 } 121 122 /** 123 * igc_power_down_phy_copper - Power down copper PHY 124 * @hw: pointer to the HW structure 125 * 126 * Power down PHY to save power when interface is down and wake on lan 127 * is not enabled. 128 */ 129 void igc_power_down_phy_copper(struct igc_hw *hw) 130 { 131 u16 mii_reg = 0; 132 133 /* The PHY will retain its settings across a power down/up cycle */ 134 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 135 mii_reg |= MII_CR_POWER_DOWN; 136 137 /* Temporary workaround - should be removed when PHY will implement 138 * IEEE registers as properly 139 */ 140 /* hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);*/ 141 usleep_range(1000, 2000); 142 } 143 144 /** 145 * igc_check_downshift - Checks whether a downshift in speed occurred 146 * @hw: pointer to the HW structure 147 * 148 * Success returns 0, Failure returns 1 149 * 150 * A downshift is detected by querying the PHY link health. 151 */ 152 s32 igc_check_downshift(struct igc_hw *hw) 153 { 154 struct igc_phy_info *phy = &hw->phy; 155 u16 phy_data, offset, mask; 156 s32 ret_val; 157 158 switch (phy->type) { 159 case igc_phy_i225: 160 default: 161 /* speed downshift not supported */ 162 phy->speed_downgraded = false; 163 ret_val = 0; 164 goto out; 165 } 166 167 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 168 169 if (!ret_val) 170 phy->speed_downgraded = (phy_data & mask) ? true : false; 171 172 out: 173 return ret_val; 174 } 175 176 /** 177 * igc_phy_hw_reset - PHY hardware reset 178 * @hw: pointer to the HW structure 179 * 180 * Verify the reset block is not blocking us from resetting. Acquire 181 * semaphore (if necessary) and read/set/write the device control reset 182 * bit in the PHY. Wait the appropriate delay time for the device to 183 * reset and release the semaphore (if necessary). 184 */ 185 s32 igc_phy_hw_reset(struct igc_hw *hw) 186 { 187 struct igc_phy_info *phy = &hw->phy; 188 s32 ret_val; 189 u32 ctrl; 190 191 ret_val = igc_check_reset_block(hw); 192 if (ret_val) { 193 ret_val = 0; 194 goto out; 195 } 196 197 ret_val = phy->ops.acquire(hw); 198 if (ret_val) 199 goto out; 200 201 ctrl = rd32(IGC_CTRL); 202 wr32(IGC_CTRL, ctrl | IGC_CTRL_PHY_RST); 203 wrfl(); 204 205 udelay(phy->reset_delay_us); 206 207 wr32(IGC_CTRL, ctrl); 208 wrfl(); 209 210 usleep_range(1500, 2000); 211 212 phy->ops.release(hw); 213 214 out: 215 return ret_val; 216 } 217 218 /** 219 * igc_copper_link_autoneg - Setup/Enable autoneg for copper link 220 * @hw: pointer to the HW structure 221 * 222 * Performs initial bounds checking on autoneg advertisement parameter, then 223 * configure to advertise the full capability. Setup the PHY to autoneg 224 * and restart the negotiation process between the link partner. If 225 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 226 */ 227 static s32 igc_copper_link_autoneg(struct igc_hw *hw) 228 { 229 struct igc_phy_info *phy = &hw->phy; 230 u16 phy_ctrl; 231 s32 ret_val; 232 233 /* Perform some bounds checking on the autoneg advertisement 234 * parameter. 235 */ 236 phy->autoneg_advertised &= phy->autoneg_mask; 237 238 /* If autoneg_advertised is zero, we assume it was not defaulted 239 * by the calling code so we set to advertise full capability. 240 */ 241 if (phy->autoneg_advertised == 0) 242 phy->autoneg_advertised = phy->autoneg_mask; 243 244 hw_dbg("Reconfiguring auto-neg advertisement params\n"); 245 ret_val = igc_phy_setup_autoneg(hw); 246 if (ret_val) { 247 hw_dbg("Error Setting up Auto-Negotiation\n"); 248 goto out; 249 } 250 hw_dbg("Restarting Auto-Neg\n"); 251 252 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 253 * the Auto Neg Restart bit in the PHY control register. 254 */ 255 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 256 if (ret_val) 257 goto out; 258 259 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 260 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 261 if (ret_val) 262 goto out; 263 264 /* Does the user want to wait for Auto-Neg to complete here, or 265 * check at a later time (for example, callback routine). 266 */ 267 if (phy->autoneg_wait_to_complete) { 268 ret_val = igc_wait_autoneg(hw); 269 if (ret_val) { 270 hw_dbg("Error while waiting for autoneg to complete\n"); 271 goto out; 272 } 273 } 274 275 hw->mac.get_link_status = true; 276 277 out: 278 return ret_val; 279 } 280 281 /** 282 * igc_wait_autoneg - Wait for auto-neg completion 283 * @hw: pointer to the HW structure 284 * 285 * Waits for auto-negotiation to complete or for the auto-negotiation time 286 * limit to expire, which ever happens first. 287 */ 288 static s32 igc_wait_autoneg(struct igc_hw *hw) 289 { 290 u16 i, phy_status; 291 s32 ret_val = 0; 292 293 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 294 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 295 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 296 if (ret_val) 297 break; 298 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 299 if (ret_val) 300 break; 301 if (phy_status & MII_SR_AUTONEG_COMPLETE) 302 break; 303 msleep(100); 304 } 305 306 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 307 * has completed. 308 */ 309 return ret_val; 310 } 311 312 /** 313 * igc_phy_setup_autoneg - Configure PHY for auto-negotiation 314 * @hw: pointer to the HW structure 315 * 316 * Reads the MII auto-neg advertisement register and/or the 1000T control 317 * register and if the PHY is already setup for auto-negotiation, then 318 * return successful. Otherwise, setup advertisement and flow control to 319 * the appropriate values for the wanted auto-negotiation. 320 */ 321 static s32 igc_phy_setup_autoneg(struct igc_hw *hw) 322 { 323 struct igc_phy_info *phy = &hw->phy; 324 u16 aneg_multigbt_an_ctrl = 0; 325 u16 mii_1000t_ctrl_reg = 0; 326 u16 mii_autoneg_adv_reg; 327 s32 ret_val; 328 329 phy->autoneg_advertised &= phy->autoneg_mask; 330 331 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 332 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 333 if (ret_val) 334 return ret_val; 335 336 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 337 /* Read the MII 1000Base-T Control Register (Address 9). */ 338 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 339 &mii_1000t_ctrl_reg); 340 if (ret_val) 341 return ret_val; 342 } 343 344 if ((phy->autoneg_mask & ADVERTISE_2500_FULL) && 345 hw->phy.id == I225_I_PHY_ID) { 346 /* Read the MULTI GBT AN Control Register - reg 7.32 */ 347 ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK << 348 MMD_DEVADDR_SHIFT) | 349 ANEG_MULTIGBT_AN_CTRL, 350 &aneg_multigbt_an_ctrl); 351 352 if (ret_val) 353 return ret_val; 354 } 355 356 /* Need to parse both autoneg_advertised and fc and set up 357 * the appropriate PHY registers. First we will parse for 358 * autoneg_advertised software override. Since we can advertise 359 * a plethora of combinations, we need to check each bit 360 * individually. 361 */ 362 363 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 364 * Advertisement Register (Address 4) and the 1000 mb speed bits in 365 * the 1000Base-T Control Register (Address 9). 366 */ 367 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 368 NWAY_AR_100TX_HD_CAPS | 369 NWAY_AR_10T_FD_CAPS | 370 NWAY_AR_10T_HD_CAPS); 371 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 372 373 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); 374 375 /* Do we want to advertise 10 Mb Half Duplex? */ 376 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 377 hw_dbg("Advertise 10mb Half duplex\n"); 378 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 379 } 380 381 /* Do we want to advertise 10 Mb Full Duplex? */ 382 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 383 hw_dbg("Advertise 10mb Full duplex\n"); 384 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 385 } 386 387 /* Do we want to advertise 100 Mb Half Duplex? */ 388 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 389 hw_dbg("Advertise 100mb Half duplex\n"); 390 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 391 } 392 393 /* Do we want to advertise 100 Mb Full Duplex? */ 394 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 395 hw_dbg("Advertise 100mb Full duplex\n"); 396 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 397 } 398 399 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 400 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 401 hw_dbg("Advertise 1000mb Half duplex request denied!\n"); 402 403 /* Do we want to advertise 1000 Mb Full Duplex? */ 404 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 405 hw_dbg("Advertise 1000mb Full duplex\n"); 406 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 407 } 408 409 /* We do not allow the Phy to advertise 2500 Mb Half Duplex */ 410 if (phy->autoneg_advertised & ADVERTISE_2500_HALF) 411 hw_dbg("Advertise 2500mb Half duplex request denied!\n"); 412 413 /* Do we want to advertise 2500 Mb Full Duplex? */ 414 if (phy->autoneg_advertised & ADVERTISE_2500_FULL) { 415 hw_dbg("Advertise 2500mb Full duplex\n"); 416 aneg_multigbt_an_ctrl |= CR_2500T_FD_CAPS; 417 } else { 418 aneg_multigbt_an_ctrl &= ~CR_2500T_FD_CAPS; 419 } 420 421 /* Check for a software override of the flow control settings, and 422 * setup the PHY advertisement registers accordingly. If 423 * auto-negotiation is enabled, then software will have to set the 424 * "PAUSE" bits to the correct value in the Auto-Negotiation 425 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 426 * negotiation. 427 * 428 * The possible values of the "fc" parameter are: 429 * 0: Flow control is completely disabled 430 * 1: Rx flow control is enabled (we can receive pause frames 431 * but not send pause frames). 432 * 2: Tx flow control is enabled (we can send pause frames 433 * but we do not support receiving pause frames). 434 * 3: Both Rx and Tx flow control (symmetric) are enabled. 435 * other: No software override. The flow control configuration 436 * in the EEPROM is used. 437 */ 438 switch (hw->fc.current_mode) { 439 case igc_fc_none: 440 /* Flow control (Rx & Tx) is completely disabled by a 441 * software over-ride. 442 */ 443 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 444 break; 445 case igc_fc_rx_pause: 446 /* Rx Flow control is enabled, and Tx Flow control is 447 * disabled, by a software over-ride. 448 * 449 * Since there really isn't a way to advertise that we are 450 * capable of Rx Pause ONLY, we will advertise that we 451 * support both symmetric and asymmetric Rx PAUSE. Later 452 * (in igc_config_fc_after_link_up) we will disable the 453 * hw's ability to send PAUSE frames. 454 */ 455 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 456 break; 457 case igc_fc_tx_pause: 458 /* Tx Flow control is enabled, and Rx Flow control is 459 * disabled, by a software over-ride. 460 */ 461 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 462 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 463 break; 464 case igc_fc_full: 465 /* Flow control (both Rx and Tx) is enabled by a software 466 * over-ride. 467 */ 468 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 469 break; 470 default: 471 hw_dbg("Flow control param set incorrectly\n"); 472 return -IGC_ERR_CONFIG; 473 } 474 475 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 476 if (ret_val) 477 return ret_val; 478 479 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 480 481 if (phy->autoneg_mask & ADVERTISE_1000_FULL) 482 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, 483 mii_1000t_ctrl_reg); 484 485 if ((phy->autoneg_mask & ADVERTISE_2500_FULL) && 486 hw->phy.id == I225_I_PHY_ID) 487 ret_val = phy->ops.write_reg(hw, 488 (STANDARD_AN_REG_MASK << 489 MMD_DEVADDR_SHIFT) | 490 ANEG_MULTIGBT_AN_CTRL, 491 aneg_multigbt_an_ctrl); 492 493 return ret_val; 494 } 495 496 /** 497 * igc_setup_copper_link - Configure copper link settings 498 * @hw: pointer to the HW structure 499 * 500 * Calls the appropriate function to configure the link for auto-neg or forced 501 * speed and duplex. Then we check for link, once link is established calls 502 * to configure collision distance and flow control are called. If link is 503 * not established, we return -IGC_ERR_PHY (-2). 504 */ 505 s32 igc_setup_copper_link(struct igc_hw *hw) 506 { 507 s32 ret_val = 0; 508 bool link; 509 510 if (hw->mac.autoneg) { 511 /* Setup autoneg and flow control advertisement and perform 512 * autonegotiation. 513 */ 514 ret_val = igc_copper_link_autoneg(hw); 515 if (ret_val) 516 goto out; 517 } else { 518 /* PHY will be set to 10H, 10F, 100H or 100F 519 * depending on user settings. 520 */ 521 hw_dbg("Forcing Speed and Duplex\n"); 522 ret_val = hw->phy.ops.force_speed_duplex(hw); 523 if (ret_val) { 524 hw_dbg("Error Forcing Speed and Duplex\n"); 525 goto out; 526 } 527 } 528 529 /* Check link status. Wait up to 100 microseconds for link to become 530 * valid. 531 */ 532 ret_val = igc_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link); 533 if (ret_val) 534 goto out; 535 536 if (link) { 537 hw_dbg("Valid link established!!!\n"); 538 igc_config_collision_dist(hw); 539 ret_val = igc_config_fc_after_link_up(hw); 540 } else { 541 hw_dbg("Unable to establish link!!!\n"); 542 } 543 544 out: 545 return ret_val; 546 } 547 548 /** 549 * igc_read_phy_reg_mdic - Read MDI control register 550 * @hw: pointer to the HW structure 551 * @offset: register offset to be read 552 * @data: pointer to the read data 553 * 554 * Reads the MDI control register in the PHY at offset and stores the 555 * information read to data. 556 */ 557 static s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data) 558 { 559 struct igc_phy_info *phy = &hw->phy; 560 u32 i, mdic = 0; 561 s32 ret_val = 0; 562 563 if (offset > MAX_PHY_REG_ADDRESS) { 564 hw_dbg("PHY Address %d is out of range\n", offset); 565 ret_val = -IGC_ERR_PARAM; 566 goto out; 567 } 568 569 /* Set up Op-code, Phy Address, and register offset in the MDI 570 * Control register. The MAC will take care of interfacing with the 571 * PHY to retrieve the desired data. 572 */ 573 mdic = ((offset << IGC_MDIC_REG_SHIFT) | 574 (phy->addr << IGC_MDIC_PHY_SHIFT) | 575 (IGC_MDIC_OP_READ)); 576 577 wr32(IGC_MDIC, mdic); 578 579 /* Poll the ready bit to see if the MDI read completed 580 * Increasing the time out as testing showed failures with 581 * the lower time out 582 */ 583 for (i = 0; i < IGC_GEN_POLL_TIMEOUT; i++) { 584 usleep_range(500, 1000); 585 mdic = rd32(IGC_MDIC); 586 if (mdic & IGC_MDIC_READY) 587 break; 588 } 589 if (!(mdic & IGC_MDIC_READY)) { 590 hw_dbg("MDI Read did not complete\n"); 591 ret_val = -IGC_ERR_PHY; 592 goto out; 593 } 594 if (mdic & IGC_MDIC_ERROR) { 595 hw_dbg("MDI Error\n"); 596 ret_val = -IGC_ERR_PHY; 597 goto out; 598 } 599 *data = (u16)mdic; 600 601 out: 602 return ret_val; 603 } 604 605 /** 606 * igc_write_phy_reg_mdic - Write MDI control register 607 * @hw: pointer to the HW structure 608 * @offset: register offset to write to 609 * @data: data to write to register at offset 610 * 611 * Writes data to MDI control register in the PHY at offset. 612 */ 613 static s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data) 614 { 615 struct igc_phy_info *phy = &hw->phy; 616 u32 i, mdic = 0; 617 s32 ret_val = 0; 618 619 if (offset > MAX_PHY_REG_ADDRESS) { 620 hw_dbg("PHY Address %d is out of range\n", offset); 621 ret_val = -IGC_ERR_PARAM; 622 goto out; 623 } 624 625 /* Set up Op-code, Phy Address, and register offset in the MDI 626 * Control register. The MAC will take care of interfacing with the 627 * PHY to write the desired data. 628 */ 629 mdic = (((u32)data) | 630 (offset << IGC_MDIC_REG_SHIFT) | 631 (phy->addr << IGC_MDIC_PHY_SHIFT) | 632 (IGC_MDIC_OP_WRITE)); 633 634 wr32(IGC_MDIC, mdic); 635 636 /* Poll the ready bit to see if the MDI read completed 637 * Increasing the time out as testing showed failures with 638 * the lower time out 639 */ 640 for (i = 0; i < IGC_GEN_POLL_TIMEOUT; i++) { 641 usleep_range(500, 1000); 642 mdic = rd32(IGC_MDIC); 643 if (mdic & IGC_MDIC_READY) 644 break; 645 } 646 if (!(mdic & IGC_MDIC_READY)) { 647 hw_dbg("MDI Write did not complete\n"); 648 ret_val = -IGC_ERR_PHY; 649 goto out; 650 } 651 if (mdic & IGC_MDIC_ERROR) { 652 hw_dbg("MDI Error\n"); 653 ret_val = -IGC_ERR_PHY; 654 goto out; 655 } 656 657 out: 658 return ret_val; 659 } 660 661 /** 662 * __igc_access_xmdio_reg - Read/write XMDIO register 663 * @hw: pointer to the HW structure 664 * @address: XMDIO address to program 665 * @dev_addr: device address to program 666 * @data: pointer to value to read/write from/to the XMDIO address 667 * @read: boolean flag to indicate read or write 668 */ 669 static s32 __igc_access_xmdio_reg(struct igc_hw *hw, u16 address, 670 u8 dev_addr, u16 *data, bool read) 671 { 672 s32 ret_val; 673 674 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr); 675 if (ret_val) 676 return ret_val; 677 678 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address); 679 if (ret_val) 680 return ret_val; 681 682 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA | 683 dev_addr); 684 if (ret_val) 685 return ret_val; 686 687 if (read) 688 ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data); 689 else 690 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data); 691 if (ret_val) 692 return ret_val; 693 694 /* Recalibrate the device back to 0 */ 695 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0); 696 if (ret_val) 697 return ret_val; 698 699 return ret_val; 700 } 701 702 /** 703 * igc_read_xmdio_reg - Read XMDIO register 704 * @hw: pointer to the HW structure 705 * @addr: XMDIO address to program 706 * @dev_addr: device address to program 707 * @data: value to be read from the EMI address 708 */ 709 static s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, 710 u8 dev_addr, u16 *data) 711 { 712 return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true); 713 } 714 715 /** 716 * igc_write_xmdio_reg - Write XMDIO register 717 * @hw: pointer to the HW structure 718 * @addr: XMDIO address to program 719 * @dev_addr: device address to program 720 * @data: value to be written to the XMDIO address 721 */ 722 static s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, 723 u8 dev_addr, u16 data) 724 { 725 return __igc_access_xmdio_reg(hw, addr, dev_addr, &data, false); 726 } 727 728 /** 729 * igc_write_phy_reg_gpy - Write GPY PHY register 730 * @hw: pointer to the HW structure 731 * @offset: register offset to write to 732 * @data: data to write at register offset 733 * 734 * Acquires semaphore, if necessary, then writes the data to PHY register 735 * at the offset. Release any acquired semaphores before exiting. 736 */ 737 s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data) 738 { 739 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT; 740 s32 ret_val; 741 742 offset = offset & GPY_REG_MASK; 743 744 if (!dev_addr) { 745 ret_val = hw->phy.ops.acquire(hw); 746 if (ret_val) 747 return ret_val; 748 ret_val = igc_write_phy_reg_mdic(hw, offset, data); 749 if (ret_val) 750 return ret_val; 751 hw->phy.ops.release(hw); 752 } else { 753 ret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr, 754 data); 755 } 756 757 return ret_val; 758 } 759 760 /** 761 * igc_read_phy_reg_gpy - Read GPY PHY register 762 * @hw: pointer to the HW structure 763 * @offset: lower half is register offset to read to 764 * upper half is MMD to use. 765 * @data: data to read at register offset 766 * 767 * Acquires semaphore, if necessary, then reads the data in the PHY register 768 * at the offset. Release any acquired semaphores before exiting. 769 */ 770 s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data) 771 { 772 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT; 773 s32 ret_val; 774 775 offset = offset & GPY_REG_MASK; 776 777 if (!dev_addr) { 778 ret_val = hw->phy.ops.acquire(hw); 779 if (ret_val) 780 return ret_val; 781 ret_val = igc_read_phy_reg_mdic(hw, offset, data); 782 if (ret_val) 783 return ret_val; 784 hw->phy.ops.release(hw); 785 } else { 786 ret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr, 787 data); 788 } 789 790 return ret_val; 791 } 792