1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #include "igc_phy.h" 5 6 /* forward declaration */ 7 static s32 igc_phy_setup_autoneg(struct igc_hw *hw); 8 static s32 igc_wait_autoneg(struct igc_hw *hw); 9 10 /** 11 * igc_check_reset_block - Check if PHY reset is blocked 12 * @hw: pointer to the HW structure 13 * 14 * Read the PHY management control register and check whether a PHY reset 15 * is blocked. If a reset is not blocked return 0, otherwise 16 * return IGC_ERR_BLK_PHY_RESET (12). 17 */ 18 s32 igc_check_reset_block(struct igc_hw *hw) 19 { 20 u32 manc; 21 22 manc = rd32(IGC_MANC); 23 24 return (manc & IGC_MANC_BLK_PHY_RST_ON_IDE) ? 25 IGC_ERR_BLK_PHY_RESET : 0; 26 } 27 28 /** 29 * igc_get_phy_id - Retrieve the PHY ID and revision 30 * @hw: pointer to the HW structure 31 * 32 * Reads the PHY registers and stores the PHY ID and possibly the PHY 33 * revision in the hardware structure. 34 */ 35 s32 igc_get_phy_id(struct igc_hw *hw) 36 { 37 struct igc_phy_info *phy = &hw->phy; 38 s32 ret_val = 0; 39 u16 phy_id; 40 41 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 42 if (ret_val) 43 goto out; 44 45 phy->id = (u32)(phy_id << 16); 46 usleep_range(200, 500); 47 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 48 if (ret_val) 49 goto out; 50 51 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 52 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 53 54 out: 55 return ret_val; 56 } 57 58 /** 59 * igc_phy_has_link - Polls PHY for link 60 * @hw: pointer to the HW structure 61 * @iterations: number of times to poll for link 62 * @usec_interval: delay between polling attempts 63 * @success: pointer to whether polling was successful or not 64 * 65 * Polls the PHY status register for link, 'iterations' number of times. 66 */ 67 s32 igc_phy_has_link(struct igc_hw *hw, u32 iterations, 68 u32 usec_interval, bool *success) 69 { 70 u16 i, phy_status; 71 s32 ret_val = 0; 72 73 for (i = 0; i < iterations; i++) { 74 /* Some PHYs require the PHY_STATUS register to be read 75 * twice due to the link bit being sticky. No harm doing 76 * it across the board. 77 */ 78 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 79 if (ret_val && usec_interval > 0) { 80 /* If the first read fails, another entity may have 81 * ownership of the resources, wait and try again to 82 * see if they have relinquished the resources yet. 83 */ 84 if (usec_interval >= 1000) 85 mdelay(usec_interval / 1000); 86 else 87 udelay(usec_interval); 88 } 89 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 90 if (ret_val) 91 break; 92 if (phy_status & MII_SR_LINK_STATUS) 93 break; 94 if (usec_interval >= 1000) 95 mdelay(usec_interval / 1000); 96 else 97 udelay(usec_interval); 98 } 99 100 *success = (i < iterations) ? true : false; 101 102 return ret_val; 103 } 104 105 /** 106 * igc_power_up_phy_copper - Restore copper link in case of PHY power down 107 * @hw: pointer to the HW structure 108 * 109 * In the case of a PHY power down to save power, or to turn off link during a 110 * driver unload, restore the link to previous settings. 111 */ 112 void igc_power_up_phy_copper(struct igc_hw *hw) 113 { 114 u16 mii_reg = 0; 115 116 /* The PHY will retain its settings across a power down/up cycle */ 117 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 118 mii_reg &= ~MII_CR_POWER_DOWN; 119 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 120 } 121 122 /** 123 * igc_power_down_phy_copper - Power down copper PHY 124 * @hw: pointer to the HW structure 125 * 126 * Power down PHY to save power when interface is down and wake on lan 127 * is not enabled. 128 */ 129 void igc_power_down_phy_copper(struct igc_hw *hw) 130 { 131 u16 mii_reg = 0; 132 133 /* The PHY will retain its settings across a power down/up cycle */ 134 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 135 mii_reg |= MII_CR_POWER_DOWN; 136 137 /* Temporary workaround - should be removed when PHY will implement 138 * IEEE registers as properly 139 */ 140 /* hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);*/ 141 usleep_range(1000, 2000); 142 } 143 144 /** 145 * igc_check_downshift - Checks whether a downshift in speed occurred 146 * @hw: pointer to the HW structure 147 * 148 * Success returns 0, Failure returns 1 149 * 150 * A downshift is detected by querying the PHY link health. 151 */ 152 s32 igc_check_downshift(struct igc_hw *hw) 153 { 154 struct igc_phy_info *phy = &hw->phy; 155 s32 ret_val; 156 157 switch (phy->type) { 158 case igc_phy_i225: 159 default: 160 /* speed downshift not supported */ 161 phy->speed_downgraded = false; 162 ret_val = 0; 163 } 164 165 return ret_val; 166 } 167 168 /** 169 * igc_phy_hw_reset - PHY hardware reset 170 * @hw: pointer to the HW structure 171 * 172 * Verify the reset block is not blocking us from resetting. Acquire 173 * semaphore (if necessary) and read/set/write the device control reset 174 * bit in the PHY. Wait the appropriate delay time for the device to 175 * reset and release the semaphore (if necessary). 176 */ 177 s32 igc_phy_hw_reset(struct igc_hw *hw) 178 { 179 struct igc_phy_info *phy = &hw->phy; 180 s32 ret_val; 181 u32 ctrl; 182 183 ret_val = igc_check_reset_block(hw); 184 if (ret_val) { 185 ret_val = 0; 186 goto out; 187 } 188 189 ret_val = phy->ops.acquire(hw); 190 if (ret_val) 191 goto out; 192 193 ctrl = rd32(IGC_CTRL); 194 wr32(IGC_CTRL, ctrl | IGC_CTRL_PHY_RST); 195 wrfl(); 196 197 udelay(phy->reset_delay_us); 198 199 wr32(IGC_CTRL, ctrl); 200 wrfl(); 201 202 usleep_range(1500, 2000); 203 204 phy->ops.release(hw); 205 206 out: 207 return ret_val; 208 } 209 210 /** 211 * igc_copper_link_autoneg - Setup/Enable autoneg for copper link 212 * @hw: pointer to the HW structure 213 * 214 * Performs initial bounds checking on autoneg advertisement parameter, then 215 * configure to advertise the full capability. Setup the PHY to autoneg 216 * and restart the negotiation process between the link partner. If 217 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 218 */ 219 static s32 igc_copper_link_autoneg(struct igc_hw *hw) 220 { 221 struct igc_phy_info *phy = &hw->phy; 222 u16 phy_ctrl; 223 s32 ret_val; 224 225 /* Perform some bounds checking on the autoneg advertisement 226 * parameter. 227 */ 228 phy->autoneg_advertised &= phy->autoneg_mask; 229 230 /* If autoneg_advertised is zero, we assume it was not defaulted 231 * by the calling code so we set to advertise full capability. 232 */ 233 if (phy->autoneg_advertised == 0) 234 phy->autoneg_advertised = phy->autoneg_mask; 235 236 hw_dbg("Reconfiguring auto-neg advertisement params\n"); 237 ret_val = igc_phy_setup_autoneg(hw); 238 if (ret_val) { 239 hw_dbg("Error Setting up Auto-Negotiation\n"); 240 goto out; 241 } 242 hw_dbg("Restarting Auto-Neg\n"); 243 244 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 245 * the Auto Neg Restart bit in the PHY control register. 246 */ 247 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 248 if (ret_val) 249 goto out; 250 251 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 252 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 253 if (ret_val) 254 goto out; 255 256 /* Does the user want to wait for Auto-Neg to complete here, or 257 * check at a later time (for example, callback routine). 258 */ 259 if (phy->autoneg_wait_to_complete) { 260 ret_val = igc_wait_autoneg(hw); 261 if (ret_val) { 262 hw_dbg("Error while waiting for autoneg to complete\n"); 263 goto out; 264 } 265 } 266 267 hw->mac.get_link_status = true; 268 269 out: 270 return ret_val; 271 } 272 273 /** 274 * igc_wait_autoneg - Wait for auto-neg completion 275 * @hw: pointer to the HW structure 276 * 277 * Waits for auto-negotiation to complete or for the auto-negotiation time 278 * limit to expire, which ever happens first. 279 */ 280 static s32 igc_wait_autoneg(struct igc_hw *hw) 281 { 282 u16 i, phy_status; 283 s32 ret_val = 0; 284 285 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 286 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 287 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 288 if (ret_val) 289 break; 290 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 291 if (ret_val) 292 break; 293 if (phy_status & MII_SR_AUTONEG_COMPLETE) 294 break; 295 msleep(100); 296 } 297 298 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 299 * has completed. 300 */ 301 return ret_val; 302 } 303 304 /** 305 * igc_phy_setup_autoneg - Configure PHY for auto-negotiation 306 * @hw: pointer to the HW structure 307 * 308 * Reads the MII auto-neg advertisement register and/or the 1000T control 309 * register and if the PHY is already setup for auto-negotiation, then 310 * return successful. Otherwise, setup advertisement and flow control to 311 * the appropriate values for the wanted auto-negotiation. 312 */ 313 static s32 igc_phy_setup_autoneg(struct igc_hw *hw) 314 { 315 struct igc_phy_info *phy = &hw->phy; 316 u16 aneg_multigbt_an_ctrl = 0; 317 u16 mii_1000t_ctrl_reg = 0; 318 u16 mii_autoneg_adv_reg; 319 s32 ret_val; 320 321 phy->autoneg_advertised &= phy->autoneg_mask; 322 323 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 324 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 325 if (ret_val) 326 return ret_val; 327 328 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 329 /* Read the MII 1000Base-T Control Register (Address 9). */ 330 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 331 &mii_1000t_ctrl_reg); 332 if (ret_val) 333 return ret_val; 334 } 335 336 if ((phy->autoneg_mask & ADVERTISE_2500_FULL) && 337 hw->phy.id == I225_I_PHY_ID) { 338 /* Read the MULTI GBT AN Control Register - reg 7.32 */ 339 ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK << 340 MMD_DEVADDR_SHIFT) | 341 ANEG_MULTIGBT_AN_CTRL, 342 &aneg_multigbt_an_ctrl); 343 344 if (ret_val) 345 return ret_val; 346 } 347 348 /* Need to parse both autoneg_advertised and fc and set up 349 * the appropriate PHY registers. First we will parse for 350 * autoneg_advertised software override. Since we can advertise 351 * a plethora of combinations, we need to check each bit 352 * individually. 353 */ 354 355 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 356 * Advertisement Register (Address 4) and the 1000 mb speed bits in 357 * the 1000Base-T Control Register (Address 9). 358 */ 359 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 360 NWAY_AR_100TX_HD_CAPS | 361 NWAY_AR_10T_FD_CAPS | 362 NWAY_AR_10T_HD_CAPS); 363 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 364 365 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); 366 367 /* Do we want to advertise 10 Mb Half Duplex? */ 368 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 369 hw_dbg("Advertise 10mb Half duplex\n"); 370 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 371 } 372 373 /* Do we want to advertise 10 Mb Full Duplex? */ 374 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 375 hw_dbg("Advertise 10mb Full duplex\n"); 376 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 377 } 378 379 /* Do we want to advertise 100 Mb Half Duplex? */ 380 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 381 hw_dbg("Advertise 100mb Half duplex\n"); 382 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 383 } 384 385 /* Do we want to advertise 100 Mb Full Duplex? */ 386 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 387 hw_dbg("Advertise 100mb Full duplex\n"); 388 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 389 } 390 391 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 392 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 393 hw_dbg("Advertise 1000mb Half duplex request denied!\n"); 394 395 /* Do we want to advertise 1000 Mb Full Duplex? */ 396 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 397 hw_dbg("Advertise 1000mb Full duplex\n"); 398 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 399 } 400 401 /* We do not allow the Phy to advertise 2500 Mb Half Duplex */ 402 if (phy->autoneg_advertised & ADVERTISE_2500_HALF) 403 hw_dbg("Advertise 2500mb Half duplex request denied!\n"); 404 405 /* Do we want to advertise 2500 Mb Full Duplex? */ 406 if (phy->autoneg_advertised & ADVERTISE_2500_FULL) { 407 hw_dbg("Advertise 2500mb Full duplex\n"); 408 aneg_multigbt_an_ctrl |= CR_2500T_FD_CAPS; 409 } else { 410 aneg_multigbt_an_ctrl &= ~CR_2500T_FD_CAPS; 411 } 412 413 /* Check for a software override of the flow control settings, and 414 * setup the PHY advertisement registers accordingly. If 415 * auto-negotiation is enabled, then software will have to set the 416 * "PAUSE" bits to the correct value in the Auto-Negotiation 417 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 418 * negotiation. 419 * 420 * The possible values of the "fc" parameter are: 421 * 0: Flow control is completely disabled 422 * 1: Rx flow control is enabled (we can receive pause frames 423 * but not send pause frames). 424 * 2: Tx flow control is enabled (we can send pause frames 425 * but we do not support receiving pause frames). 426 * 3: Both Rx and Tx flow control (symmetric) are enabled. 427 * other: No software override. The flow control configuration 428 * in the EEPROM is used. 429 */ 430 switch (hw->fc.current_mode) { 431 case igc_fc_none: 432 /* Flow control (Rx & Tx) is completely disabled by a 433 * software over-ride. 434 */ 435 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 436 break; 437 case igc_fc_rx_pause: 438 /* Rx Flow control is enabled, and Tx Flow control is 439 * disabled, by a software over-ride. 440 * 441 * Since there really isn't a way to advertise that we are 442 * capable of Rx Pause ONLY, we will advertise that we 443 * support both symmetric and asymmetric Rx PAUSE. Later 444 * (in igc_config_fc_after_link_up) we will disable the 445 * hw's ability to send PAUSE frames. 446 */ 447 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 448 break; 449 case igc_fc_tx_pause: 450 /* Tx Flow control is enabled, and Rx Flow control is 451 * disabled, by a software over-ride. 452 */ 453 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 454 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 455 break; 456 case igc_fc_full: 457 /* Flow control (both Rx and Tx) is enabled by a software 458 * over-ride. 459 */ 460 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 461 break; 462 default: 463 hw_dbg("Flow control param set incorrectly\n"); 464 return -IGC_ERR_CONFIG; 465 } 466 467 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 468 if (ret_val) 469 return ret_val; 470 471 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 472 473 if (phy->autoneg_mask & ADVERTISE_1000_FULL) 474 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, 475 mii_1000t_ctrl_reg); 476 477 if ((phy->autoneg_mask & ADVERTISE_2500_FULL) && 478 hw->phy.id == I225_I_PHY_ID) 479 ret_val = phy->ops.write_reg(hw, 480 (STANDARD_AN_REG_MASK << 481 MMD_DEVADDR_SHIFT) | 482 ANEG_MULTIGBT_AN_CTRL, 483 aneg_multigbt_an_ctrl); 484 485 return ret_val; 486 } 487 488 /** 489 * igc_setup_copper_link - Configure copper link settings 490 * @hw: pointer to the HW structure 491 * 492 * Calls the appropriate function to configure the link for auto-neg or forced 493 * speed and duplex. Then we check for link, once link is established calls 494 * to configure collision distance and flow control are called. If link is 495 * not established, we return -IGC_ERR_PHY (-2). 496 */ 497 s32 igc_setup_copper_link(struct igc_hw *hw) 498 { 499 s32 ret_val = 0; 500 bool link; 501 502 if (hw->mac.autoneg) { 503 /* Setup autoneg and flow control advertisement and perform 504 * autonegotiation. 505 */ 506 ret_val = igc_copper_link_autoneg(hw); 507 if (ret_val) 508 goto out; 509 } else { 510 /* PHY will be set to 10H, 10F, 100H or 100F 511 * depending on user settings. 512 */ 513 hw_dbg("Forcing Speed and Duplex\n"); 514 ret_val = hw->phy.ops.force_speed_duplex(hw); 515 if (ret_val) { 516 hw_dbg("Error Forcing Speed and Duplex\n"); 517 goto out; 518 } 519 } 520 521 /* Check link status. Wait up to 100 microseconds for link to become 522 * valid. 523 */ 524 ret_val = igc_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link); 525 if (ret_val) 526 goto out; 527 528 if (link) { 529 hw_dbg("Valid link established!!!\n"); 530 igc_config_collision_dist(hw); 531 ret_val = igc_config_fc_after_link_up(hw); 532 } else { 533 hw_dbg("Unable to establish link!!!\n"); 534 } 535 536 out: 537 return ret_val; 538 } 539 540 /** 541 * igc_read_phy_reg_mdic - Read MDI control register 542 * @hw: pointer to the HW structure 543 * @offset: register offset to be read 544 * @data: pointer to the read data 545 * 546 * Reads the MDI control register in the PHY at offset and stores the 547 * information read to data. 548 */ 549 static s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data) 550 { 551 struct igc_phy_info *phy = &hw->phy; 552 u32 i, mdic = 0; 553 s32 ret_val = 0; 554 555 if (offset > MAX_PHY_REG_ADDRESS) { 556 hw_dbg("PHY Address %d is out of range\n", offset); 557 ret_val = -IGC_ERR_PARAM; 558 goto out; 559 } 560 561 /* Set up Op-code, Phy Address, and register offset in the MDI 562 * Control register. The MAC will take care of interfacing with the 563 * PHY to retrieve the desired data. 564 */ 565 mdic = ((offset << IGC_MDIC_REG_SHIFT) | 566 (phy->addr << IGC_MDIC_PHY_SHIFT) | 567 (IGC_MDIC_OP_READ)); 568 569 wr32(IGC_MDIC, mdic); 570 571 /* Poll the ready bit to see if the MDI read completed 572 * Increasing the time out as testing showed failures with 573 * the lower time out 574 */ 575 for (i = 0; i < IGC_GEN_POLL_TIMEOUT; i++) { 576 usleep_range(500, 1000); 577 mdic = rd32(IGC_MDIC); 578 if (mdic & IGC_MDIC_READY) 579 break; 580 } 581 if (!(mdic & IGC_MDIC_READY)) { 582 hw_dbg("MDI Read did not complete\n"); 583 ret_val = -IGC_ERR_PHY; 584 goto out; 585 } 586 if (mdic & IGC_MDIC_ERROR) { 587 hw_dbg("MDI Error\n"); 588 ret_val = -IGC_ERR_PHY; 589 goto out; 590 } 591 *data = (u16)mdic; 592 593 out: 594 return ret_val; 595 } 596 597 /** 598 * igc_write_phy_reg_mdic - Write MDI control register 599 * @hw: pointer to the HW structure 600 * @offset: register offset to write to 601 * @data: data to write to register at offset 602 * 603 * Writes data to MDI control register in the PHY at offset. 604 */ 605 static s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data) 606 { 607 struct igc_phy_info *phy = &hw->phy; 608 u32 i, mdic = 0; 609 s32 ret_val = 0; 610 611 if (offset > MAX_PHY_REG_ADDRESS) { 612 hw_dbg("PHY Address %d is out of range\n", offset); 613 ret_val = -IGC_ERR_PARAM; 614 goto out; 615 } 616 617 /* Set up Op-code, Phy Address, and register offset in the MDI 618 * Control register. The MAC will take care of interfacing with the 619 * PHY to write the desired data. 620 */ 621 mdic = (((u32)data) | 622 (offset << IGC_MDIC_REG_SHIFT) | 623 (phy->addr << IGC_MDIC_PHY_SHIFT) | 624 (IGC_MDIC_OP_WRITE)); 625 626 wr32(IGC_MDIC, mdic); 627 628 /* Poll the ready bit to see if the MDI read completed 629 * Increasing the time out as testing showed failures with 630 * the lower time out 631 */ 632 for (i = 0; i < IGC_GEN_POLL_TIMEOUT; i++) { 633 usleep_range(500, 1000); 634 mdic = rd32(IGC_MDIC); 635 if (mdic & IGC_MDIC_READY) 636 break; 637 } 638 if (!(mdic & IGC_MDIC_READY)) { 639 hw_dbg("MDI Write did not complete\n"); 640 ret_val = -IGC_ERR_PHY; 641 goto out; 642 } 643 if (mdic & IGC_MDIC_ERROR) { 644 hw_dbg("MDI Error\n"); 645 ret_val = -IGC_ERR_PHY; 646 goto out; 647 } 648 649 out: 650 return ret_val; 651 } 652 653 /** 654 * __igc_access_xmdio_reg - Read/write XMDIO register 655 * @hw: pointer to the HW structure 656 * @address: XMDIO address to program 657 * @dev_addr: device address to program 658 * @data: pointer to value to read/write from/to the XMDIO address 659 * @read: boolean flag to indicate read or write 660 */ 661 static s32 __igc_access_xmdio_reg(struct igc_hw *hw, u16 address, 662 u8 dev_addr, u16 *data, bool read) 663 { 664 s32 ret_val; 665 666 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr); 667 if (ret_val) 668 return ret_val; 669 670 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address); 671 if (ret_val) 672 return ret_val; 673 674 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA | 675 dev_addr); 676 if (ret_val) 677 return ret_val; 678 679 if (read) 680 ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data); 681 else 682 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data); 683 if (ret_val) 684 return ret_val; 685 686 /* Recalibrate the device back to 0 */ 687 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0); 688 if (ret_val) 689 return ret_val; 690 691 return ret_val; 692 } 693 694 /** 695 * igc_read_xmdio_reg - Read XMDIO register 696 * @hw: pointer to the HW structure 697 * @addr: XMDIO address to program 698 * @dev_addr: device address to program 699 * @data: value to be read from the EMI address 700 */ 701 static s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, 702 u8 dev_addr, u16 *data) 703 { 704 return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true); 705 } 706 707 /** 708 * igc_write_xmdio_reg - Write XMDIO register 709 * @hw: pointer to the HW structure 710 * @addr: XMDIO address to program 711 * @dev_addr: device address to program 712 * @data: value to be written to the XMDIO address 713 */ 714 static s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, 715 u8 dev_addr, u16 data) 716 { 717 return __igc_access_xmdio_reg(hw, addr, dev_addr, &data, false); 718 } 719 720 /** 721 * igc_write_phy_reg_gpy - Write GPY PHY register 722 * @hw: pointer to the HW structure 723 * @offset: register offset to write to 724 * @data: data to write at register offset 725 * 726 * Acquires semaphore, if necessary, then writes the data to PHY register 727 * at the offset. Release any acquired semaphores before exiting. 728 */ 729 s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data) 730 { 731 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT; 732 s32 ret_val; 733 734 offset = offset & GPY_REG_MASK; 735 736 if (!dev_addr) { 737 ret_val = hw->phy.ops.acquire(hw); 738 if (ret_val) 739 return ret_val; 740 ret_val = igc_write_phy_reg_mdic(hw, offset, data); 741 if (ret_val) 742 return ret_val; 743 hw->phy.ops.release(hw); 744 } else { 745 ret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr, 746 data); 747 } 748 749 return ret_val; 750 } 751 752 /** 753 * igc_read_phy_reg_gpy - Read GPY PHY register 754 * @hw: pointer to the HW structure 755 * @offset: lower half is register offset to read to 756 * upper half is MMD to use. 757 * @data: data to read at register offset 758 * 759 * Acquires semaphore, if necessary, then reads the data in the PHY register 760 * at the offset. Release any acquired semaphores before exiting. 761 */ 762 s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data) 763 { 764 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT; 765 s32 ret_val; 766 767 offset = offset & GPY_REG_MASK; 768 769 if (!dev_addr) { 770 ret_val = hw->phy.ops.acquire(hw); 771 if (ret_val) 772 return ret_val; 773 ret_val = igc_read_phy_reg_mdic(hw, offset, data); 774 if (ret_val) 775 return ret_val; 776 hw->phy.ops.release(hw); 777 } else { 778 ret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr, 779 data); 780 } 781 782 return ret_val; 783 } 784