1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #include <linux/module.h> 5 #include <linux/types.h> 6 #include <linux/if_vlan.h> 7 #include <linux/aer.h> 8 9 #include "igc.h" 10 #include "igc_hw.h" 11 12 #define DRV_VERSION "0.0.1-k" 13 #define DRV_SUMMARY "Intel(R) 2.5G Ethernet Linux Driver" 14 15 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 16 17 static int debug = -1; 18 19 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 20 MODULE_DESCRIPTION(DRV_SUMMARY); 21 MODULE_LICENSE("GPL v2"); 22 MODULE_VERSION(DRV_VERSION); 23 module_param(debug, int, 0); 24 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 25 26 char igc_driver_name[] = "igc"; 27 char igc_driver_version[] = DRV_VERSION; 28 static const char igc_driver_string[] = DRV_SUMMARY; 29 static const char igc_copyright[] = 30 "Copyright(c) 2018 Intel Corporation."; 31 32 static const struct igc_info *igc_info_tbl[] = { 33 [board_base] = &igc_base_info, 34 }; 35 36 static const struct pci_device_id igc_pci_tbl[] = { 37 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LM), board_base }, 38 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_V), board_base }, 39 /* required last entry */ 40 {0, } 41 }; 42 43 MODULE_DEVICE_TABLE(pci, igc_pci_tbl); 44 45 /* forward declaration */ 46 static void igc_clean_tx_ring(struct igc_ring *tx_ring); 47 static int igc_sw_init(struct igc_adapter *); 48 static void igc_configure(struct igc_adapter *adapter); 49 static void igc_power_down_link(struct igc_adapter *adapter); 50 static void igc_set_default_mac_filter(struct igc_adapter *adapter); 51 static void igc_set_rx_mode(struct net_device *netdev); 52 static void igc_write_itr(struct igc_q_vector *q_vector); 53 static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector); 54 static void igc_free_q_vector(struct igc_adapter *adapter, int v_idx); 55 static void igc_set_interrupt_capability(struct igc_adapter *adapter, 56 bool msix); 57 static void igc_free_q_vectors(struct igc_adapter *adapter); 58 static void igc_irq_disable(struct igc_adapter *adapter); 59 static void igc_irq_enable(struct igc_adapter *adapter); 60 static void igc_configure_msix(struct igc_adapter *adapter); 61 static bool igc_alloc_mapped_page(struct igc_ring *rx_ring, 62 struct igc_rx_buffer *bi); 63 64 enum latency_range { 65 lowest_latency = 0, 66 low_latency = 1, 67 bulk_latency = 2, 68 latency_invalid = 255 69 }; 70 71 void igc_reset(struct igc_adapter *adapter) 72 { 73 struct pci_dev *pdev = adapter->pdev; 74 struct igc_hw *hw = &adapter->hw; 75 76 hw->mac.ops.reset_hw(hw); 77 78 if (hw->mac.ops.init_hw(hw)) 79 dev_err(&pdev->dev, "Hardware Error\n"); 80 81 if (!netif_running(adapter->netdev)) 82 igc_power_down_link(adapter); 83 84 igc_get_phy_info(hw); 85 } 86 87 /** 88 * igc_power_up_link - Power up the phy/serdes link 89 * @adapter: address of board private structure 90 */ 91 static void igc_power_up_link(struct igc_adapter *adapter) 92 { 93 igc_reset_phy(&adapter->hw); 94 95 if (adapter->hw.phy.media_type == igc_media_type_copper) 96 igc_power_up_phy_copper(&adapter->hw); 97 98 igc_setup_link(&adapter->hw); 99 } 100 101 /** 102 * igc_power_down_link - Power down the phy/serdes link 103 * @adapter: address of board private structure 104 */ 105 static void igc_power_down_link(struct igc_adapter *adapter) 106 { 107 if (adapter->hw.phy.media_type == igc_media_type_copper) 108 igc_power_down_phy_copper_base(&adapter->hw); 109 } 110 111 /** 112 * igc_release_hw_control - release control of the h/w to f/w 113 * @adapter: address of board private structure 114 * 115 * igc_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 116 * For ASF and Pass Through versions of f/w this means that the 117 * driver is no longer loaded. 118 */ 119 static void igc_release_hw_control(struct igc_adapter *adapter) 120 { 121 struct igc_hw *hw = &adapter->hw; 122 u32 ctrl_ext; 123 124 /* Let firmware take over control of h/w */ 125 ctrl_ext = rd32(IGC_CTRL_EXT); 126 wr32(IGC_CTRL_EXT, 127 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD); 128 } 129 130 /** 131 * igc_get_hw_control - get control of the h/w from f/w 132 * @adapter: address of board private structure 133 * 134 * igc_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 135 * For ASF and Pass Through versions of f/w this means that 136 * the driver is loaded. 137 */ 138 static void igc_get_hw_control(struct igc_adapter *adapter) 139 { 140 struct igc_hw *hw = &adapter->hw; 141 u32 ctrl_ext; 142 143 /* Let firmware know the driver has taken over */ 144 ctrl_ext = rd32(IGC_CTRL_EXT); 145 wr32(IGC_CTRL_EXT, 146 ctrl_ext | IGC_CTRL_EXT_DRV_LOAD); 147 } 148 149 /** 150 * igc_free_tx_resources - Free Tx Resources per Queue 151 * @tx_ring: Tx descriptor ring for a specific queue 152 * 153 * Free all transmit software resources 154 */ 155 void igc_free_tx_resources(struct igc_ring *tx_ring) 156 { 157 igc_clean_tx_ring(tx_ring); 158 159 vfree(tx_ring->tx_buffer_info); 160 tx_ring->tx_buffer_info = NULL; 161 162 /* if not set, then don't free */ 163 if (!tx_ring->desc) 164 return; 165 166 dma_free_coherent(tx_ring->dev, tx_ring->size, 167 tx_ring->desc, tx_ring->dma); 168 169 tx_ring->desc = NULL; 170 } 171 172 /** 173 * igc_free_all_tx_resources - Free Tx Resources for All Queues 174 * @adapter: board private structure 175 * 176 * Free all transmit software resources 177 */ 178 static void igc_free_all_tx_resources(struct igc_adapter *adapter) 179 { 180 int i; 181 182 for (i = 0; i < adapter->num_tx_queues; i++) 183 igc_free_tx_resources(adapter->tx_ring[i]); 184 } 185 186 /** 187 * igc_clean_tx_ring - Free Tx Buffers 188 * @tx_ring: ring to be cleaned 189 */ 190 static void igc_clean_tx_ring(struct igc_ring *tx_ring) 191 { 192 u16 i = tx_ring->next_to_clean; 193 struct igc_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 194 195 while (i != tx_ring->next_to_use) { 196 union igc_adv_tx_desc *eop_desc, *tx_desc; 197 198 /* Free all the Tx ring sk_buffs */ 199 dev_kfree_skb_any(tx_buffer->skb); 200 201 /* unmap skb header data */ 202 dma_unmap_single(tx_ring->dev, 203 dma_unmap_addr(tx_buffer, dma), 204 dma_unmap_len(tx_buffer, len), 205 DMA_TO_DEVICE); 206 207 /* check for eop_desc to determine the end of the packet */ 208 eop_desc = tx_buffer->next_to_watch; 209 tx_desc = IGC_TX_DESC(tx_ring, i); 210 211 /* unmap remaining buffers */ 212 while (tx_desc != eop_desc) { 213 tx_buffer++; 214 tx_desc++; 215 i++; 216 if (unlikely(i == tx_ring->count)) { 217 i = 0; 218 tx_buffer = tx_ring->tx_buffer_info; 219 tx_desc = IGC_TX_DESC(tx_ring, 0); 220 } 221 222 /* unmap any remaining paged data */ 223 if (dma_unmap_len(tx_buffer, len)) 224 dma_unmap_page(tx_ring->dev, 225 dma_unmap_addr(tx_buffer, dma), 226 dma_unmap_len(tx_buffer, len), 227 DMA_TO_DEVICE); 228 } 229 230 /* move us one more past the eop_desc for start of next pkt */ 231 tx_buffer++; 232 i++; 233 if (unlikely(i == tx_ring->count)) { 234 i = 0; 235 tx_buffer = tx_ring->tx_buffer_info; 236 } 237 } 238 239 /* reset BQL for queue */ 240 netdev_tx_reset_queue(txring_txq(tx_ring)); 241 242 /* reset next_to_use and next_to_clean */ 243 tx_ring->next_to_use = 0; 244 tx_ring->next_to_clean = 0; 245 } 246 247 /** 248 * igc_clean_all_tx_rings - Free Tx Buffers for all queues 249 * @adapter: board private structure 250 */ 251 static void igc_clean_all_tx_rings(struct igc_adapter *adapter) 252 { 253 int i; 254 255 for (i = 0; i < adapter->num_tx_queues; i++) 256 if (adapter->tx_ring[i]) 257 igc_clean_tx_ring(adapter->tx_ring[i]); 258 } 259 260 /** 261 * igc_setup_tx_resources - allocate Tx resources (Descriptors) 262 * @tx_ring: tx descriptor ring (for a specific queue) to setup 263 * 264 * Return 0 on success, negative on failure 265 */ 266 int igc_setup_tx_resources(struct igc_ring *tx_ring) 267 { 268 struct device *dev = tx_ring->dev; 269 int size = 0; 270 271 size = sizeof(struct igc_tx_buffer) * tx_ring->count; 272 tx_ring->tx_buffer_info = vzalloc(size); 273 if (!tx_ring->tx_buffer_info) 274 goto err; 275 276 /* round up to nearest 4K */ 277 tx_ring->size = tx_ring->count * sizeof(union igc_adv_tx_desc); 278 tx_ring->size = ALIGN(tx_ring->size, 4096); 279 280 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 281 &tx_ring->dma, GFP_KERNEL); 282 283 if (!tx_ring->desc) 284 goto err; 285 286 tx_ring->next_to_use = 0; 287 tx_ring->next_to_clean = 0; 288 289 return 0; 290 291 err: 292 vfree(tx_ring->tx_buffer_info); 293 dev_err(dev, 294 "Unable to allocate memory for the transmit descriptor ring\n"); 295 return -ENOMEM; 296 } 297 298 /** 299 * igc_setup_all_tx_resources - wrapper to allocate Tx resources for all queues 300 * @adapter: board private structure 301 * 302 * Return 0 on success, negative on failure 303 */ 304 static int igc_setup_all_tx_resources(struct igc_adapter *adapter) 305 { 306 struct pci_dev *pdev = adapter->pdev; 307 int i, err = 0; 308 309 for (i = 0; i < adapter->num_tx_queues; i++) { 310 err = igc_setup_tx_resources(adapter->tx_ring[i]); 311 if (err) { 312 dev_err(&pdev->dev, 313 "Allocation for Tx Queue %u failed\n", i); 314 for (i--; i >= 0; i--) 315 igc_free_tx_resources(adapter->tx_ring[i]); 316 break; 317 } 318 } 319 320 return err; 321 } 322 323 /** 324 * igc_clean_rx_ring - Free Rx Buffers per Queue 325 * @rx_ring: ring to free buffers from 326 */ 327 static void igc_clean_rx_ring(struct igc_ring *rx_ring) 328 { 329 u16 i = rx_ring->next_to_clean; 330 331 if (rx_ring->skb) 332 dev_kfree_skb(rx_ring->skb); 333 rx_ring->skb = NULL; 334 335 /* Free all the Rx ring sk_buffs */ 336 while (i != rx_ring->next_to_alloc) { 337 struct igc_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 338 339 /* Invalidate cache lines that may have been written to by 340 * device so that we avoid corrupting memory. 341 */ 342 dma_sync_single_range_for_cpu(rx_ring->dev, 343 buffer_info->dma, 344 buffer_info->page_offset, 345 igc_rx_bufsz(rx_ring), 346 DMA_FROM_DEVICE); 347 348 /* free resources associated with mapping */ 349 dma_unmap_page_attrs(rx_ring->dev, 350 buffer_info->dma, 351 igc_rx_pg_size(rx_ring), 352 DMA_FROM_DEVICE, 353 IGC_RX_DMA_ATTR); 354 __page_frag_cache_drain(buffer_info->page, 355 buffer_info->pagecnt_bias); 356 357 i++; 358 if (i == rx_ring->count) 359 i = 0; 360 } 361 362 rx_ring->next_to_alloc = 0; 363 rx_ring->next_to_clean = 0; 364 rx_ring->next_to_use = 0; 365 } 366 367 /** 368 * igc_clean_all_rx_rings - Free Rx Buffers for all queues 369 * @adapter: board private structure 370 */ 371 static void igc_clean_all_rx_rings(struct igc_adapter *adapter) 372 { 373 int i; 374 375 for (i = 0; i < adapter->num_rx_queues; i++) 376 if (adapter->rx_ring[i]) 377 igc_clean_rx_ring(adapter->rx_ring[i]); 378 } 379 380 /** 381 * igc_free_rx_resources - Free Rx Resources 382 * @rx_ring: ring to clean the resources from 383 * 384 * Free all receive software resources 385 */ 386 void igc_free_rx_resources(struct igc_ring *rx_ring) 387 { 388 igc_clean_rx_ring(rx_ring); 389 390 vfree(rx_ring->rx_buffer_info); 391 rx_ring->rx_buffer_info = NULL; 392 393 /* if not set, then don't free */ 394 if (!rx_ring->desc) 395 return; 396 397 dma_free_coherent(rx_ring->dev, rx_ring->size, 398 rx_ring->desc, rx_ring->dma); 399 400 rx_ring->desc = NULL; 401 } 402 403 /** 404 * igc_free_all_rx_resources - Free Rx Resources for All Queues 405 * @adapter: board private structure 406 * 407 * Free all receive software resources 408 */ 409 static void igc_free_all_rx_resources(struct igc_adapter *adapter) 410 { 411 int i; 412 413 for (i = 0; i < adapter->num_rx_queues; i++) 414 igc_free_rx_resources(adapter->rx_ring[i]); 415 } 416 417 /** 418 * igc_setup_rx_resources - allocate Rx resources (Descriptors) 419 * @rx_ring: rx descriptor ring (for a specific queue) to setup 420 * 421 * Returns 0 on success, negative on failure 422 */ 423 int igc_setup_rx_resources(struct igc_ring *rx_ring) 424 { 425 struct device *dev = rx_ring->dev; 426 int size, desc_len; 427 428 size = sizeof(struct igc_rx_buffer) * rx_ring->count; 429 rx_ring->rx_buffer_info = vzalloc(size); 430 if (!rx_ring->rx_buffer_info) 431 goto err; 432 433 desc_len = sizeof(union igc_adv_rx_desc); 434 435 /* Round up to nearest 4K */ 436 rx_ring->size = rx_ring->count * desc_len; 437 rx_ring->size = ALIGN(rx_ring->size, 4096); 438 439 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 440 &rx_ring->dma, GFP_KERNEL); 441 442 if (!rx_ring->desc) 443 goto err; 444 445 rx_ring->next_to_alloc = 0; 446 rx_ring->next_to_clean = 0; 447 rx_ring->next_to_use = 0; 448 449 return 0; 450 451 err: 452 vfree(rx_ring->rx_buffer_info); 453 rx_ring->rx_buffer_info = NULL; 454 dev_err(dev, 455 "Unable to allocate memory for the receive descriptor ring\n"); 456 return -ENOMEM; 457 } 458 459 /** 460 * igc_setup_all_rx_resources - wrapper to allocate Rx resources 461 * (Descriptors) for all queues 462 * @adapter: board private structure 463 * 464 * Return 0 on success, negative on failure 465 */ 466 static int igc_setup_all_rx_resources(struct igc_adapter *adapter) 467 { 468 struct pci_dev *pdev = adapter->pdev; 469 int i, err = 0; 470 471 for (i = 0; i < adapter->num_rx_queues; i++) { 472 err = igc_setup_rx_resources(adapter->rx_ring[i]); 473 if (err) { 474 dev_err(&pdev->dev, 475 "Allocation for Rx Queue %u failed\n", i); 476 for (i--; i >= 0; i--) 477 igc_free_rx_resources(adapter->rx_ring[i]); 478 break; 479 } 480 } 481 482 return err; 483 } 484 485 /** 486 * igc_configure_rx_ring - Configure a receive ring after Reset 487 * @adapter: board private structure 488 * @ring: receive ring to be configured 489 * 490 * Configure the Rx unit of the MAC after a reset. 491 */ 492 static void igc_configure_rx_ring(struct igc_adapter *adapter, 493 struct igc_ring *ring) 494 { 495 struct igc_hw *hw = &adapter->hw; 496 union igc_adv_rx_desc *rx_desc; 497 int reg_idx = ring->reg_idx; 498 u32 srrctl = 0, rxdctl = 0; 499 u64 rdba = ring->dma; 500 501 /* disable the queue */ 502 wr32(IGC_RXDCTL(reg_idx), 0); 503 504 /* Set DMA base address registers */ 505 wr32(IGC_RDBAL(reg_idx), 506 rdba & 0x00000000ffffffffULL); 507 wr32(IGC_RDBAH(reg_idx), rdba >> 32); 508 wr32(IGC_RDLEN(reg_idx), 509 ring->count * sizeof(union igc_adv_rx_desc)); 510 511 /* initialize head and tail */ 512 ring->tail = adapter->io_addr + IGC_RDT(reg_idx); 513 wr32(IGC_RDH(reg_idx), 0); 514 writel(0, ring->tail); 515 516 /* reset next-to- use/clean to place SW in sync with hardware */ 517 ring->next_to_clean = 0; 518 ring->next_to_use = 0; 519 520 /* set descriptor configuration */ 521 srrctl = IGC_RX_HDR_LEN << IGC_SRRCTL_BSIZEHDRSIZE_SHIFT; 522 if (ring_uses_large_buffer(ring)) 523 srrctl |= IGC_RXBUFFER_3072 >> IGC_SRRCTL_BSIZEPKT_SHIFT; 524 else 525 srrctl |= IGC_RXBUFFER_2048 >> IGC_SRRCTL_BSIZEPKT_SHIFT; 526 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF; 527 528 wr32(IGC_SRRCTL(reg_idx), srrctl); 529 530 rxdctl |= IGC_RX_PTHRESH; 531 rxdctl |= IGC_RX_HTHRESH << 8; 532 rxdctl |= IGC_RX_WTHRESH << 16; 533 534 /* initialize rx_buffer_info */ 535 memset(ring->rx_buffer_info, 0, 536 sizeof(struct igc_rx_buffer) * ring->count); 537 538 /* initialize Rx descriptor 0 */ 539 rx_desc = IGC_RX_DESC(ring, 0); 540 rx_desc->wb.upper.length = 0; 541 542 /* enable receive descriptor fetching */ 543 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE; 544 545 wr32(IGC_RXDCTL(reg_idx), rxdctl); 546 } 547 548 /** 549 * igc_configure_rx - Configure receive Unit after Reset 550 * @adapter: board private structure 551 * 552 * Configure the Rx unit of the MAC after a reset. 553 */ 554 static void igc_configure_rx(struct igc_adapter *adapter) 555 { 556 int i; 557 558 /* Setup the HW Rx Head and Tail Descriptor Pointers and 559 * the Base and Length of the Rx Descriptor Ring 560 */ 561 for (i = 0; i < adapter->num_rx_queues; i++) 562 igc_configure_rx_ring(adapter, adapter->rx_ring[i]); 563 } 564 565 /** 566 * igc_configure_tx_ring - Configure transmit ring after Reset 567 * @adapter: board private structure 568 * @ring: tx ring to configure 569 * 570 * Configure a transmit ring after a reset. 571 */ 572 static void igc_configure_tx_ring(struct igc_adapter *adapter, 573 struct igc_ring *ring) 574 { 575 struct igc_hw *hw = &adapter->hw; 576 int reg_idx = ring->reg_idx; 577 u64 tdba = ring->dma; 578 u32 txdctl = 0; 579 580 /* disable the queue */ 581 wr32(IGC_TXDCTL(reg_idx), 0); 582 wrfl(); 583 mdelay(10); 584 585 wr32(IGC_TDLEN(reg_idx), 586 ring->count * sizeof(union igc_adv_tx_desc)); 587 wr32(IGC_TDBAL(reg_idx), 588 tdba & 0x00000000ffffffffULL); 589 wr32(IGC_TDBAH(reg_idx), tdba >> 32); 590 591 ring->tail = adapter->io_addr + IGC_TDT(reg_idx); 592 wr32(IGC_TDH(reg_idx), 0); 593 writel(0, ring->tail); 594 595 txdctl |= IGC_TX_PTHRESH; 596 txdctl |= IGC_TX_HTHRESH << 8; 597 txdctl |= IGC_TX_WTHRESH << 16; 598 599 txdctl |= IGC_TXDCTL_QUEUE_ENABLE; 600 wr32(IGC_TXDCTL(reg_idx), txdctl); 601 } 602 603 /** 604 * igc_configure_tx - Configure transmit Unit after Reset 605 * @adapter: board private structure 606 * 607 * Configure the Tx unit of the MAC after a reset. 608 */ 609 static void igc_configure_tx(struct igc_adapter *adapter) 610 { 611 int i; 612 613 for (i = 0; i < adapter->num_tx_queues; i++) 614 igc_configure_tx_ring(adapter, adapter->tx_ring[i]); 615 } 616 617 /** 618 * igc_setup_mrqc - configure the multiple receive queue control registers 619 * @adapter: Board private structure 620 */ 621 static void igc_setup_mrqc(struct igc_adapter *adapter) 622 { 623 } 624 625 /** 626 * igc_setup_rctl - configure the receive control registers 627 * @adapter: Board private structure 628 */ 629 static void igc_setup_rctl(struct igc_adapter *adapter) 630 { 631 struct igc_hw *hw = &adapter->hw; 632 u32 rctl; 633 634 rctl = rd32(IGC_RCTL); 635 636 rctl &= ~(3 << IGC_RCTL_MO_SHIFT); 637 rctl &= ~(IGC_RCTL_LBM_TCVR | IGC_RCTL_LBM_MAC); 638 639 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | IGC_RCTL_RDMTS_HALF | 640 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT); 641 642 /* enable stripping of CRC. Newer features require 643 * that the HW strips the CRC. 644 */ 645 rctl |= IGC_RCTL_SECRC; 646 647 /* disable store bad packets and clear size bits. */ 648 rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_SZ_256); 649 650 /* enable LPE to allow for reception of jumbo frames */ 651 rctl |= IGC_RCTL_LPE; 652 653 /* disable queue 0 to prevent tail write w/o re-config */ 654 wr32(IGC_RXDCTL(0), 0); 655 656 /* This is useful for sniffing bad packets. */ 657 if (adapter->netdev->features & NETIF_F_RXALL) { 658 /* UPE and MPE will be handled by normal PROMISC logic 659 * in set_rx_mode 660 */ 661 rctl |= (IGC_RCTL_SBP | /* Receive bad packets */ 662 IGC_RCTL_BAM | /* RX All Bcast Pkts */ 663 IGC_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 664 665 rctl &= ~(IGC_RCTL_DPF | /* Allow filtered pause */ 666 IGC_RCTL_CFIEN); /* Disable VLAN CFIEN Filter */ 667 } 668 669 wr32(IGC_RCTL, rctl); 670 } 671 672 /** 673 * igc_setup_tctl - configure the transmit control registers 674 * @adapter: Board private structure 675 */ 676 static void igc_setup_tctl(struct igc_adapter *adapter) 677 { 678 struct igc_hw *hw = &adapter->hw; 679 u32 tctl; 680 681 /* disable queue 0 which icould be enabled by default */ 682 wr32(IGC_TXDCTL(0), 0); 683 684 /* Program the Transmit Control Register */ 685 tctl = rd32(IGC_TCTL); 686 tctl &= ~IGC_TCTL_CT; 687 tctl |= IGC_TCTL_PSP | IGC_TCTL_RTLC | 688 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT); 689 690 /* Enable transmits */ 691 tctl |= IGC_TCTL_EN; 692 693 wr32(IGC_TCTL, tctl); 694 } 695 696 /** 697 * igc_set_mac - Change the Ethernet Address of the NIC 698 * @netdev: network interface device structure 699 * @p: pointer to an address structure 700 * 701 * Returns 0 on success, negative on failure 702 */ 703 static int igc_set_mac(struct net_device *netdev, void *p) 704 { 705 struct igc_adapter *adapter = netdev_priv(netdev); 706 struct igc_hw *hw = &adapter->hw; 707 struct sockaddr *addr = p; 708 709 if (!is_valid_ether_addr(addr->sa_data)) 710 return -EADDRNOTAVAIL; 711 712 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 713 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 714 715 /* set the correct pool for the new PF MAC address in entry 0 */ 716 igc_set_default_mac_filter(adapter); 717 718 return 0; 719 } 720 721 static void igc_tx_csum(struct igc_ring *tx_ring, struct igc_tx_buffer *first) 722 { 723 } 724 725 static int __igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size) 726 { 727 struct net_device *netdev = tx_ring->netdev; 728 729 netif_stop_subqueue(netdev, tx_ring->queue_index); 730 731 /* memory barriier comment */ 732 smp_mb(); 733 734 /* We need to check again in a case another CPU has just 735 * made room available. 736 */ 737 if (igc_desc_unused(tx_ring) < size) 738 return -EBUSY; 739 740 /* A reprieve! */ 741 netif_wake_subqueue(netdev, tx_ring->queue_index); 742 743 u64_stats_update_begin(&tx_ring->tx_syncp2); 744 tx_ring->tx_stats.restart_queue2++; 745 u64_stats_update_end(&tx_ring->tx_syncp2); 746 747 return 0; 748 } 749 750 static inline int igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size) 751 { 752 if (igc_desc_unused(tx_ring) >= size) 753 return 0; 754 return __igc_maybe_stop_tx(tx_ring, size); 755 } 756 757 static u32 igc_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 758 { 759 /* set type for advanced descriptor with frame checksum insertion */ 760 u32 cmd_type = IGC_ADVTXD_DTYP_DATA | 761 IGC_ADVTXD_DCMD_DEXT | 762 IGC_ADVTXD_DCMD_IFCS; 763 764 return cmd_type; 765 } 766 767 static void igc_tx_olinfo_status(struct igc_ring *tx_ring, 768 union igc_adv_tx_desc *tx_desc, 769 u32 tx_flags, unsigned int paylen) 770 { 771 u32 olinfo_status = paylen << IGC_ADVTXD_PAYLEN_SHIFT; 772 773 /* insert L4 checksum */ 774 olinfo_status |= (tx_flags & IGC_TX_FLAGS_CSUM) * 775 ((IGC_TXD_POPTS_TXSM << 8) / 776 IGC_TX_FLAGS_CSUM); 777 778 /* insert IPv4 checksum */ 779 olinfo_status |= (tx_flags & IGC_TX_FLAGS_IPV4) * 780 (((IGC_TXD_POPTS_IXSM << 8)) / 781 IGC_TX_FLAGS_IPV4); 782 783 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 784 } 785 786 static int igc_tx_map(struct igc_ring *tx_ring, 787 struct igc_tx_buffer *first, 788 const u8 hdr_len) 789 { 790 struct sk_buff *skb = first->skb; 791 struct igc_tx_buffer *tx_buffer; 792 union igc_adv_tx_desc *tx_desc; 793 u32 tx_flags = first->tx_flags; 794 struct skb_frag_struct *frag; 795 u16 i = tx_ring->next_to_use; 796 unsigned int data_len, size; 797 dma_addr_t dma; 798 u32 cmd_type = igc_tx_cmd_type(skb, tx_flags); 799 800 tx_desc = IGC_TX_DESC(tx_ring, i); 801 802 igc_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 803 804 size = skb_headlen(skb); 805 data_len = skb->data_len; 806 807 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 808 809 tx_buffer = first; 810 811 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 812 if (dma_mapping_error(tx_ring->dev, dma)) 813 goto dma_error; 814 815 /* record length, and DMA address */ 816 dma_unmap_len_set(tx_buffer, len, size); 817 dma_unmap_addr_set(tx_buffer, dma, dma); 818 819 tx_desc->read.buffer_addr = cpu_to_le64(dma); 820 821 while (unlikely(size > IGC_MAX_DATA_PER_TXD)) { 822 tx_desc->read.cmd_type_len = 823 cpu_to_le32(cmd_type ^ IGC_MAX_DATA_PER_TXD); 824 825 i++; 826 tx_desc++; 827 if (i == tx_ring->count) { 828 tx_desc = IGC_TX_DESC(tx_ring, 0); 829 i = 0; 830 } 831 tx_desc->read.olinfo_status = 0; 832 833 dma += IGC_MAX_DATA_PER_TXD; 834 size -= IGC_MAX_DATA_PER_TXD; 835 836 tx_desc->read.buffer_addr = cpu_to_le64(dma); 837 } 838 839 if (likely(!data_len)) 840 break; 841 842 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 843 844 i++; 845 tx_desc++; 846 if (i == tx_ring->count) { 847 tx_desc = IGC_TX_DESC(tx_ring, 0); 848 i = 0; 849 } 850 tx_desc->read.olinfo_status = 0; 851 852 size = skb_frag_size(frag); 853 data_len -= size; 854 855 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 856 size, DMA_TO_DEVICE); 857 858 tx_buffer = &tx_ring->tx_buffer_info[i]; 859 } 860 861 /* write last descriptor with RS and EOP bits */ 862 cmd_type |= size | IGC_TXD_DCMD; 863 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 864 865 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 866 867 /* set the timestamp */ 868 first->time_stamp = jiffies; 869 870 skb_tx_timestamp(skb); 871 872 /* Force memory writes to complete before letting h/w know there 873 * are new descriptors to fetch. (Only applicable for weak-ordered 874 * memory model archs, such as IA-64). 875 * 876 * We also need this memory barrier to make certain all of the 877 * status bits have been updated before next_to_watch is written. 878 */ 879 wmb(); 880 881 /* set next_to_watch value indicating a packet is present */ 882 first->next_to_watch = tx_desc; 883 884 i++; 885 if (i == tx_ring->count) 886 i = 0; 887 888 tx_ring->next_to_use = i; 889 890 /* Make sure there is space in the ring for the next send. */ 891 igc_maybe_stop_tx(tx_ring, DESC_NEEDED); 892 893 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 894 writel(i, tx_ring->tail); 895 896 /* we need this if more than one processor can write to our tail 897 * at a time, it synchronizes IO on IA64/Altix systems 898 */ 899 mmiowb(); 900 } 901 902 return 0; 903 dma_error: 904 dev_err(tx_ring->dev, "TX DMA map failed\n"); 905 tx_buffer = &tx_ring->tx_buffer_info[i]; 906 907 /* clear dma mappings for failed tx_buffer_info map */ 908 while (tx_buffer != first) { 909 if (dma_unmap_len(tx_buffer, len)) 910 dma_unmap_page(tx_ring->dev, 911 dma_unmap_addr(tx_buffer, dma), 912 dma_unmap_len(tx_buffer, len), 913 DMA_TO_DEVICE); 914 dma_unmap_len_set(tx_buffer, len, 0); 915 916 if (i-- == 0) 917 i += tx_ring->count; 918 tx_buffer = &tx_ring->tx_buffer_info[i]; 919 } 920 921 if (dma_unmap_len(tx_buffer, len)) 922 dma_unmap_single(tx_ring->dev, 923 dma_unmap_addr(tx_buffer, dma), 924 dma_unmap_len(tx_buffer, len), 925 DMA_TO_DEVICE); 926 dma_unmap_len_set(tx_buffer, len, 0); 927 928 dev_kfree_skb_any(tx_buffer->skb); 929 tx_buffer->skb = NULL; 930 931 tx_ring->next_to_use = i; 932 933 return -1; 934 } 935 936 static netdev_tx_t igc_xmit_frame_ring(struct sk_buff *skb, 937 struct igc_ring *tx_ring) 938 { 939 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 940 __be16 protocol = vlan_get_protocol(skb); 941 struct igc_tx_buffer *first; 942 u32 tx_flags = 0; 943 unsigned short f; 944 u8 hdr_len = 0; 945 946 /* need: 1 descriptor per page * PAGE_SIZE/IGC_MAX_DATA_PER_TXD, 947 * + 1 desc for skb_headlen/IGC_MAX_DATA_PER_TXD, 948 * + 2 desc gap to keep tail from touching head, 949 * + 1 desc for context descriptor, 950 * otherwise try next time 951 */ 952 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 953 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 954 955 if (igc_maybe_stop_tx(tx_ring, count + 3)) { 956 /* this is a hard error */ 957 return NETDEV_TX_BUSY; 958 } 959 960 /* record the location of the first descriptor for this packet */ 961 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 962 first->skb = skb; 963 first->bytecount = skb->len; 964 first->gso_segs = 1; 965 966 /* record initial flags and protocol */ 967 first->tx_flags = tx_flags; 968 first->protocol = protocol; 969 970 igc_tx_csum(tx_ring, first); 971 972 igc_tx_map(tx_ring, first, hdr_len); 973 974 return NETDEV_TX_OK; 975 } 976 977 static inline struct igc_ring *igc_tx_queue_mapping(struct igc_adapter *adapter, 978 struct sk_buff *skb) 979 { 980 unsigned int r_idx = skb->queue_mapping; 981 982 if (r_idx >= adapter->num_tx_queues) 983 r_idx = r_idx % adapter->num_tx_queues; 984 985 return adapter->tx_ring[r_idx]; 986 } 987 988 static netdev_tx_t igc_xmit_frame(struct sk_buff *skb, 989 struct net_device *netdev) 990 { 991 struct igc_adapter *adapter = netdev_priv(netdev); 992 993 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 994 * in order to meet this minimum size requirement. 995 */ 996 if (skb->len < 17) { 997 if (skb_padto(skb, 17)) 998 return NETDEV_TX_OK; 999 skb->len = 17; 1000 } 1001 1002 return igc_xmit_frame_ring(skb, igc_tx_queue_mapping(adapter, skb)); 1003 } 1004 1005 static inline void igc_rx_hash(struct igc_ring *ring, 1006 union igc_adv_rx_desc *rx_desc, 1007 struct sk_buff *skb) 1008 { 1009 if (ring->netdev->features & NETIF_F_RXHASH) 1010 skb_set_hash(skb, 1011 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1012 PKT_HASH_TYPE_L3); 1013 } 1014 1015 /** 1016 * igc_process_skb_fields - Populate skb header fields from Rx descriptor 1017 * @rx_ring: rx descriptor ring packet is being transacted on 1018 * @rx_desc: pointer to the EOP Rx descriptor 1019 * @skb: pointer to current skb being populated 1020 * 1021 * This function checks the ring, descriptor, and packet information in 1022 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1023 * other fields within the skb. 1024 */ 1025 static void igc_process_skb_fields(struct igc_ring *rx_ring, 1026 union igc_adv_rx_desc *rx_desc, 1027 struct sk_buff *skb) 1028 { 1029 igc_rx_hash(rx_ring, rx_desc, skb); 1030 1031 skb_record_rx_queue(skb, rx_ring->queue_index); 1032 1033 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 1034 } 1035 1036 static struct igc_rx_buffer *igc_get_rx_buffer(struct igc_ring *rx_ring, 1037 const unsigned int size) 1038 { 1039 struct igc_rx_buffer *rx_buffer; 1040 1041 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 1042 prefetchw(rx_buffer->page); 1043 1044 /* we are reusing so sync this buffer for CPU use */ 1045 dma_sync_single_range_for_cpu(rx_ring->dev, 1046 rx_buffer->dma, 1047 rx_buffer->page_offset, 1048 size, 1049 DMA_FROM_DEVICE); 1050 1051 rx_buffer->pagecnt_bias--; 1052 1053 return rx_buffer; 1054 } 1055 1056 /** 1057 * igc_add_rx_frag - Add contents of Rx buffer to sk_buff 1058 * @rx_ring: rx descriptor ring to transact packets on 1059 * @rx_buffer: buffer containing page to add 1060 * @skb: sk_buff to place the data into 1061 * @size: size of buffer to be added 1062 * 1063 * This function will add the data contained in rx_buffer->page to the skb. 1064 */ 1065 static void igc_add_rx_frag(struct igc_ring *rx_ring, 1066 struct igc_rx_buffer *rx_buffer, 1067 struct sk_buff *skb, 1068 unsigned int size) 1069 { 1070 #if (PAGE_SIZE < 8192) 1071 unsigned int truesize = igc_rx_pg_size(rx_ring) / 2; 1072 1073 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 1074 rx_buffer->page_offset, size, truesize); 1075 rx_buffer->page_offset ^= truesize; 1076 #else 1077 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 1078 SKB_DATA_ALIGN(IGC_SKB_PAD + size) : 1079 SKB_DATA_ALIGN(size); 1080 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 1081 rx_buffer->page_offset, size, truesize); 1082 rx_buffer->page_offset += truesize; 1083 #endif 1084 } 1085 1086 static struct sk_buff *igc_build_skb(struct igc_ring *rx_ring, 1087 struct igc_rx_buffer *rx_buffer, 1088 union igc_adv_rx_desc *rx_desc, 1089 unsigned int size) 1090 { 1091 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 1092 #if (PAGE_SIZE < 8192) 1093 unsigned int truesize = igc_rx_pg_size(rx_ring) / 2; 1094 #else 1095 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1096 SKB_DATA_ALIGN(IGC_SKB_PAD + size); 1097 #endif 1098 struct sk_buff *skb; 1099 1100 /* prefetch first cache line of first page */ 1101 prefetch(va); 1102 #if L1_CACHE_BYTES < 128 1103 prefetch(va + L1_CACHE_BYTES); 1104 #endif 1105 1106 /* build an skb around the page buffer */ 1107 skb = build_skb(va - IGC_SKB_PAD, truesize); 1108 if (unlikely(!skb)) 1109 return NULL; 1110 1111 /* update pointers within the skb to store the data */ 1112 skb_reserve(skb, IGC_SKB_PAD); 1113 __skb_put(skb, size); 1114 1115 /* update buffer offset */ 1116 #if (PAGE_SIZE < 8192) 1117 rx_buffer->page_offset ^= truesize; 1118 #else 1119 rx_buffer->page_offset += truesize; 1120 #endif 1121 1122 return skb; 1123 } 1124 1125 static struct sk_buff *igc_construct_skb(struct igc_ring *rx_ring, 1126 struct igc_rx_buffer *rx_buffer, 1127 union igc_adv_rx_desc *rx_desc, 1128 unsigned int size) 1129 { 1130 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 1131 #if (PAGE_SIZE < 8192) 1132 unsigned int truesize = igc_rx_pg_size(rx_ring) / 2; 1133 #else 1134 unsigned int truesize = SKB_DATA_ALIGN(size); 1135 #endif 1136 unsigned int headlen; 1137 struct sk_buff *skb; 1138 1139 /* prefetch first cache line of first page */ 1140 prefetch(va); 1141 #if L1_CACHE_BYTES < 128 1142 prefetch(va + L1_CACHE_BYTES); 1143 #endif 1144 1145 /* allocate a skb to store the frags */ 1146 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGC_RX_HDR_LEN); 1147 if (unlikely(!skb)) 1148 return NULL; 1149 1150 /* Determine available headroom for copy */ 1151 headlen = size; 1152 if (headlen > IGC_RX_HDR_LEN) 1153 headlen = eth_get_headlen(va, IGC_RX_HDR_LEN); 1154 1155 /* align pull length to size of long to optimize memcpy performance */ 1156 memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long))); 1157 1158 /* update all of the pointers */ 1159 size -= headlen; 1160 if (size) { 1161 skb_add_rx_frag(skb, 0, rx_buffer->page, 1162 (va + headlen) - page_address(rx_buffer->page), 1163 size, truesize); 1164 #if (PAGE_SIZE < 8192) 1165 rx_buffer->page_offset ^= truesize; 1166 #else 1167 rx_buffer->page_offset += truesize; 1168 #endif 1169 } else { 1170 rx_buffer->pagecnt_bias++; 1171 } 1172 1173 return skb; 1174 } 1175 1176 /** 1177 * igc_reuse_rx_page - page flip buffer and store it back on the ring 1178 * @rx_ring: rx descriptor ring to store buffers on 1179 * @old_buff: donor buffer to have page reused 1180 * 1181 * Synchronizes page for reuse by the adapter 1182 */ 1183 static void igc_reuse_rx_page(struct igc_ring *rx_ring, 1184 struct igc_rx_buffer *old_buff) 1185 { 1186 u16 nta = rx_ring->next_to_alloc; 1187 struct igc_rx_buffer *new_buff; 1188 1189 new_buff = &rx_ring->rx_buffer_info[nta]; 1190 1191 /* update, and store next to alloc */ 1192 nta++; 1193 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1194 1195 /* Transfer page from old buffer to new buffer. 1196 * Move each member individually to avoid possible store 1197 * forwarding stalls. 1198 */ 1199 new_buff->dma = old_buff->dma; 1200 new_buff->page = old_buff->page; 1201 new_buff->page_offset = old_buff->page_offset; 1202 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1203 } 1204 1205 static inline bool igc_page_is_reserved(struct page *page) 1206 { 1207 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 1208 } 1209 1210 static bool igc_can_reuse_rx_page(struct igc_rx_buffer *rx_buffer) 1211 { 1212 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1213 struct page *page = rx_buffer->page; 1214 1215 /* avoid re-using remote pages */ 1216 if (unlikely(igc_page_is_reserved(page))) 1217 return false; 1218 1219 #if (PAGE_SIZE < 8192) 1220 /* if we are only owner of page we can reuse it */ 1221 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 1222 return false; 1223 #else 1224 #define IGC_LAST_OFFSET \ 1225 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGC_RXBUFFER_2048) 1226 1227 if (rx_buffer->page_offset > IGC_LAST_OFFSET) 1228 return false; 1229 #endif 1230 1231 /* If we have drained the page fragment pool we need to update 1232 * the pagecnt_bias and page count so that we fully restock the 1233 * number of references the driver holds. 1234 */ 1235 if (unlikely(!pagecnt_bias)) { 1236 page_ref_add(page, USHRT_MAX); 1237 rx_buffer->pagecnt_bias = USHRT_MAX; 1238 } 1239 1240 return true; 1241 } 1242 1243 /** 1244 * igc_is_non_eop - process handling of non-EOP buffers 1245 * @rx_ring: Rx ring being processed 1246 * @rx_desc: Rx descriptor for current buffer 1247 * @skb: current socket buffer containing buffer in progress 1248 * 1249 * This function updates next to clean. If the buffer is an EOP buffer 1250 * this function exits returning false, otherwise it will place the 1251 * sk_buff in the next buffer to be chained and return true indicating 1252 * that this is in fact a non-EOP buffer. 1253 */ 1254 static bool igc_is_non_eop(struct igc_ring *rx_ring, 1255 union igc_adv_rx_desc *rx_desc) 1256 { 1257 u32 ntc = rx_ring->next_to_clean + 1; 1258 1259 /* fetch, update, and store next to clean */ 1260 ntc = (ntc < rx_ring->count) ? ntc : 0; 1261 rx_ring->next_to_clean = ntc; 1262 1263 prefetch(IGC_RX_DESC(rx_ring, ntc)); 1264 1265 if (likely(igc_test_staterr(rx_desc, IGC_RXD_STAT_EOP))) 1266 return false; 1267 1268 return true; 1269 } 1270 1271 /** 1272 * igc_cleanup_headers - Correct corrupted or empty headers 1273 * @rx_ring: rx descriptor ring packet is being transacted on 1274 * @rx_desc: pointer to the EOP Rx descriptor 1275 * @skb: pointer to current skb being fixed 1276 * 1277 * Address the case where we are pulling data in on pages only 1278 * and as such no data is present in the skb header. 1279 * 1280 * In addition if skb is not at least 60 bytes we need to pad it so that 1281 * it is large enough to qualify as a valid Ethernet frame. 1282 * 1283 * Returns true if an error was encountered and skb was freed. 1284 */ 1285 static bool igc_cleanup_headers(struct igc_ring *rx_ring, 1286 union igc_adv_rx_desc *rx_desc, 1287 struct sk_buff *skb) 1288 { 1289 if (unlikely((igc_test_staterr(rx_desc, 1290 IGC_RXDEXT_ERR_FRAME_ERR_MASK)))) { 1291 struct net_device *netdev = rx_ring->netdev; 1292 1293 if (!(netdev->features & NETIF_F_RXALL)) { 1294 dev_kfree_skb_any(skb); 1295 return true; 1296 } 1297 } 1298 1299 /* if eth_skb_pad returns an error the skb was freed */ 1300 if (eth_skb_pad(skb)) 1301 return true; 1302 1303 return false; 1304 } 1305 1306 static void igc_put_rx_buffer(struct igc_ring *rx_ring, 1307 struct igc_rx_buffer *rx_buffer) 1308 { 1309 if (igc_can_reuse_rx_page(rx_buffer)) { 1310 /* hand second half of page back to the ring */ 1311 igc_reuse_rx_page(rx_ring, rx_buffer); 1312 } else { 1313 /* We are not reusing the buffer so unmap it and free 1314 * any references we are holding to it 1315 */ 1316 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 1317 igc_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 1318 IGC_RX_DMA_ATTR); 1319 __page_frag_cache_drain(rx_buffer->page, 1320 rx_buffer->pagecnt_bias); 1321 } 1322 1323 /* clear contents of rx_buffer */ 1324 rx_buffer->page = NULL; 1325 } 1326 1327 /** 1328 * igc_alloc_rx_buffers - Replace used receive buffers; packet split 1329 * @adapter: address of board private structure 1330 */ 1331 static void igc_alloc_rx_buffers(struct igc_ring *rx_ring, u16 cleaned_count) 1332 { 1333 union igc_adv_rx_desc *rx_desc; 1334 u16 i = rx_ring->next_to_use; 1335 struct igc_rx_buffer *bi; 1336 u16 bufsz; 1337 1338 /* nothing to do */ 1339 if (!cleaned_count) 1340 return; 1341 1342 rx_desc = IGC_RX_DESC(rx_ring, i); 1343 bi = &rx_ring->rx_buffer_info[i]; 1344 i -= rx_ring->count; 1345 1346 bufsz = igc_rx_bufsz(rx_ring); 1347 1348 do { 1349 if (!igc_alloc_mapped_page(rx_ring, bi)) 1350 break; 1351 1352 /* sync the buffer for use by the device */ 1353 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1354 bi->page_offset, bufsz, 1355 DMA_FROM_DEVICE); 1356 1357 /* Refresh the desc even if buffer_addrs didn't change 1358 * because each write-back erases this info. 1359 */ 1360 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1361 1362 rx_desc++; 1363 bi++; 1364 i++; 1365 if (unlikely(!i)) { 1366 rx_desc = IGC_RX_DESC(rx_ring, 0); 1367 bi = rx_ring->rx_buffer_info; 1368 i -= rx_ring->count; 1369 } 1370 1371 /* clear the length for the next_to_use descriptor */ 1372 rx_desc->wb.upper.length = 0; 1373 1374 cleaned_count--; 1375 } while (cleaned_count); 1376 1377 i += rx_ring->count; 1378 1379 if (rx_ring->next_to_use != i) { 1380 /* record the next descriptor to use */ 1381 rx_ring->next_to_use = i; 1382 1383 /* update next to alloc since we have filled the ring */ 1384 rx_ring->next_to_alloc = i; 1385 1386 /* Force memory writes to complete before letting h/w 1387 * know there are new descriptors to fetch. (Only 1388 * applicable for weak-ordered memory model archs, 1389 * such as IA-64). 1390 */ 1391 wmb(); 1392 writel(i, rx_ring->tail); 1393 } 1394 } 1395 1396 static int igc_clean_rx_irq(struct igc_q_vector *q_vector, const int budget) 1397 { 1398 unsigned int total_bytes = 0, total_packets = 0; 1399 struct igc_ring *rx_ring = q_vector->rx.ring; 1400 struct sk_buff *skb = rx_ring->skb; 1401 u16 cleaned_count = igc_desc_unused(rx_ring); 1402 1403 while (likely(total_packets < budget)) { 1404 union igc_adv_rx_desc *rx_desc; 1405 struct igc_rx_buffer *rx_buffer; 1406 unsigned int size; 1407 1408 /* return some buffers to hardware, one at a time is too slow */ 1409 if (cleaned_count >= IGC_RX_BUFFER_WRITE) { 1410 igc_alloc_rx_buffers(rx_ring, cleaned_count); 1411 cleaned_count = 0; 1412 } 1413 1414 rx_desc = IGC_RX_DESC(rx_ring, rx_ring->next_to_clean); 1415 size = le16_to_cpu(rx_desc->wb.upper.length); 1416 if (!size) 1417 break; 1418 1419 /* This memory barrier is needed to keep us from reading 1420 * any other fields out of the rx_desc until we know the 1421 * descriptor has been written back 1422 */ 1423 dma_rmb(); 1424 1425 rx_buffer = igc_get_rx_buffer(rx_ring, size); 1426 1427 /* retrieve a buffer from the ring */ 1428 if (skb) 1429 igc_add_rx_frag(rx_ring, rx_buffer, skb, size); 1430 else if (ring_uses_build_skb(rx_ring)) 1431 skb = igc_build_skb(rx_ring, rx_buffer, rx_desc, size); 1432 else 1433 skb = igc_construct_skb(rx_ring, rx_buffer, 1434 rx_desc, size); 1435 1436 /* exit if we failed to retrieve a buffer */ 1437 if (!skb) { 1438 rx_ring->rx_stats.alloc_failed++; 1439 rx_buffer->pagecnt_bias++; 1440 break; 1441 } 1442 1443 igc_put_rx_buffer(rx_ring, rx_buffer); 1444 cleaned_count++; 1445 1446 /* fetch next buffer in frame if non-eop */ 1447 if (igc_is_non_eop(rx_ring, rx_desc)) 1448 continue; 1449 1450 /* verify the packet layout is correct */ 1451 if (igc_cleanup_headers(rx_ring, rx_desc, skb)) { 1452 skb = NULL; 1453 continue; 1454 } 1455 1456 /* probably a little skewed due to removing CRC */ 1457 total_bytes += skb->len; 1458 1459 /* populate checksum, timestamp, VLAN, and protocol */ 1460 igc_process_skb_fields(rx_ring, rx_desc, skb); 1461 1462 napi_gro_receive(&q_vector->napi, skb); 1463 1464 /* reset skb pointer */ 1465 skb = NULL; 1466 1467 /* update budget accounting */ 1468 total_packets++; 1469 } 1470 1471 /* place incomplete frames back on ring for completion */ 1472 rx_ring->skb = skb; 1473 1474 u64_stats_update_begin(&rx_ring->rx_syncp); 1475 rx_ring->rx_stats.packets += total_packets; 1476 rx_ring->rx_stats.bytes += total_bytes; 1477 u64_stats_update_end(&rx_ring->rx_syncp); 1478 q_vector->rx.total_packets += total_packets; 1479 q_vector->rx.total_bytes += total_bytes; 1480 1481 if (cleaned_count) 1482 igc_alloc_rx_buffers(rx_ring, cleaned_count); 1483 1484 return total_packets; 1485 } 1486 1487 static inline unsigned int igc_rx_offset(struct igc_ring *rx_ring) 1488 { 1489 return ring_uses_build_skb(rx_ring) ? IGC_SKB_PAD : 0; 1490 } 1491 1492 static bool igc_alloc_mapped_page(struct igc_ring *rx_ring, 1493 struct igc_rx_buffer *bi) 1494 { 1495 struct page *page = bi->page; 1496 dma_addr_t dma; 1497 1498 /* since we are recycling buffers we should seldom need to alloc */ 1499 if (likely(page)) 1500 return true; 1501 1502 /* alloc new page for storage */ 1503 page = dev_alloc_pages(igc_rx_pg_order(rx_ring)); 1504 if (unlikely(!page)) { 1505 rx_ring->rx_stats.alloc_failed++; 1506 return false; 1507 } 1508 1509 /* map page for use */ 1510 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1511 igc_rx_pg_size(rx_ring), 1512 DMA_FROM_DEVICE, 1513 IGC_RX_DMA_ATTR); 1514 1515 /* if mapping failed free memory back to system since 1516 * there isn't much point in holding memory we can't use 1517 */ 1518 if (dma_mapping_error(rx_ring->dev, dma)) { 1519 __free_page(page); 1520 1521 rx_ring->rx_stats.alloc_failed++; 1522 return false; 1523 } 1524 1525 bi->dma = dma; 1526 bi->page = page; 1527 bi->page_offset = igc_rx_offset(rx_ring); 1528 bi->pagecnt_bias = 1; 1529 1530 return true; 1531 } 1532 1533 /** 1534 * igc_clean_tx_irq - Reclaim resources after transmit completes 1535 * @q_vector: pointer to q_vector containing needed info 1536 * @napi_budget: Used to determine if we are in netpoll 1537 * 1538 * returns true if ring is completely cleaned 1539 */ 1540 static bool igc_clean_tx_irq(struct igc_q_vector *q_vector, int napi_budget) 1541 { 1542 struct igc_adapter *adapter = q_vector->adapter; 1543 unsigned int total_bytes = 0, total_packets = 0; 1544 unsigned int budget = q_vector->tx.work_limit; 1545 struct igc_ring *tx_ring = q_vector->tx.ring; 1546 unsigned int i = tx_ring->next_to_clean; 1547 struct igc_tx_buffer *tx_buffer; 1548 union igc_adv_tx_desc *tx_desc; 1549 1550 if (test_bit(__IGC_DOWN, &adapter->state)) 1551 return true; 1552 1553 tx_buffer = &tx_ring->tx_buffer_info[i]; 1554 tx_desc = IGC_TX_DESC(tx_ring, i); 1555 i -= tx_ring->count; 1556 1557 do { 1558 union igc_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1559 1560 /* if next_to_watch is not set then there is no work pending */ 1561 if (!eop_desc) 1562 break; 1563 1564 /* prevent any other reads prior to eop_desc */ 1565 smp_rmb(); 1566 1567 /* if DD is not set pending work has not been completed */ 1568 if (!(eop_desc->wb.status & cpu_to_le32(IGC_TXD_STAT_DD))) 1569 break; 1570 1571 /* clear next_to_watch to prevent false hangs */ 1572 tx_buffer->next_to_watch = NULL; 1573 1574 /* update the statistics for this packet */ 1575 total_bytes += tx_buffer->bytecount; 1576 total_packets += tx_buffer->gso_segs; 1577 1578 /* free the skb */ 1579 napi_consume_skb(tx_buffer->skb, napi_budget); 1580 1581 /* unmap skb header data */ 1582 dma_unmap_single(tx_ring->dev, 1583 dma_unmap_addr(tx_buffer, dma), 1584 dma_unmap_len(tx_buffer, len), 1585 DMA_TO_DEVICE); 1586 1587 /* clear tx_buffer data */ 1588 dma_unmap_len_set(tx_buffer, len, 0); 1589 1590 /* clear last DMA location and unmap remaining buffers */ 1591 while (tx_desc != eop_desc) { 1592 tx_buffer++; 1593 tx_desc++; 1594 i++; 1595 if (unlikely(!i)) { 1596 i -= tx_ring->count; 1597 tx_buffer = tx_ring->tx_buffer_info; 1598 tx_desc = IGC_TX_DESC(tx_ring, 0); 1599 } 1600 1601 /* unmap any remaining paged data */ 1602 if (dma_unmap_len(tx_buffer, len)) { 1603 dma_unmap_page(tx_ring->dev, 1604 dma_unmap_addr(tx_buffer, dma), 1605 dma_unmap_len(tx_buffer, len), 1606 DMA_TO_DEVICE); 1607 dma_unmap_len_set(tx_buffer, len, 0); 1608 } 1609 } 1610 1611 /* move us one more past the eop_desc for start of next pkt */ 1612 tx_buffer++; 1613 tx_desc++; 1614 i++; 1615 if (unlikely(!i)) { 1616 i -= tx_ring->count; 1617 tx_buffer = tx_ring->tx_buffer_info; 1618 tx_desc = IGC_TX_DESC(tx_ring, 0); 1619 } 1620 1621 /* issue prefetch for next Tx descriptor */ 1622 prefetch(tx_desc); 1623 1624 /* update budget accounting */ 1625 budget--; 1626 } while (likely(budget)); 1627 1628 netdev_tx_completed_queue(txring_txq(tx_ring), 1629 total_packets, total_bytes); 1630 1631 i += tx_ring->count; 1632 tx_ring->next_to_clean = i; 1633 u64_stats_update_begin(&tx_ring->tx_syncp); 1634 tx_ring->tx_stats.bytes += total_bytes; 1635 tx_ring->tx_stats.packets += total_packets; 1636 u64_stats_update_end(&tx_ring->tx_syncp); 1637 q_vector->tx.total_bytes += total_bytes; 1638 q_vector->tx.total_packets += total_packets; 1639 1640 if (test_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 1641 struct igc_hw *hw = &adapter->hw; 1642 1643 /* Detect a transmit hang in hardware, this serializes the 1644 * check with the clearing of time_stamp and movement of i 1645 */ 1646 clear_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 1647 if (tx_buffer->next_to_watch && 1648 time_after(jiffies, tx_buffer->time_stamp + 1649 (adapter->tx_timeout_factor * HZ)) && 1650 !(rd32(IGC_STATUS) & IGC_STATUS_TXOFF)) { 1651 /* detected Tx unit hang */ 1652 dev_err(tx_ring->dev, 1653 "Detected Tx Unit Hang\n" 1654 " Tx Queue <%d>\n" 1655 " TDH <%x>\n" 1656 " TDT <%x>\n" 1657 " next_to_use <%x>\n" 1658 " next_to_clean <%x>\n" 1659 "buffer_info[next_to_clean]\n" 1660 " time_stamp <%lx>\n" 1661 " next_to_watch <%p>\n" 1662 " jiffies <%lx>\n" 1663 " desc.status <%x>\n", 1664 tx_ring->queue_index, 1665 rd32(IGC_TDH(tx_ring->reg_idx)), 1666 readl(tx_ring->tail), 1667 tx_ring->next_to_use, 1668 tx_ring->next_to_clean, 1669 tx_buffer->time_stamp, 1670 tx_buffer->next_to_watch, 1671 jiffies, 1672 tx_buffer->next_to_watch->wb.status); 1673 netif_stop_subqueue(tx_ring->netdev, 1674 tx_ring->queue_index); 1675 1676 /* we are about to reset, no point in enabling stuff */ 1677 return true; 1678 } 1679 } 1680 1681 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1682 if (unlikely(total_packets && 1683 netif_carrier_ok(tx_ring->netdev) && 1684 igc_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 1685 /* Make sure that anybody stopping the queue after this 1686 * sees the new next_to_clean. 1687 */ 1688 smp_mb(); 1689 if (__netif_subqueue_stopped(tx_ring->netdev, 1690 tx_ring->queue_index) && 1691 !(test_bit(__IGC_DOWN, &adapter->state))) { 1692 netif_wake_subqueue(tx_ring->netdev, 1693 tx_ring->queue_index); 1694 1695 u64_stats_update_begin(&tx_ring->tx_syncp); 1696 tx_ring->tx_stats.restart_queue++; 1697 u64_stats_update_end(&tx_ring->tx_syncp); 1698 } 1699 } 1700 1701 return !!budget; 1702 } 1703 1704 /** 1705 * igc_up - Open the interface and prepare it to handle traffic 1706 * @adapter: board private structure 1707 */ 1708 void igc_up(struct igc_adapter *adapter) 1709 { 1710 struct igc_hw *hw = &adapter->hw; 1711 int i = 0; 1712 1713 /* hardware has been reset, we need to reload some things */ 1714 igc_configure(adapter); 1715 1716 clear_bit(__IGC_DOWN, &adapter->state); 1717 1718 for (i = 0; i < adapter->num_q_vectors; i++) 1719 napi_enable(&adapter->q_vector[i]->napi); 1720 1721 if (adapter->msix_entries) 1722 igc_configure_msix(adapter); 1723 else 1724 igc_assign_vector(adapter->q_vector[0], 0); 1725 1726 /* Clear any pending interrupts. */ 1727 rd32(IGC_ICR); 1728 igc_irq_enable(adapter); 1729 1730 netif_tx_start_all_queues(adapter->netdev); 1731 1732 /* start the watchdog. */ 1733 hw->mac.get_link_status = 1; 1734 schedule_work(&adapter->watchdog_task); 1735 } 1736 1737 /** 1738 * igc_update_stats - Update the board statistics counters 1739 * @adapter: board private structure 1740 */ 1741 static void igc_update_stats(struct igc_adapter *adapter) 1742 { 1743 } 1744 1745 static void igc_nfc_filter_exit(struct igc_adapter *adapter) 1746 { 1747 } 1748 1749 /** 1750 * igc_down - Close the interface 1751 * @adapter: board private structure 1752 */ 1753 void igc_down(struct igc_adapter *adapter) 1754 { 1755 struct net_device *netdev = adapter->netdev; 1756 struct igc_hw *hw = &adapter->hw; 1757 u32 tctl, rctl; 1758 int i = 0; 1759 1760 set_bit(__IGC_DOWN, &adapter->state); 1761 1762 /* disable receives in the hardware */ 1763 rctl = rd32(IGC_RCTL); 1764 wr32(IGC_RCTL, rctl & ~IGC_RCTL_EN); 1765 /* flush and sleep below */ 1766 1767 igc_nfc_filter_exit(adapter); 1768 1769 /* set trans_start so we don't get spurious watchdogs during reset */ 1770 netif_trans_update(netdev); 1771 1772 netif_carrier_off(netdev); 1773 netif_tx_stop_all_queues(netdev); 1774 1775 /* disable transmits in the hardware */ 1776 tctl = rd32(IGC_TCTL); 1777 tctl &= ~IGC_TCTL_EN; 1778 wr32(IGC_TCTL, tctl); 1779 /* flush both disables and wait for them to finish */ 1780 wrfl(); 1781 usleep_range(10000, 20000); 1782 1783 igc_irq_disable(adapter); 1784 1785 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE; 1786 1787 for (i = 0; i < adapter->num_q_vectors; i++) { 1788 if (adapter->q_vector[i]) { 1789 napi_synchronize(&adapter->q_vector[i]->napi); 1790 napi_disable(&adapter->q_vector[i]->napi); 1791 } 1792 } 1793 1794 del_timer_sync(&adapter->watchdog_timer); 1795 del_timer_sync(&adapter->phy_info_timer); 1796 1797 /* record the stats before reset*/ 1798 spin_lock(&adapter->stats64_lock); 1799 igc_update_stats(adapter); 1800 spin_unlock(&adapter->stats64_lock); 1801 1802 adapter->link_speed = 0; 1803 adapter->link_duplex = 0; 1804 1805 if (!pci_channel_offline(adapter->pdev)) 1806 igc_reset(adapter); 1807 1808 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 1809 adapter->flags &= ~IGC_FLAG_VLAN_PROMISC; 1810 1811 igc_clean_all_tx_rings(adapter); 1812 igc_clean_all_rx_rings(adapter); 1813 } 1814 1815 void igc_reinit_locked(struct igc_adapter *adapter) 1816 { 1817 WARN_ON(in_interrupt()); 1818 while (test_and_set_bit(__IGC_RESETTING, &adapter->state)) 1819 usleep_range(1000, 2000); 1820 igc_down(adapter); 1821 igc_up(adapter); 1822 clear_bit(__IGC_RESETTING, &adapter->state); 1823 } 1824 1825 static void igc_reset_task(struct work_struct *work) 1826 { 1827 struct igc_adapter *adapter; 1828 1829 adapter = container_of(work, struct igc_adapter, reset_task); 1830 1831 netdev_err(adapter->netdev, "Reset adapter\n"); 1832 igc_reinit_locked(adapter); 1833 } 1834 1835 /** 1836 * igc_change_mtu - Change the Maximum Transfer Unit 1837 * @netdev: network interface device structure 1838 * @new_mtu: new value for maximum frame size 1839 * 1840 * Returns 0 on success, negative on failure 1841 */ 1842 static int igc_change_mtu(struct net_device *netdev, int new_mtu) 1843 { 1844 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 1845 struct igc_adapter *adapter = netdev_priv(netdev); 1846 struct pci_dev *pdev = adapter->pdev; 1847 1848 /* adjust max frame to be at least the size of a standard frame */ 1849 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 1850 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 1851 1852 while (test_and_set_bit(__IGC_RESETTING, &adapter->state)) 1853 usleep_range(1000, 2000); 1854 1855 /* igc_down has a dependency on max_frame_size */ 1856 adapter->max_frame_size = max_frame; 1857 1858 if (netif_running(netdev)) 1859 igc_down(adapter); 1860 1861 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 1862 netdev->mtu, new_mtu); 1863 netdev->mtu = new_mtu; 1864 1865 if (netif_running(netdev)) 1866 igc_up(adapter); 1867 else 1868 igc_reset(adapter); 1869 1870 clear_bit(__IGC_RESETTING, &adapter->state); 1871 1872 return 0; 1873 } 1874 1875 /** 1876 * igc_get_stats - Get System Network Statistics 1877 * @netdev: network interface device structure 1878 * 1879 * Returns the address of the device statistics structure. 1880 * The statistics are updated here and also from the timer callback. 1881 */ 1882 static struct net_device_stats *igc_get_stats(struct net_device *netdev) 1883 { 1884 struct igc_adapter *adapter = netdev_priv(netdev); 1885 1886 if (!test_bit(__IGC_RESETTING, &adapter->state)) 1887 igc_update_stats(adapter); 1888 1889 /* only return the current stats */ 1890 return &netdev->stats; 1891 } 1892 1893 /** 1894 * igc_configure - configure the hardware for RX and TX 1895 * @adapter: private board structure 1896 */ 1897 static void igc_configure(struct igc_adapter *adapter) 1898 { 1899 struct net_device *netdev = adapter->netdev; 1900 int i = 0; 1901 1902 igc_get_hw_control(adapter); 1903 igc_set_rx_mode(netdev); 1904 1905 igc_setup_tctl(adapter); 1906 igc_setup_mrqc(adapter); 1907 igc_setup_rctl(adapter); 1908 1909 igc_configure_tx(adapter); 1910 igc_configure_rx(adapter); 1911 1912 igc_rx_fifo_flush_base(&adapter->hw); 1913 1914 /* call igc_desc_unused which always leaves 1915 * at least 1 descriptor unused to make sure 1916 * next_to_use != next_to_clean 1917 */ 1918 for (i = 0; i < adapter->num_rx_queues; i++) { 1919 struct igc_ring *ring = adapter->rx_ring[i]; 1920 1921 igc_alloc_rx_buffers(ring, igc_desc_unused(ring)); 1922 } 1923 } 1924 1925 /** 1926 * igc_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 1927 * @adapter: address of board private structure 1928 * @index: Index of the RAR entry which need to be synced with MAC table 1929 */ 1930 static void igc_rar_set_index(struct igc_adapter *adapter, u32 index) 1931 { 1932 u8 *addr = adapter->mac_table[index].addr; 1933 struct igc_hw *hw = &adapter->hw; 1934 u32 rar_low, rar_high; 1935 1936 /* HW expects these to be in network order when they are plugged 1937 * into the registers which are little endian. In order to guarantee 1938 * that ordering we need to do an leXX_to_cpup here in order to be 1939 * ready for the byteswap that occurs with writel 1940 */ 1941 rar_low = le32_to_cpup((__le32 *)(addr)); 1942 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 1943 1944 /* Indicate to hardware the Address is Valid. */ 1945 if (adapter->mac_table[index].state & IGC_MAC_STATE_IN_USE) { 1946 if (is_valid_ether_addr(addr)) 1947 rar_high |= IGC_RAH_AV; 1948 1949 rar_high |= IGC_RAH_POOL_1 << 1950 adapter->mac_table[index].queue; 1951 } 1952 1953 wr32(IGC_RAL(index), rar_low); 1954 wrfl(); 1955 wr32(IGC_RAH(index), rar_high); 1956 wrfl(); 1957 } 1958 1959 /* Set default MAC address for the PF in the first RAR entry */ 1960 static void igc_set_default_mac_filter(struct igc_adapter *adapter) 1961 { 1962 struct igc_mac_addr *mac_table = &adapter->mac_table[0]; 1963 1964 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 1965 mac_table->state = IGC_MAC_STATE_DEFAULT | IGC_MAC_STATE_IN_USE; 1966 1967 igc_rar_set_index(adapter, 0); 1968 } 1969 1970 /** 1971 * igc_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 1972 * @netdev: network interface device structure 1973 * 1974 * The set_rx_mode entry point is called whenever the unicast or multicast 1975 * address lists or the network interface flags are updated. This routine is 1976 * responsible for configuring the hardware for proper unicast, multicast, 1977 * promiscuous mode, and all-multi behavior. 1978 */ 1979 static void igc_set_rx_mode(struct net_device *netdev) 1980 { 1981 } 1982 1983 /** 1984 * igc_msix_other - msix other interrupt handler 1985 * @irq: interrupt number 1986 * @data: pointer to a q_vector 1987 */ 1988 static irqreturn_t igc_msix_other(int irq, void *data) 1989 { 1990 struct igc_adapter *adapter = data; 1991 struct igc_hw *hw = &adapter->hw; 1992 u32 icr = rd32(IGC_ICR); 1993 1994 /* reading ICR causes bit 31 of EICR to be cleared */ 1995 if (icr & IGC_ICR_DRSTA) 1996 schedule_work(&adapter->reset_task); 1997 1998 if (icr & IGC_ICR_DOUTSYNC) { 1999 /* HW is reporting DMA is out of sync */ 2000 adapter->stats.doosync++; 2001 } 2002 2003 if (icr & IGC_ICR_LSC) { 2004 hw->mac.get_link_status = 1; 2005 /* guard against interrupt when we're going down */ 2006 if (!test_bit(__IGC_DOWN, &adapter->state)) 2007 mod_timer(&adapter->watchdog_timer, jiffies + 1); 2008 } 2009 2010 wr32(IGC_EIMS, adapter->eims_other); 2011 2012 return IRQ_HANDLED; 2013 } 2014 2015 /** 2016 * igc_write_ivar - configure ivar for given MSI-X vector 2017 * @hw: pointer to the HW structure 2018 * @msix_vector: vector number we are allocating to a given ring 2019 * @index: row index of IVAR register to write within IVAR table 2020 * @offset: column offset of in IVAR, should be multiple of 8 2021 * 2022 * The IVAR table consists of 2 columns, 2023 * each containing an cause allocation for an Rx and Tx ring, and a 2024 * variable number of rows depending on the number of queues supported. 2025 */ 2026 static void igc_write_ivar(struct igc_hw *hw, int msix_vector, 2027 int index, int offset) 2028 { 2029 u32 ivar = array_rd32(IGC_IVAR0, index); 2030 2031 /* clear any bits that are currently set */ 2032 ivar &= ~((u32)0xFF << offset); 2033 2034 /* write vector and valid bit */ 2035 ivar |= (msix_vector | IGC_IVAR_VALID) << offset; 2036 2037 array_wr32(IGC_IVAR0, index, ivar); 2038 } 2039 2040 static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector) 2041 { 2042 struct igc_adapter *adapter = q_vector->adapter; 2043 struct igc_hw *hw = &adapter->hw; 2044 int rx_queue = IGC_N0_QUEUE; 2045 int tx_queue = IGC_N0_QUEUE; 2046 2047 if (q_vector->rx.ring) 2048 rx_queue = q_vector->rx.ring->reg_idx; 2049 if (q_vector->tx.ring) 2050 tx_queue = q_vector->tx.ring->reg_idx; 2051 2052 switch (hw->mac.type) { 2053 case igc_i225: 2054 if (rx_queue > IGC_N0_QUEUE) 2055 igc_write_ivar(hw, msix_vector, 2056 rx_queue >> 1, 2057 (rx_queue & 0x1) << 4); 2058 if (tx_queue > IGC_N0_QUEUE) 2059 igc_write_ivar(hw, msix_vector, 2060 tx_queue >> 1, 2061 ((tx_queue & 0x1) << 4) + 8); 2062 q_vector->eims_value = BIT(msix_vector); 2063 break; 2064 default: 2065 WARN_ONCE(hw->mac.type != igc_i225, "Wrong MAC type\n"); 2066 break; 2067 } 2068 2069 /* add q_vector eims value to global eims_enable_mask */ 2070 adapter->eims_enable_mask |= q_vector->eims_value; 2071 2072 /* configure q_vector to set itr on first interrupt */ 2073 q_vector->set_itr = 1; 2074 } 2075 2076 /** 2077 * igc_configure_msix - Configure MSI-X hardware 2078 * @adapter: Pointer to adapter structure 2079 * 2080 * igc_configure_msix sets up the hardware to properly 2081 * generate MSI-X interrupts. 2082 */ 2083 static void igc_configure_msix(struct igc_adapter *adapter) 2084 { 2085 struct igc_hw *hw = &adapter->hw; 2086 int i, vector = 0; 2087 u32 tmp; 2088 2089 adapter->eims_enable_mask = 0; 2090 2091 /* set vector for other causes, i.e. link changes */ 2092 switch (hw->mac.type) { 2093 case igc_i225: 2094 /* Turn on MSI-X capability first, or our settings 2095 * won't stick. And it will take days to debug. 2096 */ 2097 wr32(IGC_GPIE, IGC_GPIE_MSIX_MODE | 2098 IGC_GPIE_PBA | IGC_GPIE_EIAME | 2099 IGC_GPIE_NSICR); 2100 2101 /* enable msix_other interrupt */ 2102 adapter->eims_other = BIT(vector); 2103 tmp = (vector++ | IGC_IVAR_VALID) << 8; 2104 2105 wr32(IGC_IVAR_MISC, tmp); 2106 break; 2107 default: 2108 /* do nothing, since nothing else supports MSI-X */ 2109 break; 2110 } /* switch (hw->mac.type) */ 2111 2112 adapter->eims_enable_mask |= adapter->eims_other; 2113 2114 for (i = 0; i < adapter->num_q_vectors; i++) 2115 igc_assign_vector(adapter->q_vector[i], vector++); 2116 2117 wrfl(); 2118 } 2119 2120 static irqreturn_t igc_msix_ring(int irq, void *data) 2121 { 2122 struct igc_q_vector *q_vector = data; 2123 2124 /* Write the ITR value calculated from the previous interrupt. */ 2125 igc_write_itr(q_vector); 2126 2127 napi_schedule(&q_vector->napi); 2128 2129 return IRQ_HANDLED; 2130 } 2131 2132 /** 2133 * igc_request_msix - Initialize MSI-X interrupts 2134 * @adapter: Pointer to adapter structure 2135 * 2136 * igc_request_msix allocates MSI-X vectors and requests interrupts from the 2137 * kernel. 2138 */ 2139 static int igc_request_msix(struct igc_adapter *adapter) 2140 { 2141 int i = 0, err = 0, vector = 0, free_vector = 0; 2142 struct net_device *netdev = adapter->netdev; 2143 2144 err = request_irq(adapter->msix_entries[vector].vector, 2145 &igc_msix_other, 0, netdev->name, adapter); 2146 if (err) 2147 goto err_out; 2148 2149 for (i = 0; i < adapter->num_q_vectors; i++) { 2150 struct igc_q_vector *q_vector = adapter->q_vector[i]; 2151 2152 vector++; 2153 2154 q_vector->itr_register = adapter->io_addr + IGC_EITR(vector); 2155 2156 if (q_vector->rx.ring && q_vector->tx.ring) 2157 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 2158 q_vector->rx.ring->queue_index); 2159 else if (q_vector->tx.ring) 2160 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 2161 q_vector->tx.ring->queue_index); 2162 else if (q_vector->rx.ring) 2163 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 2164 q_vector->rx.ring->queue_index); 2165 else 2166 sprintf(q_vector->name, "%s-unused", netdev->name); 2167 2168 err = request_irq(adapter->msix_entries[vector].vector, 2169 igc_msix_ring, 0, q_vector->name, 2170 q_vector); 2171 if (err) 2172 goto err_free; 2173 } 2174 2175 igc_configure_msix(adapter); 2176 return 0; 2177 2178 err_free: 2179 /* free already assigned IRQs */ 2180 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 2181 2182 vector--; 2183 for (i = 0; i < vector; i++) { 2184 free_irq(adapter->msix_entries[free_vector++].vector, 2185 adapter->q_vector[i]); 2186 } 2187 err_out: 2188 return err; 2189 } 2190 2191 /** 2192 * igc_reset_q_vector - Reset config for interrupt vector 2193 * @adapter: board private structure to initialize 2194 * @v_idx: Index of vector to be reset 2195 * 2196 * If NAPI is enabled it will delete any references to the 2197 * NAPI struct. This is preparation for igc_free_q_vector. 2198 */ 2199 static void igc_reset_q_vector(struct igc_adapter *adapter, int v_idx) 2200 { 2201 struct igc_q_vector *q_vector = adapter->q_vector[v_idx]; 2202 2203 /* if we're coming from igc_set_interrupt_capability, the vectors are 2204 * not yet allocated 2205 */ 2206 if (!q_vector) 2207 return; 2208 2209 if (q_vector->tx.ring) 2210 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 2211 2212 if (q_vector->rx.ring) 2213 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 2214 2215 netif_napi_del(&q_vector->napi); 2216 } 2217 2218 static void igc_reset_interrupt_capability(struct igc_adapter *adapter) 2219 { 2220 int v_idx = adapter->num_q_vectors; 2221 2222 if (adapter->msix_entries) { 2223 pci_disable_msix(adapter->pdev); 2224 kfree(adapter->msix_entries); 2225 adapter->msix_entries = NULL; 2226 } else if (adapter->flags & IGC_FLAG_HAS_MSI) { 2227 pci_disable_msi(adapter->pdev); 2228 } 2229 2230 while (v_idx--) 2231 igc_reset_q_vector(adapter, v_idx); 2232 } 2233 2234 /** 2235 * igc_clear_interrupt_scheme - reset the device to a state of no interrupts 2236 * @adapter: Pointer to adapter structure 2237 * 2238 * This function resets the device so that it has 0 rx queues, tx queues, and 2239 * MSI-X interrupts allocated. 2240 */ 2241 static void igc_clear_interrupt_scheme(struct igc_adapter *adapter) 2242 { 2243 igc_free_q_vectors(adapter); 2244 igc_reset_interrupt_capability(adapter); 2245 } 2246 2247 /** 2248 * igc_free_q_vectors - Free memory allocated for interrupt vectors 2249 * @adapter: board private structure to initialize 2250 * 2251 * This function frees the memory allocated to the q_vectors. In addition if 2252 * NAPI is enabled it will delete any references to the NAPI struct prior 2253 * to freeing the q_vector. 2254 */ 2255 static void igc_free_q_vectors(struct igc_adapter *adapter) 2256 { 2257 int v_idx = adapter->num_q_vectors; 2258 2259 adapter->num_tx_queues = 0; 2260 adapter->num_rx_queues = 0; 2261 adapter->num_q_vectors = 0; 2262 2263 while (v_idx--) { 2264 igc_reset_q_vector(adapter, v_idx); 2265 igc_free_q_vector(adapter, v_idx); 2266 } 2267 } 2268 2269 /** 2270 * igc_free_q_vector - Free memory allocated for specific interrupt vector 2271 * @adapter: board private structure to initialize 2272 * @v_idx: Index of vector to be freed 2273 * 2274 * This function frees the memory allocated to the q_vector. 2275 */ 2276 static void igc_free_q_vector(struct igc_adapter *adapter, int v_idx) 2277 { 2278 struct igc_q_vector *q_vector = adapter->q_vector[v_idx]; 2279 2280 adapter->q_vector[v_idx] = NULL; 2281 2282 /* igc_get_stats64() might access the rings on this vector, 2283 * we must wait a grace period before freeing it. 2284 */ 2285 if (q_vector) 2286 kfree_rcu(q_vector, rcu); 2287 } 2288 2289 /* Need to wait a few seconds after link up to get diagnostic information from 2290 * the phy 2291 */ 2292 static void igc_update_phy_info(struct timer_list *t) 2293 { 2294 struct igc_adapter *adapter = from_timer(adapter, t, phy_info_timer); 2295 2296 igc_get_phy_info(&adapter->hw); 2297 } 2298 2299 /** 2300 * igc_has_link - check shared code for link and determine up/down 2301 * @adapter: pointer to driver private info 2302 */ 2303 bool igc_has_link(struct igc_adapter *adapter) 2304 { 2305 struct igc_hw *hw = &adapter->hw; 2306 bool link_active = false; 2307 2308 /* get_link_status is set on LSC (link status) interrupt or 2309 * rx sequence error interrupt. get_link_status will stay 2310 * false until the igc_check_for_link establishes link 2311 * for copper adapters ONLY 2312 */ 2313 switch (hw->phy.media_type) { 2314 case igc_media_type_copper: 2315 if (!hw->mac.get_link_status) 2316 return true; 2317 hw->mac.ops.check_for_link(hw); 2318 link_active = !hw->mac.get_link_status; 2319 break; 2320 default: 2321 case igc_media_type_unknown: 2322 break; 2323 } 2324 2325 if (hw->mac.type == igc_i225 && 2326 hw->phy.id == I225_I_PHY_ID) { 2327 if (!netif_carrier_ok(adapter->netdev)) { 2328 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE; 2329 } else if (!(adapter->flags & IGC_FLAG_NEED_LINK_UPDATE)) { 2330 adapter->flags |= IGC_FLAG_NEED_LINK_UPDATE; 2331 adapter->link_check_timeout = jiffies; 2332 } 2333 } 2334 2335 return link_active; 2336 } 2337 2338 /** 2339 * igc_watchdog - Timer Call-back 2340 * @data: pointer to adapter cast into an unsigned long 2341 */ 2342 static void igc_watchdog(struct timer_list *t) 2343 { 2344 struct igc_adapter *adapter = from_timer(adapter, t, watchdog_timer); 2345 /* Do the rest outside of interrupt context */ 2346 schedule_work(&adapter->watchdog_task); 2347 } 2348 2349 static void igc_watchdog_task(struct work_struct *work) 2350 { 2351 struct igc_adapter *adapter = container_of(work, 2352 struct igc_adapter, 2353 watchdog_task); 2354 struct net_device *netdev = adapter->netdev; 2355 struct igc_hw *hw = &adapter->hw; 2356 struct igc_phy_info *phy = &hw->phy; 2357 u16 phy_data, retry_count = 20; 2358 u32 connsw; 2359 u32 link; 2360 int i; 2361 2362 link = igc_has_link(adapter); 2363 2364 if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE) { 2365 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 2366 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE; 2367 else 2368 link = false; 2369 } 2370 2371 /* Force link down if we have fiber to swap to */ 2372 if (adapter->flags & IGC_FLAG_MAS_ENABLE) { 2373 if (hw->phy.media_type == igc_media_type_copper) { 2374 connsw = rd32(IGC_CONNSW); 2375 if (!(connsw & IGC_CONNSW_AUTOSENSE_EN)) 2376 link = 0; 2377 } 2378 } 2379 if (link) { 2380 if (!netif_carrier_ok(netdev)) { 2381 u32 ctrl; 2382 2383 hw->mac.ops.get_speed_and_duplex(hw, 2384 &adapter->link_speed, 2385 &adapter->link_duplex); 2386 2387 ctrl = rd32(IGC_CTRL); 2388 /* Link status message must follow this format */ 2389 netdev_info(netdev, 2390 "igc: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 2391 netdev->name, 2392 adapter->link_speed, 2393 adapter->link_duplex == FULL_DUPLEX ? 2394 "Full" : "Half", 2395 (ctrl & IGC_CTRL_TFCE) && 2396 (ctrl & IGC_CTRL_RFCE) ? "RX/TX" : 2397 (ctrl & IGC_CTRL_RFCE) ? "RX" : 2398 (ctrl & IGC_CTRL_TFCE) ? "TX" : "None"); 2399 2400 /* check if SmartSpeed worked */ 2401 igc_check_downshift(hw); 2402 if (phy->speed_downgraded) 2403 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 2404 2405 /* adjust timeout factor according to speed/duplex */ 2406 adapter->tx_timeout_factor = 1; 2407 switch (adapter->link_speed) { 2408 case SPEED_10: 2409 adapter->tx_timeout_factor = 14; 2410 break; 2411 case SPEED_100: 2412 /* maybe add some timeout factor ? */ 2413 break; 2414 } 2415 2416 if (adapter->link_speed != SPEED_1000) 2417 goto no_wait; 2418 2419 /* wait for Remote receiver status OK */ 2420 retry_read_status: 2421 if (!igc_read_phy_reg(hw, PHY_1000T_STATUS, 2422 &phy_data)) { 2423 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 2424 retry_count) { 2425 msleep(100); 2426 retry_count--; 2427 goto retry_read_status; 2428 } else if (!retry_count) { 2429 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 2430 } 2431 } else { 2432 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 2433 } 2434 no_wait: 2435 netif_carrier_on(netdev); 2436 2437 /* link state has changed, schedule phy info update */ 2438 if (!test_bit(__IGC_DOWN, &adapter->state)) 2439 mod_timer(&adapter->phy_info_timer, 2440 round_jiffies(jiffies + 2 * HZ)); 2441 } 2442 } else { 2443 if (netif_carrier_ok(netdev)) { 2444 adapter->link_speed = 0; 2445 adapter->link_duplex = 0; 2446 2447 /* Links status message must follow this format */ 2448 netdev_info(netdev, "igc: %s NIC Link is Down\n", 2449 netdev->name); 2450 netif_carrier_off(netdev); 2451 2452 /* link state has changed, schedule phy info update */ 2453 if (!test_bit(__IGC_DOWN, &adapter->state)) 2454 mod_timer(&adapter->phy_info_timer, 2455 round_jiffies(jiffies + 2 * HZ)); 2456 2457 /* link is down, time to check for alternate media */ 2458 if (adapter->flags & IGC_FLAG_MAS_ENABLE) { 2459 if (adapter->flags & IGC_FLAG_MEDIA_RESET) { 2460 schedule_work(&adapter->reset_task); 2461 /* return immediately */ 2462 return; 2463 } 2464 } 2465 2466 /* also check for alternate media here */ 2467 } else if (!netif_carrier_ok(netdev) && 2468 (adapter->flags & IGC_FLAG_MAS_ENABLE)) { 2469 if (adapter->flags & IGC_FLAG_MEDIA_RESET) { 2470 schedule_work(&adapter->reset_task); 2471 /* return immediately */ 2472 return; 2473 } 2474 } 2475 } 2476 2477 spin_lock(&adapter->stats64_lock); 2478 igc_update_stats(adapter); 2479 spin_unlock(&adapter->stats64_lock); 2480 2481 for (i = 0; i < adapter->num_tx_queues; i++) { 2482 struct igc_ring *tx_ring = adapter->tx_ring[i]; 2483 2484 if (!netif_carrier_ok(netdev)) { 2485 /* We've lost link, so the controller stops DMA, 2486 * but we've got queued Tx work that's never going 2487 * to get done, so reset controller to flush Tx. 2488 * (Do the reset outside of interrupt context). 2489 */ 2490 if (igc_desc_unused(tx_ring) + 1 < tx_ring->count) { 2491 adapter->tx_timeout_count++; 2492 schedule_work(&adapter->reset_task); 2493 /* return immediately since reset is imminent */ 2494 return; 2495 } 2496 } 2497 2498 /* Force detection of hung controller every watchdog period */ 2499 set_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 2500 } 2501 2502 /* Cause software interrupt to ensure Rx ring is cleaned */ 2503 if (adapter->flags & IGC_FLAG_HAS_MSIX) { 2504 u32 eics = 0; 2505 2506 for (i = 0; i < adapter->num_q_vectors; i++) 2507 eics |= adapter->q_vector[i]->eims_value; 2508 wr32(IGC_EICS, eics); 2509 } else { 2510 wr32(IGC_ICS, IGC_ICS_RXDMT0); 2511 } 2512 2513 /* Reset the timer */ 2514 if (!test_bit(__IGC_DOWN, &adapter->state)) { 2515 if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE) 2516 mod_timer(&adapter->watchdog_timer, 2517 round_jiffies(jiffies + HZ)); 2518 else 2519 mod_timer(&adapter->watchdog_timer, 2520 round_jiffies(jiffies + 2 * HZ)); 2521 } 2522 } 2523 2524 /** 2525 * igc_update_ring_itr - update the dynamic ITR value based on packet size 2526 * @q_vector: pointer to q_vector 2527 * 2528 * Stores a new ITR value based on strictly on packet size. This 2529 * algorithm is less sophisticated than that used in igc_update_itr, 2530 * due to the difficulty of synchronizing statistics across multiple 2531 * receive rings. The divisors and thresholds used by this function 2532 * were determined based on theoretical maximum wire speed and testing 2533 * data, in order to minimize response time while increasing bulk 2534 * throughput. 2535 * NOTE: This function is called only when operating in a multiqueue 2536 * receive environment. 2537 */ 2538 static void igc_update_ring_itr(struct igc_q_vector *q_vector) 2539 { 2540 struct igc_adapter *adapter = q_vector->adapter; 2541 int new_val = q_vector->itr_val; 2542 int avg_wire_size = 0; 2543 unsigned int packets; 2544 2545 /* For non-gigabit speeds, just fix the interrupt rate at 4000 2546 * ints/sec - ITR timer value of 120 ticks. 2547 */ 2548 switch (adapter->link_speed) { 2549 case SPEED_10: 2550 case SPEED_100: 2551 new_val = IGC_4K_ITR; 2552 goto set_itr_val; 2553 default: 2554 break; 2555 } 2556 2557 packets = q_vector->rx.total_packets; 2558 if (packets) 2559 avg_wire_size = q_vector->rx.total_bytes / packets; 2560 2561 packets = q_vector->tx.total_packets; 2562 if (packets) 2563 avg_wire_size = max_t(u32, avg_wire_size, 2564 q_vector->tx.total_bytes / packets); 2565 2566 /* if avg_wire_size isn't set no work was done */ 2567 if (!avg_wire_size) 2568 goto clear_counts; 2569 2570 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 2571 avg_wire_size += 24; 2572 2573 /* Don't starve jumbo frames */ 2574 avg_wire_size = min(avg_wire_size, 3000); 2575 2576 /* Give a little boost to mid-size frames */ 2577 if (avg_wire_size > 300 && avg_wire_size < 1200) 2578 new_val = avg_wire_size / 3; 2579 else 2580 new_val = avg_wire_size / 2; 2581 2582 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2583 if (new_val < IGC_20K_ITR && 2584 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 2585 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 2586 new_val = IGC_20K_ITR; 2587 2588 set_itr_val: 2589 if (new_val != q_vector->itr_val) { 2590 q_vector->itr_val = new_val; 2591 q_vector->set_itr = 1; 2592 } 2593 clear_counts: 2594 q_vector->rx.total_bytes = 0; 2595 q_vector->rx.total_packets = 0; 2596 q_vector->tx.total_bytes = 0; 2597 q_vector->tx.total_packets = 0; 2598 } 2599 2600 /** 2601 * igc_update_itr - update the dynamic ITR value based on statistics 2602 * @q_vector: pointer to q_vector 2603 * @ring_container: ring info to update the itr for 2604 * 2605 * Stores a new ITR value based on packets and byte 2606 * counts during the last interrupt. The advantage of per interrupt 2607 * computation is faster updates and more accurate ITR for the current 2608 * traffic pattern. Constants in this function were computed 2609 * based on theoretical maximum wire speed and thresholds were set based 2610 * on testing data as well as attempting to minimize response time 2611 * while increasing bulk throughput. 2612 * NOTE: These calculations are only valid when operating in a single- 2613 * queue environment. 2614 */ 2615 static void igc_update_itr(struct igc_q_vector *q_vector, 2616 struct igc_ring_container *ring_container) 2617 { 2618 unsigned int packets = ring_container->total_packets; 2619 unsigned int bytes = ring_container->total_bytes; 2620 u8 itrval = ring_container->itr; 2621 2622 /* no packets, exit with status unchanged */ 2623 if (packets == 0) 2624 return; 2625 2626 switch (itrval) { 2627 case lowest_latency: 2628 /* handle TSO and jumbo frames */ 2629 if (bytes / packets > 8000) 2630 itrval = bulk_latency; 2631 else if ((packets < 5) && (bytes > 512)) 2632 itrval = low_latency; 2633 break; 2634 case low_latency: /* 50 usec aka 20000 ints/s */ 2635 if (bytes > 10000) { 2636 /* this if handles the TSO accounting */ 2637 if (bytes / packets > 8000) 2638 itrval = bulk_latency; 2639 else if ((packets < 10) || ((bytes / packets) > 1200)) 2640 itrval = bulk_latency; 2641 else if ((packets > 35)) 2642 itrval = lowest_latency; 2643 } else if (bytes / packets > 2000) { 2644 itrval = bulk_latency; 2645 } else if (packets <= 2 && bytes < 512) { 2646 itrval = lowest_latency; 2647 } 2648 break; 2649 case bulk_latency: /* 250 usec aka 4000 ints/s */ 2650 if (bytes > 25000) { 2651 if (packets > 35) 2652 itrval = low_latency; 2653 } else if (bytes < 1500) { 2654 itrval = low_latency; 2655 } 2656 break; 2657 } 2658 2659 /* clear work counters since we have the values we need */ 2660 ring_container->total_bytes = 0; 2661 ring_container->total_packets = 0; 2662 2663 /* write updated itr to ring container */ 2664 ring_container->itr = itrval; 2665 } 2666 2667 /** 2668 * igc_intr_msi - Interrupt Handler 2669 * @irq: interrupt number 2670 * @data: pointer to a network interface device structure 2671 */ 2672 static irqreturn_t igc_intr_msi(int irq, void *data) 2673 { 2674 struct igc_adapter *adapter = data; 2675 struct igc_q_vector *q_vector = adapter->q_vector[0]; 2676 struct igc_hw *hw = &adapter->hw; 2677 /* read ICR disables interrupts using IAM */ 2678 u32 icr = rd32(IGC_ICR); 2679 2680 igc_write_itr(q_vector); 2681 2682 if (icr & IGC_ICR_DRSTA) 2683 schedule_work(&adapter->reset_task); 2684 2685 if (icr & IGC_ICR_DOUTSYNC) { 2686 /* HW is reporting DMA is out of sync */ 2687 adapter->stats.doosync++; 2688 } 2689 2690 if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) { 2691 hw->mac.get_link_status = 1; 2692 if (!test_bit(__IGC_DOWN, &adapter->state)) 2693 mod_timer(&adapter->watchdog_timer, jiffies + 1); 2694 } 2695 2696 napi_schedule(&q_vector->napi); 2697 2698 return IRQ_HANDLED; 2699 } 2700 2701 /** 2702 * igc_intr - Legacy Interrupt Handler 2703 * @irq: interrupt number 2704 * @data: pointer to a network interface device structure 2705 */ 2706 static irqreturn_t igc_intr(int irq, void *data) 2707 { 2708 struct igc_adapter *adapter = data; 2709 struct igc_q_vector *q_vector = adapter->q_vector[0]; 2710 struct igc_hw *hw = &adapter->hw; 2711 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 2712 * need for the IMC write 2713 */ 2714 u32 icr = rd32(IGC_ICR); 2715 2716 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 2717 * not set, then the adapter didn't send an interrupt 2718 */ 2719 if (!(icr & IGC_ICR_INT_ASSERTED)) 2720 return IRQ_NONE; 2721 2722 igc_write_itr(q_vector); 2723 2724 if (icr & IGC_ICR_DRSTA) 2725 schedule_work(&adapter->reset_task); 2726 2727 if (icr & IGC_ICR_DOUTSYNC) { 2728 /* HW is reporting DMA is out of sync */ 2729 adapter->stats.doosync++; 2730 } 2731 2732 if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) { 2733 hw->mac.get_link_status = 1; 2734 /* guard against interrupt when we're going down */ 2735 if (!test_bit(__IGC_DOWN, &adapter->state)) 2736 mod_timer(&adapter->watchdog_timer, jiffies + 1); 2737 } 2738 2739 napi_schedule(&q_vector->napi); 2740 2741 return IRQ_HANDLED; 2742 } 2743 2744 static void igc_set_itr(struct igc_q_vector *q_vector) 2745 { 2746 struct igc_adapter *adapter = q_vector->adapter; 2747 u32 new_itr = q_vector->itr_val; 2748 u8 current_itr = 0; 2749 2750 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 2751 switch (adapter->link_speed) { 2752 case SPEED_10: 2753 case SPEED_100: 2754 current_itr = 0; 2755 new_itr = IGC_4K_ITR; 2756 goto set_itr_now; 2757 default: 2758 break; 2759 } 2760 2761 igc_update_itr(q_vector, &q_vector->tx); 2762 igc_update_itr(q_vector, &q_vector->rx); 2763 2764 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 2765 2766 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 2767 if (current_itr == lowest_latency && 2768 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 2769 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 2770 current_itr = low_latency; 2771 2772 switch (current_itr) { 2773 /* counts and packets in update_itr are dependent on these numbers */ 2774 case lowest_latency: 2775 new_itr = IGC_70K_ITR; /* 70,000 ints/sec */ 2776 break; 2777 case low_latency: 2778 new_itr = IGC_20K_ITR; /* 20,000 ints/sec */ 2779 break; 2780 case bulk_latency: 2781 new_itr = IGC_4K_ITR; /* 4,000 ints/sec */ 2782 break; 2783 default: 2784 break; 2785 } 2786 2787 set_itr_now: 2788 if (new_itr != q_vector->itr_val) { 2789 /* this attempts to bias the interrupt rate towards Bulk 2790 * by adding intermediate steps when interrupt rate is 2791 * increasing 2792 */ 2793 new_itr = new_itr > q_vector->itr_val ? 2794 max((new_itr * q_vector->itr_val) / 2795 (new_itr + (q_vector->itr_val >> 2)), 2796 new_itr) : new_itr; 2797 /* Don't write the value here; it resets the adapter's 2798 * internal timer, and causes us to delay far longer than 2799 * we should between interrupts. Instead, we write the ITR 2800 * value at the beginning of the next interrupt so the timing 2801 * ends up being correct. 2802 */ 2803 q_vector->itr_val = new_itr; 2804 q_vector->set_itr = 1; 2805 } 2806 } 2807 2808 static void igc_ring_irq_enable(struct igc_q_vector *q_vector) 2809 { 2810 struct igc_adapter *adapter = q_vector->adapter; 2811 struct igc_hw *hw = &adapter->hw; 2812 2813 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 2814 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 2815 if (adapter->num_q_vectors == 1) 2816 igc_set_itr(q_vector); 2817 else 2818 igc_update_ring_itr(q_vector); 2819 } 2820 2821 if (!test_bit(__IGC_DOWN, &adapter->state)) { 2822 if (adapter->msix_entries) 2823 wr32(IGC_EIMS, q_vector->eims_value); 2824 else 2825 igc_irq_enable(adapter); 2826 } 2827 } 2828 2829 /** 2830 * igc_poll - NAPI Rx polling callback 2831 * @napi: napi polling structure 2832 * @budget: count of how many packets we should handle 2833 */ 2834 static int igc_poll(struct napi_struct *napi, int budget) 2835 { 2836 struct igc_q_vector *q_vector = container_of(napi, 2837 struct igc_q_vector, 2838 napi); 2839 bool clean_complete = true; 2840 int work_done = 0; 2841 2842 if (q_vector->tx.ring) 2843 clean_complete = igc_clean_tx_irq(q_vector, budget); 2844 2845 if (q_vector->rx.ring) { 2846 int cleaned = igc_clean_rx_irq(q_vector, budget); 2847 2848 work_done += cleaned; 2849 if (cleaned >= budget) 2850 clean_complete = false; 2851 } 2852 2853 /* If all work not completed, return budget and keep polling */ 2854 if (!clean_complete) 2855 return budget; 2856 2857 /* Exit the polling mode, but don't re-enable interrupts if stack might 2858 * poll us due to busy-polling 2859 */ 2860 if (likely(napi_complete_done(napi, work_done))) 2861 igc_ring_irq_enable(q_vector); 2862 2863 return min(work_done, budget - 1); 2864 } 2865 2866 /** 2867 * igc_set_interrupt_capability - set MSI or MSI-X if supported 2868 * @adapter: Pointer to adapter structure 2869 * 2870 * Attempt to configure interrupts using the best available 2871 * capabilities of the hardware and kernel. 2872 */ 2873 static void igc_set_interrupt_capability(struct igc_adapter *adapter, 2874 bool msix) 2875 { 2876 int numvecs, i; 2877 int err; 2878 2879 if (!msix) 2880 goto msi_only; 2881 adapter->flags |= IGC_FLAG_HAS_MSIX; 2882 2883 /* Number of supported queues. */ 2884 adapter->num_rx_queues = adapter->rss_queues; 2885 2886 adapter->num_tx_queues = adapter->rss_queues; 2887 2888 /* start with one vector for every Rx queue */ 2889 numvecs = adapter->num_rx_queues; 2890 2891 /* if Tx handler is separate add 1 for every Tx queue */ 2892 if (!(adapter->flags & IGC_FLAG_QUEUE_PAIRS)) 2893 numvecs += adapter->num_tx_queues; 2894 2895 /* store the number of vectors reserved for queues */ 2896 adapter->num_q_vectors = numvecs; 2897 2898 /* add 1 vector for link status interrupts */ 2899 numvecs++; 2900 2901 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), 2902 GFP_KERNEL); 2903 2904 if (!adapter->msix_entries) 2905 return; 2906 2907 /* populate entry values */ 2908 for (i = 0; i < numvecs; i++) 2909 adapter->msix_entries[i].entry = i; 2910 2911 err = pci_enable_msix_range(adapter->pdev, 2912 adapter->msix_entries, 2913 numvecs, 2914 numvecs); 2915 if (err > 0) 2916 return; 2917 2918 kfree(adapter->msix_entries); 2919 adapter->msix_entries = NULL; 2920 2921 igc_reset_interrupt_capability(adapter); 2922 2923 msi_only: 2924 adapter->flags &= ~IGC_FLAG_HAS_MSIX; 2925 2926 adapter->rss_queues = 1; 2927 adapter->flags |= IGC_FLAG_QUEUE_PAIRS; 2928 adapter->num_rx_queues = 1; 2929 adapter->num_tx_queues = 1; 2930 adapter->num_q_vectors = 1; 2931 if (!pci_enable_msi(adapter->pdev)) 2932 adapter->flags |= IGC_FLAG_HAS_MSI; 2933 } 2934 2935 static void igc_add_ring(struct igc_ring *ring, 2936 struct igc_ring_container *head) 2937 { 2938 head->ring = ring; 2939 head->count++; 2940 } 2941 2942 /** 2943 * igc_alloc_q_vector - Allocate memory for a single interrupt vector 2944 * @adapter: board private structure to initialize 2945 * @v_count: q_vectors allocated on adapter, used for ring interleaving 2946 * @v_idx: index of vector in adapter struct 2947 * @txr_count: total number of Tx rings to allocate 2948 * @txr_idx: index of first Tx ring to allocate 2949 * @rxr_count: total number of Rx rings to allocate 2950 * @rxr_idx: index of first Rx ring to allocate 2951 * 2952 * We allocate one q_vector. If allocation fails we return -ENOMEM. 2953 */ 2954 static int igc_alloc_q_vector(struct igc_adapter *adapter, 2955 unsigned int v_count, unsigned int v_idx, 2956 unsigned int txr_count, unsigned int txr_idx, 2957 unsigned int rxr_count, unsigned int rxr_idx) 2958 { 2959 struct igc_q_vector *q_vector; 2960 struct igc_ring *ring; 2961 int ring_count; 2962 2963 /* igc only supports 1 Tx and/or 1 Rx queue per vector */ 2964 if (txr_count > 1 || rxr_count > 1) 2965 return -ENOMEM; 2966 2967 ring_count = txr_count + rxr_count; 2968 2969 /* allocate q_vector and rings */ 2970 q_vector = adapter->q_vector[v_idx]; 2971 if (!q_vector) 2972 q_vector = kzalloc(struct_size(q_vector, ring, ring_count), 2973 GFP_KERNEL); 2974 else 2975 memset(q_vector, 0, struct_size(q_vector, ring, ring_count)); 2976 if (!q_vector) 2977 return -ENOMEM; 2978 2979 /* initialize NAPI */ 2980 netif_napi_add(adapter->netdev, &q_vector->napi, 2981 igc_poll, 64); 2982 2983 /* tie q_vector and adapter together */ 2984 adapter->q_vector[v_idx] = q_vector; 2985 q_vector->adapter = adapter; 2986 2987 /* initialize work limits */ 2988 q_vector->tx.work_limit = adapter->tx_work_limit; 2989 2990 /* initialize ITR configuration */ 2991 q_vector->itr_register = adapter->io_addr + IGC_EITR(0); 2992 q_vector->itr_val = IGC_START_ITR; 2993 2994 /* initialize pointer to rings */ 2995 ring = q_vector->ring; 2996 2997 /* initialize ITR */ 2998 if (rxr_count) { 2999 /* rx or rx/tx vector */ 3000 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 3001 q_vector->itr_val = adapter->rx_itr_setting; 3002 } else { 3003 /* tx only vector */ 3004 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 3005 q_vector->itr_val = adapter->tx_itr_setting; 3006 } 3007 3008 if (txr_count) { 3009 /* assign generic ring traits */ 3010 ring->dev = &adapter->pdev->dev; 3011 ring->netdev = adapter->netdev; 3012 3013 /* configure backlink on ring */ 3014 ring->q_vector = q_vector; 3015 3016 /* update q_vector Tx values */ 3017 igc_add_ring(ring, &q_vector->tx); 3018 3019 /* apply Tx specific ring traits */ 3020 ring->count = adapter->tx_ring_count; 3021 ring->queue_index = txr_idx; 3022 3023 /* assign ring to adapter */ 3024 adapter->tx_ring[txr_idx] = ring; 3025 3026 /* push pointer to next ring */ 3027 ring++; 3028 } 3029 3030 if (rxr_count) { 3031 /* assign generic ring traits */ 3032 ring->dev = &adapter->pdev->dev; 3033 ring->netdev = adapter->netdev; 3034 3035 /* configure backlink on ring */ 3036 ring->q_vector = q_vector; 3037 3038 /* update q_vector Rx values */ 3039 igc_add_ring(ring, &q_vector->rx); 3040 3041 /* apply Rx specific ring traits */ 3042 ring->count = adapter->rx_ring_count; 3043 ring->queue_index = rxr_idx; 3044 3045 /* assign ring to adapter */ 3046 adapter->rx_ring[rxr_idx] = ring; 3047 } 3048 3049 return 0; 3050 } 3051 3052 /** 3053 * igc_alloc_q_vectors - Allocate memory for interrupt vectors 3054 * @adapter: board private structure to initialize 3055 * 3056 * We allocate one q_vector per queue interrupt. If allocation fails we 3057 * return -ENOMEM. 3058 */ 3059 static int igc_alloc_q_vectors(struct igc_adapter *adapter) 3060 { 3061 int rxr_remaining = adapter->num_rx_queues; 3062 int txr_remaining = adapter->num_tx_queues; 3063 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 3064 int q_vectors = adapter->num_q_vectors; 3065 int err; 3066 3067 if (q_vectors >= (rxr_remaining + txr_remaining)) { 3068 for (; rxr_remaining; v_idx++) { 3069 err = igc_alloc_q_vector(adapter, q_vectors, v_idx, 3070 0, 0, 1, rxr_idx); 3071 3072 if (err) 3073 goto err_out; 3074 3075 /* update counts and index */ 3076 rxr_remaining--; 3077 rxr_idx++; 3078 } 3079 } 3080 3081 for (; v_idx < q_vectors; v_idx++) { 3082 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 3083 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 3084 3085 err = igc_alloc_q_vector(adapter, q_vectors, v_idx, 3086 tqpv, txr_idx, rqpv, rxr_idx); 3087 3088 if (err) 3089 goto err_out; 3090 3091 /* update counts and index */ 3092 rxr_remaining -= rqpv; 3093 txr_remaining -= tqpv; 3094 rxr_idx++; 3095 txr_idx++; 3096 } 3097 3098 return 0; 3099 3100 err_out: 3101 adapter->num_tx_queues = 0; 3102 adapter->num_rx_queues = 0; 3103 adapter->num_q_vectors = 0; 3104 3105 while (v_idx--) 3106 igc_free_q_vector(adapter, v_idx); 3107 3108 return -ENOMEM; 3109 } 3110 3111 /** 3112 * igc_cache_ring_register - Descriptor ring to register mapping 3113 * @adapter: board private structure to initialize 3114 * 3115 * Once we know the feature-set enabled for the device, we'll cache 3116 * the register offset the descriptor ring is assigned to. 3117 */ 3118 static void igc_cache_ring_register(struct igc_adapter *adapter) 3119 { 3120 int i = 0, j = 0; 3121 3122 switch (adapter->hw.mac.type) { 3123 case igc_i225: 3124 /* Fall through */ 3125 default: 3126 for (; i < adapter->num_rx_queues; i++) 3127 adapter->rx_ring[i]->reg_idx = i; 3128 for (; j < adapter->num_tx_queues; j++) 3129 adapter->tx_ring[j]->reg_idx = j; 3130 break; 3131 } 3132 } 3133 3134 /** 3135 * igc_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 3136 * @adapter: Pointer to adapter structure 3137 * 3138 * This function initializes the interrupts and allocates all of the queues. 3139 */ 3140 static int igc_init_interrupt_scheme(struct igc_adapter *adapter, bool msix) 3141 { 3142 struct pci_dev *pdev = adapter->pdev; 3143 int err = 0; 3144 3145 igc_set_interrupt_capability(adapter, msix); 3146 3147 err = igc_alloc_q_vectors(adapter); 3148 if (err) { 3149 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 3150 goto err_alloc_q_vectors; 3151 } 3152 3153 igc_cache_ring_register(adapter); 3154 3155 return 0; 3156 3157 err_alloc_q_vectors: 3158 igc_reset_interrupt_capability(adapter); 3159 return err; 3160 } 3161 3162 static void igc_free_irq(struct igc_adapter *adapter) 3163 { 3164 if (adapter->msix_entries) { 3165 int vector = 0, i; 3166 3167 free_irq(adapter->msix_entries[vector++].vector, adapter); 3168 3169 for (i = 0; i < adapter->num_q_vectors; i++) 3170 free_irq(adapter->msix_entries[vector++].vector, 3171 adapter->q_vector[i]); 3172 } else { 3173 free_irq(adapter->pdev->irq, adapter); 3174 } 3175 } 3176 3177 /** 3178 * igc_irq_disable - Mask off interrupt generation on the NIC 3179 * @adapter: board private structure 3180 */ 3181 static void igc_irq_disable(struct igc_adapter *adapter) 3182 { 3183 struct igc_hw *hw = &adapter->hw; 3184 3185 if (adapter->msix_entries) { 3186 u32 regval = rd32(IGC_EIAM); 3187 3188 wr32(IGC_EIAM, regval & ~adapter->eims_enable_mask); 3189 wr32(IGC_EIMC, adapter->eims_enable_mask); 3190 regval = rd32(IGC_EIAC); 3191 wr32(IGC_EIAC, regval & ~adapter->eims_enable_mask); 3192 } 3193 3194 wr32(IGC_IAM, 0); 3195 wr32(IGC_IMC, ~0); 3196 wrfl(); 3197 3198 if (adapter->msix_entries) { 3199 int vector = 0, i; 3200 3201 synchronize_irq(adapter->msix_entries[vector++].vector); 3202 3203 for (i = 0; i < adapter->num_q_vectors; i++) 3204 synchronize_irq(adapter->msix_entries[vector++].vector); 3205 } else { 3206 synchronize_irq(adapter->pdev->irq); 3207 } 3208 } 3209 3210 /** 3211 * igc_irq_enable - Enable default interrupt generation settings 3212 * @adapter: board private structure 3213 */ 3214 static void igc_irq_enable(struct igc_adapter *adapter) 3215 { 3216 struct igc_hw *hw = &adapter->hw; 3217 3218 if (adapter->msix_entries) { 3219 u32 ims = IGC_IMS_LSC | IGC_IMS_DOUTSYNC | IGC_IMS_DRSTA; 3220 u32 regval = rd32(IGC_EIAC); 3221 3222 wr32(IGC_EIAC, regval | adapter->eims_enable_mask); 3223 regval = rd32(IGC_EIAM); 3224 wr32(IGC_EIAM, regval | adapter->eims_enable_mask); 3225 wr32(IGC_EIMS, adapter->eims_enable_mask); 3226 wr32(IGC_IMS, ims); 3227 } else { 3228 wr32(IGC_IMS, IMS_ENABLE_MASK | IGC_IMS_DRSTA); 3229 wr32(IGC_IAM, IMS_ENABLE_MASK | IGC_IMS_DRSTA); 3230 } 3231 } 3232 3233 /** 3234 * igc_request_irq - initialize interrupts 3235 * @adapter: Pointer to adapter structure 3236 * 3237 * Attempts to configure interrupts using the best available 3238 * capabilities of the hardware and kernel. 3239 */ 3240 static int igc_request_irq(struct igc_adapter *adapter) 3241 { 3242 struct net_device *netdev = adapter->netdev; 3243 struct pci_dev *pdev = adapter->pdev; 3244 int err = 0; 3245 3246 if (adapter->flags & IGC_FLAG_HAS_MSIX) { 3247 err = igc_request_msix(adapter); 3248 if (!err) 3249 goto request_done; 3250 /* fall back to MSI */ 3251 igc_free_all_tx_resources(adapter); 3252 igc_free_all_rx_resources(adapter); 3253 3254 igc_clear_interrupt_scheme(adapter); 3255 err = igc_init_interrupt_scheme(adapter, false); 3256 if (err) 3257 goto request_done; 3258 igc_setup_all_tx_resources(adapter); 3259 igc_setup_all_rx_resources(adapter); 3260 igc_configure(adapter); 3261 } 3262 3263 igc_assign_vector(adapter->q_vector[0], 0); 3264 3265 if (adapter->flags & IGC_FLAG_HAS_MSI) { 3266 err = request_irq(pdev->irq, &igc_intr_msi, 0, 3267 netdev->name, adapter); 3268 if (!err) 3269 goto request_done; 3270 3271 /* fall back to legacy interrupts */ 3272 igc_reset_interrupt_capability(adapter); 3273 adapter->flags &= ~IGC_FLAG_HAS_MSI; 3274 } 3275 3276 err = request_irq(pdev->irq, &igc_intr, IRQF_SHARED, 3277 netdev->name, adapter); 3278 3279 if (err) 3280 dev_err(&pdev->dev, "Error %d getting interrupt\n", 3281 err); 3282 3283 request_done: 3284 return err; 3285 } 3286 3287 static void igc_write_itr(struct igc_q_vector *q_vector) 3288 { 3289 u32 itr_val = q_vector->itr_val & IGC_QVECTOR_MASK; 3290 3291 if (!q_vector->set_itr) 3292 return; 3293 3294 if (!itr_val) 3295 itr_val = IGC_ITR_VAL_MASK; 3296 3297 itr_val |= IGC_EITR_CNT_IGNR; 3298 3299 writel(itr_val, q_vector->itr_register); 3300 q_vector->set_itr = 0; 3301 } 3302 3303 /** 3304 * igc_open - Called when a network interface is made active 3305 * @netdev: network interface device structure 3306 * 3307 * Returns 0 on success, negative value on failure 3308 * 3309 * The open entry point is called when a network interface is made 3310 * active by the system (IFF_UP). At this point all resources needed 3311 * for transmit and receive operations are allocated, the interrupt 3312 * handler is registered with the OS, the watchdog timer is started, 3313 * and the stack is notified that the interface is ready. 3314 */ 3315 static int __igc_open(struct net_device *netdev, bool resuming) 3316 { 3317 struct igc_adapter *adapter = netdev_priv(netdev); 3318 struct igc_hw *hw = &adapter->hw; 3319 int err = 0; 3320 int i = 0; 3321 3322 /* disallow open during test */ 3323 3324 if (test_bit(__IGC_TESTING, &adapter->state)) { 3325 WARN_ON(resuming); 3326 return -EBUSY; 3327 } 3328 3329 netif_carrier_off(netdev); 3330 3331 /* allocate transmit descriptors */ 3332 err = igc_setup_all_tx_resources(adapter); 3333 if (err) 3334 goto err_setup_tx; 3335 3336 /* allocate receive descriptors */ 3337 err = igc_setup_all_rx_resources(adapter); 3338 if (err) 3339 goto err_setup_rx; 3340 3341 igc_power_up_link(adapter); 3342 3343 igc_configure(adapter); 3344 3345 err = igc_request_irq(adapter); 3346 if (err) 3347 goto err_req_irq; 3348 3349 /* Notify the stack of the actual queue counts. */ 3350 err = netif_set_real_num_tx_queues(netdev, adapter->num_tx_queues); 3351 if (err) 3352 goto err_set_queues; 3353 3354 err = netif_set_real_num_rx_queues(netdev, adapter->num_rx_queues); 3355 if (err) 3356 goto err_set_queues; 3357 3358 clear_bit(__IGC_DOWN, &adapter->state); 3359 3360 for (i = 0; i < adapter->num_q_vectors; i++) 3361 napi_enable(&adapter->q_vector[i]->napi); 3362 3363 /* Clear any pending interrupts. */ 3364 rd32(IGC_ICR); 3365 igc_irq_enable(adapter); 3366 3367 netif_tx_start_all_queues(netdev); 3368 3369 /* start the watchdog. */ 3370 hw->mac.get_link_status = 1; 3371 schedule_work(&adapter->watchdog_task); 3372 3373 return IGC_SUCCESS; 3374 3375 err_set_queues: 3376 igc_free_irq(adapter); 3377 err_req_irq: 3378 igc_release_hw_control(adapter); 3379 igc_power_down_link(adapter); 3380 igc_free_all_rx_resources(adapter); 3381 err_setup_rx: 3382 igc_free_all_tx_resources(adapter); 3383 err_setup_tx: 3384 igc_reset(adapter); 3385 3386 return err; 3387 } 3388 3389 static int igc_open(struct net_device *netdev) 3390 { 3391 return __igc_open(netdev, false); 3392 } 3393 3394 /** 3395 * igc_close - Disables a network interface 3396 * @netdev: network interface device structure 3397 * 3398 * Returns 0, this is not allowed to fail 3399 * 3400 * The close entry point is called when an interface is de-activated 3401 * by the OS. The hardware is still under the driver's control, but 3402 * needs to be disabled. A global MAC reset is issued to stop the 3403 * hardware, and all transmit and receive resources are freed. 3404 */ 3405 static int __igc_close(struct net_device *netdev, bool suspending) 3406 { 3407 struct igc_adapter *adapter = netdev_priv(netdev); 3408 3409 WARN_ON(test_bit(__IGC_RESETTING, &adapter->state)); 3410 3411 igc_down(adapter); 3412 3413 igc_release_hw_control(adapter); 3414 3415 igc_free_irq(adapter); 3416 3417 igc_free_all_tx_resources(adapter); 3418 igc_free_all_rx_resources(adapter); 3419 3420 return 0; 3421 } 3422 3423 static int igc_close(struct net_device *netdev) 3424 { 3425 if (netif_device_present(netdev) || netdev->dismantle) 3426 return __igc_close(netdev, false); 3427 return 0; 3428 } 3429 3430 static const struct net_device_ops igc_netdev_ops = { 3431 .ndo_open = igc_open, 3432 .ndo_stop = igc_close, 3433 .ndo_start_xmit = igc_xmit_frame, 3434 .ndo_set_mac_address = igc_set_mac, 3435 .ndo_change_mtu = igc_change_mtu, 3436 .ndo_get_stats = igc_get_stats, 3437 }; 3438 3439 /* PCIe configuration access */ 3440 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value) 3441 { 3442 struct igc_adapter *adapter = hw->back; 3443 3444 pci_read_config_word(adapter->pdev, reg, value); 3445 } 3446 3447 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value) 3448 { 3449 struct igc_adapter *adapter = hw->back; 3450 3451 pci_write_config_word(adapter->pdev, reg, *value); 3452 } 3453 3454 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value) 3455 { 3456 struct igc_adapter *adapter = hw->back; 3457 u16 cap_offset; 3458 3459 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); 3460 if (!cap_offset) 3461 return -IGC_ERR_CONFIG; 3462 3463 pci_read_config_word(adapter->pdev, cap_offset + reg, value); 3464 3465 return IGC_SUCCESS; 3466 } 3467 3468 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value) 3469 { 3470 struct igc_adapter *adapter = hw->back; 3471 u16 cap_offset; 3472 3473 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); 3474 if (!cap_offset) 3475 return -IGC_ERR_CONFIG; 3476 3477 pci_write_config_word(adapter->pdev, cap_offset + reg, *value); 3478 3479 return IGC_SUCCESS; 3480 } 3481 3482 u32 igc_rd32(struct igc_hw *hw, u32 reg) 3483 { 3484 struct igc_adapter *igc = container_of(hw, struct igc_adapter, hw); 3485 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 3486 u32 value = 0; 3487 3488 if (IGC_REMOVED(hw_addr)) 3489 return ~value; 3490 3491 value = readl(&hw_addr[reg]); 3492 3493 /* reads should not return all F's */ 3494 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 3495 struct net_device *netdev = igc->netdev; 3496 3497 hw->hw_addr = NULL; 3498 netif_device_detach(netdev); 3499 netdev_err(netdev, "PCIe link lost, device now detached\n"); 3500 } 3501 3502 return value; 3503 } 3504 3505 int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx) 3506 { 3507 struct pci_dev *pdev = adapter->pdev; 3508 struct igc_mac_info *mac = &adapter->hw.mac; 3509 3510 mac->autoneg = 0; 3511 3512 /* Make sure dplx is at most 1 bit and lsb of speed is not set 3513 * for the switch() below to work 3514 */ 3515 if ((spd & 1) || (dplx & ~1)) 3516 goto err_inval; 3517 3518 switch (spd + dplx) { 3519 case SPEED_10 + DUPLEX_HALF: 3520 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3521 break; 3522 case SPEED_10 + DUPLEX_FULL: 3523 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3524 break; 3525 case SPEED_100 + DUPLEX_HALF: 3526 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3527 break; 3528 case SPEED_100 + DUPLEX_FULL: 3529 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3530 break; 3531 case SPEED_1000 + DUPLEX_FULL: 3532 mac->autoneg = 1; 3533 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 3534 break; 3535 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 3536 goto err_inval; 3537 case SPEED_2500 + DUPLEX_FULL: 3538 mac->autoneg = 1; 3539 adapter->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL; 3540 break; 3541 case SPEED_2500 + DUPLEX_HALF: /* not supported */ 3542 default: 3543 goto err_inval; 3544 } 3545 3546 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 3547 adapter->hw.phy.mdix = AUTO_ALL_MODES; 3548 3549 return 0; 3550 3551 err_inval: 3552 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 3553 return -EINVAL; 3554 } 3555 3556 /** 3557 * igc_probe - Device Initialization Routine 3558 * @pdev: PCI device information struct 3559 * @ent: entry in igc_pci_tbl 3560 * 3561 * Returns 0 on success, negative on failure 3562 * 3563 * igc_probe initializes an adapter identified by a pci_dev structure. 3564 * The OS initialization, configuring the adapter private structure, 3565 * and a hardware reset occur. 3566 */ 3567 static int igc_probe(struct pci_dev *pdev, 3568 const struct pci_device_id *ent) 3569 { 3570 struct igc_adapter *adapter; 3571 struct net_device *netdev; 3572 struct igc_hw *hw; 3573 const struct igc_info *ei = igc_info_tbl[ent->driver_data]; 3574 int err; 3575 3576 err = pci_enable_device_mem(pdev); 3577 if (err) 3578 return err; 3579 3580 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 3581 if (!err) { 3582 err = dma_set_coherent_mask(&pdev->dev, 3583 DMA_BIT_MASK(64)); 3584 } else { 3585 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 3586 if (err) { 3587 err = dma_set_coherent_mask(&pdev->dev, 3588 DMA_BIT_MASK(32)); 3589 if (err) { 3590 dev_err(&pdev->dev, "igc: Wrong DMA config\n"); 3591 goto err_dma; 3592 } 3593 } 3594 } 3595 3596 err = pci_request_selected_regions(pdev, 3597 pci_select_bars(pdev, 3598 IORESOURCE_MEM), 3599 igc_driver_name); 3600 if (err) 3601 goto err_pci_reg; 3602 3603 pci_enable_pcie_error_reporting(pdev); 3604 3605 pci_set_master(pdev); 3606 3607 err = -ENOMEM; 3608 netdev = alloc_etherdev_mq(sizeof(struct igc_adapter), 3609 IGC_MAX_TX_QUEUES); 3610 3611 if (!netdev) 3612 goto err_alloc_etherdev; 3613 3614 SET_NETDEV_DEV(netdev, &pdev->dev); 3615 3616 pci_set_drvdata(pdev, netdev); 3617 adapter = netdev_priv(netdev); 3618 adapter->netdev = netdev; 3619 adapter->pdev = pdev; 3620 hw = &adapter->hw; 3621 hw->back = adapter; 3622 adapter->port_num = hw->bus.func; 3623 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3624 3625 err = pci_save_state(pdev); 3626 if (err) 3627 goto err_ioremap; 3628 3629 err = -EIO; 3630 adapter->io_addr = ioremap(pci_resource_start(pdev, 0), 3631 pci_resource_len(pdev, 0)); 3632 if (!adapter->io_addr) 3633 goto err_ioremap; 3634 3635 /* hw->hw_addr can be zeroed, so use adapter->io_addr for unmap */ 3636 hw->hw_addr = adapter->io_addr; 3637 3638 netdev->netdev_ops = &igc_netdev_ops; 3639 igc_set_ethtool_ops(netdev); 3640 netdev->watchdog_timeo = 5 * HZ; 3641 3642 netdev->mem_start = pci_resource_start(pdev, 0); 3643 netdev->mem_end = pci_resource_end(pdev, 0); 3644 3645 /* PCI config space info */ 3646 hw->vendor_id = pdev->vendor; 3647 hw->device_id = pdev->device; 3648 hw->revision_id = pdev->revision; 3649 hw->subsystem_vendor_id = pdev->subsystem_vendor; 3650 hw->subsystem_device_id = pdev->subsystem_device; 3651 3652 /* Copy the default MAC and PHY function pointers */ 3653 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 3654 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 3655 3656 /* Initialize skew-specific constants */ 3657 err = ei->get_invariants(hw); 3658 if (err) 3659 goto err_sw_init; 3660 3661 /* setup the private structure */ 3662 err = igc_sw_init(adapter); 3663 if (err) 3664 goto err_sw_init; 3665 3666 /* MTU range: 68 - 9216 */ 3667 netdev->min_mtu = ETH_MIN_MTU; 3668 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 3669 3670 /* before reading the NVM, reset the controller to put the device in a 3671 * known good starting state 3672 */ 3673 hw->mac.ops.reset_hw(hw); 3674 3675 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 3676 /* copy the MAC address out of the NVM */ 3677 if (hw->mac.ops.read_mac_addr(hw)) 3678 dev_err(&pdev->dev, "NVM Read Error\n"); 3679 } 3680 3681 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 3682 3683 if (!is_valid_ether_addr(netdev->dev_addr)) { 3684 dev_err(&pdev->dev, "Invalid MAC Address\n"); 3685 err = -EIO; 3686 goto err_eeprom; 3687 } 3688 3689 /* configure RXPBSIZE and TXPBSIZE */ 3690 wr32(IGC_RXPBS, I225_RXPBSIZE_DEFAULT); 3691 wr32(IGC_TXPBS, I225_TXPBSIZE_DEFAULT); 3692 3693 timer_setup(&adapter->watchdog_timer, igc_watchdog, 0); 3694 timer_setup(&adapter->phy_info_timer, igc_update_phy_info, 0); 3695 3696 INIT_WORK(&adapter->reset_task, igc_reset_task); 3697 INIT_WORK(&adapter->watchdog_task, igc_watchdog_task); 3698 3699 /* Initialize link properties that are user-changeable */ 3700 adapter->fc_autoneg = true; 3701 hw->mac.autoneg = true; 3702 hw->phy.autoneg_advertised = 0xaf; 3703 3704 hw->fc.requested_mode = igc_fc_default; 3705 hw->fc.current_mode = igc_fc_default; 3706 3707 /* reset the hardware with the new settings */ 3708 igc_reset(adapter); 3709 3710 /* let the f/w know that the h/w is now under the control of the 3711 * driver. 3712 */ 3713 igc_get_hw_control(adapter); 3714 3715 strncpy(netdev->name, "eth%d", IFNAMSIZ); 3716 err = register_netdev(netdev); 3717 if (err) 3718 goto err_register; 3719 3720 /* carrier off reporting is important to ethtool even BEFORE open */ 3721 netif_carrier_off(netdev); 3722 3723 /* Check if Media Autosense is enabled */ 3724 adapter->ei = *ei; 3725 3726 /* print pcie link status and MAC address */ 3727 pcie_print_link_status(pdev); 3728 netdev_info(netdev, "MAC: %pM\n", netdev->dev_addr); 3729 3730 return 0; 3731 3732 err_register: 3733 igc_release_hw_control(adapter); 3734 err_eeprom: 3735 if (!igc_check_reset_block(hw)) 3736 igc_reset_phy(hw); 3737 err_sw_init: 3738 igc_clear_interrupt_scheme(adapter); 3739 iounmap(adapter->io_addr); 3740 err_ioremap: 3741 free_netdev(netdev); 3742 err_alloc_etherdev: 3743 pci_release_selected_regions(pdev, 3744 pci_select_bars(pdev, IORESOURCE_MEM)); 3745 err_pci_reg: 3746 err_dma: 3747 pci_disable_device(pdev); 3748 return err; 3749 } 3750 3751 /** 3752 * igc_remove - Device Removal Routine 3753 * @pdev: PCI device information struct 3754 * 3755 * igc_remove is called by the PCI subsystem to alert the driver 3756 * that it should release a PCI device. This could be caused by a 3757 * Hot-Plug event, or because the driver is going to be removed from 3758 * memory. 3759 */ 3760 static void igc_remove(struct pci_dev *pdev) 3761 { 3762 struct net_device *netdev = pci_get_drvdata(pdev); 3763 struct igc_adapter *adapter = netdev_priv(netdev); 3764 3765 set_bit(__IGC_DOWN, &adapter->state); 3766 3767 del_timer_sync(&adapter->watchdog_timer); 3768 del_timer_sync(&adapter->phy_info_timer); 3769 3770 cancel_work_sync(&adapter->reset_task); 3771 cancel_work_sync(&adapter->watchdog_task); 3772 3773 /* Release control of h/w to f/w. If f/w is AMT enabled, this 3774 * would have already happened in close and is redundant. 3775 */ 3776 igc_release_hw_control(adapter); 3777 unregister_netdev(netdev); 3778 3779 igc_clear_interrupt_scheme(adapter); 3780 pci_iounmap(pdev, adapter->io_addr); 3781 pci_release_mem_regions(pdev); 3782 3783 kfree(adapter->mac_table); 3784 kfree(adapter->shadow_vfta); 3785 free_netdev(netdev); 3786 3787 pci_disable_pcie_error_reporting(pdev); 3788 3789 pci_disable_device(pdev); 3790 } 3791 3792 static struct pci_driver igc_driver = { 3793 .name = igc_driver_name, 3794 .id_table = igc_pci_tbl, 3795 .probe = igc_probe, 3796 .remove = igc_remove, 3797 }; 3798 3799 void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 3800 const u32 max_rss_queues) 3801 { 3802 /* Determine if we need to pair queues. */ 3803 /* If rss_queues > half of max_rss_queues, pair the queues in 3804 * order to conserve interrupts due to limited supply. 3805 */ 3806 if (adapter->rss_queues > (max_rss_queues / 2)) 3807 adapter->flags |= IGC_FLAG_QUEUE_PAIRS; 3808 else 3809 adapter->flags &= ~IGC_FLAG_QUEUE_PAIRS; 3810 } 3811 3812 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter) 3813 { 3814 unsigned int max_rss_queues; 3815 3816 /* Determine the maximum number of RSS queues supported. */ 3817 max_rss_queues = IGC_MAX_RX_QUEUES; 3818 3819 return max_rss_queues; 3820 } 3821 3822 static void igc_init_queue_configuration(struct igc_adapter *adapter) 3823 { 3824 u32 max_rss_queues; 3825 3826 max_rss_queues = igc_get_max_rss_queues(adapter); 3827 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 3828 3829 igc_set_flag_queue_pairs(adapter, max_rss_queues); 3830 } 3831 3832 /** 3833 * igc_sw_init - Initialize general software structures (struct igc_adapter) 3834 * @adapter: board private structure to initialize 3835 * 3836 * igc_sw_init initializes the Adapter private data structure. 3837 * Fields are initialized based on PCI device information and 3838 * OS network device settings (MTU size). 3839 */ 3840 static int igc_sw_init(struct igc_adapter *adapter) 3841 { 3842 struct net_device *netdev = adapter->netdev; 3843 struct pci_dev *pdev = adapter->pdev; 3844 struct igc_hw *hw = &adapter->hw; 3845 3846 int size = sizeof(struct igc_mac_addr) * hw->mac.rar_entry_count; 3847 3848 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 3849 3850 /* set default ring sizes */ 3851 adapter->tx_ring_count = IGC_DEFAULT_TXD; 3852 adapter->rx_ring_count = IGC_DEFAULT_RXD; 3853 3854 /* set default ITR values */ 3855 adapter->rx_itr_setting = IGC_DEFAULT_ITR; 3856 adapter->tx_itr_setting = IGC_DEFAULT_ITR; 3857 3858 /* set default work limits */ 3859 adapter->tx_work_limit = IGC_DEFAULT_TX_WORK; 3860 3861 /* adjust max frame to be at least the size of a standard frame */ 3862 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 3863 VLAN_HLEN; 3864 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 3865 3866 spin_lock_init(&adapter->nfc_lock); 3867 spin_lock_init(&adapter->stats64_lock); 3868 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 3869 adapter->flags |= IGC_FLAG_HAS_MSIX; 3870 3871 adapter->mac_table = kzalloc(size, GFP_ATOMIC); 3872 if (!adapter->mac_table) 3873 return -ENOMEM; 3874 3875 igc_init_queue_configuration(adapter); 3876 3877 /* This call may decrease the number of queues */ 3878 if (igc_init_interrupt_scheme(adapter, true)) { 3879 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3880 return -ENOMEM; 3881 } 3882 3883 /* Explicitly disable IRQ since the NIC can be in any state. */ 3884 igc_irq_disable(adapter); 3885 3886 set_bit(__IGC_DOWN, &adapter->state); 3887 3888 return 0; 3889 } 3890 3891 /** 3892 * igc_reinit_queues - return error 3893 * @adapter: pointer to adapter structure 3894 */ 3895 int igc_reinit_queues(struct igc_adapter *adapter) 3896 { 3897 struct net_device *netdev = adapter->netdev; 3898 struct pci_dev *pdev = adapter->pdev; 3899 int err = 0; 3900 3901 if (netif_running(netdev)) 3902 igc_close(netdev); 3903 3904 igc_reset_interrupt_capability(adapter); 3905 3906 if (igc_init_interrupt_scheme(adapter, true)) { 3907 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 3908 return -ENOMEM; 3909 } 3910 3911 if (netif_running(netdev)) 3912 err = igc_open(netdev); 3913 3914 return err; 3915 } 3916 3917 /** 3918 * igc_get_hw_dev - return device 3919 * @hw: pointer to hardware structure 3920 * 3921 * used by hardware layer to print debugging information 3922 */ 3923 struct net_device *igc_get_hw_dev(struct igc_hw *hw) 3924 { 3925 struct igc_adapter *adapter = hw->back; 3926 3927 return adapter->netdev; 3928 } 3929 3930 /** 3931 * igc_init_module - Driver Registration Routine 3932 * 3933 * igc_init_module is the first routine called when the driver is 3934 * loaded. All it does is register with the PCI subsystem. 3935 */ 3936 static int __init igc_init_module(void) 3937 { 3938 int ret; 3939 3940 pr_info("%s - version %s\n", 3941 igc_driver_string, igc_driver_version); 3942 3943 pr_info("%s\n", igc_copyright); 3944 3945 ret = pci_register_driver(&igc_driver); 3946 return ret; 3947 } 3948 3949 module_init(igc_init_module); 3950 3951 /** 3952 * igc_exit_module - Driver Exit Cleanup Routine 3953 * 3954 * igc_exit_module is called just before the driver is removed 3955 * from memory. 3956 */ 3957 static void __exit igc_exit_module(void) 3958 { 3959 pci_unregister_driver(&igc_driver); 3960 } 3961 3962 module_exit(igc_exit_module); 3963 /* igc_main.c */ 3964