1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #include <linux/module.h> 5 #include <linux/types.h> 6 #include <linux/if_vlan.h> 7 #include <linux/tcp.h> 8 #include <linux/udp.h> 9 #include <linux/ip.h> 10 #include <linux/pm_runtime.h> 11 #include <net/pkt_sched.h> 12 #include <linux/bpf_trace.h> 13 #include <net/xdp_sock_drv.h> 14 #include <linux/pci.h> 15 16 #include <net/ipv6.h> 17 18 #include "igc.h" 19 #include "igc_hw.h" 20 #include "igc_tsn.h" 21 #include "igc_xdp.h" 22 23 #define DRV_SUMMARY "Intel(R) 2.5G Ethernet Linux Driver" 24 25 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 26 27 #define IGC_XDP_PASS 0 28 #define IGC_XDP_CONSUMED BIT(0) 29 #define IGC_XDP_TX BIT(1) 30 #define IGC_XDP_REDIRECT BIT(2) 31 32 static int debug = -1; 33 34 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 35 MODULE_DESCRIPTION(DRV_SUMMARY); 36 MODULE_LICENSE("GPL v2"); 37 module_param(debug, int, 0); 38 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 39 40 char igc_driver_name[] = "igc"; 41 static const char igc_driver_string[] = DRV_SUMMARY; 42 static const char igc_copyright[] = 43 "Copyright(c) 2018 Intel Corporation."; 44 45 static const struct igc_info *igc_info_tbl[] = { 46 [board_base] = &igc_base_info, 47 }; 48 49 static const struct pci_device_id igc_pci_tbl[] = { 50 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LM), board_base }, 51 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_V), board_base }, 52 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_I), board_base }, 53 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I220_V), board_base }, 54 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_K), board_base }, 55 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_K2), board_base }, 56 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_K), board_base }, 57 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LMVP), board_base }, 58 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_LMVP), board_base }, 59 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_IT), board_base }, 60 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_LM), board_base }, 61 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_V), board_base }, 62 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_IT), board_base }, 63 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I221_V), board_base }, 64 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_BLANK_NVM), board_base }, 65 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_BLANK_NVM), board_base }, 66 /* required last entry */ 67 {0, } 68 }; 69 70 MODULE_DEVICE_TABLE(pci, igc_pci_tbl); 71 72 enum latency_range { 73 lowest_latency = 0, 74 low_latency = 1, 75 bulk_latency = 2, 76 latency_invalid = 255 77 }; 78 79 void igc_reset(struct igc_adapter *adapter) 80 { 81 struct net_device *dev = adapter->netdev; 82 struct igc_hw *hw = &adapter->hw; 83 struct igc_fc_info *fc = &hw->fc; 84 u32 pba, hwm; 85 86 /* Repartition PBA for greater than 9k MTU if required */ 87 pba = IGC_PBA_34K; 88 89 /* flow control settings 90 * The high water mark must be low enough to fit one full frame 91 * after transmitting the pause frame. As such we must have enough 92 * space to allow for us to complete our current transmit and then 93 * receive the frame that is in progress from the link partner. 94 * Set it to: 95 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 96 */ 97 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 98 99 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 100 fc->low_water = fc->high_water - 16; 101 fc->pause_time = 0xFFFF; 102 fc->send_xon = 1; 103 fc->current_mode = fc->requested_mode; 104 105 hw->mac.ops.reset_hw(hw); 106 107 if (hw->mac.ops.init_hw(hw)) 108 netdev_err(dev, "Error on hardware initialization\n"); 109 110 /* Re-establish EEE setting */ 111 igc_set_eee_i225(hw, true, true, true); 112 113 if (!netif_running(adapter->netdev)) 114 igc_power_down_phy_copper_base(&adapter->hw); 115 116 /* Enable HW to recognize an 802.1Q VLAN Ethernet packet */ 117 wr32(IGC_VET, ETH_P_8021Q); 118 119 /* Re-enable PTP, where applicable. */ 120 igc_ptp_reset(adapter); 121 122 /* Re-enable TSN offloading, where applicable. */ 123 igc_tsn_reset(adapter); 124 125 igc_get_phy_info(hw); 126 } 127 128 /** 129 * igc_power_up_link - Power up the phy link 130 * @adapter: address of board private structure 131 */ 132 static void igc_power_up_link(struct igc_adapter *adapter) 133 { 134 igc_reset_phy(&adapter->hw); 135 136 igc_power_up_phy_copper(&adapter->hw); 137 138 igc_setup_link(&adapter->hw); 139 } 140 141 /** 142 * igc_release_hw_control - release control of the h/w to f/w 143 * @adapter: address of board private structure 144 * 145 * igc_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 146 * For ASF and Pass Through versions of f/w this means that the 147 * driver is no longer loaded. 148 */ 149 static void igc_release_hw_control(struct igc_adapter *adapter) 150 { 151 struct igc_hw *hw = &adapter->hw; 152 u32 ctrl_ext; 153 154 if (!pci_device_is_present(adapter->pdev)) 155 return; 156 157 /* Let firmware take over control of h/w */ 158 ctrl_ext = rd32(IGC_CTRL_EXT); 159 wr32(IGC_CTRL_EXT, 160 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD); 161 } 162 163 /** 164 * igc_get_hw_control - get control of the h/w from f/w 165 * @adapter: address of board private structure 166 * 167 * igc_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 168 * For ASF and Pass Through versions of f/w this means that 169 * the driver is loaded. 170 */ 171 static void igc_get_hw_control(struct igc_adapter *adapter) 172 { 173 struct igc_hw *hw = &adapter->hw; 174 u32 ctrl_ext; 175 176 /* Let firmware know the driver has taken over */ 177 ctrl_ext = rd32(IGC_CTRL_EXT); 178 wr32(IGC_CTRL_EXT, 179 ctrl_ext | IGC_CTRL_EXT_DRV_LOAD); 180 } 181 182 static void igc_unmap_tx_buffer(struct device *dev, struct igc_tx_buffer *buf) 183 { 184 dma_unmap_single(dev, dma_unmap_addr(buf, dma), 185 dma_unmap_len(buf, len), DMA_TO_DEVICE); 186 187 dma_unmap_len_set(buf, len, 0); 188 } 189 190 /** 191 * igc_clean_tx_ring - Free Tx Buffers 192 * @tx_ring: ring to be cleaned 193 */ 194 static void igc_clean_tx_ring(struct igc_ring *tx_ring) 195 { 196 u16 i = tx_ring->next_to_clean; 197 struct igc_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 198 u32 xsk_frames = 0; 199 200 while (i != tx_ring->next_to_use) { 201 union igc_adv_tx_desc *eop_desc, *tx_desc; 202 203 switch (tx_buffer->type) { 204 case IGC_TX_BUFFER_TYPE_XSK: 205 xsk_frames++; 206 break; 207 case IGC_TX_BUFFER_TYPE_XDP: 208 xdp_return_frame(tx_buffer->xdpf); 209 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 210 break; 211 case IGC_TX_BUFFER_TYPE_SKB: 212 dev_kfree_skb_any(tx_buffer->skb); 213 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 214 break; 215 default: 216 netdev_warn_once(tx_ring->netdev, "Unknown Tx buffer type\n"); 217 break; 218 } 219 220 /* check for eop_desc to determine the end of the packet */ 221 eop_desc = tx_buffer->next_to_watch; 222 tx_desc = IGC_TX_DESC(tx_ring, i); 223 224 /* unmap remaining buffers */ 225 while (tx_desc != eop_desc) { 226 tx_buffer++; 227 tx_desc++; 228 i++; 229 if (unlikely(i == tx_ring->count)) { 230 i = 0; 231 tx_buffer = tx_ring->tx_buffer_info; 232 tx_desc = IGC_TX_DESC(tx_ring, 0); 233 } 234 235 /* unmap any remaining paged data */ 236 if (dma_unmap_len(tx_buffer, len)) 237 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 238 } 239 240 tx_buffer->next_to_watch = NULL; 241 242 /* move us one more past the eop_desc for start of next pkt */ 243 tx_buffer++; 244 i++; 245 if (unlikely(i == tx_ring->count)) { 246 i = 0; 247 tx_buffer = tx_ring->tx_buffer_info; 248 } 249 } 250 251 if (tx_ring->xsk_pool && xsk_frames) 252 xsk_tx_completed(tx_ring->xsk_pool, xsk_frames); 253 254 /* reset BQL for queue */ 255 netdev_tx_reset_queue(txring_txq(tx_ring)); 256 257 /* Zero out the buffer ring */ 258 memset(tx_ring->tx_buffer_info, 0, 259 sizeof(*tx_ring->tx_buffer_info) * tx_ring->count); 260 261 /* Zero out the descriptor ring */ 262 memset(tx_ring->desc, 0, tx_ring->size); 263 264 /* reset next_to_use and next_to_clean */ 265 tx_ring->next_to_use = 0; 266 tx_ring->next_to_clean = 0; 267 } 268 269 /** 270 * igc_free_tx_resources - Free Tx Resources per Queue 271 * @tx_ring: Tx descriptor ring for a specific queue 272 * 273 * Free all transmit software resources 274 */ 275 void igc_free_tx_resources(struct igc_ring *tx_ring) 276 { 277 igc_disable_tx_ring(tx_ring); 278 279 vfree(tx_ring->tx_buffer_info); 280 tx_ring->tx_buffer_info = NULL; 281 282 /* if not set, then don't free */ 283 if (!tx_ring->desc) 284 return; 285 286 dma_free_coherent(tx_ring->dev, tx_ring->size, 287 tx_ring->desc, tx_ring->dma); 288 289 tx_ring->desc = NULL; 290 } 291 292 /** 293 * igc_free_all_tx_resources - Free Tx Resources for All Queues 294 * @adapter: board private structure 295 * 296 * Free all transmit software resources 297 */ 298 static void igc_free_all_tx_resources(struct igc_adapter *adapter) 299 { 300 int i; 301 302 for (i = 0; i < adapter->num_tx_queues; i++) 303 igc_free_tx_resources(adapter->tx_ring[i]); 304 } 305 306 /** 307 * igc_clean_all_tx_rings - Free Tx Buffers for all queues 308 * @adapter: board private structure 309 */ 310 static void igc_clean_all_tx_rings(struct igc_adapter *adapter) 311 { 312 int i; 313 314 for (i = 0; i < adapter->num_tx_queues; i++) 315 if (adapter->tx_ring[i]) 316 igc_clean_tx_ring(adapter->tx_ring[i]); 317 } 318 319 static void igc_disable_tx_ring_hw(struct igc_ring *ring) 320 { 321 struct igc_hw *hw = &ring->q_vector->adapter->hw; 322 u8 idx = ring->reg_idx; 323 u32 txdctl; 324 325 txdctl = rd32(IGC_TXDCTL(idx)); 326 txdctl &= ~IGC_TXDCTL_QUEUE_ENABLE; 327 txdctl |= IGC_TXDCTL_SWFLUSH; 328 wr32(IGC_TXDCTL(idx), txdctl); 329 } 330 331 /** 332 * igc_disable_all_tx_rings_hw - Disable all transmit queue operation 333 * @adapter: board private structure 334 */ 335 static void igc_disable_all_tx_rings_hw(struct igc_adapter *adapter) 336 { 337 int i; 338 339 for (i = 0; i < adapter->num_tx_queues; i++) { 340 struct igc_ring *tx_ring = adapter->tx_ring[i]; 341 342 igc_disable_tx_ring_hw(tx_ring); 343 } 344 } 345 346 /** 347 * igc_setup_tx_resources - allocate Tx resources (Descriptors) 348 * @tx_ring: tx descriptor ring (for a specific queue) to setup 349 * 350 * Return 0 on success, negative on failure 351 */ 352 int igc_setup_tx_resources(struct igc_ring *tx_ring) 353 { 354 struct net_device *ndev = tx_ring->netdev; 355 struct device *dev = tx_ring->dev; 356 int size = 0; 357 358 size = sizeof(struct igc_tx_buffer) * tx_ring->count; 359 tx_ring->tx_buffer_info = vzalloc(size); 360 if (!tx_ring->tx_buffer_info) 361 goto err; 362 363 /* round up to nearest 4K */ 364 tx_ring->size = tx_ring->count * sizeof(union igc_adv_tx_desc); 365 tx_ring->size = ALIGN(tx_ring->size, 4096); 366 367 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 368 &tx_ring->dma, GFP_KERNEL); 369 370 if (!tx_ring->desc) 371 goto err; 372 373 tx_ring->next_to_use = 0; 374 tx_ring->next_to_clean = 0; 375 376 return 0; 377 378 err: 379 vfree(tx_ring->tx_buffer_info); 380 netdev_err(ndev, "Unable to allocate memory for Tx descriptor ring\n"); 381 return -ENOMEM; 382 } 383 384 /** 385 * igc_setup_all_tx_resources - wrapper to allocate Tx resources for all queues 386 * @adapter: board private structure 387 * 388 * Return 0 on success, negative on failure 389 */ 390 static int igc_setup_all_tx_resources(struct igc_adapter *adapter) 391 { 392 struct net_device *dev = adapter->netdev; 393 int i, err = 0; 394 395 for (i = 0; i < adapter->num_tx_queues; i++) { 396 err = igc_setup_tx_resources(adapter->tx_ring[i]); 397 if (err) { 398 netdev_err(dev, "Error on Tx queue %u setup\n", i); 399 for (i--; i >= 0; i--) 400 igc_free_tx_resources(adapter->tx_ring[i]); 401 break; 402 } 403 } 404 405 return err; 406 } 407 408 static void igc_clean_rx_ring_page_shared(struct igc_ring *rx_ring) 409 { 410 u16 i = rx_ring->next_to_clean; 411 412 dev_kfree_skb(rx_ring->skb); 413 rx_ring->skb = NULL; 414 415 /* Free all the Rx ring sk_buffs */ 416 while (i != rx_ring->next_to_alloc) { 417 struct igc_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 418 419 /* Invalidate cache lines that may have been written to by 420 * device so that we avoid corrupting memory. 421 */ 422 dma_sync_single_range_for_cpu(rx_ring->dev, 423 buffer_info->dma, 424 buffer_info->page_offset, 425 igc_rx_bufsz(rx_ring), 426 DMA_FROM_DEVICE); 427 428 /* free resources associated with mapping */ 429 dma_unmap_page_attrs(rx_ring->dev, 430 buffer_info->dma, 431 igc_rx_pg_size(rx_ring), 432 DMA_FROM_DEVICE, 433 IGC_RX_DMA_ATTR); 434 __page_frag_cache_drain(buffer_info->page, 435 buffer_info->pagecnt_bias); 436 437 i++; 438 if (i == rx_ring->count) 439 i = 0; 440 } 441 } 442 443 static void igc_clean_rx_ring_xsk_pool(struct igc_ring *ring) 444 { 445 struct igc_rx_buffer *bi; 446 u16 i; 447 448 for (i = 0; i < ring->count; i++) { 449 bi = &ring->rx_buffer_info[i]; 450 if (!bi->xdp) 451 continue; 452 453 xsk_buff_free(bi->xdp); 454 bi->xdp = NULL; 455 } 456 } 457 458 /** 459 * igc_clean_rx_ring - Free Rx Buffers per Queue 460 * @ring: ring to free buffers from 461 */ 462 static void igc_clean_rx_ring(struct igc_ring *ring) 463 { 464 if (ring->xsk_pool) 465 igc_clean_rx_ring_xsk_pool(ring); 466 else 467 igc_clean_rx_ring_page_shared(ring); 468 469 clear_ring_uses_large_buffer(ring); 470 471 ring->next_to_alloc = 0; 472 ring->next_to_clean = 0; 473 ring->next_to_use = 0; 474 } 475 476 /** 477 * igc_clean_all_rx_rings - Free Rx Buffers for all queues 478 * @adapter: board private structure 479 */ 480 static void igc_clean_all_rx_rings(struct igc_adapter *adapter) 481 { 482 int i; 483 484 for (i = 0; i < adapter->num_rx_queues; i++) 485 if (adapter->rx_ring[i]) 486 igc_clean_rx_ring(adapter->rx_ring[i]); 487 } 488 489 /** 490 * igc_free_rx_resources - Free Rx Resources 491 * @rx_ring: ring to clean the resources from 492 * 493 * Free all receive software resources 494 */ 495 void igc_free_rx_resources(struct igc_ring *rx_ring) 496 { 497 igc_clean_rx_ring(rx_ring); 498 499 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 500 501 vfree(rx_ring->rx_buffer_info); 502 rx_ring->rx_buffer_info = NULL; 503 504 /* if not set, then don't free */ 505 if (!rx_ring->desc) 506 return; 507 508 dma_free_coherent(rx_ring->dev, rx_ring->size, 509 rx_ring->desc, rx_ring->dma); 510 511 rx_ring->desc = NULL; 512 } 513 514 /** 515 * igc_free_all_rx_resources - Free Rx Resources for All Queues 516 * @adapter: board private structure 517 * 518 * Free all receive software resources 519 */ 520 static void igc_free_all_rx_resources(struct igc_adapter *adapter) 521 { 522 int i; 523 524 for (i = 0; i < adapter->num_rx_queues; i++) 525 igc_free_rx_resources(adapter->rx_ring[i]); 526 } 527 528 /** 529 * igc_setup_rx_resources - allocate Rx resources (Descriptors) 530 * @rx_ring: rx descriptor ring (for a specific queue) to setup 531 * 532 * Returns 0 on success, negative on failure 533 */ 534 int igc_setup_rx_resources(struct igc_ring *rx_ring) 535 { 536 struct net_device *ndev = rx_ring->netdev; 537 struct device *dev = rx_ring->dev; 538 u8 index = rx_ring->queue_index; 539 int size, desc_len, res; 540 541 /* XDP RX-queue info */ 542 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 543 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 544 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, ndev, index, 545 rx_ring->q_vector->napi.napi_id); 546 if (res < 0) { 547 netdev_err(ndev, "Failed to register xdp_rxq index %u\n", 548 index); 549 return res; 550 } 551 552 size = sizeof(struct igc_rx_buffer) * rx_ring->count; 553 rx_ring->rx_buffer_info = vzalloc(size); 554 if (!rx_ring->rx_buffer_info) 555 goto err; 556 557 desc_len = sizeof(union igc_adv_rx_desc); 558 559 /* Round up to nearest 4K */ 560 rx_ring->size = rx_ring->count * desc_len; 561 rx_ring->size = ALIGN(rx_ring->size, 4096); 562 563 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 564 &rx_ring->dma, GFP_KERNEL); 565 566 if (!rx_ring->desc) 567 goto err; 568 569 rx_ring->next_to_alloc = 0; 570 rx_ring->next_to_clean = 0; 571 rx_ring->next_to_use = 0; 572 573 return 0; 574 575 err: 576 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 577 vfree(rx_ring->rx_buffer_info); 578 rx_ring->rx_buffer_info = NULL; 579 netdev_err(ndev, "Unable to allocate memory for Rx descriptor ring\n"); 580 return -ENOMEM; 581 } 582 583 /** 584 * igc_setup_all_rx_resources - wrapper to allocate Rx resources 585 * (Descriptors) for all queues 586 * @adapter: board private structure 587 * 588 * Return 0 on success, negative on failure 589 */ 590 static int igc_setup_all_rx_resources(struct igc_adapter *adapter) 591 { 592 struct net_device *dev = adapter->netdev; 593 int i, err = 0; 594 595 for (i = 0; i < adapter->num_rx_queues; i++) { 596 err = igc_setup_rx_resources(adapter->rx_ring[i]); 597 if (err) { 598 netdev_err(dev, "Error on Rx queue %u setup\n", i); 599 for (i--; i >= 0; i--) 600 igc_free_rx_resources(adapter->rx_ring[i]); 601 break; 602 } 603 } 604 605 return err; 606 } 607 608 static struct xsk_buff_pool *igc_get_xsk_pool(struct igc_adapter *adapter, 609 struct igc_ring *ring) 610 { 611 if (!igc_xdp_is_enabled(adapter) || 612 !test_bit(IGC_RING_FLAG_AF_XDP_ZC, &ring->flags)) 613 return NULL; 614 615 return xsk_get_pool_from_qid(ring->netdev, ring->queue_index); 616 } 617 618 /** 619 * igc_configure_rx_ring - Configure a receive ring after Reset 620 * @adapter: board private structure 621 * @ring: receive ring to be configured 622 * 623 * Configure the Rx unit of the MAC after a reset. 624 */ 625 static void igc_configure_rx_ring(struct igc_adapter *adapter, 626 struct igc_ring *ring) 627 { 628 struct igc_hw *hw = &adapter->hw; 629 union igc_adv_rx_desc *rx_desc; 630 int reg_idx = ring->reg_idx; 631 u32 srrctl = 0, rxdctl = 0; 632 u64 rdba = ring->dma; 633 u32 buf_size; 634 635 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 636 ring->xsk_pool = igc_get_xsk_pool(adapter, ring); 637 if (ring->xsk_pool) { 638 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 639 MEM_TYPE_XSK_BUFF_POOL, 640 NULL)); 641 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 642 } else { 643 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 644 MEM_TYPE_PAGE_SHARED, 645 NULL)); 646 } 647 648 if (igc_xdp_is_enabled(adapter)) 649 set_ring_uses_large_buffer(ring); 650 651 /* disable the queue */ 652 wr32(IGC_RXDCTL(reg_idx), 0); 653 654 /* Set DMA base address registers */ 655 wr32(IGC_RDBAL(reg_idx), 656 rdba & 0x00000000ffffffffULL); 657 wr32(IGC_RDBAH(reg_idx), rdba >> 32); 658 wr32(IGC_RDLEN(reg_idx), 659 ring->count * sizeof(union igc_adv_rx_desc)); 660 661 /* initialize head and tail */ 662 ring->tail = adapter->io_addr + IGC_RDT(reg_idx); 663 wr32(IGC_RDH(reg_idx), 0); 664 writel(0, ring->tail); 665 666 /* reset next-to- use/clean to place SW in sync with hardware */ 667 ring->next_to_clean = 0; 668 ring->next_to_use = 0; 669 670 if (ring->xsk_pool) 671 buf_size = xsk_pool_get_rx_frame_size(ring->xsk_pool); 672 else if (ring_uses_large_buffer(ring)) 673 buf_size = IGC_RXBUFFER_3072; 674 else 675 buf_size = IGC_RXBUFFER_2048; 676 677 srrctl = rd32(IGC_SRRCTL(reg_idx)); 678 srrctl &= ~(IGC_SRRCTL_BSIZEPKT_MASK | IGC_SRRCTL_BSIZEHDR_MASK | 679 IGC_SRRCTL_DESCTYPE_MASK); 680 srrctl |= IGC_SRRCTL_BSIZEHDR(IGC_RX_HDR_LEN); 681 srrctl |= IGC_SRRCTL_BSIZEPKT(buf_size); 682 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF; 683 684 wr32(IGC_SRRCTL(reg_idx), srrctl); 685 686 rxdctl |= IGC_RX_PTHRESH; 687 rxdctl |= IGC_RX_HTHRESH << 8; 688 rxdctl |= IGC_RX_WTHRESH << 16; 689 690 /* initialize rx_buffer_info */ 691 memset(ring->rx_buffer_info, 0, 692 sizeof(struct igc_rx_buffer) * ring->count); 693 694 /* initialize Rx descriptor 0 */ 695 rx_desc = IGC_RX_DESC(ring, 0); 696 rx_desc->wb.upper.length = 0; 697 698 /* enable receive descriptor fetching */ 699 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE; 700 701 wr32(IGC_RXDCTL(reg_idx), rxdctl); 702 } 703 704 /** 705 * igc_configure_rx - Configure receive Unit after Reset 706 * @adapter: board private structure 707 * 708 * Configure the Rx unit of the MAC after a reset. 709 */ 710 static void igc_configure_rx(struct igc_adapter *adapter) 711 { 712 int i; 713 714 /* Setup the HW Rx Head and Tail Descriptor Pointers and 715 * the Base and Length of the Rx Descriptor Ring 716 */ 717 for (i = 0; i < adapter->num_rx_queues; i++) 718 igc_configure_rx_ring(adapter, adapter->rx_ring[i]); 719 } 720 721 /** 722 * igc_configure_tx_ring - Configure transmit ring after Reset 723 * @adapter: board private structure 724 * @ring: tx ring to configure 725 * 726 * Configure a transmit ring after a reset. 727 */ 728 static void igc_configure_tx_ring(struct igc_adapter *adapter, 729 struct igc_ring *ring) 730 { 731 struct igc_hw *hw = &adapter->hw; 732 int reg_idx = ring->reg_idx; 733 u64 tdba = ring->dma; 734 u32 txdctl = 0; 735 736 ring->xsk_pool = igc_get_xsk_pool(adapter, ring); 737 738 /* disable the queue */ 739 wr32(IGC_TXDCTL(reg_idx), 0); 740 wrfl(); 741 742 wr32(IGC_TDLEN(reg_idx), 743 ring->count * sizeof(union igc_adv_tx_desc)); 744 wr32(IGC_TDBAL(reg_idx), 745 tdba & 0x00000000ffffffffULL); 746 wr32(IGC_TDBAH(reg_idx), tdba >> 32); 747 748 ring->tail = adapter->io_addr + IGC_TDT(reg_idx); 749 wr32(IGC_TDH(reg_idx), 0); 750 writel(0, ring->tail); 751 752 txdctl |= IGC_TX_PTHRESH; 753 txdctl |= IGC_TX_HTHRESH << 8; 754 txdctl |= IGC_TX_WTHRESH << 16; 755 756 txdctl |= IGC_TXDCTL_QUEUE_ENABLE; 757 wr32(IGC_TXDCTL(reg_idx), txdctl); 758 } 759 760 /** 761 * igc_configure_tx - Configure transmit Unit after Reset 762 * @adapter: board private structure 763 * 764 * Configure the Tx unit of the MAC after a reset. 765 */ 766 static void igc_configure_tx(struct igc_adapter *adapter) 767 { 768 int i; 769 770 for (i = 0; i < adapter->num_tx_queues; i++) 771 igc_configure_tx_ring(adapter, adapter->tx_ring[i]); 772 } 773 774 /** 775 * igc_setup_mrqc - configure the multiple receive queue control registers 776 * @adapter: Board private structure 777 */ 778 static void igc_setup_mrqc(struct igc_adapter *adapter) 779 { 780 struct igc_hw *hw = &adapter->hw; 781 u32 j, num_rx_queues; 782 u32 mrqc, rxcsum; 783 u32 rss_key[10]; 784 785 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 786 for (j = 0; j < 10; j++) 787 wr32(IGC_RSSRK(j), rss_key[j]); 788 789 num_rx_queues = adapter->rss_queues; 790 791 if (adapter->rss_indir_tbl_init != num_rx_queues) { 792 for (j = 0; j < IGC_RETA_SIZE; j++) 793 adapter->rss_indir_tbl[j] = 794 (j * num_rx_queues) / IGC_RETA_SIZE; 795 adapter->rss_indir_tbl_init = num_rx_queues; 796 } 797 igc_write_rss_indir_tbl(adapter); 798 799 /* Disable raw packet checksumming so that RSS hash is placed in 800 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 801 * offloads as they are enabled by default 802 */ 803 rxcsum = rd32(IGC_RXCSUM); 804 rxcsum |= IGC_RXCSUM_PCSD; 805 806 /* Enable Receive Checksum Offload for SCTP */ 807 rxcsum |= IGC_RXCSUM_CRCOFL; 808 809 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 810 wr32(IGC_RXCSUM, rxcsum); 811 812 /* Generate RSS hash based on packet types, TCP/UDP 813 * port numbers and/or IPv4/v6 src and dst addresses 814 */ 815 mrqc = IGC_MRQC_RSS_FIELD_IPV4 | 816 IGC_MRQC_RSS_FIELD_IPV4_TCP | 817 IGC_MRQC_RSS_FIELD_IPV6 | 818 IGC_MRQC_RSS_FIELD_IPV6_TCP | 819 IGC_MRQC_RSS_FIELD_IPV6_TCP_EX; 820 821 if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV4_UDP) 822 mrqc |= IGC_MRQC_RSS_FIELD_IPV4_UDP; 823 if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV6_UDP) 824 mrqc |= IGC_MRQC_RSS_FIELD_IPV6_UDP; 825 826 mrqc |= IGC_MRQC_ENABLE_RSS_MQ; 827 828 wr32(IGC_MRQC, mrqc); 829 } 830 831 /** 832 * igc_setup_rctl - configure the receive control registers 833 * @adapter: Board private structure 834 */ 835 static void igc_setup_rctl(struct igc_adapter *adapter) 836 { 837 struct igc_hw *hw = &adapter->hw; 838 u32 rctl; 839 840 rctl = rd32(IGC_RCTL); 841 842 rctl &= ~(3 << IGC_RCTL_MO_SHIFT); 843 rctl &= ~(IGC_RCTL_LBM_TCVR | IGC_RCTL_LBM_MAC); 844 845 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | IGC_RCTL_RDMTS_HALF | 846 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT); 847 848 /* enable stripping of CRC. Newer features require 849 * that the HW strips the CRC. 850 */ 851 rctl |= IGC_RCTL_SECRC; 852 853 /* disable store bad packets and clear size bits. */ 854 rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_SZ_256); 855 856 /* enable LPE to allow for reception of jumbo frames */ 857 rctl |= IGC_RCTL_LPE; 858 859 /* disable queue 0 to prevent tail write w/o re-config */ 860 wr32(IGC_RXDCTL(0), 0); 861 862 /* This is useful for sniffing bad packets. */ 863 if (adapter->netdev->features & NETIF_F_RXALL) { 864 /* UPE and MPE will be handled by normal PROMISC logic 865 * in set_rx_mode 866 */ 867 rctl |= (IGC_RCTL_SBP | /* Receive bad packets */ 868 IGC_RCTL_BAM | /* RX All Bcast Pkts */ 869 IGC_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 870 871 rctl &= ~(IGC_RCTL_DPF | /* Allow filtered pause */ 872 IGC_RCTL_CFIEN); /* Disable VLAN CFIEN Filter */ 873 } 874 875 wr32(IGC_RCTL, rctl); 876 } 877 878 /** 879 * igc_setup_tctl - configure the transmit control registers 880 * @adapter: Board private structure 881 */ 882 static void igc_setup_tctl(struct igc_adapter *adapter) 883 { 884 struct igc_hw *hw = &adapter->hw; 885 u32 tctl; 886 887 /* disable queue 0 which icould be enabled by default */ 888 wr32(IGC_TXDCTL(0), 0); 889 890 /* Program the Transmit Control Register */ 891 tctl = rd32(IGC_TCTL); 892 tctl &= ~IGC_TCTL_CT; 893 tctl |= IGC_TCTL_PSP | IGC_TCTL_RTLC | 894 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT); 895 896 /* Enable transmits */ 897 tctl |= IGC_TCTL_EN; 898 899 wr32(IGC_TCTL, tctl); 900 } 901 902 /** 903 * igc_set_mac_filter_hw() - Set MAC address filter in hardware 904 * @adapter: Pointer to adapter where the filter should be set 905 * @index: Filter index 906 * @type: MAC address filter type (source or destination) 907 * @addr: MAC address 908 * @queue: If non-negative, queue assignment feature is enabled and frames 909 * matching the filter are enqueued onto 'queue'. Otherwise, queue 910 * assignment is disabled. 911 */ 912 static void igc_set_mac_filter_hw(struct igc_adapter *adapter, int index, 913 enum igc_mac_filter_type type, 914 const u8 *addr, int queue) 915 { 916 struct net_device *dev = adapter->netdev; 917 struct igc_hw *hw = &adapter->hw; 918 u32 ral, rah; 919 920 if (WARN_ON(index >= hw->mac.rar_entry_count)) 921 return; 922 923 ral = le32_to_cpup((__le32 *)(addr)); 924 rah = le16_to_cpup((__le16 *)(addr + 4)); 925 926 if (type == IGC_MAC_FILTER_TYPE_SRC) { 927 rah &= ~IGC_RAH_ASEL_MASK; 928 rah |= IGC_RAH_ASEL_SRC_ADDR; 929 } 930 931 if (queue >= 0) { 932 rah &= ~IGC_RAH_QSEL_MASK; 933 rah |= (queue << IGC_RAH_QSEL_SHIFT); 934 rah |= IGC_RAH_QSEL_ENABLE; 935 } 936 937 rah |= IGC_RAH_AV; 938 939 wr32(IGC_RAL(index), ral); 940 wr32(IGC_RAH(index), rah); 941 942 netdev_dbg(dev, "MAC address filter set in HW: index %d", index); 943 } 944 945 /** 946 * igc_clear_mac_filter_hw() - Clear MAC address filter in hardware 947 * @adapter: Pointer to adapter where the filter should be cleared 948 * @index: Filter index 949 */ 950 static void igc_clear_mac_filter_hw(struct igc_adapter *adapter, int index) 951 { 952 struct net_device *dev = adapter->netdev; 953 struct igc_hw *hw = &adapter->hw; 954 955 if (WARN_ON(index >= hw->mac.rar_entry_count)) 956 return; 957 958 wr32(IGC_RAL(index), 0); 959 wr32(IGC_RAH(index), 0); 960 961 netdev_dbg(dev, "MAC address filter cleared in HW: index %d", index); 962 } 963 964 /* Set default MAC address for the PF in the first RAR entry */ 965 static void igc_set_default_mac_filter(struct igc_adapter *adapter) 966 { 967 struct net_device *dev = adapter->netdev; 968 u8 *addr = adapter->hw.mac.addr; 969 970 netdev_dbg(dev, "Set default MAC address filter: address %pM", addr); 971 972 igc_set_mac_filter_hw(adapter, 0, IGC_MAC_FILTER_TYPE_DST, addr, -1); 973 } 974 975 /** 976 * igc_set_mac - Change the Ethernet Address of the NIC 977 * @netdev: network interface device structure 978 * @p: pointer to an address structure 979 * 980 * Returns 0 on success, negative on failure 981 */ 982 static int igc_set_mac(struct net_device *netdev, void *p) 983 { 984 struct igc_adapter *adapter = netdev_priv(netdev); 985 struct igc_hw *hw = &adapter->hw; 986 struct sockaddr *addr = p; 987 988 if (!is_valid_ether_addr(addr->sa_data)) 989 return -EADDRNOTAVAIL; 990 991 eth_hw_addr_set(netdev, addr->sa_data); 992 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 993 994 /* set the correct pool for the new PF MAC address in entry 0 */ 995 igc_set_default_mac_filter(adapter); 996 997 return 0; 998 } 999 1000 /** 1001 * igc_write_mc_addr_list - write multicast addresses to MTA 1002 * @netdev: network interface device structure 1003 * 1004 * Writes multicast address list to the MTA hash table. 1005 * Returns: -ENOMEM on failure 1006 * 0 on no addresses written 1007 * X on writing X addresses to MTA 1008 **/ 1009 static int igc_write_mc_addr_list(struct net_device *netdev) 1010 { 1011 struct igc_adapter *adapter = netdev_priv(netdev); 1012 struct igc_hw *hw = &adapter->hw; 1013 struct netdev_hw_addr *ha; 1014 u8 *mta_list; 1015 int i; 1016 1017 if (netdev_mc_empty(netdev)) { 1018 /* nothing to program, so clear mc list */ 1019 igc_update_mc_addr_list(hw, NULL, 0); 1020 return 0; 1021 } 1022 1023 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 1024 if (!mta_list) 1025 return -ENOMEM; 1026 1027 /* The shared function expects a packed array of only addresses. */ 1028 i = 0; 1029 netdev_for_each_mc_addr(ha, netdev) 1030 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 1031 1032 igc_update_mc_addr_list(hw, mta_list, i); 1033 kfree(mta_list); 1034 1035 return netdev_mc_count(netdev); 1036 } 1037 1038 static __le32 igc_tx_launchtime(struct igc_ring *ring, ktime_t txtime, 1039 bool *first_flag, bool *insert_empty) 1040 { 1041 struct igc_adapter *adapter = netdev_priv(ring->netdev); 1042 ktime_t cycle_time = adapter->cycle_time; 1043 ktime_t base_time = adapter->base_time; 1044 ktime_t now = ktime_get_clocktai(); 1045 ktime_t baset_est, end_of_cycle; 1046 s32 launchtime; 1047 s64 n; 1048 1049 n = div64_s64(ktime_sub_ns(now, base_time), cycle_time); 1050 1051 baset_est = ktime_add_ns(base_time, cycle_time * (n)); 1052 end_of_cycle = ktime_add_ns(baset_est, cycle_time); 1053 1054 if (ktime_compare(txtime, end_of_cycle) >= 0) { 1055 if (baset_est != ring->last_ff_cycle) { 1056 *first_flag = true; 1057 ring->last_ff_cycle = baset_est; 1058 1059 if (ktime_compare(end_of_cycle, ring->last_tx_cycle) > 0) 1060 *insert_empty = true; 1061 } 1062 } 1063 1064 /* Introducing a window at end of cycle on which packets 1065 * potentially not honor launchtime. Window of 5us chosen 1066 * considering software update the tail pointer and packets 1067 * are dma'ed to packet buffer. 1068 */ 1069 if ((ktime_sub_ns(end_of_cycle, now) < 5 * NSEC_PER_USEC)) 1070 netdev_warn(ring->netdev, "Packet with txtime=%llu may not be honoured\n", 1071 txtime); 1072 1073 ring->last_tx_cycle = end_of_cycle; 1074 1075 launchtime = ktime_sub_ns(txtime, baset_est); 1076 if (launchtime > 0) 1077 div_s64_rem(launchtime, cycle_time, &launchtime); 1078 else 1079 launchtime = 0; 1080 1081 return cpu_to_le32(launchtime); 1082 } 1083 1084 static int igc_init_empty_frame(struct igc_ring *ring, 1085 struct igc_tx_buffer *buffer, 1086 struct sk_buff *skb) 1087 { 1088 unsigned int size; 1089 dma_addr_t dma; 1090 1091 size = skb_headlen(skb); 1092 1093 dma = dma_map_single(ring->dev, skb->data, size, DMA_TO_DEVICE); 1094 if (dma_mapping_error(ring->dev, dma)) { 1095 netdev_err_once(ring->netdev, "Failed to map DMA for TX\n"); 1096 return -ENOMEM; 1097 } 1098 1099 buffer->skb = skb; 1100 buffer->protocol = 0; 1101 buffer->bytecount = skb->len; 1102 buffer->gso_segs = 1; 1103 buffer->time_stamp = jiffies; 1104 dma_unmap_len_set(buffer, len, skb->len); 1105 dma_unmap_addr_set(buffer, dma, dma); 1106 1107 return 0; 1108 } 1109 1110 static int igc_init_tx_empty_descriptor(struct igc_ring *ring, 1111 struct sk_buff *skb, 1112 struct igc_tx_buffer *first) 1113 { 1114 union igc_adv_tx_desc *desc; 1115 u32 cmd_type, olinfo_status; 1116 int err; 1117 1118 if (!igc_desc_unused(ring)) 1119 return -EBUSY; 1120 1121 err = igc_init_empty_frame(ring, first, skb); 1122 if (err) 1123 return err; 1124 1125 cmd_type = IGC_ADVTXD_DTYP_DATA | IGC_ADVTXD_DCMD_DEXT | 1126 IGC_ADVTXD_DCMD_IFCS | IGC_TXD_DCMD | 1127 first->bytecount; 1128 olinfo_status = first->bytecount << IGC_ADVTXD_PAYLEN_SHIFT; 1129 1130 desc = IGC_TX_DESC(ring, ring->next_to_use); 1131 desc->read.cmd_type_len = cpu_to_le32(cmd_type); 1132 desc->read.olinfo_status = cpu_to_le32(olinfo_status); 1133 desc->read.buffer_addr = cpu_to_le64(dma_unmap_addr(first, dma)); 1134 1135 netdev_tx_sent_queue(txring_txq(ring), skb->len); 1136 1137 first->next_to_watch = desc; 1138 1139 ring->next_to_use++; 1140 if (ring->next_to_use == ring->count) 1141 ring->next_to_use = 0; 1142 1143 return 0; 1144 } 1145 1146 #define IGC_EMPTY_FRAME_SIZE 60 1147 1148 static void igc_tx_ctxtdesc(struct igc_ring *tx_ring, 1149 __le32 launch_time, bool first_flag, 1150 u32 vlan_macip_lens, u32 type_tucmd, 1151 u32 mss_l4len_idx) 1152 { 1153 struct igc_adv_tx_context_desc *context_desc; 1154 u16 i = tx_ring->next_to_use; 1155 1156 context_desc = IGC_TX_CTXTDESC(tx_ring, i); 1157 1158 i++; 1159 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 1160 1161 /* set bits to identify this as an advanced context descriptor */ 1162 type_tucmd |= IGC_TXD_CMD_DEXT | IGC_ADVTXD_DTYP_CTXT; 1163 1164 /* For i225, context index must be unique per ring. */ 1165 if (test_bit(IGC_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 1166 mss_l4len_idx |= tx_ring->reg_idx << 4; 1167 1168 if (first_flag) 1169 mss_l4len_idx |= IGC_ADVTXD_TSN_CNTX_FIRST; 1170 1171 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 1172 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 1173 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 1174 context_desc->launch_time = launch_time; 1175 } 1176 1177 static void igc_tx_csum(struct igc_ring *tx_ring, struct igc_tx_buffer *first, 1178 __le32 launch_time, bool first_flag) 1179 { 1180 struct sk_buff *skb = first->skb; 1181 u32 vlan_macip_lens = 0; 1182 u32 type_tucmd = 0; 1183 1184 if (skb->ip_summed != CHECKSUM_PARTIAL) { 1185 csum_failed: 1186 if (!(first->tx_flags & IGC_TX_FLAGS_VLAN) && 1187 !tx_ring->launchtime_enable) 1188 return; 1189 goto no_csum; 1190 } 1191 1192 switch (skb->csum_offset) { 1193 case offsetof(struct tcphdr, check): 1194 type_tucmd = IGC_ADVTXD_TUCMD_L4T_TCP; 1195 fallthrough; 1196 case offsetof(struct udphdr, check): 1197 break; 1198 case offsetof(struct sctphdr, checksum): 1199 /* validate that this is actually an SCTP request */ 1200 if (skb_csum_is_sctp(skb)) { 1201 type_tucmd = IGC_ADVTXD_TUCMD_L4T_SCTP; 1202 break; 1203 } 1204 fallthrough; 1205 default: 1206 skb_checksum_help(skb); 1207 goto csum_failed; 1208 } 1209 1210 /* update TX checksum flag */ 1211 first->tx_flags |= IGC_TX_FLAGS_CSUM; 1212 vlan_macip_lens = skb_checksum_start_offset(skb) - 1213 skb_network_offset(skb); 1214 no_csum: 1215 vlan_macip_lens |= skb_network_offset(skb) << IGC_ADVTXD_MACLEN_SHIFT; 1216 vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK; 1217 1218 igc_tx_ctxtdesc(tx_ring, launch_time, first_flag, 1219 vlan_macip_lens, type_tucmd, 0); 1220 } 1221 1222 static int __igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size) 1223 { 1224 struct net_device *netdev = tx_ring->netdev; 1225 1226 netif_stop_subqueue(netdev, tx_ring->queue_index); 1227 1228 /* memory barriier comment */ 1229 smp_mb(); 1230 1231 /* We need to check again in a case another CPU has just 1232 * made room available. 1233 */ 1234 if (igc_desc_unused(tx_ring) < size) 1235 return -EBUSY; 1236 1237 /* A reprieve! */ 1238 netif_wake_subqueue(netdev, tx_ring->queue_index); 1239 1240 u64_stats_update_begin(&tx_ring->tx_syncp2); 1241 tx_ring->tx_stats.restart_queue2++; 1242 u64_stats_update_end(&tx_ring->tx_syncp2); 1243 1244 return 0; 1245 } 1246 1247 static inline int igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size) 1248 { 1249 if (igc_desc_unused(tx_ring) >= size) 1250 return 0; 1251 return __igc_maybe_stop_tx(tx_ring, size); 1252 } 1253 1254 #define IGC_SET_FLAG(_input, _flag, _result) \ 1255 (((_flag) <= (_result)) ? \ 1256 ((u32)((_input) & (_flag)) * ((_result) / (_flag))) : \ 1257 ((u32)((_input) & (_flag)) / ((_flag) / (_result)))) 1258 1259 static u32 igc_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 1260 { 1261 /* set type for advanced descriptor with frame checksum insertion */ 1262 u32 cmd_type = IGC_ADVTXD_DTYP_DATA | 1263 IGC_ADVTXD_DCMD_DEXT | 1264 IGC_ADVTXD_DCMD_IFCS; 1265 1266 /* set HW vlan bit if vlan is present */ 1267 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_VLAN, 1268 IGC_ADVTXD_DCMD_VLE); 1269 1270 /* set segmentation bits for TSO */ 1271 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSO, 1272 (IGC_ADVTXD_DCMD_TSE)); 1273 1274 /* set timestamp bit if present */ 1275 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP, 1276 (IGC_ADVTXD_MAC_TSTAMP)); 1277 1278 /* insert frame checksum */ 1279 cmd_type ^= IGC_SET_FLAG(skb->no_fcs, 1, IGC_ADVTXD_DCMD_IFCS); 1280 1281 return cmd_type; 1282 } 1283 1284 static void igc_tx_olinfo_status(struct igc_ring *tx_ring, 1285 union igc_adv_tx_desc *tx_desc, 1286 u32 tx_flags, unsigned int paylen) 1287 { 1288 u32 olinfo_status = paylen << IGC_ADVTXD_PAYLEN_SHIFT; 1289 1290 /* insert L4 checksum */ 1291 olinfo_status |= (tx_flags & IGC_TX_FLAGS_CSUM) * 1292 ((IGC_TXD_POPTS_TXSM << 8) / 1293 IGC_TX_FLAGS_CSUM); 1294 1295 /* insert IPv4 checksum */ 1296 olinfo_status |= (tx_flags & IGC_TX_FLAGS_IPV4) * 1297 (((IGC_TXD_POPTS_IXSM << 8)) / 1298 IGC_TX_FLAGS_IPV4); 1299 1300 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 1301 } 1302 1303 static int igc_tx_map(struct igc_ring *tx_ring, 1304 struct igc_tx_buffer *first, 1305 const u8 hdr_len) 1306 { 1307 struct sk_buff *skb = first->skb; 1308 struct igc_tx_buffer *tx_buffer; 1309 union igc_adv_tx_desc *tx_desc; 1310 u32 tx_flags = first->tx_flags; 1311 skb_frag_t *frag; 1312 u16 i = tx_ring->next_to_use; 1313 unsigned int data_len, size; 1314 dma_addr_t dma; 1315 u32 cmd_type; 1316 1317 cmd_type = igc_tx_cmd_type(skb, tx_flags); 1318 tx_desc = IGC_TX_DESC(tx_ring, i); 1319 1320 igc_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 1321 1322 size = skb_headlen(skb); 1323 data_len = skb->data_len; 1324 1325 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 1326 1327 tx_buffer = first; 1328 1329 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 1330 if (dma_mapping_error(tx_ring->dev, dma)) 1331 goto dma_error; 1332 1333 /* record length, and DMA address */ 1334 dma_unmap_len_set(tx_buffer, len, size); 1335 dma_unmap_addr_set(tx_buffer, dma, dma); 1336 1337 tx_desc->read.buffer_addr = cpu_to_le64(dma); 1338 1339 while (unlikely(size > IGC_MAX_DATA_PER_TXD)) { 1340 tx_desc->read.cmd_type_len = 1341 cpu_to_le32(cmd_type ^ IGC_MAX_DATA_PER_TXD); 1342 1343 i++; 1344 tx_desc++; 1345 if (i == tx_ring->count) { 1346 tx_desc = IGC_TX_DESC(tx_ring, 0); 1347 i = 0; 1348 } 1349 tx_desc->read.olinfo_status = 0; 1350 1351 dma += IGC_MAX_DATA_PER_TXD; 1352 size -= IGC_MAX_DATA_PER_TXD; 1353 1354 tx_desc->read.buffer_addr = cpu_to_le64(dma); 1355 } 1356 1357 if (likely(!data_len)) 1358 break; 1359 1360 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 1361 1362 i++; 1363 tx_desc++; 1364 if (i == tx_ring->count) { 1365 tx_desc = IGC_TX_DESC(tx_ring, 0); 1366 i = 0; 1367 } 1368 tx_desc->read.olinfo_status = 0; 1369 1370 size = skb_frag_size(frag); 1371 data_len -= size; 1372 1373 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 1374 size, DMA_TO_DEVICE); 1375 1376 tx_buffer = &tx_ring->tx_buffer_info[i]; 1377 } 1378 1379 /* write last descriptor with RS and EOP bits */ 1380 cmd_type |= size | IGC_TXD_DCMD; 1381 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 1382 1383 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 1384 1385 /* set the timestamp */ 1386 first->time_stamp = jiffies; 1387 1388 skb_tx_timestamp(skb); 1389 1390 /* Force memory writes to complete before letting h/w know there 1391 * are new descriptors to fetch. (Only applicable for weak-ordered 1392 * memory model archs, such as IA-64). 1393 * 1394 * We also need this memory barrier to make certain all of the 1395 * status bits have been updated before next_to_watch is written. 1396 */ 1397 wmb(); 1398 1399 /* set next_to_watch value indicating a packet is present */ 1400 first->next_to_watch = tx_desc; 1401 1402 i++; 1403 if (i == tx_ring->count) 1404 i = 0; 1405 1406 tx_ring->next_to_use = i; 1407 1408 /* Make sure there is space in the ring for the next send. */ 1409 igc_maybe_stop_tx(tx_ring, DESC_NEEDED); 1410 1411 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 1412 writel(i, tx_ring->tail); 1413 } 1414 1415 return 0; 1416 dma_error: 1417 netdev_err(tx_ring->netdev, "TX DMA map failed\n"); 1418 tx_buffer = &tx_ring->tx_buffer_info[i]; 1419 1420 /* clear dma mappings for failed tx_buffer_info map */ 1421 while (tx_buffer != first) { 1422 if (dma_unmap_len(tx_buffer, len)) 1423 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 1424 1425 if (i-- == 0) 1426 i += tx_ring->count; 1427 tx_buffer = &tx_ring->tx_buffer_info[i]; 1428 } 1429 1430 if (dma_unmap_len(tx_buffer, len)) 1431 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 1432 1433 dev_kfree_skb_any(tx_buffer->skb); 1434 tx_buffer->skb = NULL; 1435 1436 tx_ring->next_to_use = i; 1437 1438 return -1; 1439 } 1440 1441 static int igc_tso(struct igc_ring *tx_ring, 1442 struct igc_tx_buffer *first, 1443 __le32 launch_time, bool first_flag, 1444 u8 *hdr_len) 1445 { 1446 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 1447 struct sk_buff *skb = first->skb; 1448 union { 1449 struct iphdr *v4; 1450 struct ipv6hdr *v6; 1451 unsigned char *hdr; 1452 } ip; 1453 union { 1454 struct tcphdr *tcp; 1455 struct udphdr *udp; 1456 unsigned char *hdr; 1457 } l4; 1458 u32 paylen, l4_offset; 1459 int err; 1460 1461 if (skb->ip_summed != CHECKSUM_PARTIAL) 1462 return 0; 1463 1464 if (!skb_is_gso(skb)) 1465 return 0; 1466 1467 err = skb_cow_head(skb, 0); 1468 if (err < 0) 1469 return err; 1470 1471 ip.hdr = skb_network_header(skb); 1472 l4.hdr = skb_checksum_start(skb); 1473 1474 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 1475 type_tucmd = IGC_ADVTXD_TUCMD_L4T_TCP; 1476 1477 /* initialize outer IP header fields */ 1478 if (ip.v4->version == 4) { 1479 unsigned char *csum_start = skb_checksum_start(skb); 1480 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 1481 1482 /* IP header will have to cancel out any data that 1483 * is not a part of the outer IP header 1484 */ 1485 ip.v4->check = csum_fold(csum_partial(trans_start, 1486 csum_start - trans_start, 1487 0)); 1488 type_tucmd |= IGC_ADVTXD_TUCMD_IPV4; 1489 1490 ip.v4->tot_len = 0; 1491 first->tx_flags |= IGC_TX_FLAGS_TSO | 1492 IGC_TX_FLAGS_CSUM | 1493 IGC_TX_FLAGS_IPV4; 1494 } else { 1495 ip.v6->payload_len = 0; 1496 first->tx_flags |= IGC_TX_FLAGS_TSO | 1497 IGC_TX_FLAGS_CSUM; 1498 } 1499 1500 /* determine offset of inner transport header */ 1501 l4_offset = l4.hdr - skb->data; 1502 1503 /* remove payload length from inner checksum */ 1504 paylen = skb->len - l4_offset; 1505 if (type_tucmd & IGC_ADVTXD_TUCMD_L4T_TCP) { 1506 /* compute length of segmentation header */ 1507 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 1508 csum_replace_by_diff(&l4.tcp->check, 1509 (__force __wsum)htonl(paylen)); 1510 } else { 1511 /* compute length of segmentation header */ 1512 *hdr_len = sizeof(*l4.udp) + l4_offset; 1513 csum_replace_by_diff(&l4.udp->check, 1514 (__force __wsum)htonl(paylen)); 1515 } 1516 1517 /* update gso size and bytecount with header size */ 1518 first->gso_segs = skb_shinfo(skb)->gso_segs; 1519 first->bytecount += (first->gso_segs - 1) * *hdr_len; 1520 1521 /* MSS L4LEN IDX */ 1522 mss_l4len_idx = (*hdr_len - l4_offset) << IGC_ADVTXD_L4LEN_SHIFT; 1523 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IGC_ADVTXD_MSS_SHIFT; 1524 1525 /* VLAN MACLEN IPLEN */ 1526 vlan_macip_lens = l4.hdr - ip.hdr; 1527 vlan_macip_lens |= (ip.hdr - skb->data) << IGC_ADVTXD_MACLEN_SHIFT; 1528 vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK; 1529 1530 igc_tx_ctxtdesc(tx_ring, launch_time, first_flag, 1531 vlan_macip_lens, type_tucmd, mss_l4len_idx); 1532 1533 return 1; 1534 } 1535 1536 static netdev_tx_t igc_xmit_frame_ring(struct sk_buff *skb, 1537 struct igc_ring *tx_ring) 1538 { 1539 struct igc_adapter *adapter = netdev_priv(tx_ring->netdev); 1540 bool first_flag = false, insert_empty = false; 1541 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 1542 __be16 protocol = vlan_get_protocol(skb); 1543 struct igc_tx_buffer *first; 1544 __le32 launch_time = 0; 1545 u32 tx_flags = 0; 1546 unsigned short f; 1547 ktime_t txtime; 1548 u8 hdr_len = 0; 1549 int tso = 0; 1550 1551 /* need: 1 descriptor per page * PAGE_SIZE/IGC_MAX_DATA_PER_TXD, 1552 * + 1 desc for skb_headlen/IGC_MAX_DATA_PER_TXD, 1553 * + 2 desc gap to keep tail from touching head, 1554 * + 1 desc for context descriptor, 1555 * otherwise try next time 1556 */ 1557 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 1558 count += TXD_USE_COUNT(skb_frag_size( 1559 &skb_shinfo(skb)->frags[f])); 1560 1561 if (igc_maybe_stop_tx(tx_ring, count + 5)) { 1562 /* this is a hard error */ 1563 return NETDEV_TX_BUSY; 1564 } 1565 1566 if (!tx_ring->launchtime_enable) 1567 goto done; 1568 1569 txtime = skb->tstamp; 1570 skb->tstamp = ktime_set(0, 0); 1571 launch_time = igc_tx_launchtime(tx_ring, txtime, &first_flag, &insert_empty); 1572 1573 if (insert_empty) { 1574 struct igc_tx_buffer *empty_info; 1575 struct sk_buff *empty; 1576 void *data; 1577 1578 empty_info = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 1579 empty = alloc_skb(IGC_EMPTY_FRAME_SIZE, GFP_ATOMIC); 1580 if (!empty) 1581 goto done; 1582 1583 data = skb_put(empty, IGC_EMPTY_FRAME_SIZE); 1584 memset(data, 0, IGC_EMPTY_FRAME_SIZE); 1585 1586 igc_tx_ctxtdesc(tx_ring, 0, false, 0, 0, 0); 1587 1588 if (igc_init_tx_empty_descriptor(tx_ring, 1589 empty, 1590 empty_info) < 0) 1591 dev_kfree_skb_any(empty); 1592 } 1593 1594 done: 1595 /* record the location of the first descriptor for this packet */ 1596 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 1597 first->type = IGC_TX_BUFFER_TYPE_SKB; 1598 first->skb = skb; 1599 first->bytecount = skb->len; 1600 first->gso_segs = 1; 1601 1602 if (adapter->qbv_transition || tx_ring->oper_gate_closed) 1603 goto out_drop; 1604 1605 if (tx_ring->max_sdu > 0 && first->bytecount > tx_ring->max_sdu) { 1606 adapter->stats.txdrop++; 1607 goto out_drop; 1608 } 1609 1610 if (unlikely(test_bit(IGC_RING_FLAG_TX_HWTSTAMP, &tx_ring->flags) && 1611 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 1612 /* FIXME: add support for retrieving timestamps from 1613 * the other timer registers before skipping the 1614 * timestamping request. 1615 */ 1616 unsigned long flags; 1617 1618 spin_lock_irqsave(&adapter->ptp_tx_lock, flags); 1619 if (!adapter->ptp_tx_skb) { 1620 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1621 tx_flags |= IGC_TX_FLAGS_TSTAMP; 1622 1623 adapter->ptp_tx_skb = skb_get(skb); 1624 adapter->ptp_tx_start = jiffies; 1625 } else { 1626 adapter->tx_hwtstamp_skipped++; 1627 } 1628 1629 spin_unlock_irqrestore(&adapter->ptp_tx_lock, flags); 1630 } 1631 1632 if (skb_vlan_tag_present(skb)) { 1633 tx_flags |= IGC_TX_FLAGS_VLAN; 1634 tx_flags |= (skb_vlan_tag_get(skb) << IGC_TX_FLAGS_VLAN_SHIFT); 1635 } 1636 1637 /* record initial flags and protocol */ 1638 first->tx_flags = tx_flags; 1639 first->protocol = protocol; 1640 1641 tso = igc_tso(tx_ring, first, launch_time, first_flag, &hdr_len); 1642 if (tso < 0) 1643 goto out_drop; 1644 else if (!tso) 1645 igc_tx_csum(tx_ring, first, launch_time, first_flag); 1646 1647 igc_tx_map(tx_ring, first, hdr_len); 1648 1649 return NETDEV_TX_OK; 1650 1651 out_drop: 1652 dev_kfree_skb_any(first->skb); 1653 first->skb = NULL; 1654 1655 return NETDEV_TX_OK; 1656 } 1657 1658 static inline struct igc_ring *igc_tx_queue_mapping(struct igc_adapter *adapter, 1659 struct sk_buff *skb) 1660 { 1661 unsigned int r_idx = skb->queue_mapping; 1662 1663 if (r_idx >= adapter->num_tx_queues) 1664 r_idx = r_idx % adapter->num_tx_queues; 1665 1666 return adapter->tx_ring[r_idx]; 1667 } 1668 1669 static netdev_tx_t igc_xmit_frame(struct sk_buff *skb, 1670 struct net_device *netdev) 1671 { 1672 struct igc_adapter *adapter = netdev_priv(netdev); 1673 1674 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 1675 * in order to meet this minimum size requirement. 1676 */ 1677 if (skb->len < 17) { 1678 if (skb_padto(skb, 17)) 1679 return NETDEV_TX_OK; 1680 skb->len = 17; 1681 } 1682 1683 return igc_xmit_frame_ring(skb, igc_tx_queue_mapping(adapter, skb)); 1684 } 1685 1686 static void igc_rx_checksum(struct igc_ring *ring, 1687 union igc_adv_rx_desc *rx_desc, 1688 struct sk_buff *skb) 1689 { 1690 skb_checksum_none_assert(skb); 1691 1692 /* Ignore Checksum bit is set */ 1693 if (igc_test_staterr(rx_desc, IGC_RXD_STAT_IXSM)) 1694 return; 1695 1696 /* Rx checksum disabled via ethtool */ 1697 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1698 return; 1699 1700 /* TCP/UDP checksum error bit is set */ 1701 if (igc_test_staterr(rx_desc, 1702 IGC_RXDEXT_STATERR_L4E | 1703 IGC_RXDEXT_STATERR_IPE)) { 1704 /* work around errata with sctp packets where the TCPE aka 1705 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 1706 * packets (aka let the stack check the crc32c) 1707 */ 1708 if (!(skb->len == 60 && 1709 test_bit(IGC_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 1710 u64_stats_update_begin(&ring->rx_syncp); 1711 ring->rx_stats.csum_err++; 1712 u64_stats_update_end(&ring->rx_syncp); 1713 } 1714 /* let the stack verify checksum errors */ 1715 return; 1716 } 1717 /* It must be a TCP or UDP packet with a valid checksum */ 1718 if (igc_test_staterr(rx_desc, IGC_RXD_STAT_TCPCS | 1719 IGC_RXD_STAT_UDPCS)) 1720 skb->ip_summed = CHECKSUM_UNNECESSARY; 1721 1722 netdev_dbg(ring->netdev, "cksum success: bits %08X\n", 1723 le32_to_cpu(rx_desc->wb.upper.status_error)); 1724 } 1725 1726 /* Mapping HW RSS Type to enum pkt_hash_types */ 1727 static const enum pkt_hash_types igc_rss_type_table[IGC_RSS_TYPE_MAX_TABLE] = { 1728 [IGC_RSS_TYPE_NO_HASH] = PKT_HASH_TYPE_L2, 1729 [IGC_RSS_TYPE_HASH_TCP_IPV4] = PKT_HASH_TYPE_L4, 1730 [IGC_RSS_TYPE_HASH_IPV4] = PKT_HASH_TYPE_L3, 1731 [IGC_RSS_TYPE_HASH_TCP_IPV6] = PKT_HASH_TYPE_L4, 1732 [IGC_RSS_TYPE_HASH_IPV6_EX] = PKT_HASH_TYPE_L3, 1733 [IGC_RSS_TYPE_HASH_IPV6] = PKT_HASH_TYPE_L3, 1734 [IGC_RSS_TYPE_HASH_TCP_IPV6_EX] = PKT_HASH_TYPE_L4, 1735 [IGC_RSS_TYPE_HASH_UDP_IPV4] = PKT_HASH_TYPE_L4, 1736 [IGC_RSS_TYPE_HASH_UDP_IPV6] = PKT_HASH_TYPE_L4, 1737 [IGC_RSS_TYPE_HASH_UDP_IPV6_EX] = PKT_HASH_TYPE_L4, 1738 [10] = PKT_HASH_TYPE_NONE, /* RSS Type above 9 "Reserved" by HW */ 1739 [11] = PKT_HASH_TYPE_NONE, /* keep array sized for SW bit-mask */ 1740 [12] = PKT_HASH_TYPE_NONE, /* to handle future HW revisons */ 1741 [13] = PKT_HASH_TYPE_NONE, 1742 [14] = PKT_HASH_TYPE_NONE, 1743 [15] = PKT_HASH_TYPE_NONE, 1744 }; 1745 1746 static inline void igc_rx_hash(struct igc_ring *ring, 1747 union igc_adv_rx_desc *rx_desc, 1748 struct sk_buff *skb) 1749 { 1750 if (ring->netdev->features & NETIF_F_RXHASH) { 1751 u32 rss_hash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); 1752 u32 rss_type = igc_rss_type(rx_desc); 1753 1754 skb_set_hash(skb, rss_hash, igc_rss_type_table[rss_type]); 1755 } 1756 } 1757 1758 static void igc_rx_vlan(struct igc_ring *rx_ring, 1759 union igc_adv_rx_desc *rx_desc, 1760 struct sk_buff *skb) 1761 { 1762 struct net_device *dev = rx_ring->netdev; 1763 u16 vid; 1764 1765 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1766 igc_test_staterr(rx_desc, IGC_RXD_STAT_VP)) { 1767 if (igc_test_staterr(rx_desc, IGC_RXDEXT_STATERR_LB) && 1768 test_bit(IGC_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 1769 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 1770 else 1771 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1772 1773 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1774 } 1775 } 1776 1777 /** 1778 * igc_process_skb_fields - Populate skb header fields from Rx descriptor 1779 * @rx_ring: rx descriptor ring packet is being transacted on 1780 * @rx_desc: pointer to the EOP Rx descriptor 1781 * @skb: pointer to current skb being populated 1782 * 1783 * This function checks the ring, descriptor, and packet information in order 1784 * to populate the hash, checksum, VLAN, protocol, and other fields within the 1785 * skb. 1786 */ 1787 static void igc_process_skb_fields(struct igc_ring *rx_ring, 1788 union igc_adv_rx_desc *rx_desc, 1789 struct sk_buff *skb) 1790 { 1791 igc_rx_hash(rx_ring, rx_desc, skb); 1792 1793 igc_rx_checksum(rx_ring, rx_desc, skb); 1794 1795 igc_rx_vlan(rx_ring, rx_desc, skb); 1796 1797 skb_record_rx_queue(skb, rx_ring->queue_index); 1798 1799 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 1800 } 1801 1802 static void igc_vlan_mode(struct net_device *netdev, netdev_features_t features) 1803 { 1804 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 1805 struct igc_adapter *adapter = netdev_priv(netdev); 1806 struct igc_hw *hw = &adapter->hw; 1807 u32 ctrl; 1808 1809 ctrl = rd32(IGC_CTRL); 1810 1811 if (enable) { 1812 /* enable VLAN tag insert/strip */ 1813 ctrl |= IGC_CTRL_VME; 1814 } else { 1815 /* disable VLAN tag insert/strip */ 1816 ctrl &= ~IGC_CTRL_VME; 1817 } 1818 wr32(IGC_CTRL, ctrl); 1819 } 1820 1821 static void igc_restore_vlan(struct igc_adapter *adapter) 1822 { 1823 igc_vlan_mode(adapter->netdev, adapter->netdev->features); 1824 } 1825 1826 static struct igc_rx_buffer *igc_get_rx_buffer(struct igc_ring *rx_ring, 1827 const unsigned int size, 1828 int *rx_buffer_pgcnt) 1829 { 1830 struct igc_rx_buffer *rx_buffer; 1831 1832 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 1833 *rx_buffer_pgcnt = 1834 #if (PAGE_SIZE < 8192) 1835 page_count(rx_buffer->page); 1836 #else 1837 0; 1838 #endif 1839 prefetchw(rx_buffer->page); 1840 1841 /* we are reusing so sync this buffer for CPU use */ 1842 dma_sync_single_range_for_cpu(rx_ring->dev, 1843 rx_buffer->dma, 1844 rx_buffer->page_offset, 1845 size, 1846 DMA_FROM_DEVICE); 1847 1848 rx_buffer->pagecnt_bias--; 1849 1850 return rx_buffer; 1851 } 1852 1853 static void igc_rx_buffer_flip(struct igc_rx_buffer *buffer, 1854 unsigned int truesize) 1855 { 1856 #if (PAGE_SIZE < 8192) 1857 buffer->page_offset ^= truesize; 1858 #else 1859 buffer->page_offset += truesize; 1860 #endif 1861 } 1862 1863 static unsigned int igc_get_rx_frame_truesize(struct igc_ring *ring, 1864 unsigned int size) 1865 { 1866 unsigned int truesize; 1867 1868 #if (PAGE_SIZE < 8192) 1869 truesize = igc_rx_pg_size(ring) / 2; 1870 #else 1871 truesize = ring_uses_build_skb(ring) ? 1872 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1873 SKB_DATA_ALIGN(IGC_SKB_PAD + size) : 1874 SKB_DATA_ALIGN(size); 1875 #endif 1876 return truesize; 1877 } 1878 1879 /** 1880 * igc_add_rx_frag - Add contents of Rx buffer to sk_buff 1881 * @rx_ring: rx descriptor ring to transact packets on 1882 * @rx_buffer: buffer containing page to add 1883 * @skb: sk_buff to place the data into 1884 * @size: size of buffer to be added 1885 * 1886 * This function will add the data contained in rx_buffer->page to the skb. 1887 */ 1888 static void igc_add_rx_frag(struct igc_ring *rx_ring, 1889 struct igc_rx_buffer *rx_buffer, 1890 struct sk_buff *skb, 1891 unsigned int size) 1892 { 1893 unsigned int truesize; 1894 1895 #if (PAGE_SIZE < 8192) 1896 truesize = igc_rx_pg_size(rx_ring) / 2; 1897 #else 1898 truesize = ring_uses_build_skb(rx_ring) ? 1899 SKB_DATA_ALIGN(IGC_SKB_PAD + size) : 1900 SKB_DATA_ALIGN(size); 1901 #endif 1902 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 1903 rx_buffer->page_offset, size, truesize); 1904 1905 igc_rx_buffer_flip(rx_buffer, truesize); 1906 } 1907 1908 static struct sk_buff *igc_build_skb(struct igc_ring *rx_ring, 1909 struct igc_rx_buffer *rx_buffer, 1910 struct xdp_buff *xdp) 1911 { 1912 unsigned int size = xdp->data_end - xdp->data; 1913 unsigned int truesize = igc_get_rx_frame_truesize(rx_ring, size); 1914 unsigned int metasize = xdp->data - xdp->data_meta; 1915 struct sk_buff *skb; 1916 1917 /* prefetch first cache line of first page */ 1918 net_prefetch(xdp->data_meta); 1919 1920 /* build an skb around the page buffer */ 1921 skb = napi_build_skb(xdp->data_hard_start, truesize); 1922 if (unlikely(!skb)) 1923 return NULL; 1924 1925 /* update pointers within the skb to store the data */ 1926 skb_reserve(skb, xdp->data - xdp->data_hard_start); 1927 __skb_put(skb, size); 1928 if (metasize) 1929 skb_metadata_set(skb, metasize); 1930 1931 igc_rx_buffer_flip(rx_buffer, truesize); 1932 return skb; 1933 } 1934 1935 static struct sk_buff *igc_construct_skb(struct igc_ring *rx_ring, 1936 struct igc_rx_buffer *rx_buffer, 1937 struct xdp_buff *xdp, 1938 ktime_t timestamp) 1939 { 1940 unsigned int metasize = xdp->data - xdp->data_meta; 1941 unsigned int size = xdp->data_end - xdp->data; 1942 unsigned int truesize = igc_get_rx_frame_truesize(rx_ring, size); 1943 void *va = xdp->data; 1944 unsigned int headlen; 1945 struct sk_buff *skb; 1946 1947 /* prefetch first cache line of first page */ 1948 net_prefetch(xdp->data_meta); 1949 1950 /* allocate a skb to store the frags */ 1951 skb = napi_alloc_skb(&rx_ring->q_vector->napi, 1952 IGC_RX_HDR_LEN + metasize); 1953 if (unlikely(!skb)) 1954 return NULL; 1955 1956 if (timestamp) 1957 skb_hwtstamps(skb)->hwtstamp = timestamp; 1958 1959 /* Determine available headroom for copy */ 1960 headlen = size; 1961 if (headlen > IGC_RX_HDR_LEN) 1962 headlen = eth_get_headlen(skb->dev, va, IGC_RX_HDR_LEN); 1963 1964 /* align pull length to size of long to optimize memcpy performance */ 1965 memcpy(__skb_put(skb, headlen + metasize), xdp->data_meta, 1966 ALIGN(headlen + metasize, sizeof(long))); 1967 1968 if (metasize) { 1969 skb_metadata_set(skb, metasize); 1970 __skb_pull(skb, metasize); 1971 } 1972 1973 /* update all of the pointers */ 1974 size -= headlen; 1975 if (size) { 1976 skb_add_rx_frag(skb, 0, rx_buffer->page, 1977 (va + headlen) - page_address(rx_buffer->page), 1978 size, truesize); 1979 igc_rx_buffer_flip(rx_buffer, truesize); 1980 } else { 1981 rx_buffer->pagecnt_bias++; 1982 } 1983 1984 return skb; 1985 } 1986 1987 /** 1988 * igc_reuse_rx_page - page flip buffer and store it back on the ring 1989 * @rx_ring: rx descriptor ring to store buffers on 1990 * @old_buff: donor buffer to have page reused 1991 * 1992 * Synchronizes page for reuse by the adapter 1993 */ 1994 static void igc_reuse_rx_page(struct igc_ring *rx_ring, 1995 struct igc_rx_buffer *old_buff) 1996 { 1997 u16 nta = rx_ring->next_to_alloc; 1998 struct igc_rx_buffer *new_buff; 1999 2000 new_buff = &rx_ring->rx_buffer_info[nta]; 2001 2002 /* update, and store next to alloc */ 2003 nta++; 2004 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 2005 2006 /* Transfer page from old buffer to new buffer. 2007 * Move each member individually to avoid possible store 2008 * forwarding stalls. 2009 */ 2010 new_buff->dma = old_buff->dma; 2011 new_buff->page = old_buff->page; 2012 new_buff->page_offset = old_buff->page_offset; 2013 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 2014 } 2015 2016 static bool igc_can_reuse_rx_page(struct igc_rx_buffer *rx_buffer, 2017 int rx_buffer_pgcnt) 2018 { 2019 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 2020 struct page *page = rx_buffer->page; 2021 2022 /* avoid re-using remote and pfmemalloc pages */ 2023 if (!dev_page_is_reusable(page)) 2024 return false; 2025 2026 #if (PAGE_SIZE < 8192) 2027 /* if we are only owner of page we can reuse it */ 2028 if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1)) 2029 return false; 2030 #else 2031 #define IGC_LAST_OFFSET \ 2032 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGC_RXBUFFER_2048) 2033 2034 if (rx_buffer->page_offset > IGC_LAST_OFFSET) 2035 return false; 2036 #endif 2037 2038 /* If we have drained the page fragment pool we need to update 2039 * the pagecnt_bias and page count so that we fully restock the 2040 * number of references the driver holds. 2041 */ 2042 if (unlikely(pagecnt_bias == 1)) { 2043 page_ref_add(page, USHRT_MAX - 1); 2044 rx_buffer->pagecnt_bias = USHRT_MAX; 2045 } 2046 2047 return true; 2048 } 2049 2050 /** 2051 * igc_is_non_eop - process handling of non-EOP buffers 2052 * @rx_ring: Rx ring being processed 2053 * @rx_desc: Rx descriptor for current buffer 2054 * 2055 * This function updates next to clean. If the buffer is an EOP buffer 2056 * this function exits returning false, otherwise it will place the 2057 * sk_buff in the next buffer to be chained and return true indicating 2058 * that this is in fact a non-EOP buffer. 2059 */ 2060 static bool igc_is_non_eop(struct igc_ring *rx_ring, 2061 union igc_adv_rx_desc *rx_desc) 2062 { 2063 u32 ntc = rx_ring->next_to_clean + 1; 2064 2065 /* fetch, update, and store next to clean */ 2066 ntc = (ntc < rx_ring->count) ? ntc : 0; 2067 rx_ring->next_to_clean = ntc; 2068 2069 prefetch(IGC_RX_DESC(rx_ring, ntc)); 2070 2071 if (likely(igc_test_staterr(rx_desc, IGC_RXD_STAT_EOP))) 2072 return false; 2073 2074 return true; 2075 } 2076 2077 /** 2078 * igc_cleanup_headers - Correct corrupted or empty headers 2079 * @rx_ring: rx descriptor ring packet is being transacted on 2080 * @rx_desc: pointer to the EOP Rx descriptor 2081 * @skb: pointer to current skb being fixed 2082 * 2083 * Address the case where we are pulling data in on pages only 2084 * and as such no data is present in the skb header. 2085 * 2086 * In addition if skb is not at least 60 bytes we need to pad it so that 2087 * it is large enough to qualify as a valid Ethernet frame. 2088 * 2089 * Returns true if an error was encountered and skb was freed. 2090 */ 2091 static bool igc_cleanup_headers(struct igc_ring *rx_ring, 2092 union igc_adv_rx_desc *rx_desc, 2093 struct sk_buff *skb) 2094 { 2095 /* XDP packets use error pointer so abort at this point */ 2096 if (IS_ERR(skb)) 2097 return true; 2098 2099 if (unlikely(igc_test_staterr(rx_desc, IGC_RXDEXT_STATERR_RXE))) { 2100 struct net_device *netdev = rx_ring->netdev; 2101 2102 if (!(netdev->features & NETIF_F_RXALL)) { 2103 dev_kfree_skb_any(skb); 2104 return true; 2105 } 2106 } 2107 2108 /* if eth_skb_pad returns an error the skb was freed */ 2109 if (eth_skb_pad(skb)) 2110 return true; 2111 2112 return false; 2113 } 2114 2115 static void igc_put_rx_buffer(struct igc_ring *rx_ring, 2116 struct igc_rx_buffer *rx_buffer, 2117 int rx_buffer_pgcnt) 2118 { 2119 if (igc_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) { 2120 /* hand second half of page back to the ring */ 2121 igc_reuse_rx_page(rx_ring, rx_buffer); 2122 } else { 2123 /* We are not reusing the buffer so unmap it and free 2124 * any references we are holding to it 2125 */ 2126 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2127 igc_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 2128 IGC_RX_DMA_ATTR); 2129 __page_frag_cache_drain(rx_buffer->page, 2130 rx_buffer->pagecnt_bias); 2131 } 2132 2133 /* clear contents of rx_buffer */ 2134 rx_buffer->page = NULL; 2135 } 2136 2137 static inline unsigned int igc_rx_offset(struct igc_ring *rx_ring) 2138 { 2139 struct igc_adapter *adapter = rx_ring->q_vector->adapter; 2140 2141 if (ring_uses_build_skb(rx_ring)) 2142 return IGC_SKB_PAD; 2143 if (igc_xdp_is_enabled(adapter)) 2144 return XDP_PACKET_HEADROOM; 2145 2146 return 0; 2147 } 2148 2149 static bool igc_alloc_mapped_page(struct igc_ring *rx_ring, 2150 struct igc_rx_buffer *bi) 2151 { 2152 struct page *page = bi->page; 2153 dma_addr_t dma; 2154 2155 /* since we are recycling buffers we should seldom need to alloc */ 2156 if (likely(page)) 2157 return true; 2158 2159 /* alloc new page for storage */ 2160 page = dev_alloc_pages(igc_rx_pg_order(rx_ring)); 2161 if (unlikely(!page)) { 2162 rx_ring->rx_stats.alloc_failed++; 2163 return false; 2164 } 2165 2166 /* map page for use */ 2167 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 2168 igc_rx_pg_size(rx_ring), 2169 DMA_FROM_DEVICE, 2170 IGC_RX_DMA_ATTR); 2171 2172 /* if mapping failed free memory back to system since 2173 * there isn't much point in holding memory we can't use 2174 */ 2175 if (dma_mapping_error(rx_ring->dev, dma)) { 2176 __free_page(page); 2177 2178 rx_ring->rx_stats.alloc_failed++; 2179 return false; 2180 } 2181 2182 bi->dma = dma; 2183 bi->page = page; 2184 bi->page_offset = igc_rx_offset(rx_ring); 2185 page_ref_add(page, USHRT_MAX - 1); 2186 bi->pagecnt_bias = USHRT_MAX; 2187 2188 return true; 2189 } 2190 2191 /** 2192 * igc_alloc_rx_buffers - Replace used receive buffers; packet split 2193 * @rx_ring: rx descriptor ring 2194 * @cleaned_count: number of buffers to clean 2195 */ 2196 static void igc_alloc_rx_buffers(struct igc_ring *rx_ring, u16 cleaned_count) 2197 { 2198 union igc_adv_rx_desc *rx_desc; 2199 u16 i = rx_ring->next_to_use; 2200 struct igc_rx_buffer *bi; 2201 u16 bufsz; 2202 2203 /* nothing to do */ 2204 if (!cleaned_count) 2205 return; 2206 2207 rx_desc = IGC_RX_DESC(rx_ring, i); 2208 bi = &rx_ring->rx_buffer_info[i]; 2209 i -= rx_ring->count; 2210 2211 bufsz = igc_rx_bufsz(rx_ring); 2212 2213 do { 2214 if (!igc_alloc_mapped_page(rx_ring, bi)) 2215 break; 2216 2217 /* sync the buffer for use by the device */ 2218 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 2219 bi->page_offset, bufsz, 2220 DMA_FROM_DEVICE); 2221 2222 /* Refresh the desc even if buffer_addrs didn't change 2223 * because each write-back erases this info. 2224 */ 2225 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 2226 2227 rx_desc++; 2228 bi++; 2229 i++; 2230 if (unlikely(!i)) { 2231 rx_desc = IGC_RX_DESC(rx_ring, 0); 2232 bi = rx_ring->rx_buffer_info; 2233 i -= rx_ring->count; 2234 } 2235 2236 /* clear the length for the next_to_use descriptor */ 2237 rx_desc->wb.upper.length = 0; 2238 2239 cleaned_count--; 2240 } while (cleaned_count); 2241 2242 i += rx_ring->count; 2243 2244 if (rx_ring->next_to_use != i) { 2245 /* record the next descriptor to use */ 2246 rx_ring->next_to_use = i; 2247 2248 /* update next to alloc since we have filled the ring */ 2249 rx_ring->next_to_alloc = i; 2250 2251 /* Force memory writes to complete before letting h/w 2252 * know there are new descriptors to fetch. (Only 2253 * applicable for weak-ordered memory model archs, 2254 * such as IA-64). 2255 */ 2256 wmb(); 2257 writel(i, rx_ring->tail); 2258 } 2259 } 2260 2261 static bool igc_alloc_rx_buffers_zc(struct igc_ring *ring, u16 count) 2262 { 2263 union igc_adv_rx_desc *desc; 2264 u16 i = ring->next_to_use; 2265 struct igc_rx_buffer *bi; 2266 dma_addr_t dma; 2267 bool ok = true; 2268 2269 if (!count) 2270 return ok; 2271 2272 XSK_CHECK_PRIV_TYPE(struct igc_xdp_buff); 2273 2274 desc = IGC_RX_DESC(ring, i); 2275 bi = &ring->rx_buffer_info[i]; 2276 i -= ring->count; 2277 2278 do { 2279 bi->xdp = xsk_buff_alloc(ring->xsk_pool); 2280 if (!bi->xdp) { 2281 ok = false; 2282 break; 2283 } 2284 2285 dma = xsk_buff_xdp_get_dma(bi->xdp); 2286 desc->read.pkt_addr = cpu_to_le64(dma); 2287 2288 desc++; 2289 bi++; 2290 i++; 2291 if (unlikely(!i)) { 2292 desc = IGC_RX_DESC(ring, 0); 2293 bi = ring->rx_buffer_info; 2294 i -= ring->count; 2295 } 2296 2297 /* Clear the length for the next_to_use descriptor. */ 2298 desc->wb.upper.length = 0; 2299 2300 count--; 2301 } while (count); 2302 2303 i += ring->count; 2304 2305 if (ring->next_to_use != i) { 2306 ring->next_to_use = i; 2307 2308 /* Force memory writes to complete before letting h/w 2309 * know there are new descriptors to fetch. (Only 2310 * applicable for weak-ordered memory model archs, 2311 * such as IA-64). 2312 */ 2313 wmb(); 2314 writel(i, ring->tail); 2315 } 2316 2317 return ok; 2318 } 2319 2320 /* This function requires __netif_tx_lock is held by the caller. */ 2321 static int igc_xdp_init_tx_descriptor(struct igc_ring *ring, 2322 struct xdp_frame *xdpf) 2323 { 2324 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 2325 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 2326 u16 count, index = ring->next_to_use; 2327 struct igc_tx_buffer *head = &ring->tx_buffer_info[index]; 2328 struct igc_tx_buffer *buffer = head; 2329 union igc_adv_tx_desc *desc = IGC_TX_DESC(ring, index); 2330 u32 olinfo_status, len = xdpf->len, cmd_type; 2331 void *data = xdpf->data; 2332 u16 i; 2333 2334 count = TXD_USE_COUNT(len); 2335 for (i = 0; i < nr_frags; i++) 2336 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 2337 2338 if (igc_maybe_stop_tx(ring, count + 3)) { 2339 /* this is a hard error */ 2340 return -EBUSY; 2341 } 2342 2343 i = 0; 2344 head->bytecount = xdp_get_frame_len(xdpf); 2345 head->type = IGC_TX_BUFFER_TYPE_XDP; 2346 head->gso_segs = 1; 2347 head->xdpf = xdpf; 2348 2349 olinfo_status = head->bytecount << IGC_ADVTXD_PAYLEN_SHIFT; 2350 desc->read.olinfo_status = cpu_to_le32(olinfo_status); 2351 2352 for (;;) { 2353 dma_addr_t dma; 2354 2355 dma = dma_map_single(ring->dev, data, len, DMA_TO_DEVICE); 2356 if (dma_mapping_error(ring->dev, dma)) { 2357 netdev_err_once(ring->netdev, 2358 "Failed to map DMA for TX\n"); 2359 goto unmap; 2360 } 2361 2362 dma_unmap_len_set(buffer, len, len); 2363 dma_unmap_addr_set(buffer, dma, dma); 2364 2365 cmd_type = IGC_ADVTXD_DTYP_DATA | IGC_ADVTXD_DCMD_DEXT | 2366 IGC_ADVTXD_DCMD_IFCS | len; 2367 2368 desc->read.cmd_type_len = cpu_to_le32(cmd_type); 2369 desc->read.buffer_addr = cpu_to_le64(dma); 2370 2371 buffer->protocol = 0; 2372 2373 if (++index == ring->count) 2374 index = 0; 2375 2376 if (i == nr_frags) 2377 break; 2378 2379 buffer = &ring->tx_buffer_info[index]; 2380 desc = IGC_TX_DESC(ring, index); 2381 desc->read.olinfo_status = 0; 2382 2383 data = skb_frag_address(&sinfo->frags[i]); 2384 len = skb_frag_size(&sinfo->frags[i]); 2385 i++; 2386 } 2387 desc->read.cmd_type_len |= cpu_to_le32(IGC_TXD_DCMD); 2388 2389 netdev_tx_sent_queue(txring_txq(ring), head->bytecount); 2390 /* set the timestamp */ 2391 head->time_stamp = jiffies; 2392 /* set next_to_watch value indicating a packet is present */ 2393 head->next_to_watch = desc; 2394 ring->next_to_use = index; 2395 2396 return 0; 2397 2398 unmap: 2399 for (;;) { 2400 buffer = &ring->tx_buffer_info[index]; 2401 if (dma_unmap_len(buffer, len)) 2402 dma_unmap_page(ring->dev, 2403 dma_unmap_addr(buffer, dma), 2404 dma_unmap_len(buffer, len), 2405 DMA_TO_DEVICE); 2406 dma_unmap_len_set(buffer, len, 0); 2407 if (buffer == head) 2408 break; 2409 2410 if (!index) 2411 index += ring->count; 2412 index--; 2413 } 2414 2415 return -ENOMEM; 2416 } 2417 2418 static struct igc_ring *igc_xdp_get_tx_ring(struct igc_adapter *adapter, 2419 int cpu) 2420 { 2421 int index = cpu; 2422 2423 if (unlikely(index < 0)) 2424 index = 0; 2425 2426 while (index >= adapter->num_tx_queues) 2427 index -= adapter->num_tx_queues; 2428 2429 return adapter->tx_ring[index]; 2430 } 2431 2432 static int igc_xdp_xmit_back(struct igc_adapter *adapter, struct xdp_buff *xdp) 2433 { 2434 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2435 int cpu = smp_processor_id(); 2436 struct netdev_queue *nq; 2437 struct igc_ring *ring; 2438 int res; 2439 2440 if (unlikely(!xdpf)) 2441 return -EFAULT; 2442 2443 ring = igc_xdp_get_tx_ring(adapter, cpu); 2444 nq = txring_txq(ring); 2445 2446 __netif_tx_lock(nq, cpu); 2447 /* Avoid transmit queue timeout since we share it with the slow path */ 2448 txq_trans_cond_update(nq); 2449 res = igc_xdp_init_tx_descriptor(ring, xdpf); 2450 __netif_tx_unlock(nq); 2451 return res; 2452 } 2453 2454 /* This function assumes rcu_read_lock() is held by the caller. */ 2455 static int __igc_xdp_run_prog(struct igc_adapter *adapter, 2456 struct bpf_prog *prog, 2457 struct xdp_buff *xdp) 2458 { 2459 u32 act = bpf_prog_run_xdp(prog, xdp); 2460 2461 switch (act) { 2462 case XDP_PASS: 2463 return IGC_XDP_PASS; 2464 case XDP_TX: 2465 if (igc_xdp_xmit_back(adapter, xdp) < 0) 2466 goto out_failure; 2467 return IGC_XDP_TX; 2468 case XDP_REDIRECT: 2469 if (xdp_do_redirect(adapter->netdev, xdp, prog) < 0) 2470 goto out_failure; 2471 return IGC_XDP_REDIRECT; 2472 break; 2473 default: 2474 bpf_warn_invalid_xdp_action(adapter->netdev, prog, act); 2475 fallthrough; 2476 case XDP_ABORTED: 2477 out_failure: 2478 trace_xdp_exception(adapter->netdev, prog, act); 2479 fallthrough; 2480 case XDP_DROP: 2481 return IGC_XDP_CONSUMED; 2482 } 2483 } 2484 2485 static struct sk_buff *igc_xdp_run_prog(struct igc_adapter *adapter, 2486 struct xdp_buff *xdp) 2487 { 2488 struct bpf_prog *prog; 2489 int res; 2490 2491 prog = READ_ONCE(adapter->xdp_prog); 2492 if (!prog) { 2493 res = IGC_XDP_PASS; 2494 goto out; 2495 } 2496 2497 res = __igc_xdp_run_prog(adapter, prog, xdp); 2498 2499 out: 2500 return ERR_PTR(-res); 2501 } 2502 2503 /* This function assumes __netif_tx_lock is held by the caller. */ 2504 static void igc_flush_tx_descriptors(struct igc_ring *ring) 2505 { 2506 /* Once tail pointer is updated, hardware can fetch the descriptors 2507 * any time so we issue a write membar here to ensure all memory 2508 * writes are complete before the tail pointer is updated. 2509 */ 2510 wmb(); 2511 writel(ring->next_to_use, ring->tail); 2512 } 2513 2514 static void igc_finalize_xdp(struct igc_adapter *adapter, int status) 2515 { 2516 int cpu = smp_processor_id(); 2517 struct netdev_queue *nq; 2518 struct igc_ring *ring; 2519 2520 if (status & IGC_XDP_TX) { 2521 ring = igc_xdp_get_tx_ring(adapter, cpu); 2522 nq = txring_txq(ring); 2523 2524 __netif_tx_lock(nq, cpu); 2525 igc_flush_tx_descriptors(ring); 2526 __netif_tx_unlock(nq); 2527 } 2528 2529 if (status & IGC_XDP_REDIRECT) 2530 xdp_do_flush(); 2531 } 2532 2533 static void igc_update_rx_stats(struct igc_q_vector *q_vector, 2534 unsigned int packets, unsigned int bytes) 2535 { 2536 struct igc_ring *ring = q_vector->rx.ring; 2537 2538 u64_stats_update_begin(&ring->rx_syncp); 2539 ring->rx_stats.packets += packets; 2540 ring->rx_stats.bytes += bytes; 2541 u64_stats_update_end(&ring->rx_syncp); 2542 2543 q_vector->rx.total_packets += packets; 2544 q_vector->rx.total_bytes += bytes; 2545 } 2546 2547 static int igc_clean_rx_irq(struct igc_q_vector *q_vector, const int budget) 2548 { 2549 unsigned int total_bytes = 0, total_packets = 0; 2550 struct igc_adapter *adapter = q_vector->adapter; 2551 struct igc_ring *rx_ring = q_vector->rx.ring; 2552 struct sk_buff *skb = rx_ring->skb; 2553 u16 cleaned_count = igc_desc_unused(rx_ring); 2554 int xdp_status = 0, rx_buffer_pgcnt; 2555 2556 while (likely(total_packets < budget)) { 2557 union igc_adv_rx_desc *rx_desc; 2558 struct igc_rx_buffer *rx_buffer; 2559 unsigned int size, truesize; 2560 struct igc_xdp_buff ctx; 2561 ktime_t timestamp = 0; 2562 int pkt_offset = 0; 2563 void *pktbuf; 2564 2565 /* return some buffers to hardware, one at a time is too slow */ 2566 if (cleaned_count >= IGC_RX_BUFFER_WRITE) { 2567 igc_alloc_rx_buffers(rx_ring, cleaned_count); 2568 cleaned_count = 0; 2569 } 2570 2571 rx_desc = IGC_RX_DESC(rx_ring, rx_ring->next_to_clean); 2572 size = le16_to_cpu(rx_desc->wb.upper.length); 2573 if (!size) 2574 break; 2575 2576 /* This memory barrier is needed to keep us from reading 2577 * any other fields out of the rx_desc until we know the 2578 * descriptor has been written back 2579 */ 2580 dma_rmb(); 2581 2582 rx_buffer = igc_get_rx_buffer(rx_ring, size, &rx_buffer_pgcnt); 2583 truesize = igc_get_rx_frame_truesize(rx_ring, size); 2584 2585 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 2586 2587 if (igc_test_staterr(rx_desc, IGC_RXDADV_STAT_TSIP)) { 2588 timestamp = igc_ptp_rx_pktstamp(q_vector->adapter, 2589 pktbuf); 2590 ctx.rx_ts = timestamp; 2591 pkt_offset = IGC_TS_HDR_LEN; 2592 size -= IGC_TS_HDR_LEN; 2593 } 2594 2595 if (!skb) { 2596 xdp_init_buff(&ctx.xdp, truesize, &rx_ring->xdp_rxq); 2597 xdp_prepare_buff(&ctx.xdp, pktbuf - igc_rx_offset(rx_ring), 2598 igc_rx_offset(rx_ring) + pkt_offset, 2599 size, true); 2600 xdp_buff_clear_frags_flag(&ctx.xdp); 2601 ctx.rx_desc = rx_desc; 2602 2603 skb = igc_xdp_run_prog(adapter, &ctx.xdp); 2604 } 2605 2606 if (IS_ERR(skb)) { 2607 unsigned int xdp_res = -PTR_ERR(skb); 2608 2609 switch (xdp_res) { 2610 case IGC_XDP_CONSUMED: 2611 rx_buffer->pagecnt_bias++; 2612 break; 2613 case IGC_XDP_TX: 2614 case IGC_XDP_REDIRECT: 2615 igc_rx_buffer_flip(rx_buffer, truesize); 2616 xdp_status |= xdp_res; 2617 break; 2618 } 2619 2620 total_packets++; 2621 total_bytes += size; 2622 } else if (skb) 2623 igc_add_rx_frag(rx_ring, rx_buffer, skb, size); 2624 else if (ring_uses_build_skb(rx_ring)) 2625 skb = igc_build_skb(rx_ring, rx_buffer, &ctx.xdp); 2626 else 2627 skb = igc_construct_skb(rx_ring, rx_buffer, &ctx.xdp, 2628 timestamp); 2629 2630 /* exit if we failed to retrieve a buffer */ 2631 if (!skb) { 2632 rx_ring->rx_stats.alloc_failed++; 2633 rx_buffer->pagecnt_bias++; 2634 break; 2635 } 2636 2637 igc_put_rx_buffer(rx_ring, rx_buffer, rx_buffer_pgcnt); 2638 cleaned_count++; 2639 2640 /* fetch next buffer in frame if non-eop */ 2641 if (igc_is_non_eop(rx_ring, rx_desc)) 2642 continue; 2643 2644 /* verify the packet layout is correct */ 2645 if (igc_cleanup_headers(rx_ring, rx_desc, skb)) { 2646 skb = NULL; 2647 continue; 2648 } 2649 2650 /* probably a little skewed due to removing CRC */ 2651 total_bytes += skb->len; 2652 2653 /* populate checksum, VLAN, and protocol */ 2654 igc_process_skb_fields(rx_ring, rx_desc, skb); 2655 2656 napi_gro_receive(&q_vector->napi, skb); 2657 2658 /* reset skb pointer */ 2659 skb = NULL; 2660 2661 /* update budget accounting */ 2662 total_packets++; 2663 } 2664 2665 if (xdp_status) 2666 igc_finalize_xdp(adapter, xdp_status); 2667 2668 /* place incomplete frames back on ring for completion */ 2669 rx_ring->skb = skb; 2670 2671 igc_update_rx_stats(q_vector, total_packets, total_bytes); 2672 2673 if (cleaned_count) 2674 igc_alloc_rx_buffers(rx_ring, cleaned_count); 2675 2676 return total_packets; 2677 } 2678 2679 static struct sk_buff *igc_construct_skb_zc(struct igc_ring *ring, 2680 struct xdp_buff *xdp) 2681 { 2682 unsigned int totalsize = xdp->data_end - xdp->data_meta; 2683 unsigned int metasize = xdp->data - xdp->data_meta; 2684 struct sk_buff *skb; 2685 2686 net_prefetch(xdp->data_meta); 2687 2688 skb = __napi_alloc_skb(&ring->q_vector->napi, totalsize, 2689 GFP_ATOMIC | __GFP_NOWARN); 2690 if (unlikely(!skb)) 2691 return NULL; 2692 2693 memcpy(__skb_put(skb, totalsize), xdp->data_meta, 2694 ALIGN(totalsize, sizeof(long))); 2695 2696 if (metasize) { 2697 skb_metadata_set(skb, metasize); 2698 __skb_pull(skb, metasize); 2699 } 2700 2701 return skb; 2702 } 2703 2704 static void igc_dispatch_skb_zc(struct igc_q_vector *q_vector, 2705 union igc_adv_rx_desc *desc, 2706 struct xdp_buff *xdp, 2707 ktime_t timestamp) 2708 { 2709 struct igc_ring *ring = q_vector->rx.ring; 2710 struct sk_buff *skb; 2711 2712 skb = igc_construct_skb_zc(ring, xdp); 2713 if (!skb) { 2714 ring->rx_stats.alloc_failed++; 2715 return; 2716 } 2717 2718 if (timestamp) 2719 skb_hwtstamps(skb)->hwtstamp = timestamp; 2720 2721 if (igc_cleanup_headers(ring, desc, skb)) 2722 return; 2723 2724 igc_process_skb_fields(ring, desc, skb); 2725 napi_gro_receive(&q_vector->napi, skb); 2726 } 2727 2728 static struct igc_xdp_buff *xsk_buff_to_igc_ctx(struct xdp_buff *xdp) 2729 { 2730 /* xdp_buff pointer used by ZC code path is alloc as xdp_buff_xsk. The 2731 * igc_xdp_buff shares its layout with xdp_buff_xsk and private 2732 * igc_xdp_buff fields fall into xdp_buff_xsk->cb 2733 */ 2734 return (struct igc_xdp_buff *)xdp; 2735 } 2736 2737 static int igc_clean_rx_irq_zc(struct igc_q_vector *q_vector, const int budget) 2738 { 2739 struct igc_adapter *adapter = q_vector->adapter; 2740 struct igc_ring *ring = q_vector->rx.ring; 2741 u16 cleaned_count = igc_desc_unused(ring); 2742 int total_bytes = 0, total_packets = 0; 2743 u16 ntc = ring->next_to_clean; 2744 struct bpf_prog *prog; 2745 bool failure = false; 2746 int xdp_status = 0; 2747 2748 rcu_read_lock(); 2749 2750 prog = READ_ONCE(adapter->xdp_prog); 2751 2752 while (likely(total_packets < budget)) { 2753 union igc_adv_rx_desc *desc; 2754 struct igc_rx_buffer *bi; 2755 struct igc_xdp_buff *ctx; 2756 ktime_t timestamp = 0; 2757 unsigned int size; 2758 int res; 2759 2760 desc = IGC_RX_DESC(ring, ntc); 2761 size = le16_to_cpu(desc->wb.upper.length); 2762 if (!size) 2763 break; 2764 2765 /* This memory barrier is needed to keep us from reading 2766 * any other fields out of the rx_desc until we know the 2767 * descriptor has been written back 2768 */ 2769 dma_rmb(); 2770 2771 bi = &ring->rx_buffer_info[ntc]; 2772 2773 ctx = xsk_buff_to_igc_ctx(bi->xdp); 2774 ctx->rx_desc = desc; 2775 2776 if (igc_test_staterr(desc, IGC_RXDADV_STAT_TSIP)) { 2777 timestamp = igc_ptp_rx_pktstamp(q_vector->adapter, 2778 bi->xdp->data); 2779 ctx->rx_ts = timestamp; 2780 2781 bi->xdp->data += IGC_TS_HDR_LEN; 2782 2783 /* HW timestamp has been copied into local variable. Metadata 2784 * length when XDP program is called should be 0. 2785 */ 2786 bi->xdp->data_meta += IGC_TS_HDR_LEN; 2787 size -= IGC_TS_HDR_LEN; 2788 } 2789 2790 bi->xdp->data_end = bi->xdp->data + size; 2791 xsk_buff_dma_sync_for_cpu(bi->xdp, ring->xsk_pool); 2792 2793 res = __igc_xdp_run_prog(adapter, prog, bi->xdp); 2794 switch (res) { 2795 case IGC_XDP_PASS: 2796 igc_dispatch_skb_zc(q_vector, desc, bi->xdp, timestamp); 2797 fallthrough; 2798 case IGC_XDP_CONSUMED: 2799 xsk_buff_free(bi->xdp); 2800 break; 2801 case IGC_XDP_TX: 2802 case IGC_XDP_REDIRECT: 2803 xdp_status |= res; 2804 break; 2805 } 2806 2807 bi->xdp = NULL; 2808 total_bytes += size; 2809 total_packets++; 2810 cleaned_count++; 2811 ntc++; 2812 if (ntc == ring->count) 2813 ntc = 0; 2814 } 2815 2816 ring->next_to_clean = ntc; 2817 rcu_read_unlock(); 2818 2819 if (cleaned_count >= IGC_RX_BUFFER_WRITE) 2820 failure = !igc_alloc_rx_buffers_zc(ring, cleaned_count); 2821 2822 if (xdp_status) 2823 igc_finalize_xdp(adapter, xdp_status); 2824 2825 igc_update_rx_stats(q_vector, total_packets, total_bytes); 2826 2827 if (xsk_uses_need_wakeup(ring->xsk_pool)) { 2828 if (failure || ring->next_to_clean == ring->next_to_use) 2829 xsk_set_rx_need_wakeup(ring->xsk_pool); 2830 else 2831 xsk_clear_rx_need_wakeup(ring->xsk_pool); 2832 return total_packets; 2833 } 2834 2835 return failure ? budget : total_packets; 2836 } 2837 2838 static void igc_update_tx_stats(struct igc_q_vector *q_vector, 2839 unsigned int packets, unsigned int bytes) 2840 { 2841 struct igc_ring *ring = q_vector->tx.ring; 2842 2843 u64_stats_update_begin(&ring->tx_syncp); 2844 ring->tx_stats.bytes += bytes; 2845 ring->tx_stats.packets += packets; 2846 u64_stats_update_end(&ring->tx_syncp); 2847 2848 q_vector->tx.total_bytes += bytes; 2849 q_vector->tx.total_packets += packets; 2850 } 2851 2852 static void igc_xdp_xmit_zc(struct igc_ring *ring) 2853 { 2854 struct xsk_buff_pool *pool = ring->xsk_pool; 2855 struct netdev_queue *nq = txring_txq(ring); 2856 union igc_adv_tx_desc *tx_desc = NULL; 2857 int cpu = smp_processor_id(); 2858 struct xdp_desc xdp_desc; 2859 u16 budget, ntu; 2860 2861 if (!netif_carrier_ok(ring->netdev)) 2862 return; 2863 2864 __netif_tx_lock(nq, cpu); 2865 2866 /* Avoid transmit queue timeout since we share it with the slow path */ 2867 txq_trans_cond_update(nq); 2868 2869 ntu = ring->next_to_use; 2870 budget = igc_desc_unused(ring); 2871 2872 while (xsk_tx_peek_desc(pool, &xdp_desc) && budget--) { 2873 u32 cmd_type, olinfo_status; 2874 struct igc_tx_buffer *bi; 2875 dma_addr_t dma; 2876 2877 cmd_type = IGC_ADVTXD_DTYP_DATA | IGC_ADVTXD_DCMD_DEXT | 2878 IGC_ADVTXD_DCMD_IFCS | IGC_TXD_DCMD | 2879 xdp_desc.len; 2880 olinfo_status = xdp_desc.len << IGC_ADVTXD_PAYLEN_SHIFT; 2881 2882 dma = xsk_buff_raw_get_dma(pool, xdp_desc.addr); 2883 xsk_buff_raw_dma_sync_for_device(pool, dma, xdp_desc.len); 2884 2885 tx_desc = IGC_TX_DESC(ring, ntu); 2886 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 2887 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 2888 tx_desc->read.buffer_addr = cpu_to_le64(dma); 2889 2890 bi = &ring->tx_buffer_info[ntu]; 2891 bi->type = IGC_TX_BUFFER_TYPE_XSK; 2892 bi->protocol = 0; 2893 bi->bytecount = xdp_desc.len; 2894 bi->gso_segs = 1; 2895 bi->time_stamp = jiffies; 2896 bi->next_to_watch = tx_desc; 2897 2898 netdev_tx_sent_queue(txring_txq(ring), xdp_desc.len); 2899 2900 ntu++; 2901 if (ntu == ring->count) 2902 ntu = 0; 2903 } 2904 2905 ring->next_to_use = ntu; 2906 if (tx_desc) { 2907 igc_flush_tx_descriptors(ring); 2908 xsk_tx_release(pool); 2909 } 2910 2911 __netif_tx_unlock(nq); 2912 } 2913 2914 /** 2915 * igc_clean_tx_irq - Reclaim resources after transmit completes 2916 * @q_vector: pointer to q_vector containing needed info 2917 * @napi_budget: Used to determine if we are in netpoll 2918 * 2919 * returns true if ring is completely cleaned 2920 */ 2921 static bool igc_clean_tx_irq(struct igc_q_vector *q_vector, int napi_budget) 2922 { 2923 struct igc_adapter *adapter = q_vector->adapter; 2924 unsigned int total_bytes = 0, total_packets = 0; 2925 unsigned int budget = q_vector->tx.work_limit; 2926 struct igc_ring *tx_ring = q_vector->tx.ring; 2927 unsigned int i = tx_ring->next_to_clean; 2928 struct igc_tx_buffer *tx_buffer; 2929 union igc_adv_tx_desc *tx_desc; 2930 u32 xsk_frames = 0; 2931 2932 if (test_bit(__IGC_DOWN, &adapter->state)) 2933 return true; 2934 2935 tx_buffer = &tx_ring->tx_buffer_info[i]; 2936 tx_desc = IGC_TX_DESC(tx_ring, i); 2937 i -= tx_ring->count; 2938 2939 do { 2940 union igc_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 2941 2942 /* if next_to_watch is not set then there is no work pending */ 2943 if (!eop_desc) 2944 break; 2945 2946 /* prevent any other reads prior to eop_desc */ 2947 smp_rmb(); 2948 2949 /* if DD is not set pending work has not been completed */ 2950 if (!(eop_desc->wb.status & cpu_to_le32(IGC_TXD_STAT_DD))) 2951 break; 2952 2953 /* clear next_to_watch to prevent false hangs */ 2954 tx_buffer->next_to_watch = NULL; 2955 2956 /* update the statistics for this packet */ 2957 total_bytes += tx_buffer->bytecount; 2958 total_packets += tx_buffer->gso_segs; 2959 2960 switch (tx_buffer->type) { 2961 case IGC_TX_BUFFER_TYPE_XSK: 2962 xsk_frames++; 2963 break; 2964 case IGC_TX_BUFFER_TYPE_XDP: 2965 xdp_return_frame(tx_buffer->xdpf); 2966 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 2967 break; 2968 case IGC_TX_BUFFER_TYPE_SKB: 2969 napi_consume_skb(tx_buffer->skb, napi_budget); 2970 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 2971 break; 2972 default: 2973 netdev_warn_once(tx_ring->netdev, "Unknown Tx buffer type\n"); 2974 break; 2975 } 2976 2977 /* clear last DMA location and unmap remaining buffers */ 2978 while (tx_desc != eop_desc) { 2979 tx_buffer++; 2980 tx_desc++; 2981 i++; 2982 if (unlikely(!i)) { 2983 i -= tx_ring->count; 2984 tx_buffer = tx_ring->tx_buffer_info; 2985 tx_desc = IGC_TX_DESC(tx_ring, 0); 2986 } 2987 2988 /* unmap any remaining paged data */ 2989 if (dma_unmap_len(tx_buffer, len)) 2990 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 2991 } 2992 2993 /* move us one more past the eop_desc for start of next pkt */ 2994 tx_buffer++; 2995 tx_desc++; 2996 i++; 2997 if (unlikely(!i)) { 2998 i -= tx_ring->count; 2999 tx_buffer = tx_ring->tx_buffer_info; 3000 tx_desc = IGC_TX_DESC(tx_ring, 0); 3001 } 3002 3003 /* issue prefetch for next Tx descriptor */ 3004 prefetch(tx_desc); 3005 3006 /* update budget accounting */ 3007 budget--; 3008 } while (likely(budget)); 3009 3010 netdev_tx_completed_queue(txring_txq(tx_ring), 3011 total_packets, total_bytes); 3012 3013 i += tx_ring->count; 3014 tx_ring->next_to_clean = i; 3015 3016 igc_update_tx_stats(q_vector, total_packets, total_bytes); 3017 3018 if (tx_ring->xsk_pool) { 3019 if (xsk_frames) 3020 xsk_tx_completed(tx_ring->xsk_pool, xsk_frames); 3021 if (xsk_uses_need_wakeup(tx_ring->xsk_pool)) 3022 xsk_set_tx_need_wakeup(tx_ring->xsk_pool); 3023 igc_xdp_xmit_zc(tx_ring); 3024 } 3025 3026 if (test_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 3027 struct igc_hw *hw = &adapter->hw; 3028 3029 /* Detect a transmit hang in hardware, this serializes the 3030 * check with the clearing of time_stamp and movement of i 3031 */ 3032 clear_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 3033 if (tx_buffer->next_to_watch && 3034 time_after(jiffies, tx_buffer->time_stamp + 3035 (adapter->tx_timeout_factor * HZ)) && 3036 !(rd32(IGC_STATUS) & IGC_STATUS_TXOFF) && 3037 (rd32(IGC_TDH(tx_ring->reg_idx)) != readl(tx_ring->tail)) && 3038 !tx_ring->oper_gate_closed) { 3039 /* detected Tx unit hang */ 3040 netdev_err(tx_ring->netdev, 3041 "Detected Tx Unit Hang\n" 3042 " Tx Queue <%d>\n" 3043 " TDH <%x>\n" 3044 " TDT <%x>\n" 3045 " next_to_use <%x>\n" 3046 " next_to_clean <%x>\n" 3047 "buffer_info[next_to_clean]\n" 3048 " time_stamp <%lx>\n" 3049 " next_to_watch <%p>\n" 3050 " jiffies <%lx>\n" 3051 " desc.status <%x>\n", 3052 tx_ring->queue_index, 3053 rd32(IGC_TDH(tx_ring->reg_idx)), 3054 readl(tx_ring->tail), 3055 tx_ring->next_to_use, 3056 tx_ring->next_to_clean, 3057 tx_buffer->time_stamp, 3058 tx_buffer->next_to_watch, 3059 jiffies, 3060 tx_buffer->next_to_watch->wb.status); 3061 netif_stop_subqueue(tx_ring->netdev, 3062 tx_ring->queue_index); 3063 3064 /* we are about to reset, no point in enabling stuff */ 3065 return true; 3066 } 3067 } 3068 3069 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 3070 if (unlikely(total_packets && 3071 netif_carrier_ok(tx_ring->netdev) && 3072 igc_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 3073 /* Make sure that anybody stopping the queue after this 3074 * sees the new next_to_clean. 3075 */ 3076 smp_mb(); 3077 if (__netif_subqueue_stopped(tx_ring->netdev, 3078 tx_ring->queue_index) && 3079 !(test_bit(__IGC_DOWN, &adapter->state))) { 3080 netif_wake_subqueue(tx_ring->netdev, 3081 tx_ring->queue_index); 3082 3083 u64_stats_update_begin(&tx_ring->tx_syncp); 3084 tx_ring->tx_stats.restart_queue++; 3085 u64_stats_update_end(&tx_ring->tx_syncp); 3086 } 3087 } 3088 3089 return !!budget; 3090 } 3091 3092 static int igc_find_mac_filter(struct igc_adapter *adapter, 3093 enum igc_mac_filter_type type, const u8 *addr) 3094 { 3095 struct igc_hw *hw = &adapter->hw; 3096 int max_entries = hw->mac.rar_entry_count; 3097 u32 ral, rah; 3098 int i; 3099 3100 for (i = 0; i < max_entries; i++) { 3101 ral = rd32(IGC_RAL(i)); 3102 rah = rd32(IGC_RAH(i)); 3103 3104 if (!(rah & IGC_RAH_AV)) 3105 continue; 3106 if (!!(rah & IGC_RAH_ASEL_SRC_ADDR) != type) 3107 continue; 3108 if ((rah & IGC_RAH_RAH_MASK) != 3109 le16_to_cpup((__le16 *)(addr + 4))) 3110 continue; 3111 if (ral != le32_to_cpup((__le32 *)(addr))) 3112 continue; 3113 3114 return i; 3115 } 3116 3117 return -1; 3118 } 3119 3120 static int igc_get_avail_mac_filter_slot(struct igc_adapter *adapter) 3121 { 3122 struct igc_hw *hw = &adapter->hw; 3123 int max_entries = hw->mac.rar_entry_count; 3124 u32 rah; 3125 int i; 3126 3127 for (i = 0; i < max_entries; i++) { 3128 rah = rd32(IGC_RAH(i)); 3129 3130 if (!(rah & IGC_RAH_AV)) 3131 return i; 3132 } 3133 3134 return -1; 3135 } 3136 3137 /** 3138 * igc_add_mac_filter() - Add MAC address filter 3139 * @adapter: Pointer to adapter where the filter should be added 3140 * @type: MAC address filter type (source or destination) 3141 * @addr: MAC address 3142 * @queue: If non-negative, queue assignment feature is enabled and frames 3143 * matching the filter are enqueued onto 'queue'. Otherwise, queue 3144 * assignment is disabled. 3145 * 3146 * Return: 0 in case of success, negative errno code otherwise. 3147 */ 3148 static int igc_add_mac_filter(struct igc_adapter *adapter, 3149 enum igc_mac_filter_type type, const u8 *addr, 3150 int queue) 3151 { 3152 struct net_device *dev = adapter->netdev; 3153 int index; 3154 3155 index = igc_find_mac_filter(adapter, type, addr); 3156 if (index >= 0) 3157 goto update_filter; 3158 3159 index = igc_get_avail_mac_filter_slot(adapter); 3160 if (index < 0) 3161 return -ENOSPC; 3162 3163 netdev_dbg(dev, "Add MAC address filter: index %d type %s address %pM queue %d\n", 3164 index, type == IGC_MAC_FILTER_TYPE_DST ? "dst" : "src", 3165 addr, queue); 3166 3167 update_filter: 3168 igc_set_mac_filter_hw(adapter, index, type, addr, queue); 3169 return 0; 3170 } 3171 3172 /** 3173 * igc_del_mac_filter() - Delete MAC address filter 3174 * @adapter: Pointer to adapter where the filter should be deleted from 3175 * @type: MAC address filter type (source or destination) 3176 * @addr: MAC address 3177 */ 3178 static void igc_del_mac_filter(struct igc_adapter *adapter, 3179 enum igc_mac_filter_type type, const u8 *addr) 3180 { 3181 struct net_device *dev = adapter->netdev; 3182 int index; 3183 3184 index = igc_find_mac_filter(adapter, type, addr); 3185 if (index < 0) 3186 return; 3187 3188 if (index == 0) { 3189 /* If this is the default filter, we don't actually delete it. 3190 * We just reset to its default value i.e. disable queue 3191 * assignment. 3192 */ 3193 netdev_dbg(dev, "Disable default MAC filter queue assignment"); 3194 3195 igc_set_mac_filter_hw(adapter, 0, type, addr, -1); 3196 } else { 3197 netdev_dbg(dev, "Delete MAC address filter: index %d type %s address %pM\n", 3198 index, 3199 type == IGC_MAC_FILTER_TYPE_DST ? "dst" : "src", 3200 addr); 3201 3202 igc_clear_mac_filter_hw(adapter, index); 3203 } 3204 } 3205 3206 /** 3207 * igc_add_vlan_prio_filter() - Add VLAN priority filter 3208 * @adapter: Pointer to adapter where the filter should be added 3209 * @prio: VLAN priority value 3210 * @queue: Queue number which matching frames are assigned to 3211 * 3212 * Return: 0 in case of success, negative errno code otherwise. 3213 */ 3214 static int igc_add_vlan_prio_filter(struct igc_adapter *adapter, int prio, 3215 int queue) 3216 { 3217 struct net_device *dev = adapter->netdev; 3218 struct igc_hw *hw = &adapter->hw; 3219 u32 vlanpqf; 3220 3221 vlanpqf = rd32(IGC_VLANPQF); 3222 3223 if (vlanpqf & IGC_VLANPQF_VALID(prio)) { 3224 netdev_dbg(dev, "VLAN priority filter already in use\n"); 3225 return -EEXIST; 3226 } 3227 3228 vlanpqf |= IGC_VLANPQF_QSEL(prio, queue); 3229 vlanpqf |= IGC_VLANPQF_VALID(prio); 3230 3231 wr32(IGC_VLANPQF, vlanpqf); 3232 3233 netdev_dbg(dev, "Add VLAN priority filter: prio %d queue %d\n", 3234 prio, queue); 3235 return 0; 3236 } 3237 3238 /** 3239 * igc_del_vlan_prio_filter() - Delete VLAN priority filter 3240 * @adapter: Pointer to adapter where the filter should be deleted from 3241 * @prio: VLAN priority value 3242 */ 3243 static void igc_del_vlan_prio_filter(struct igc_adapter *adapter, int prio) 3244 { 3245 struct igc_hw *hw = &adapter->hw; 3246 u32 vlanpqf; 3247 3248 vlanpqf = rd32(IGC_VLANPQF); 3249 3250 vlanpqf &= ~IGC_VLANPQF_VALID(prio); 3251 vlanpqf &= ~IGC_VLANPQF_QSEL(prio, IGC_VLANPQF_QUEUE_MASK); 3252 3253 wr32(IGC_VLANPQF, vlanpqf); 3254 3255 netdev_dbg(adapter->netdev, "Delete VLAN priority filter: prio %d\n", 3256 prio); 3257 } 3258 3259 static int igc_get_avail_etype_filter_slot(struct igc_adapter *adapter) 3260 { 3261 struct igc_hw *hw = &adapter->hw; 3262 int i; 3263 3264 for (i = 0; i < MAX_ETYPE_FILTER; i++) { 3265 u32 etqf = rd32(IGC_ETQF(i)); 3266 3267 if (!(etqf & IGC_ETQF_FILTER_ENABLE)) 3268 return i; 3269 } 3270 3271 return -1; 3272 } 3273 3274 /** 3275 * igc_add_etype_filter() - Add ethertype filter 3276 * @adapter: Pointer to adapter where the filter should be added 3277 * @etype: Ethertype value 3278 * @queue: If non-negative, queue assignment feature is enabled and frames 3279 * matching the filter are enqueued onto 'queue'. Otherwise, queue 3280 * assignment is disabled. 3281 * 3282 * Return: 0 in case of success, negative errno code otherwise. 3283 */ 3284 static int igc_add_etype_filter(struct igc_adapter *adapter, u16 etype, 3285 int queue) 3286 { 3287 struct igc_hw *hw = &adapter->hw; 3288 int index; 3289 u32 etqf; 3290 3291 index = igc_get_avail_etype_filter_slot(adapter); 3292 if (index < 0) 3293 return -ENOSPC; 3294 3295 etqf = rd32(IGC_ETQF(index)); 3296 3297 etqf &= ~IGC_ETQF_ETYPE_MASK; 3298 etqf |= etype; 3299 3300 if (queue >= 0) { 3301 etqf &= ~IGC_ETQF_QUEUE_MASK; 3302 etqf |= (queue << IGC_ETQF_QUEUE_SHIFT); 3303 etqf |= IGC_ETQF_QUEUE_ENABLE; 3304 } 3305 3306 etqf |= IGC_ETQF_FILTER_ENABLE; 3307 3308 wr32(IGC_ETQF(index), etqf); 3309 3310 netdev_dbg(adapter->netdev, "Add ethertype filter: etype %04x queue %d\n", 3311 etype, queue); 3312 return 0; 3313 } 3314 3315 static int igc_find_etype_filter(struct igc_adapter *adapter, u16 etype) 3316 { 3317 struct igc_hw *hw = &adapter->hw; 3318 int i; 3319 3320 for (i = 0; i < MAX_ETYPE_FILTER; i++) { 3321 u32 etqf = rd32(IGC_ETQF(i)); 3322 3323 if ((etqf & IGC_ETQF_ETYPE_MASK) == etype) 3324 return i; 3325 } 3326 3327 return -1; 3328 } 3329 3330 /** 3331 * igc_del_etype_filter() - Delete ethertype filter 3332 * @adapter: Pointer to adapter where the filter should be deleted from 3333 * @etype: Ethertype value 3334 */ 3335 static void igc_del_etype_filter(struct igc_adapter *adapter, u16 etype) 3336 { 3337 struct igc_hw *hw = &adapter->hw; 3338 int index; 3339 3340 index = igc_find_etype_filter(adapter, etype); 3341 if (index < 0) 3342 return; 3343 3344 wr32(IGC_ETQF(index), 0); 3345 3346 netdev_dbg(adapter->netdev, "Delete ethertype filter: etype %04x\n", 3347 etype); 3348 } 3349 3350 static int igc_flex_filter_select(struct igc_adapter *adapter, 3351 struct igc_flex_filter *input, 3352 u32 *fhft) 3353 { 3354 struct igc_hw *hw = &adapter->hw; 3355 u8 fhft_index; 3356 u32 fhftsl; 3357 3358 if (input->index >= MAX_FLEX_FILTER) { 3359 dev_err(&adapter->pdev->dev, "Wrong Flex Filter index selected!\n"); 3360 return -EINVAL; 3361 } 3362 3363 /* Indirect table select register */ 3364 fhftsl = rd32(IGC_FHFTSL); 3365 fhftsl &= ~IGC_FHFTSL_FTSL_MASK; 3366 switch (input->index) { 3367 case 0 ... 7: 3368 fhftsl |= 0x00; 3369 break; 3370 case 8 ... 15: 3371 fhftsl |= 0x01; 3372 break; 3373 case 16 ... 23: 3374 fhftsl |= 0x02; 3375 break; 3376 case 24 ... 31: 3377 fhftsl |= 0x03; 3378 break; 3379 } 3380 wr32(IGC_FHFTSL, fhftsl); 3381 3382 /* Normalize index down to host table register */ 3383 fhft_index = input->index % 8; 3384 3385 *fhft = (fhft_index < 4) ? IGC_FHFT(fhft_index) : 3386 IGC_FHFT_EXT(fhft_index - 4); 3387 3388 return 0; 3389 } 3390 3391 static int igc_write_flex_filter_ll(struct igc_adapter *adapter, 3392 struct igc_flex_filter *input) 3393 { 3394 struct device *dev = &adapter->pdev->dev; 3395 struct igc_hw *hw = &adapter->hw; 3396 u8 *data = input->data; 3397 u8 *mask = input->mask; 3398 u32 queuing; 3399 u32 fhft; 3400 u32 wufc; 3401 int ret; 3402 int i; 3403 3404 /* Length has to be aligned to 8. Otherwise the filter will fail. Bail 3405 * out early to avoid surprises later. 3406 */ 3407 if (input->length % 8 != 0) { 3408 dev_err(dev, "The length of a flex filter has to be 8 byte aligned!\n"); 3409 return -EINVAL; 3410 } 3411 3412 /* Select corresponding flex filter register and get base for host table. */ 3413 ret = igc_flex_filter_select(adapter, input, &fhft); 3414 if (ret) 3415 return ret; 3416 3417 /* When adding a filter globally disable flex filter feature. That is 3418 * recommended within the datasheet. 3419 */ 3420 wufc = rd32(IGC_WUFC); 3421 wufc &= ~IGC_WUFC_FLEX_HQ; 3422 wr32(IGC_WUFC, wufc); 3423 3424 /* Configure filter */ 3425 queuing = input->length & IGC_FHFT_LENGTH_MASK; 3426 queuing |= (input->rx_queue << IGC_FHFT_QUEUE_SHIFT) & IGC_FHFT_QUEUE_MASK; 3427 queuing |= (input->prio << IGC_FHFT_PRIO_SHIFT) & IGC_FHFT_PRIO_MASK; 3428 3429 if (input->immediate_irq) 3430 queuing |= IGC_FHFT_IMM_INT; 3431 3432 if (input->drop) 3433 queuing |= IGC_FHFT_DROP; 3434 3435 wr32(fhft + 0xFC, queuing); 3436 3437 /* Write data (128 byte) and mask (128 bit) */ 3438 for (i = 0; i < 16; ++i) { 3439 const size_t data_idx = i * 8; 3440 const size_t row_idx = i * 16; 3441 u32 dw0 = 3442 (data[data_idx + 0] << 0) | 3443 (data[data_idx + 1] << 8) | 3444 (data[data_idx + 2] << 16) | 3445 (data[data_idx + 3] << 24); 3446 u32 dw1 = 3447 (data[data_idx + 4] << 0) | 3448 (data[data_idx + 5] << 8) | 3449 (data[data_idx + 6] << 16) | 3450 (data[data_idx + 7] << 24); 3451 u32 tmp; 3452 3453 /* Write row: dw0, dw1 and mask */ 3454 wr32(fhft + row_idx, dw0); 3455 wr32(fhft + row_idx + 4, dw1); 3456 3457 /* mask is only valid for MASK(7, 0) */ 3458 tmp = rd32(fhft + row_idx + 8); 3459 tmp &= ~GENMASK(7, 0); 3460 tmp |= mask[i]; 3461 wr32(fhft + row_idx + 8, tmp); 3462 } 3463 3464 /* Enable filter. */ 3465 wufc |= IGC_WUFC_FLEX_HQ; 3466 if (input->index > 8) { 3467 /* Filter 0-7 are enabled via WUFC. The other 24 filters are not. */ 3468 u32 wufc_ext = rd32(IGC_WUFC_EXT); 3469 3470 wufc_ext |= (IGC_WUFC_EXT_FLX8 << (input->index - 8)); 3471 3472 wr32(IGC_WUFC_EXT, wufc_ext); 3473 } else { 3474 wufc |= (IGC_WUFC_FLX0 << input->index); 3475 } 3476 wr32(IGC_WUFC, wufc); 3477 3478 dev_dbg(&adapter->pdev->dev, "Added flex filter %u to HW.\n", 3479 input->index); 3480 3481 return 0; 3482 } 3483 3484 static void igc_flex_filter_add_field(struct igc_flex_filter *flex, 3485 const void *src, unsigned int offset, 3486 size_t len, const void *mask) 3487 { 3488 int i; 3489 3490 /* data */ 3491 memcpy(&flex->data[offset], src, len); 3492 3493 /* mask */ 3494 for (i = 0; i < len; ++i) { 3495 const unsigned int idx = i + offset; 3496 const u8 *ptr = mask; 3497 3498 if (mask) { 3499 if (ptr[i] & 0xff) 3500 flex->mask[idx / 8] |= BIT(idx % 8); 3501 3502 continue; 3503 } 3504 3505 flex->mask[idx / 8] |= BIT(idx % 8); 3506 } 3507 } 3508 3509 static int igc_find_avail_flex_filter_slot(struct igc_adapter *adapter) 3510 { 3511 struct igc_hw *hw = &adapter->hw; 3512 u32 wufc, wufc_ext; 3513 int i; 3514 3515 wufc = rd32(IGC_WUFC); 3516 wufc_ext = rd32(IGC_WUFC_EXT); 3517 3518 for (i = 0; i < MAX_FLEX_FILTER; i++) { 3519 if (i < 8) { 3520 if (!(wufc & (IGC_WUFC_FLX0 << i))) 3521 return i; 3522 } else { 3523 if (!(wufc_ext & (IGC_WUFC_EXT_FLX8 << (i - 8)))) 3524 return i; 3525 } 3526 } 3527 3528 return -ENOSPC; 3529 } 3530 3531 static bool igc_flex_filter_in_use(struct igc_adapter *adapter) 3532 { 3533 struct igc_hw *hw = &adapter->hw; 3534 u32 wufc, wufc_ext; 3535 3536 wufc = rd32(IGC_WUFC); 3537 wufc_ext = rd32(IGC_WUFC_EXT); 3538 3539 if (wufc & IGC_WUFC_FILTER_MASK) 3540 return true; 3541 3542 if (wufc_ext & IGC_WUFC_EXT_FILTER_MASK) 3543 return true; 3544 3545 return false; 3546 } 3547 3548 static int igc_add_flex_filter(struct igc_adapter *adapter, 3549 struct igc_nfc_rule *rule) 3550 { 3551 struct igc_flex_filter flex = { }; 3552 struct igc_nfc_filter *filter = &rule->filter; 3553 unsigned int eth_offset, user_offset; 3554 int ret, index; 3555 bool vlan; 3556 3557 index = igc_find_avail_flex_filter_slot(adapter); 3558 if (index < 0) 3559 return -ENOSPC; 3560 3561 /* Construct the flex filter: 3562 * -> dest_mac [6] 3563 * -> src_mac [6] 3564 * -> tpid [2] 3565 * -> vlan tci [2] 3566 * -> ether type [2] 3567 * -> user data [8] 3568 * -> = 26 bytes => 32 length 3569 */ 3570 flex.index = index; 3571 flex.length = 32; 3572 flex.rx_queue = rule->action; 3573 3574 vlan = rule->filter.vlan_tci || rule->filter.vlan_etype; 3575 eth_offset = vlan ? 16 : 12; 3576 user_offset = vlan ? 18 : 14; 3577 3578 /* Add destination MAC */ 3579 if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR) 3580 igc_flex_filter_add_field(&flex, &filter->dst_addr, 0, 3581 ETH_ALEN, NULL); 3582 3583 /* Add source MAC */ 3584 if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR) 3585 igc_flex_filter_add_field(&flex, &filter->src_addr, 6, 3586 ETH_ALEN, NULL); 3587 3588 /* Add VLAN etype */ 3589 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_ETYPE) 3590 igc_flex_filter_add_field(&flex, &filter->vlan_etype, 12, 3591 sizeof(filter->vlan_etype), 3592 NULL); 3593 3594 /* Add VLAN TCI */ 3595 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) 3596 igc_flex_filter_add_field(&flex, &filter->vlan_tci, 14, 3597 sizeof(filter->vlan_tci), NULL); 3598 3599 /* Add Ether type */ 3600 if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) { 3601 __be16 etype = cpu_to_be16(filter->etype); 3602 3603 igc_flex_filter_add_field(&flex, &etype, eth_offset, 3604 sizeof(etype), NULL); 3605 } 3606 3607 /* Add user data */ 3608 if (rule->filter.match_flags & IGC_FILTER_FLAG_USER_DATA) 3609 igc_flex_filter_add_field(&flex, &filter->user_data, 3610 user_offset, 3611 sizeof(filter->user_data), 3612 filter->user_mask); 3613 3614 /* Add it down to the hardware and enable it. */ 3615 ret = igc_write_flex_filter_ll(adapter, &flex); 3616 if (ret) 3617 return ret; 3618 3619 filter->flex_index = index; 3620 3621 return 0; 3622 } 3623 3624 static void igc_del_flex_filter(struct igc_adapter *adapter, 3625 u16 reg_index) 3626 { 3627 struct igc_hw *hw = &adapter->hw; 3628 u32 wufc; 3629 3630 /* Just disable the filter. The filter table itself is kept 3631 * intact. Another flex_filter_add() should override the "old" data 3632 * then. 3633 */ 3634 if (reg_index > 8) { 3635 u32 wufc_ext = rd32(IGC_WUFC_EXT); 3636 3637 wufc_ext &= ~(IGC_WUFC_EXT_FLX8 << (reg_index - 8)); 3638 wr32(IGC_WUFC_EXT, wufc_ext); 3639 } else { 3640 wufc = rd32(IGC_WUFC); 3641 3642 wufc &= ~(IGC_WUFC_FLX0 << reg_index); 3643 wr32(IGC_WUFC, wufc); 3644 } 3645 3646 if (igc_flex_filter_in_use(adapter)) 3647 return; 3648 3649 /* No filters are in use, we may disable flex filters */ 3650 wufc = rd32(IGC_WUFC); 3651 wufc &= ~IGC_WUFC_FLEX_HQ; 3652 wr32(IGC_WUFC, wufc); 3653 } 3654 3655 static int igc_enable_nfc_rule(struct igc_adapter *adapter, 3656 struct igc_nfc_rule *rule) 3657 { 3658 int err; 3659 3660 if (rule->flex) { 3661 return igc_add_flex_filter(adapter, rule); 3662 } 3663 3664 if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) { 3665 err = igc_add_etype_filter(adapter, rule->filter.etype, 3666 rule->action); 3667 if (err) 3668 return err; 3669 } 3670 3671 if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR) { 3672 err = igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_SRC, 3673 rule->filter.src_addr, rule->action); 3674 if (err) 3675 return err; 3676 } 3677 3678 if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR) { 3679 err = igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, 3680 rule->filter.dst_addr, rule->action); 3681 if (err) 3682 return err; 3683 } 3684 3685 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) { 3686 int prio = (rule->filter.vlan_tci & VLAN_PRIO_MASK) >> 3687 VLAN_PRIO_SHIFT; 3688 3689 err = igc_add_vlan_prio_filter(adapter, prio, rule->action); 3690 if (err) 3691 return err; 3692 } 3693 3694 return 0; 3695 } 3696 3697 static void igc_disable_nfc_rule(struct igc_adapter *adapter, 3698 const struct igc_nfc_rule *rule) 3699 { 3700 if (rule->flex) { 3701 igc_del_flex_filter(adapter, rule->filter.flex_index); 3702 return; 3703 } 3704 3705 if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) 3706 igc_del_etype_filter(adapter, rule->filter.etype); 3707 3708 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) { 3709 int prio = (rule->filter.vlan_tci & VLAN_PRIO_MASK) >> 3710 VLAN_PRIO_SHIFT; 3711 3712 igc_del_vlan_prio_filter(adapter, prio); 3713 } 3714 3715 if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR) 3716 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_SRC, 3717 rule->filter.src_addr); 3718 3719 if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR) 3720 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, 3721 rule->filter.dst_addr); 3722 } 3723 3724 /** 3725 * igc_get_nfc_rule() - Get NFC rule 3726 * @adapter: Pointer to adapter 3727 * @location: Rule location 3728 * 3729 * Context: Expects adapter->nfc_rule_lock to be held by caller. 3730 * 3731 * Return: Pointer to NFC rule at @location. If not found, NULL. 3732 */ 3733 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter, 3734 u32 location) 3735 { 3736 struct igc_nfc_rule *rule; 3737 3738 list_for_each_entry(rule, &adapter->nfc_rule_list, list) { 3739 if (rule->location == location) 3740 return rule; 3741 if (rule->location > location) 3742 break; 3743 } 3744 3745 return NULL; 3746 } 3747 3748 /** 3749 * igc_del_nfc_rule() - Delete NFC rule 3750 * @adapter: Pointer to adapter 3751 * @rule: Pointer to rule to be deleted 3752 * 3753 * Disable NFC rule in hardware and delete it from adapter. 3754 * 3755 * Context: Expects adapter->nfc_rule_lock to be held by caller. 3756 */ 3757 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule) 3758 { 3759 igc_disable_nfc_rule(adapter, rule); 3760 3761 list_del(&rule->list); 3762 adapter->nfc_rule_count--; 3763 3764 kfree(rule); 3765 } 3766 3767 static void igc_flush_nfc_rules(struct igc_adapter *adapter) 3768 { 3769 struct igc_nfc_rule *rule, *tmp; 3770 3771 mutex_lock(&adapter->nfc_rule_lock); 3772 3773 list_for_each_entry_safe(rule, tmp, &adapter->nfc_rule_list, list) 3774 igc_del_nfc_rule(adapter, rule); 3775 3776 mutex_unlock(&adapter->nfc_rule_lock); 3777 } 3778 3779 /** 3780 * igc_add_nfc_rule() - Add NFC rule 3781 * @adapter: Pointer to adapter 3782 * @rule: Pointer to rule to be added 3783 * 3784 * Enable NFC rule in hardware and add it to adapter. 3785 * 3786 * Context: Expects adapter->nfc_rule_lock to be held by caller. 3787 * 3788 * Return: 0 on success, negative errno on failure. 3789 */ 3790 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule) 3791 { 3792 struct igc_nfc_rule *pred, *cur; 3793 int err; 3794 3795 err = igc_enable_nfc_rule(adapter, rule); 3796 if (err) 3797 return err; 3798 3799 pred = NULL; 3800 list_for_each_entry(cur, &adapter->nfc_rule_list, list) { 3801 if (cur->location >= rule->location) 3802 break; 3803 pred = cur; 3804 } 3805 3806 list_add(&rule->list, pred ? &pred->list : &adapter->nfc_rule_list); 3807 adapter->nfc_rule_count++; 3808 return 0; 3809 } 3810 3811 static void igc_restore_nfc_rules(struct igc_adapter *adapter) 3812 { 3813 struct igc_nfc_rule *rule; 3814 3815 mutex_lock(&adapter->nfc_rule_lock); 3816 3817 list_for_each_entry_reverse(rule, &adapter->nfc_rule_list, list) 3818 igc_enable_nfc_rule(adapter, rule); 3819 3820 mutex_unlock(&adapter->nfc_rule_lock); 3821 } 3822 3823 static int igc_uc_sync(struct net_device *netdev, const unsigned char *addr) 3824 { 3825 struct igc_adapter *adapter = netdev_priv(netdev); 3826 3827 return igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, addr, -1); 3828 } 3829 3830 static int igc_uc_unsync(struct net_device *netdev, const unsigned char *addr) 3831 { 3832 struct igc_adapter *adapter = netdev_priv(netdev); 3833 3834 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, addr); 3835 return 0; 3836 } 3837 3838 /** 3839 * igc_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 3840 * @netdev: network interface device structure 3841 * 3842 * The set_rx_mode entry point is called whenever the unicast or multicast 3843 * address lists or the network interface flags are updated. This routine is 3844 * responsible for configuring the hardware for proper unicast, multicast, 3845 * promiscuous mode, and all-multi behavior. 3846 */ 3847 static void igc_set_rx_mode(struct net_device *netdev) 3848 { 3849 struct igc_adapter *adapter = netdev_priv(netdev); 3850 struct igc_hw *hw = &adapter->hw; 3851 u32 rctl = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 3852 int count; 3853 3854 /* Check for Promiscuous and All Multicast modes */ 3855 if (netdev->flags & IFF_PROMISC) { 3856 rctl |= IGC_RCTL_UPE | IGC_RCTL_MPE; 3857 } else { 3858 if (netdev->flags & IFF_ALLMULTI) { 3859 rctl |= IGC_RCTL_MPE; 3860 } else { 3861 /* Write addresses to the MTA, if the attempt fails 3862 * then we should just turn on promiscuous mode so 3863 * that we can at least receive multicast traffic 3864 */ 3865 count = igc_write_mc_addr_list(netdev); 3866 if (count < 0) 3867 rctl |= IGC_RCTL_MPE; 3868 } 3869 } 3870 3871 /* Write addresses to available RAR registers, if there is not 3872 * sufficient space to store all the addresses then enable 3873 * unicast promiscuous mode 3874 */ 3875 if (__dev_uc_sync(netdev, igc_uc_sync, igc_uc_unsync)) 3876 rctl |= IGC_RCTL_UPE; 3877 3878 /* update state of unicast and multicast */ 3879 rctl |= rd32(IGC_RCTL) & ~(IGC_RCTL_UPE | IGC_RCTL_MPE); 3880 wr32(IGC_RCTL, rctl); 3881 3882 #if (PAGE_SIZE < 8192) 3883 if (adapter->max_frame_size <= IGC_MAX_FRAME_BUILD_SKB) 3884 rlpml = IGC_MAX_FRAME_BUILD_SKB; 3885 #endif 3886 wr32(IGC_RLPML, rlpml); 3887 } 3888 3889 /** 3890 * igc_configure - configure the hardware for RX and TX 3891 * @adapter: private board structure 3892 */ 3893 static void igc_configure(struct igc_adapter *adapter) 3894 { 3895 struct net_device *netdev = adapter->netdev; 3896 int i = 0; 3897 3898 igc_get_hw_control(adapter); 3899 igc_set_rx_mode(netdev); 3900 3901 igc_restore_vlan(adapter); 3902 3903 igc_setup_tctl(adapter); 3904 igc_setup_mrqc(adapter); 3905 igc_setup_rctl(adapter); 3906 3907 igc_set_default_mac_filter(adapter); 3908 igc_restore_nfc_rules(adapter); 3909 3910 igc_configure_tx(adapter); 3911 igc_configure_rx(adapter); 3912 3913 igc_rx_fifo_flush_base(&adapter->hw); 3914 3915 /* call igc_desc_unused which always leaves 3916 * at least 1 descriptor unused to make sure 3917 * next_to_use != next_to_clean 3918 */ 3919 for (i = 0; i < adapter->num_rx_queues; i++) { 3920 struct igc_ring *ring = adapter->rx_ring[i]; 3921 3922 if (ring->xsk_pool) 3923 igc_alloc_rx_buffers_zc(ring, igc_desc_unused(ring)); 3924 else 3925 igc_alloc_rx_buffers(ring, igc_desc_unused(ring)); 3926 } 3927 } 3928 3929 /** 3930 * igc_write_ivar - configure ivar for given MSI-X vector 3931 * @hw: pointer to the HW structure 3932 * @msix_vector: vector number we are allocating to a given ring 3933 * @index: row index of IVAR register to write within IVAR table 3934 * @offset: column offset of in IVAR, should be multiple of 8 3935 * 3936 * The IVAR table consists of 2 columns, 3937 * each containing an cause allocation for an Rx and Tx ring, and a 3938 * variable number of rows depending on the number of queues supported. 3939 */ 3940 static void igc_write_ivar(struct igc_hw *hw, int msix_vector, 3941 int index, int offset) 3942 { 3943 u32 ivar = array_rd32(IGC_IVAR0, index); 3944 3945 /* clear any bits that are currently set */ 3946 ivar &= ~((u32)0xFF << offset); 3947 3948 /* write vector and valid bit */ 3949 ivar |= (msix_vector | IGC_IVAR_VALID) << offset; 3950 3951 array_wr32(IGC_IVAR0, index, ivar); 3952 } 3953 3954 static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector) 3955 { 3956 struct igc_adapter *adapter = q_vector->adapter; 3957 struct igc_hw *hw = &adapter->hw; 3958 int rx_queue = IGC_N0_QUEUE; 3959 int tx_queue = IGC_N0_QUEUE; 3960 3961 if (q_vector->rx.ring) 3962 rx_queue = q_vector->rx.ring->reg_idx; 3963 if (q_vector->tx.ring) 3964 tx_queue = q_vector->tx.ring->reg_idx; 3965 3966 switch (hw->mac.type) { 3967 case igc_i225: 3968 if (rx_queue > IGC_N0_QUEUE) 3969 igc_write_ivar(hw, msix_vector, 3970 rx_queue >> 1, 3971 (rx_queue & 0x1) << 4); 3972 if (tx_queue > IGC_N0_QUEUE) 3973 igc_write_ivar(hw, msix_vector, 3974 tx_queue >> 1, 3975 ((tx_queue & 0x1) << 4) + 8); 3976 q_vector->eims_value = BIT(msix_vector); 3977 break; 3978 default: 3979 WARN_ONCE(hw->mac.type != igc_i225, "Wrong MAC type\n"); 3980 break; 3981 } 3982 3983 /* add q_vector eims value to global eims_enable_mask */ 3984 adapter->eims_enable_mask |= q_vector->eims_value; 3985 3986 /* configure q_vector to set itr on first interrupt */ 3987 q_vector->set_itr = 1; 3988 } 3989 3990 /** 3991 * igc_configure_msix - Configure MSI-X hardware 3992 * @adapter: Pointer to adapter structure 3993 * 3994 * igc_configure_msix sets up the hardware to properly 3995 * generate MSI-X interrupts. 3996 */ 3997 static void igc_configure_msix(struct igc_adapter *adapter) 3998 { 3999 struct igc_hw *hw = &adapter->hw; 4000 int i, vector = 0; 4001 u32 tmp; 4002 4003 adapter->eims_enable_mask = 0; 4004 4005 /* set vector for other causes, i.e. link changes */ 4006 switch (hw->mac.type) { 4007 case igc_i225: 4008 /* Turn on MSI-X capability first, or our settings 4009 * won't stick. And it will take days to debug. 4010 */ 4011 wr32(IGC_GPIE, IGC_GPIE_MSIX_MODE | 4012 IGC_GPIE_PBA | IGC_GPIE_EIAME | 4013 IGC_GPIE_NSICR); 4014 4015 /* enable msix_other interrupt */ 4016 adapter->eims_other = BIT(vector); 4017 tmp = (vector++ | IGC_IVAR_VALID) << 8; 4018 4019 wr32(IGC_IVAR_MISC, tmp); 4020 break; 4021 default: 4022 /* do nothing, since nothing else supports MSI-X */ 4023 break; 4024 } /* switch (hw->mac.type) */ 4025 4026 adapter->eims_enable_mask |= adapter->eims_other; 4027 4028 for (i = 0; i < adapter->num_q_vectors; i++) 4029 igc_assign_vector(adapter->q_vector[i], vector++); 4030 4031 wrfl(); 4032 } 4033 4034 /** 4035 * igc_irq_enable - Enable default interrupt generation settings 4036 * @adapter: board private structure 4037 */ 4038 static void igc_irq_enable(struct igc_adapter *adapter) 4039 { 4040 struct igc_hw *hw = &adapter->hw; 4041 4042 if (adapter->msix_entries) { 4043 u32 ims = IGC_IMS_LSC | IGC_IMS_DOUTSYNC | IGC_IMS_DRSTA; 4044 u32 regval = rd32(IGC_EIAC); 4045 4046 wr32(IGC_EIAC, regval | adapter->eims_enable_mask); 4047 regval = rd32(IGC_EIAM); 4048 wr32(IGC_EIAM, regval | adapter->eims_enable_mask); 4049 wr32(IGC_EIMS, adapter->eims_enable_mask); 4050 wr32(IGC_IMS, ims); 4051 } else { 4052 wr32(IGC_IMS, IMS_ENABLE_MASK | IGC_IMS_DRSTA); 4053 wr32(IGC_IAM, IMS_ENABLE_MASK | IGC_IMS_DRSTA); 4054 } 4055 } 4056 4057 /** 4058 * igc_irq_disable - Mask off interrupt generation on the NIC 4059 * @adapter: board private structure 4060 */ 4061 static void igc_irq_disable(struct igc_adapter *adapter) 4062 { 4063 struct igc_hw *hw = &adapter->hw; 4064 4065 if (adapter->msix_entries) { 4066 u32 regval = rd32(IGC_EIAM); 4067 4068 wr32(IGC_EIAM, regval & ~adapter->eims_enable_mask); 4069 wr32(IGC_EIMC, adapter->eims_enable_mask); 4070 regval = rd32(IGC_EIAC); 4071 wr32(IGC_EIAC, regval & ~adapter->eims_enable_mask); 4072 } 4073 4074 wr32(IGC_IAM, 0); 4075 wr32(IGC_IMC, ~0); 4076 wrfl(); 4077 4078 if (adapter->msix_entries) { 4079 int vector = 0, i; 4080 4081 synchronize_irq(adapter->msix_entries[vector++].vector); 4082 4083 for (i = 0; i < adapter->num_q_vectors; i++) 4084 synchronize_irq(adapter->msix_entries[vector++].vector); 4085 } else { 4086 synchronize_irq(adapter->pdev->irq); 4087 } 4088 } 4089 4090 void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 4091 const u32 max_rss_queues) 4092 { 4093 /* Determine if we need to pair queues. */ 4094 /* If rss_queues > half of max_rss_queues, pair the queues in 4095 * order to conserve interrupts due to limited supply. 4096 */ 4097 if (adapter->rss_queues > (max_rss_queues / 2)) 4098 adapter->flags |= IGC_FLAG_QUEUE_PAIRS; 4099 else 4100 adapter->flags &= ~IGC_FLAG_QUEUE_PAIRS; 4101 } 4102 4103 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter) 4104 { 4105 return IGC_MAX_RX_QUEUES; 4106 } 4107 4108 static void igc_init_queue_configuration(struct igc_adapter *adapter) 4109 { 4110 u32 max_rss_queues; 4111 4112 max_rss_queues = igc_get_max_rss_queues(adapter); 4113 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 4114 4115 igc_set_flag_queue_pairs(adapter, max_rss_queues); 4116 } 4117 4118 /** 4119 * igc_reset_q_vector - Reset config for interrupt vector 4120 * @adapter: board private structure to initialize 4121 * @v_idx: Index of vector to be reset 4122 * 4123 * If NAPI is enabled it will delete any references to the 4124 * NAPI struct. This is preparation for igc_free_q_vector. 4125 */ 4126 static void igc_reset_q_vector(struct igc_adapter *adapter, int v_idx) 4127 { 4128 struct igc_q_vector *q_vector = adapter->q_vector[v_idx]; 4129 4130 /* if we're coming from igc_set_interrupt_capability, the vectors are 4131 * not yet allocated 4132 */ 4133 if (!q_vector) 4134 return; 4135 4136 if (q_vector->tx.ring) 4137 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 4138 4139 if (q_vector->rx.ring) 4140 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 4141 4142 netif_napi_del(&q_vector->napi); 4143 } 4144 4145 /** 4146 * igc_free_q_vector - Free memory allocated for specific interrupt vector 4147 * @adapter: board private structure to initialize 4148 * @v_idx: Index of vector to be freed 4149 * 4150 * This function frees the memory allocated to the q_vector. 4151 */ 4152 static void igc_free_q_vector(struct igc_adapter *adapter, int v_idx) 4153 { 4154 struct igc_q_vector *q_vector = adapter->q_vector[v_idx]; 4155 4156 adapter->q_vector[v_idx] = NULL; 4157 4158 /* igc_get_stats64() might access the rings on this vector, 4159 * we must wait a grace period before freeing it. 4160 */ 4161 if (q_vector) 4162 kfree_rcu(q_vector, rcu); 4163 } 4164 4165 /** 4166 * igc_free_q_vectors - Free memory allocated for interrupt vectors 4167 * @adapter: board private structure to initialize 4168 * 4169 * This function frees the memory allocated to the q_vectors. In addition if 4170 * NAPI is enabled it will delete any references to the NAPI struct prior 4171 * to freeing the q_vector. 4172 */ 4173 static void igc_free_q_vectors(struct igc_adapter *adapter) 4174 { 4175 int v_idx = adapter->num_q_vectors; 4176 4177 adapter->num_tx_queues = 0; 4178 adapter->num_rx_queues = 0; 4179 adapter->num_q_vectors = 0; 4180 4181 while (v_idx--) { 4182 igc_reset_q_vector(adapter, v_idx); 4183 igc_free_q_vector(adapter, v_idx); 4184 } 4185 } 4186 4187 /** 4188 * igc_update_itr - update the dynamic ITR value based on statistics 4189 * @q_vector: pointer to q_vector 4190 * @ring_container: ring info to update the itr for 4191 * 4192 * Stores a new ITR value based on packets and byte 4193 * counts during the last interrupt. The advantage of per interrupt 4194 * computation is faster updates and more accurate ITR for the current 4195 * traffic pattern. Constants in this function were computed 4196 * based on theoretical maximum wire speed and thresholds were set based 4197 * on testing data as well as attempting to minimize response time 4198 * while increasing bulk throughput. 4199 * NOTE: These calculations are only valid when operating in a single- 4200 * queue environment. 4201 */ 4202 static void igc_update_itr(struct igc_q_vector *q_vector, 4203 struct igc_ring_container *ring_container) 4204 { 4205 unsigned int packets = ring_container->total_packets; 4206 unsigned int bytes = ring_container->total_bytes; 4207 u8 itrval = ring_container->itr; 4208 4209 /* no packets, exit with status unchanged */ 4210 if (packets == 0) 4211 return; 4212 4213 switch (itrval) { 4214 case lowest_latency: 4215 /* handle TSO and jumbo frames */ 4216 if (bytes / packets > 8000) 4217 itrval = bulk_latency; 4218 else if ((packets < 5) && (bytes > 512)) 4219 itrval = low_latency; 4220 break; 4221 case low_latency: /* 50 usec aka 20000 ints/s */ 4222 if (bytes > 10000) { 4223 /* this if handles the TSO accounting */ 4224 if (bytes / packets > 8000) 4225 itrval = bulk_latency; 4226 else if ((packets < 10) || ((bytes / packets) > 1200)) 4227 itrval = bulk_latency; 4228 else if ((packets > 35)) 4229 itrval = lowest_latency; 4230 } else if (bytes / packets > 2000) { 4231 itrval = bulk_latency; 4232 } else if (packets <= 2 && bytes < 512) { 4233 itrval = lowest_latency; 4234 } 4235 break; 4236 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4237 if (bytes > 25000) { 4238 if (packets > 35) 4239 itrval = low_latency; 4240 } else if (bytes < 1500) { 4241 itrval = low_latency; 4242 } 4243 break; 4244 } 4245 4246 /* clear work counters since we have the values we need */ 4247 ring_container->total_bytes = 0; 4248 ring_container->total_packets = 0; 4249 4250 /* write updated itr to ring container */ 4251 ring_container->itr = itrval; 4252 } 4253 4254 static void igc_set_itr(struct igc_q_vector *q_vector) 4255 { 4256 struct igc_adapter *adapter = q_vector->adapter; 4257 u32 new_itr = q_vector->itr_val; 4258 u8 current_itr = 0; 4259 4260 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4261 switch (adapter->link_speed) { 4262 case SPEED_10: 4263 case SPEED_100: 4264 current_itr = 0; 4265 new_itr = IGC_4K_ITR; 4266 goto set_itr_now; 4267 default: 4268 break; 4269 } 4270 4271 igc_update_itr(q_vector, &q_vector->tx); 4272 igc_update_itr(q_vector, &q_vector->rx); 4273 4274 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4275 4276 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4277 if (current_itr == lowest_latency && 4278 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4279 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4280 current_itr = low_latency; 4281 4282 switch (current_itr) { 4283 /* counts and packets in update_itr are dependent on these numbers */ 4284 case lowest_latency: 4285 new_itr = IGC_70K_ITR; /* 70,000 ints/sec */ 4286 break; 4287 case low_latency: 4288 new_itr = IGC_20K_ITR; /* 20,000 ints/sec */ 4289 break; 4290 case bulk_latency: 4291 new_itr = IGC_4K_ITR; /* 4,000 ints/sec */ 4292 break; 4293 default: 4294 break; 4295 } 4296 4297 set_itr_now: 4298 if (new_itr != q_vector->itr_val) { 4299 /* this attempts to bias the interrupt rate towards Bulk 4300 * by adding intermediate steps when interrupt rate is 4301 * increasing 4302 */ 4303 new_itr = new_itr > q_vector->itr_val ? 4304 max((new_itr * q_vector->itr_val) / 4305 (new_itr + (q_vector->itr_val >> 2)), 4306 new_itr) : new_itr; 4307 /* Don't write the value here; it resets the adapter's 4308 * internal timer, and causes us to delay far longer than 4309 * we should between interrupts. Instead, we write the ITR 4310 * value at the beginning of the next interrupt so the timing 4311 * ends up being correct. 4312 */ 4313 q_vector->itr_val = new_itr; 4314 q_vector->set_itr = 1; 4315 } 4316 } 4317 4318 static void igc_reset_interrupt_capability(struct igc_adapter *adapter) 4319 { 4320 int v_idx = adapter->num_q_vectors; 4321 4322 if (adapter->msix_entries) { 4323 pci_disable_msix(adapter->pdev); 4324 kfree(adapter->msix_entries); 4325 adapter->msix_entries = NULL; 4326 } else if (adapter->flags & IGC_FLAG_HAS_MSI) { 4327 pci_disable_msi(adapter->pdev); 4328 } 4329 4330 while (v_idx--) 4331 igc_reset_q_vector(adapter, v_idx); 4332 } 4333 4334 /** 4335 * igc_set_interrupt_capability - set MSI or MSI-X if supported 4336 * @adapter: Pointer to adapter structure 4337 * @msix: boolean value for MSI-X capability 4338 * 4339 * Attempt to configure interrupts using the best available 4340 * capabilities of the hardware and kernel. 4341 */ 4342 static void igc_set_interrupt_capability(struct igc_adapter *adapter, 4343 bool msix) 4344 { 4345 int numvecs, i; 4346 int err; 4347 4348 if (!msix) 4349 goto msi_only; 4350 adapter->flags |= IGC_FLAG_HAS_MSIX; 4351 4352 /* Number of supported queues. */ 4353 adapter->num_rx_queues = adapter->rss_queues; 4354 4355 adapter->num_tx_queues = adapter->rss_queues; 4356 4357 /* start with one vector for every Rx queue */ 4358 numvecs = adapter->num_rx_queues; 4359 4360 /* if Tx handler is separate add 1 for every Tx queue */ 4361 if (!(adapter->flags & IGC_FLAG_QUEUE_PAIRS)) 4362 numvecs += adapter->num_tx_queues; 4363 4364 /* store the number of vectors reserved for queues */ 4365 adapter->num_q_vectors = numvecs; 4366 4367 /* add 1 vector for link status interrupts */ 4368 numvecs++; 4369 4370 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), 4371 GFP_KERNEL); 4372 4373 if (!adapter->msix_entries) 4374 return; 4375 4376 /* populate entry values */ 4377 for (i = 0; i < numvecs; i++) 4378 adapter->msix_entries[i].entry = i; 4379 4380 err = pci_enable_msix_range(adapter->pdev, 4381 adapter->msix_entries, 4382 numvecs, 4383 numvecs); 4384 if (err > 0) 4385 return; 4386 4387 kfree(adapter->msix_entries); 4388 adapter->msix_entries = NULL; 4389 4390 igc_reset_interrupt_capability(adapter); 4391 4392 msi_only: 4393 adapter->flags &= ~IGC_FLAG_HAS_MSIX; 4394 4395 adapter->rss_queues = 1; 4396 adapter->flags |= IGC_FLAG_QUEUE_PAIRS; 4397 adapter->num_rx_queues = 1; 4398 adapter->num_tx_queues = 1; 4399 adapter->num_q_vectors = 1; 4400 if (!pci_enable_msi(adapter->pdev)) 4401 adapter->flags |= IGC_FLAG_HAS_MSI; 4402 } 4403 4404 /** 4405 * igc_update_ring_itr - update the dynamic ITR value based on packet size 4406 * @q_vector: pointer to q_vector 4407 * 4408 * Stores a new ITR value based on strictly on packet size. This 4409 * algorithm is less sophisticated than that used in igc_update_itr, 4410 * due to the difficulty of synchronizing statistics across multiple 4411 * receive rings. The divisors and thresholds used by this function 4412 * were determined based on theoretical maximum wire speed and testing 4413 * data, in order to minimize response time while increasing bulk 4414 * throughput. 4415 * NOTE: This function is called only when operating in a multiqueue 4416 * receive environment. 4417 */ 4418 static void igc_update_ring_itr(struct igc_q_vector *q_vector) 4419 { 4420 struct igc_adapter *adapter = q_vector->adapter; 4421 int new_val = q_vector->itr_val; 4422 int avg_wire_size = 0; 4423 unsigned int packets; 4424 4425 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4426 * ints/sec - ITR timer value of 120 ticks. 4427 */ 4428 switch (adapter->link_speed) { 4429 case SPEED_10: 4430 case SPEED_100: 4431 new_val = IGC_4K_ITR; 4432 goto set_itr_val; 4433 default: 4434 break; 4435 } 4436 4437 packets = q_vector->rx.total_packets; 4438 if (packets) 4439 avg_wire_size = q_vector->rx.total_bytes / packets; 4440 4441 packets = q_vector->tx.total_packets; 4442 if (packets) 4443 avg_wire_size = max_t(u32, avg_wire_size, 4444 q_vector->tx.total_bytes / packets); 4445 4446 /* if avg_wire_size isn't set no work was done */ 4447 if (!avg_wire_size) 4448 goto clear_counts; 4449 4450 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4451 avg_wire_size += 24; 4452 4453 /* Don't starve jumbo frames */ 4454 avg_wire_size = min(avg_wire_size, 3000); 4455 4456 /* Give a little boost to mid-size frames */ 4457 if (avg_wire_size > 300 && avg_wire_size < 1200) 4458 new_val = avg_wire_size / 3; 4459 else 4460 new_val = avg_wire_size / 2; 4461 4462 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4463 if (new_val < IGC_20K_ITR && 4464 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4465 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4466 new_val = IGC_20K_ITR; 4467 4468 set_itr_val: 4469 if (new_val != q_vector->itr_val) { 4470 q_vector->itr_val = new_val; 4471 q_vector->set_itr = 1; 4472 } 4473 clear_counts: 4474 q_vector->rx.total_bytes = 0; 4475 q_vector->rx.total_packets = 0; 4476 q_vector->tx.total_bytes = 0; 4477 q_vector->tx.total_packets = 0; 4478 } 4479 4480 static void igc_ring_irq_enable(struct igc_q_vector *q_vector) 4481 { 4482 struct igc_adapter *adapter = q_vector->adapter; 4483 struct igc_hw *hw = &adapter->hw; 4484 4485 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 4486 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 4487 if (adapter->num_q_vectors == 1) 4488 igc_set_itr(q_vector); 4489 else 4490 igc_update_ring_itr(q_vector); 4491 } 4492 4493 if (!test_bit(__IGC_DOWN, &adapter->state)) { 4494 if (adapter->msix_entries) 4495 wr32(IGC_EIMS, q_vector->eims_value); 4496 else 4497 igc_irq_enable(adapter); 4498 } 4499 } 4500 4501 static void igc_add_ring(struct igc_ring *ring, 4502 struct igc_ring_container *head) 4503 { 4504 head->ring = ring; 4505 head->count++; 4506 } 4507 4508 /** 4509 * igc_cache_ring_register - Descriptor ring to register mapping 4510 * @adapter: board private structure to initialize 4511 * 4512 * Once we know the feature-set enabled for the device, we'll cache 4513 * the register offset the descriptor ring is assigned to. 4514 */ 4515 static void igc_cache_ring_register(struct igc_adapter *adapter) 4516 { 4517 int i = 0, j = 0; 4518 4519 switch (adapter->hw.mac.type) { 4520 case igc_i225: 4521 default: 4522 for (; i < adapter->num_rx_queues; i++) 4523 adapter->rx_ring[i]->reg_idx = i; 4524 for (; j < adapter->num_tx_queues; j++) 4525 adapter->tx_ring[j]->reg_idx = j; 4526 break; 4527 } 4528 } 4529 4530 /** 4531 * igc_poll - NAPI Rx polling callback 4532 * @napi: napi polling structure 4533 * @budget: count of how many packets we should handle 4534 */ 4535 static int igc_poll(struct napi_struct *napi, int budget) 4536 { 4537 struct igc_q_vector *q_vector = container_of(napi, 4538 struct igc_q_vector, 4539 napi); 4540 struct igc_ring *rx_ring = q_vector->rx.ring; 4541 bool clean_complete = true; 4542 int work_done = 0; 4543 4544 if (q_vector->tx.ring) 4545 clean_complete = igc_clean_tx_irq(q_vector, budget); 4546 4547 if (rx_ring) { 4548 int cleaned = rx_ring->xsk_pool ? 4549 igc_clean_rx_irq_zc(q_vector, budget) : 4550 igc_clean_rx_irq(q_vector, budget); 4551 4552 work_done += cleaned; 4553 if (cleaned >= budget) 4554 clean_complete = false; 4555 } 4556 4557 /* If all work not completed, return budget and keep polling */ 4558 if (!clean_complete) 4559 return budget; 4560 4561 /* Exit the polling mode, but don't re-enable interrupts if stack might 4562 * poll us due to busy-polling 4563 */ 4564 if (likely(napi_complete_done(napi, work_done))) 4565 igc_ring_irq_enable(q_vector); 4566 4567 return min(work_done, budget - 1); 4568 } 4569 4570 /** 4571 * igc_alloc_q_vector - Allocate memory for a single interrupt vector 4572 * @adapter: board private structure to initialize 4573 * @v_count: q_vectors allocated on adapter, used for ring interleaving 4574 * @v_idx: index of vector in adapter struct 4575 * @txr_count: total number of Tx rings to allocate 4576 * @txr_idx: index of first Tx ring to allocate 4577 * @rxr_count: total number of Rx rings to allocate 4578 * @rxr_idx: index of first Rx ring to allocate 4579 * 4580 * We allocate one q_vector. If allocation fails we return -ENOMEM. 4581 */ 4582 static int igc_alloc_q_vector(struct igc_adapter *adapter, 4583 unsigned int v_count, unsigned int v_idx, 4584 unsigned int txr_count, unsigned int txr_idx, 4585 unsigned int rxr_count, unsigned int rxr_idx) 4586 { 4587 struct igc_q_vector *q_vector; 4588 struct igc_ring *ring; 4589 int ring_count; 4590 4591 /* igc only supports 1 Tx and/or 1 Rx queue per vector */ 4592 if (txr_count > 1 || rxr_count > 1) 4593 return -ENOMEM; 4594 4595 ring_count = txr_count + rxr_count; 4596 4597 /* allocate q_vector and rings */ 4598 q_vector = adapter->q_vector[v_idx]; 4599 if (!q_vector) 4600 q_vector = kzalloc(struct_size(q_vector, ring, ring_count), 4601 GFP_KERNEL); 4602 else 4603 memset(q_vector, 0, struct_size(q_vector, ring, ring_count)); 4604 if (!q_vector) 4605 return -ENOMEM; 4606 4607 /* initialize NAPI */ 4608 netif_napi_add(adapter->netdev, &q_vector->napi, igc_poll); 4609 4610 /* tie q_vector and adapter together */ 4611 adapter->q_vector[v_idx] = q_vector; 4612 q_vector->adapter = adapter; 4613 4614 /* initialize work limits */ 4615 q_vector->tx.work_limit = adapter->tx_work_limit; 4616 4617 /* initialize ITR configuration */ 4618 q_vector->itr_register = adapter->io_addr + IGC_EITR(0); 4619 q_vector->itr_val = IGC_START_ITR; 4620 4621 /* initialize pointer to rings */ 4622 ring = q_vector->ring; 4623 4624 /* initialize ITR */ 4625 if (rxr_count) { 4626 /* rx or rx/tx vector */ 4627 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 4628 q_vector->itr_val = adapter->rx_itr_setting; 4629 } else { 4630 /* tx only vector */ 4631 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 4632 q_vector->itr_val = adapter->tx_itr_setting; 4633 } 4634 4635 if (txr_count) { 4636 /* assign generic ring traits */ 4637 ring->dev = &adapter->pdev->dev; 4638 ring->netdev = adapter->netdev; 4639 4640 /* configure backlink on ring */ 4641 ring->q_vector = q_vector; 4642 4643 /* update q_vector Tx values */ 4644 igc_add_ring(ring, &q_vector->tx); 4645 4646 /* apply Tx specific ring traits */ 4647 ring->count = adapter->tx_ring_count; 4648 ring->queue_index = txr_idx; 4649 4650 /* assign ring to adapter */ 4651 adapter->tx_ring[txr_idx] = ring; 4652 4653 /* push pointer to next ring */ 4654 ring++; 4655 } 4656 4657 if (rxr_count) { 4658 /* assign generic ring traits */ 4659 ring->dev = &adapter->pdev->dev; 4660 ring->netdev = adapter->netdev; 4661 4662 /* configure backlink on ring */ 4663 ring->q_vector = q_vector; 4664 4665 /* update q_vector Rx values */ 4666 igc_add_ring(ring, &q_vector->rx); 4667 4668 /* apply Rx specific ring traits */ 4669 ring->count = adapter->rx_ring_count; 4670 ring->queue_index = rxr_idx; 4671 4672 /* assign ring to adapter */ 4673 adapter->rx_ring[rxr_idx] = ring; 4674 } 4675 4676 return 0; 4677 } 4678 4679 /** 4680 * igc_alloc_q_vectors - Allocate memory for interrupt vectors 4681 * @adapter: board private structure to initialize 4682 * 4683 * We allocate one q_vector per queue interrupt. If allocation fails we 4684 * return -ENOMEM. 4685 */ 4686 static int igc_alloc_q_vectors(struct igc_adapter *adapter) 4687 { 4688 int rxr_remaining = adapter->num_rx_queues; 4689 int txr_remaining = adapter->num_tx_queues; 4690 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 4691 int q_vectors = adapter->num_q_vectors; 4692 int err; 4693 4694 if (q_vectors >= (rxr_remaining + txr_remaining)) { 4695 for (; rxr_remaining; v_idx++) { 4696 err = igc_alloc_q_vector(adapter, q_vectors, v_idx, 4697 0, 0, 1, rxr_idx); 4698 4699 if (err) 4700 goto err_out; 4701 4702 /* update counts and index */ 4703 rxr_remaining--; 4704 rxr_idx++; 4705 } 4706 } 4707 4708 for (; v_idx < q_vectors; v_idx++) { 4709 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 4710 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 4711 4712 err = igc_alloc_q_vector(adapter, q_vectors, v_idx, 4713 tqpv, txr_idx, rqpv, rxr_idx); 4714 4715 if (err) 4716 goto err_out; 4717 4718 /* update counts and index */ 4719 rxr_remaining -= rqpv; 4720 txr_remaining -= tqpv; 4721 rxr_idx++; 4722 txr_idx++; 4723 } 4724 4725 return 0; 4726 4727 err_out: 4728 adapter->num_tx_queues = 0; 4729 adapter->num_rx_queues = 0; 4730 adapter->num_q_vectors = 0; 4731 4732 while (v_idx--) 4733 igc_free_q_vector(adapter, v_idx); 4734 4735 return -ENOMEM; 4736 } 4737 4738 /** 4739 * igc_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 4740 * @adapter: Pointer to adapter structure 4741 * @msix: boolean for MSI-X capability 4742 * 4743 * This function initializes the interrupts and allocates all of the queues. 4744 */ 4745 static int igc_init_interrupt_scheme(struct igc_adapter *adapter, bool msix) 4746 { 4747 struct net_device *dev = adapter->netdev; 4748 int err = 0; 4749 4750 igc_set_interrupt_capability(adapter, msix); 4751 4752 err = igc_alloc_q_vectors(adapter); 4753 if (err) { 4754 netdev_err(dev, "Unable to allocate memory for vectors\n"); 4755 goto err_alloc_q_vectors; 4756 } 4757 4758 igc_cache_ring_register(adapter); 4759 4760 return 0; 4761 4762 err_alloc_q_vectors: 4763 igc_reset_interrupt_capability(adapter); 4764 return err; 4765 } 4766 4767 /** 4768 * igc_sw_init - Initialize general software structures (struct igc_adapter) 4769 * @adapter: board private structure to initialize 4770 * 4771 * igc_sw_init initializes the Adapter private data structure. 4772 * Fields are initialized based on PCI device information and 4773 * OS network device settings (MTU size). 4774 */ 4775 static int igc_sw_init(struct igc_adapter *adapter) 4776 { 4777 struct net_device *netdev = adapter->netdev; 4778 struct pci_dev *pdev = adapter->pdev; 4779 struct igc_hw *hw = &adapter->hw; 4780 4781 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 4782 4783 /* set default ring sizes */ 4784 adapter->tx_ring_count = IGC_DEFAULT_TXD; 4785 adapter->rx_ring_count = IGC_DEFAULT_RXD; 4786 4787 /* set default ITR values */ 4788 adapter->rx_itr_setting = IGC_DEFAULT_ITR; 4789 adapter->tx_itr_setting = IGC_DEFAULT_ITR; 4790 4791 /* set default work limits */ 4792 adapter->tx_work_limit = IGC_DEFAULT_TX_WORK; 4793 4794 /* adjust max frame to be at least the size of a standard frame */ 4795 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 4796 VLAN_HLEN; 4797 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4798 4799 mutex_init(&adapter->nfc_rule_lock); 4800 INIT_LIST_HEAD(&adapter->nfc_rule_list); 4801 adapter->nfc_rule_count = 0; 4802 4803 spin_lock_init(&adapter->stats64_lock); 4804 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4805 adapter->flags |= IGC_FLAG_HAS_MSIX; 4806 4807 igc_init_queue_configuration(adapter); 4808 4809 /* This call may decrease the number of queues */ 4810 if (igc_init_interrupt_scheme(adapter, true)) { 4811 netdev_err(netdev, "Unable to allocate memory for queues\n"); 4812 return -ENOMEM; 4813 } 4814 4815 /* Explicitly disable IRQ since the NIC can be in any state. */ 4816 igc_irq_disable(adapter); 4817 4818 set_bit(__IGC_DOWN, &adapter->state); 4819 4820 return 0; 4821 } 4822 4823 /** 4824 * igc_up - Open the interface and prepare it to handle traffic 4825 * @adapter: board private structure 4826 */ 4827 void igc_up(struct igc_adapter *adapter) 4828 { 4829 struct igc_hw *hw = &adapter->hw; 4830 int i = 0; 4831 4832 /* hardware has been reset, we need to reload some things */ 4833 igc_configure(adapter); 4834 4835 clear_bit(__IGC_DOWN, &adapter->state); 4836 4837 for (i = 0; i < adapter->num_q_vectors; i++) 4838 napi_enable(&adapter->q_vector[i]->napi); 4839 4840 if (adapter->msix_entries) 4841 igc_configure_msix(adapter); 4842 else 4843 igc_assign_vector(adapter->q_vector[0], 0); 4844 4845 /* Clear any pending interrupts. */ 4846 rd32(IGC_ICR); 4847 igc_irq_enable(adapter); 4848 4849 netif_tx_start_all_queues(adapter->netdev); 4850 4851 /* start the watchdog. */ 4852 hw->mac.get_link_status = true; 4853 schedule_work(&adapter->watchdog_task); 4854 } 4855 4856 /** 4857 * igc_update_stats - Update the board statistics counters 4858 * @adapter: board private structure 4859 */ 4860 void igc_update_stats(struct igc_adapter *adapter) 4861 { 4862 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 4863 struct pci_dev *pdev = adapter->pdev; 4864 struct igc_hw *hw = &adapter->hw; 4865 u64 _bytes, _packets; 4866 u64 bytes, packets; 4867 unsigned int start; 4868 u32 mpc; 4869 int i; 4870 4871 /* Prevent stats update while adapter is being reset, or if the pci 4872 * connection is down. 4873 */ 4874 if (adapter->link_speed == 0) 4875 return; 4876 if (pci_channel_offline(pdev)) 4877 return; 4878 4879 packets = 0; 4880 bytes = 0; 4881 4882 rcu_read_lock(); 4883 for (i = 0; i < adapter->num_rx_queues; i++) { 4884 struct igc_ring *ring = adapter->rx_ring[i]; 4885 u32 rqdpc = rd32(IGC_RQDPC(i)); 4886 4887 if (hw->mac.type >= igc_i225) 4888 wr32(IGC_RQDPC(i), 0); 4889 4890 if (rqdpc) { 4891 ring->rx_stats.drops += rqdpc; 4892 net_stats->rx_fifo_errors += rqdpc; 4893 } 4894 4895 do { 4896 start = u64_stats_fetch_begin(&ring->rx_syncp); 4897 _bytes = ring->rx_stats.bytes; 4898 _packets = ring->rx_stats.packets; 4899 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 4900 bytes += _bytes; 4901 packets += _packets; 4902 } 4903 4904 net_stats->rx_bytes = bytes; 4905 net_stats->rx_packets = packets; 4906 4907 packets = 0; 4908 bytes = 0; 4909 for (i = 0; i < adapter->num_tx_queues; i++) { 4910 struct igc_ring *ring = adapter->tx_ring[i]; 4911 4912 do { 4913 start = u64_stats_fetch_begin(&ring->tx_syncp); 4914 _bytes = ring->tx_stats.bytes; 4915 _packets = ring->tx_stats.packets; 4916 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 4917 bytes += _bytes; 4918 packets += _packets; 4919 } 4920 net_stats->tx_bytes = bytes; 4921 net_stats->tx_packets = packets; 4922 rcu_read_unlock(); 4923 4924 /* read stats registers */ 4925 adapter->stats.crcerrs += rd32(IGC_CRCERRS); 4926 adapter->stats.gprc += rd32(IGC_GPRC); 4927 adapter->stats.gorc += rd32(IGC_GORCL); 4928 rd32(IGC_GORCH); /* clear GORCL */ 4929 adapter->stats.bprc += rd32(IGC_BPRC); 4930 adapter->stats.mprc += rd32(IGC_MPRC); 4931 adapter->stats.roc += rd32(IGC_ROC); 4932 4933 adapter->stats.prc64 += rd32(IGC_PRC64); 4934 adapter->stats.prc127 += rd32(IGC_PRC127); 4935 adapter->stats.prc255 += rd32(IGC_PRC255); 4936 adapter->stats.prc511 += rd32(IGC_PRC511); 4937 adapter->stats.prc1023 += rd32(IGC_PRC1023); 4938 adapter->stats.prc1522 += rd32(IGC_PRC1522); 4939 adapter->stats.tlpic += rd32(IGC_TLPIC); 4940 adapter->stats.rlpic += rd32(IGC_RLPIC); 4941 adapter->stats.hgptc += rd32(IGC_HGPTC); 4942 4943 mpc = rd32(IGC_MPC); 4944 adapter->stats.mpc += mpc; 4945 net_stats->rx_fifo_errors += mpc; 4946 adapter->stats.scc += rd32(IGC_SCC); 4947 adapter->stats.ecol += rd32(IGC_ECOL); 4948 adapter->stats.mcc += rd32(IGC_MCC); 4949 adapter->stats.latecol += rd32(IGC_LATECOL); 4950 adapter->stats.dc += rd32(IGC_DC); 4951 adapter->stats.rlec += rd32(IGC_RLEC); 4952 adapter->stats.xonrxc += rd32(IGC_XONRXC); 4953 adapter->stats.xontxc += rd32(IGC_XONTXC); 4954 adapter->stats.xoffrxc += rd32(IGC_XOFFRXC); 4955 adapter->stats.xofftxc += rd32(IGC_XOFFTXC); 4956 adapter->stats.fcruc += rd32(IGC_FCRUC); 4957 adapter->stats.gptc += rd32(IGC_GPTC); 4958 adapter->stats.gotc += rd32(IGC_GOTCL); 4959 rd32(IGC_GOTCH); /* clear GOTCL */ 4960 adapter->stats.rnbc += rd32(IGC_RNBC); 4961 adapter->stats.ruc += rd32(IGC_RUC); 4962 adapter->stats.rfc += rd32(IGC_RFC); 4963 adapter->stats.rjc += rd32(IGC_RJC); 4964 adapter->stats.tor += rd32(IGC_TORH); 4965 adapter->stats.tot += rd32(IGC_TOTH); 4966 adapter->stats.tpr += rd32(IGC_TPR); 4967 4968 adapter->stats.ptc64 += rd32(IGC_PTC64); 4969 adapter->stats.ptc127 += rd32(IGC_PTC127); 4970 adapter->stats.ptc255 += rd32(IGC_PTC255); 4971 adapter->stats.ptc511 += rd32(IGC_PTC511); 4972 adapter->stats.ptc1023 += rd32(IGC_PTC1023); 4973 adapter->stats.ptc1522 += rd32(IGC_PTC1522); 4974 4975 adapter->stats.mptc += rd32(IGC_MPTC); 4976 adapter->stats.bptc += rd32(IGC_BPTC); 4977 4978 adapter->stats.tpt += rd32(IGC_TPT); 4979 adapter->stats.colc += rd32(IGC_COLC); 4980 adapter->stats.colc += rd32(IGC_RERC); 4981 4982 adapter->stats.algnerrc += rd32(IGC_ALGNERRC); 4983 4984 adapter->stats.tsctc += rd32(IGC_TSCTC); 4985 4986 adapter->stats.iac += rd32(IGC_IAC); 4987 4988 /* Fill out the OS statistics structure */ 4989 net_stats->multicast = adapter->stats.mprc; 4990 net_stats->collisions = adapter->stats.colc; 4991 4992 /* Rx Errors */ 4993 4994 /* RLEC on some newer hardware can be incorrect so build 4995 * our own version based on RUC and ROC 4996 */ 4997 net_stats->rx_errors = adapter->stats.rxerrc + 4998 adapter->stats.crcerrs + adapter->stats.algnerrc + 4999 adapter->stats.ruc + adapter->stats.roc + 5000 adapter->stats.cexterr; 5001 net_stats->rx_length_errors = adapter->stats.ruc + 5002 adapter->stats.roc; 5003 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5004 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5005 net_stats->rx_missed_errors = adapter->stats.mpc; 5006 5007 /* Tx Errors */ 5008 net_stats->tx_errors = adapter->stats.ecol + 5009 adapter->stats.latecol; 5010 net_stats->tx_aborted_errors = adapter->stats.ecol; 5011 net_stats->tx_window_errors = adapter->stats.latecol; 5012 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5013 5014 /* Tx Dropped */ 5015 net_stats->tx_dropped = adapter->stats.txdrop; 5016 5017 /* Management Stats */ 5018 adapter->stats.mgptc += rd32(IGC_MGTPTC); 5019 adapter->stats.mgprc += rd32(IGC_MGTPRC); 5020 adapter->stats.mgpdc += rd32(IGC_MGTPDC); 5021 } 5022 5023 /** 5024 * igc_down - Close the interface 5025 * @adapter: board private structure 5026 */ 5027 void igc_down(struct igc_adapter *adapter) 5028 { 5029 struct net_device *netdev = adapter->netdev; 5030 struct igc_hw *hw = &adapter->hw; 5031 u32 tctl, rctl; 5032 int i = 0; 5033 5034 set_bit(__IGC_DOWN, &adapter->state); 5035 5036 igc_ptp_suspend(adapter); 5037 5038 if (pci_device_is_present(adapter->pdev)) { 5039 /* disable receives in the hardware */ 5040 rctl = rd32(IGC_RCTL); 5041 wr32(IGC_RCTL, rctl & ~IGC_RCTL_EN); 5042 /* flush and sleep below */ 5043 } 5044 /* set trans_start so we don't get spurious watchdogs during reset */ 5045 netif_trans_update(netdev); 5046 5047 netif_carrier_off(netdev); 5048 netif_tx_stop_all_queues(netdev); 5049 5050 if (pci_device_is_present(adapter->pdev)) { 5051 /* disable transmits in the hardware */ 5052 tctl = rd32(IGC_TCTL); 5053 tctl &= ~IGC_TCTL_EN; 5054 wr32(IGC_TCTL, tctl); 5055 /* flush both disables and wait for them to finish */ 5056 wrfl(); 5057 usleep_range(10000, 20000); 5058 5059 igc_irq_disable(adapter); 5060 } 5061 5062 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE; 5063 5064 for (i = 0; i < adapter->num_q_vectors; i++) { 5065 if (adapter->q_vector[i]) { 5066 napi_synchronize(&adapter->q_vector[i]->napi); 5067 napi_disable(&adapter->q_vector[i]->napi); 5068 } 5069 } 5070 5071 del_timer_sync(&adapter->watchdog_timer); 5072 del_timer_sync(&adapter->phy_info_timer); 5073 5074 /* record the stats before reset*/ 5075 spin_lock(&adapter->stats64_lock); 5076 igc_update_stats(adapter); 5077 spin_unlock(&adapter->stats64_lock); 5078 5079 adapter->link_speed = 0; 5080 adapter->link_duplex = 0; 5081 5082 if (!pci_channel_offline(adapter->pdev)) 5083 igc_reset(adapter); 5084 5085 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 5086 adapter->flags &= ~IGC_FLAG_VLAN_PROMISC; 5087 5088 igc_disable_all_tx_rings_hw(adapter); 5089 igc_clean_all_tx_rings(adapter); 5090 igc_clean_all_rx_rings(adapter); 5091 } 5092 5093 void igc_reinit_locked(struct igc_adapter *adapter) 5094 { 5095 while (test_and_set_bit(__IGC_RESETTING, &adapter->state)) 5096 usleep_range(1000, 2000); 5097 igc_down(adapter); 5098 igc_up(adapter); 5099 clear_bit(__IGC_RESETTING, &adapter->state); 5100 } 5101 5102 static void igc_reset_task(struct work_struct *work) 5103 { 5104 struct igc_adapter *adapter; 5105 5106 adapter = container_of(work, struct igc_adapter, reset_task); 5107 5108 rtnl_lock(); 5109 /* If we're already down or resetting, just bail */ 5110 if (test_bit(__IGC_DOWN, &adapter->state) || 5111 test_bit(__IGC_RESETTING, &adapter->state)) { 5112 rtnl_unlock(); 5113 return; 5114 } 5115 5116 igc_rings_dump(adapter); 5117 igc_regs_dump(adapter); 5118 netdev_err(adapter->netdev, "Reset adapter\n"); 5119 igc_reinit_locked(adapter); 5120 rtnl_unlock(); 5121 } 5122 5123 /** 5124 * igc_change_mtu - Change the Maximum Transfer Unit 5125 * @netdev: network interface device structure 5126 * @new_mtu: new value for maximum frame size 5127 * 5128 * Returns 0 on success, negative on failure 5129 */ 5130 static int igc_change_mtu(struct net_device *netdev, int new_mtu) 5131 { 5132 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5133 struct igc_adapter *adapter = netdev_priv(netdev); 5134 5135 if (igc_xdp_is_enabled(adapter) && new_mtu > ETH_DATA_LEN) { 5136 netdev_dbg(netdev, "Jumbo frames not supported with XDP"); 5137 return -EINVAL; 5138 } 5139 5140 /* adjust max frame to be at least the size of a standard frame */ 5141 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5142 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5143 5144 while (test_and_set_bit(__IGC_RESETTING, &adapter->state)) 5145 usleep_range(1000, 2000); 5146 5147 /* igc_down has a dependency on max_frame_size */ 5148 adapter->max_frame_size = max_frame; 5149 5150 if (netif_running(netdev)) 5151 igc_down(adapter); 5152 5153 netdev_dbg(netdev, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 5154 netdev->mtu = new_mtu; 5155 5156 if (netif_running(netdev)) 5157 igc_up(adapter); 5158 else 5159 igc_reset(adapter); 5160 5161 clear_bit(__IGC_RESETTING, &adapter->state); 5162 5163 return 0; 5164 } 5165 5166 /** 5167 * igc_tx_timeout - Respond to a Tx Hang 5168 * @netdev: network interface device structure 5169 * @txqueue: queue number that timed out 5170 **/ 5171 static void igc_tx_timeout(struct net_device *netdev, 5172 unsigned int __always_unused txqueue) 5173 { 5174 struct igc_adapter *adapter = netdev_priv(netdev); 5175 struct igc_hw *hw = &adapter->hw; 5176 5177 /* Do the reset outside of interrupt context */ 5178 adapter->tx_timeout_count++; 5179 schedule_work(&adapter->reset_task); 5180 wr32(IGC_EICS, 5181 (adapter->eims_enable_mask & ~adapter->eims_other)); 5182 } 5183 5184 /** 5185 * igc_get_stats64 - Get System Network Statistics 5186 * @netdev: network interface device structure 5187 * @stats: rtnl_link_stats64 pointer 5188 * 5189 * Returns the address of the device statistics structure. 5190 * The statistics are updated here and also from the timer callback. 5191 */ 5192 static void igc_get_stats64(struct net_device *netdev, 5193 struct rtnl_link_stats64 *stats) 5194 { 5195 struct igc_adapter *adapter = netdev_priv(netdev); 5196 5197 spin_lock(&adapter->stats64_lock); 5198 if (!test_bit(__IGC_RESETTING, &adapter->state)) 5199 igc_update_stats(adapter); 5200 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5201 spin_unlock(&adapter->stats64_lock); 5202 } 5203 5204 static netdev_features_t igc_fix_features(struct net_device *netdev, 5205 netdev_features_t features) 5206 { 5207 /* Since there is no support for separate Rx/Tx vlan accel 5208 * enable/disable make sure Tx flag is always in same state as Rx. 5209 */ 5210 if (features & NETIF_F_HW_VLAN_CTAG_RX) 5211 features |= NETIF_F_HW_VLAN_CTAG_TX; 5212 else 5213 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 5214 5215 return features; 5216 } 5217 5218 static int igc_set_features(struct net_device *netdev, 5219 netdev_features_t features) 5220 { 5221 netdev_features_t changed = netdev->features ^ features; 5222 struct igc_adapter *adapter = netdev_priv(netdev); 5223 5224 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 5225 igc_vlan_mode(netdev, features); 5226 5227 /* Add VLAN support */ 5228 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 5229 return 0; 5230 5231 if (!(features & NETIF_F_NTUPLE)) 5232 igc_flush_nfc_rules(adapter); 5233 5234 netdev->features = features; 5235 5236 if (netif_running(netdev)) 5237 igc_reinit_locked(adapter); 5238 else 5239 igc_reset(adapter); 5240 5241 return 1; 5242 } 5243 5244 static netdev_features_t 5245 igc_features_check(struct sk_buff *skb, struct net_device *dev, 5246 netdev_features_t features) 5247 { 5248 unsigned int network_hdr_len, mac_hdr_len; 5249 5250 /* Make certain the headers can be described by a context descriptor */ 5251 mac_hdr_len = skb_network_header(skb) - skb->data; 5252 if (unlikely(mac_hdr_len > IGC_MAX_MAC_HDR_LEN)) 5253 return features & ~(NETIF_F_HW_CSUM | 5254 NETIF_F_SCTP_CRC | 5255 NETIF_F_HW_VLAN_CTAG_TX | 5256 NETIF_F_TSO | 5257 NETIF_F_TSO6); 5258 5259 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 5260 if (unlikely(network_hdr_len > IGC_MAX_NETWORK_HDR_LEN)) 5261 return features & ~(NETIF_F_HW_CSUM | 5262 NETIF_F_SCTP_CRC | 5263 NETIF_F_TSO | 5264 NETIF_F_TSO6); 5265 5266 /* We can only support IPv4 TSO in tunnels if we can mangle the 5267 * inner IP ID field, so strip TSO if MANGLEID is not supported. 5268 */ 5269 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 5270 features &= ~NETIF_F_TSO; 5271 5272 return features; 5273 } 5274 5275 static void igc_tsync_interrupt(struct igc_adapter *adapter) 5276 { 5277 u32 ack, tsauxc, sec, nsec, tsicr; 5278 struct igc_hw *hw = &adapter->hw; 5279 struct ptp_clock_event event; 5280 struct timespec64 ts; 5281 5282 tsicr = rd32(IGC_TSICR); 5283 ack = 0; 5284 5285 if (tsicr & IGC_TSICR_SYS_WRAP) { 5286 event.type = PTP_CLOCK_PPS; 5287 if (adapter->ptp_caps.pps) 5288 ptp_clock_event(adapter->ptp_clock, &event); 5289 ack |= IGC_TSICR_SYS_WRAP; 5290 } 5291 5292 if (tsicr & IGC_TSICR_TXTS) { 5293 /* retrieve hardware timestamp */ 5294 igc_ptp_tx_tstamp_event(adapter); 5295 ack |= IGC_TSICR_TXTS; 5296 } 5297 5298 if (tsicr & IGC_TSICR_TT0) { 5299 spin_lock(&adapter->tmreg_lock); 5300 ts = timespec64_add(adapter->perout[0].start, 5301 adapter->perout[0].period); 5302 wr32(IGC_TRGTTIML0, ts.tv_nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0); 5303 wr32(IGC_TRGTTIMH0, (u32)ts.tv_sec); 5304 tsauxc = rd32(IGC_TSAUXC); 5305 tsauxc |= IGC_TSAUXC_EN_TT0; 5306 wr32(IGC_TSAUXC, tsauxc); 5307 adapter->perout[0].start = ts; 5308 spin_unlock(&adapter->tmreg_lock); 5309 ack |= IGC_TSICR_TT0; 5310 } 5311 5312 if (tsicr & IGC_TSICR_TT1) { 5313 spin_lock(&adapter->tmreg_lock); 5314 ts = timespec64_add(adapter->perout[1].start, 5315 adapter->perout[1].period); 5316 wr32(IGC_TRGTTIML1, ts.tv_nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0); 5317 wr32(IGC_TRGTTIMH1, (u32)ts.tv_sec); 5318 tsauxc = rd32(IGC_TSAUXC); 5319 tsauxc |= IGC_TSAUXC_EN_TT1; 5320 wr32(IGC_TSAUXC, tsauxc); 5321 adapter->perout[1].start = ts; 5322 spin_unlock(&adapter->tmreg_lock); 5323 ack |= IGC_TSICR_TT1; 5324 } 5325 5326 if (tsicr & IGC_TSICR_AUTT0) { 5327 nsec = rd32(IGC_AUXSTMPL0); 5328 sec = rd32(IGC_AUXSTMPH0); 5329 event.type = PTP_CLOCK_EXTTS; 5330 event.index = 0; 5331 event.timestamp = sec * NSEC_PER_SEC + nsec; 5332 ptp_clock_event(adapter->ptp_clock, &event); 5333 ack |= IGC_TSICR_AUTT0; 5334 } 5335 5336 if (tsicr & IGC_TSICR_AUTT1) { 5337 nsec = rd32(IGC_AUXSTMPL1); 5338 sec = rd32(IGC_AUXSTMPH1); 5339 event.type = PTP_CLOCK_EXTTS; 5340 event.index = 1; 5341 event.timestamp = sec * NSEC_PER_SEC + nsec; 5342 ptp_clock_event(adapter->ptp_clock, &event); 5343 ack |= IGC_TSICR_AUTT1; 5344 } 5345 5346 /* acknowledge the interrupts */ 5347 wr32(IGC_TSICR, ack); 5348 } 5349 5350 /** 5351 * igc_msix_other - msix other interrupt handler 5352 * @irq: interrupt number 5353 * @data: pointer to a q_vector 5354 */ 5355 static irqreturn_t igc_msix_other(int irq, void *data) 5356 { 5357 struct igc_adapter *adapter = data; 5358 struct igc_hw *hw = &adapter->hw; 5359 u32 icr = rd32(IGC_ICR); 5360 5361 /* reading ICR causes bit 31 of EICR to be cleared */ 5362 if (icr & IGC_ICR_DRSTA) 5363 schedule_work(&adapter->reset_task); 5364 5365 if (icr & IGC_ICR_DOUTSYNC) { 5366 /* HW is reporting DMA is out of sync */ 5367 adapter->stats.doosync++; 5368 } 5369 5370 if (icr & IGC_ICR_LSC) { 5371 hw->mac.get_link_status = true; 5372 /* guard against interrupt when we're going down */ 5373 if (!test_bit(__IGC_DOWN, &adapter->state)) 5374 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5375 } 5376 5377 if (icr & IGC_ICR_TS) 5378 igc_tsync_interrupt(adapter); 5379 5380 wr32(IGC_EIMS, adapter->eims_other); 5381 5382 return IRQ_HANDLED; 5383 } 5384 5385 static void igc_write_itr(struct igc_q_vector *q_vector) 5386 { 5387 u32 itr_val = q_vector->itr_val & IGC_QVECTOR_MASK; 5388 5389 if (!q_vector->set_itr) 5390 return; 5391 5392 if (!itr_val) 5393 itr_val = IGC_ITR_VAL_MASK; 5394 5395 itr_val |= IGC_EITR_CNT_IGNR; 5396 5397 writel(itr_val, q_vector->itr_register); 5398 q_vector->set_itr = 0; 5399 } 5400 5401 static irqreturn_t igc_msix_ring(int irq, void *data) 5402 { 5403 struct igc_q_vector *q_vector = data; 5404 5405 /* Write the ITR value calculated from the previous interrupt. */ 5406 igc_write_itr(q_vector); 5407 5408 napi_schedule(&q_vector->napi); 5409 5410 return IRQ_HANDLED; 5411 } 5412 5413 /** 5414 * igc_request_msix - Initialize MSI-X interrupts 5415 * @adapter: Pointer to adapter structure 5416 * 5417 * igc_request_msix allocates MSI-X vectors and requests interrupts from the 5418 * kernel. 5419 */ 5420 static int igc_request_msix(struct igc_adapter *adapter) 5421 { 5422 unsigned int num_q_vectors = adapter->num_q_vectors; 5423 int i = 0, err = 0, vector = 0, free_vector = 0; 5424 struct net_device *netdev = adapter->netdev; 5425 5426 err = request_irq(adapter->msix_entries[vector].vector, 5427 &igc_msix_other, 0, netdev->name, adapter); 5428 if (err) 5429 goto err_out; 5430 5431 if (num_q_vectors > MAX_Q_VECTORS) { 5432 num_q_vectors = MAX_Q_VECTORS; 5433 dev_warn(&adapter->pdev->dev, 5434 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 5435 adapter->num_q_vectors, MAX_Q_VECTORS); 5436 } 5437 for (i = 0; i < num_q_vectors; i++) { 5438 struct igc_q_vector *q_vector = adapter->q_vector[i]; 5439 5440 vector++; 5441 5442 q_vector->itr_register = adapter->io_addr + IGC_EITR(vector); 5443 5444 if (q_vector->rx.ring && q_vector->tx.ring) 5445 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 5446 q_vector->rx.ring->queue_index); 5447 else if (q_vector->tx.ring) 5448 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 5449 q_vector->tx.ring->queue_index); 5450 else if (q_vector->rx.ring) 5451 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 5452 q_vector->rx.ring->queue_index); 5453 else 5454 sprintf(q_vector->name, "%s-unused", netdev->name); 5455 5456 err = request_irq(adapter->msix_entries[vector].vector, 5457 igc_msix_ring, 0, q_vector->name, 5458 q_vector); 5459 if (err) 5460 goto err_free; 5461 } 5462 5463 igc_configure_msix(adapter); 5464 return 0; 5465 5466 err_free: 5467 /* free already assigned IRQs */ 5468 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 5469 5470 vector--; 5471 for (i = 0; i < vector; i++) { 5472 free_irq(adapter->msix_entries[free_vector++].vector, 5473 adapter->q_vector[i]); 5474 } 5475 err_out: 5476 return err; 5477 } 5478 5479 /** 5480 * igc_clear_interrupt_scheme - reset the device to a state of no interrupts 5481 * @adapter: Pointer to adapter structure 5482 * 5483 * This function resets the device so that it has 0 rx queues, tx queues, and 5484 * MSI-X interrupts allocated. 5485 */ 5486 static void igc_clear_interrupt_scheme(struct igc_adapter *adapter) 5487 { 5488 igc_free_q_vectors(adapter); 5489 igc_reset_interrupt_capability(adapter); 5490 } 5491 5492 /* Need to wait a few seconds after link up to get diagnostic information from 5493 * the phy 5494 */ 5495 static void igc_update_phy_info(struct timer_list *t) 5496 { 5497 struct igc_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5498 5499 igc_get_phy_info(&adapter->hw); 5500 } 5501 5502 /** 5503 * igc_has_link - check shared code for link and determine up/down 5504 * @adapter: pointer to driver private info 5505 */ 5506 bool igc_has_link(struct igc_adapter *adapter) 5507 { 5508 struct igc_hw *hw = &adapter->hw; 5509 bool link_active = false; 5510 5511 /* get_link_status is set on LSC (link status) interrupt or 5512 * rx sequence error interrupt. get_link_status will stay 5513 * false until the igc_check_for_link establishes link 5514 * for copper adapters ONLY 5515 */ 5516 if (!hw->mac.get_link_status) 5517 return true; 5518 hw->mac.ops.check_for_link(hw); 5519 link_active = !hw->mac.get_link_status; 5520 5521 if (hw->mac.type == igc_i225) { 5522 if (!netif_carrier_ok(adapter->netdev)) { 5523 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE; 5524 } else if (!(adapter->flags & IGC_FLAG_NEED_LINK_UPDATE)) { 5525 adapter->flags |= IGC_FLAG_NEED_LINK_UPDATE; 5526 adapter->link_check_timeout = jiffies; 5527 } 5528 } 5529 5530 return link_active; 5531 } 5532 5533 /** 5534 * igc_watchdog - Timer Call-back 5535 * @t: timer for the watchdog 5536 */ 5537 static void igc_watchdog(struct timer_list *t) 5538 { 5539 struct igc_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5540 /* Do the rest outside of interrupt context */ 5541 schedule_work(&adapter->watchdog_task); 5542 } 5543 5544 static void igc_watchdog_task(struct work_struct *work) 5545 { 5546 struct igc_adapter *adapter = container_of(work, 5547 struct igc_adapter, 5548 watchdog_task); 5549 struct net_device *netdev = adapter->netdev; 5550 struct igc_hw *hw = &adapter->hw; 5551 struct igc_phy_info *phy = &hw->phy; 5552 u16 phy_data, retry_count = 20; 5553 u32 link; 5554 int i; 5555 5556 link = igc_has_link(adapter); 5557 5558 if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE) { 5559 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5560 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE; 5561 else 5562 link = false; 5563 } 5564 5565 if (link) { 5566 /* Cancel scheduled suspend requests. */ 5567 pm_runtime_resume(netdev->dev.parent); 5568 5569 if (!netif_carrier_ok(netdev)) { 5570 u32 ctrl; 5571 5572 hw->mac.ops.get_speed_and_duplex(hw, 5573 &adapter->link_speed, 5574 &adapter->link_duplex); 5575 5576 ctrl = rd32(IGC_CTRL); 5577 /* Link status message must follow this format */ 5578 netdev_info(netdev, 5579 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5580 adapter->link_speed, 5581 adapter->link_duplex == FULL_DUPLEX ? 5582 "Full" : "Half", 5583 (ctrl & IGC_CTRL_TFCE) && 5584 (ctrl & IGC_CTRL_RFCE) ? "RX/TX" : 5585 (ctrl & IGC_CTRL_RFCE) ? "RX" : 5586 (ctrl & IGC_CTRL_TFCE) ? "TX" : "None"); 5587 5588 /* disable EEE if enabled */ 5589 if ((adapter->flags & IGC_FLAG_EEE) && 5590 adapter->link_duplex == HALF_DUPLEX) { 5591 netdev_info(netdev, 5592 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex\n"); 5593 adapter->hw.dev_spec._base.eee_enable = false; 5594 adapter->flags &= ~IGC_FLAG_EEE; 5595 } 5596 5597 /* check if SmartSpeed worked */ 5598 igc_check_downshift(hw); 5599 if (phy->speed_downgraded) 5600 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5601 5602 /* adjust timeout factor according to speed/duplex */ 5603 adapter->tx_timeout_factor = 1; 5604 switch (adapter->link_speed) { 5605 case SPEED_10: 5606 adapter->tx_timeout_factor = 14; 5607 break; 5608 case SPEED_100: 5609 case SPEED_1000: 5610 case SPEED_2500: 5611 adapter->tx_timeout_factor = 1; 5612 break; 5613 } 5614 5615 /* Once the launch time has been set on the wire, there 5616 * is a delay before the link speed can be determined 5617 * based on link-up activity. Write into the register 5618 * as soon as we know the correct link speed. 5619 */ 5620 igc_tsn_adjust_txtime_offset(adapter); 5621 5622 if (adapter->link_speed != SPEED_1000) 5623 goto no_wait; 5624 5625 /* wait for Remote receiver status OK */ 5626 retry_read_status: 5627 if (!igc_read_phy_reg(hw, PHY_1000T_STATUS, 5628 &phy_data)) { 5629 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5630 retry_count) { 5631 msleep(100); 5632 retry_count--; 5633 goto retry_read_status; 5634 } else if (!retry_count) { 5635 netdev_err(netdev, "exceed max 2 second\n"); 5636 } 5637 } else { 5638 netdev_err(netdev, "read 1000Base-T Status Reg\n"); 5639 } 5640 no_wait: 5641 netif_carrier_on(netdev); 5642 5643 /* link state has changed, schedule phy info update */ 5644 if (!test_bit(__IGC_DOWN, &adapter->state)) 5645 mod_timer(&adapter->phy_info_timer, 5646 round_jiffies(jiffies + 2 * HZ)); 5647 } 5648 } else { 5649 if (netif_carrier_ok(netdev)) { 5650 adapter->link_speed = 0; 5651 adapter->link_duplex = 0; 5652 5653 /* Links status message must follow this format */ 5654 netdev_info(netdev, "NIC Link is Down\n"); 5655 netif_carrier_off(netdev); 5656 5657 /* link state has changed, schedule phy info update */ 5658 if (!test_bit(__IGC_DOWN, &adapter->state)) 5659 mod_timer(&adapter->phy_info_timer, 5660 round_jiffies(jiffies + 2 * HZ)); 5661 5662 pm_schedule_suspend(netdev->dev.parent, 5663 MSEC_PER_SEC * 5); 5664 } 5665 } 5666 5667 spin_lock(&adapter->stats64_lock); 5668 igc_update_stats(adapter); 5669 spin_unlock(&adapter->stats64_lock); 5670 5671 for (i = 0; i < adapter->num_tx_queues; i++) { 5672 struct igc_ring *tx_ring = adapter->tx_ring[i]; 5673 5674 if (!netif_carrier_ok(netdev)) { 5675 /* We've lost link, so the controller stops DMA, 5676 * but we've got queued Tx work that's never going 5677 * to get done, so reset controller to flush Tx. 5678 * (Do the reset outside of interrupt context). 5679 */ 5680 if (igc_desc_unused(tx_ring) + 1 < tx_ring->count) { 5681 adapter->tx_timeout_count++; 5682 schedule_work(&adapter->reset_task); 5683 /* return immediately since reset is imminent */ 5684 return; 5685 } 5686 } 5687 5688 /* Force detection of hung controller every watchdog period */ 5689 set_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5690 } 5691 5692 /* Cause software interrupt to ensure Rx ring is cleaned */ 5693 if (adapter->flags & IGC_FLAG_HAS_MSIX) { 5694 u32 eics = 0; 5695 5696 for (i = 0; i < adapter->num_q_vectors; i++) 5697 eics |= adapter->q_vector[i]->eims_value; 5698 wr32(IGC_EICS, eics); 5699 } else { 5700 wr32(IGC_ICS, IGC_ICS_RXDMT0); 5701 } 5702 5703 igc_ptp_tx_hang(adapter); 5704 5705 /* Reset the timer */ 5706 if (!test_bit(__IGC_DOWN, &adapter->state)) { 5707 if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE) 5708 mod_timer(&adapter->watchdog_timer, 5709 round_jiffies(jiffies + HZ)); 5710 else 5711 mod_timer(&adapter->watchdog_timer, 5712 round_jiffies(jiffies + 2 * HZ)); 5713 } 5714 } 5715 5716 /** 5717 * igc_intr_msi - Interrupt Handler 5718 * @irq: interrupt number 5719 * @data: pointer to a network interface device structure 5720 */ 5721 static irqreturn_t igc_intr_msi(int irq, void *data) 5722 { 5723 struct igc_adapter *adapter = data; 5724 struct igc_q_vector *q_vector = adapter->q_vector[0]; 5725 struct igc_hw *hw = &adapter->hw; 5726 /* read ICR disables interrupts using IAM */ 5727 u32 icr = rd32(IGC_ICR); 5728 5729 igc_write_itr(q_vector); 5730 5731 if (icr & IGC_ICR_DRSTA) 5732 schedule_work(&adapter->reset_task); 5733 5734 if (icr & IGC_ICR_DOUTSYNC) { 5735 /* HW is reporting DMA is out of sync */ 5736 adapter->stats.doosync++; 5737 } 5738 5739 if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) { 5740 hw->mac.get_link_status = true; 5741 if (!test_bit(__IGC_DOWN, &adapter->state)) 5742 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5743 } 5744 5745 if (icr & IGC_ICR_TS) 5746 igc_tsync_interrupt(adapter); 5747 5748 napi_schedule(&q_vector->napi); 5749 5750 return IRQ_HANDLED; 5751 } 5752 5753 /** 5754 * igc_intr - Legacy Interrupt Handler 5755 * @irq: interrupt number 5756 * @data: pointer to a network interface device structure 5757 */ 5758 static irqreturn_t igc_intr(int irq, void *data) 5759 { 5760 struct igc_adapter *adapter = data; 5761 struct igc_q_vector *q_vector = adapter->q_vector[0]; 5762 struct igc_hw *hw = &adapter->hw; 5763 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 5764 * need for the IMC write 5765 */ 5766 u32 icr = rd32(IGC_ICR); 5767 5768 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 5769 * not set, then the adapter didn't send an interrupt 5770 */ 5771 if (!(icr & IGC_ICR_INT_ASSERTED)) 5772 return IRQ_NONE; 5773 5774 igc_write_itr(q_vector); 5775 5776 if (icr & IGC_ICR_DRSTA) 5777 schedule_work(&adapter->reset_task); 5778 5779 if (icr & IGC_ICR_DOUTSYNC) { 5780 /* HW is reporting DMA is out of sync */ 5781 adapter->stats.doosync++; 5782 } 5783 5784 if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) { 5785 hw->mac.get_link_status = true; 5786 /* guard against interrupt when we're going down */ 5787 if (!test_bit(__IGC_DOWN, &adapter->state)) 5788 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5789 } 5790 5791 if (icr & IGC_ICR_TS) 5792 igc_tsync_interrupt(adapter); 5793 5794 napi_schedule(&q_vector->napi); 5795 5796 return IRQ_HANDLED; 5797 } 5798 5799 static void igc_free_irq(struct igc_adapter *adapter) 5800 { 5801 if (adapter->msix_entries) { 5802 int vector = 0, i; 5803 5804 free_irq(adapter->msix_entries[vector++].vector, adapter); 5805 5806 for (i = 0; i < adapter->num_q_vectors; i++) 5807 free_irq(adapter->msix_entries[vector++].vector, 5808 adapter->q_vector[i]); 5809 } else { 5810 free_irq(adapter->pdev->irq, adapter); 5811 } 5812 } 5813 5814 /** 5815 * igc_request_irq - initialize interrupts 5816 * @adapter: Pointer to adapter structure 5817 * 5818 * Attempts to configure interrupts using the best available 5819 * capabilities of the hardware and kernel. 5820 */ 5821 static int igc_request_irq(struct igc_adapter *adapter) 5822 { 5823 struct net_device *netdev = adapter->netdev; 5824 struct pci_dev *pdev = adapter->pdev; 5825 int err = 0; 5826 5827 if (adapter->flags & IGC_FLAG_HAS_MSIX) { 5828 err = igc_request_msix(adapter); 5829 if (!err) 5830 goto request_done; 5831 /* fall back to MSI */ 5832 igc_free_all_tx_resources(adapter); 5833 igc_free_all_rx_resources(adapter); 5834 5835 igc_clear_interrupt_scheme(adapter); 5836 err = igc_init_interrupt_scheme(adapter, false); 5837 if (err) 5838 goto request_done; 5839 igc_setup_all_tx_resources(adapter); 5840 igc_setup_all_rx_resources(adapter); 5841 igc_configure(adapter); 5842 } 5843 5844 igc_assign_vector(adapter->q_vector[0], 0); 5845 5846 if (adapter->flags & IGC_FLAG_HAS_MSI) { 5847 err = request_irq(pdev->irq, &igc_intr_msi, 0, 5848 netdev->name, adapter); 5849 if (!err) 5850 goto request_done; 5851 5852 /* fall back to legacy interrupts */ 5853 igc_reset_interrupt_capability(adapter); 5854 adapter->flags &= ~IGC_FLAG_HAS_MSI; 5855 } 5856 5857 err = request_irq(pdev->irq, &igc_intr, IRQF_SHARED, 5858 netdev->name, adapter); 5859 5860 if (err) 5861 netdev_err(netdev, "Error %d getting interrupt\n", err); 5862 5863 request_done: 5864 return err; 5865 } 5866 5867 /** 5868 * __igc_open - Called when a network interface is made active 5869 * @netdev: network interface device structure 5870 * @resuming: boolean indicating if the device is resuming 5871 * 5872 * Returns 0 on success, negative value on failure 5873 * 5874 * The open entry point is called when a network interface is made 5875 * active by the system (IFF_UP). At this point all resources needed 5876 * for transmit and receive operations are allocated, the interrupt 5877 * handler is registered with the OS, the watchdog timer is started, 5878 * and the stack is notified that the interface is ready. 5879 */ 5880 static int __igc_open(struct net_device *netdev, bool resuming) 5881 { 5882 struct igc_adapter *adapter = netdev_priv(netdev); 5883 struct pci_dev *pdev = adapter->pdev; 5884 struct igc_hw *hw = &adapter->hw; 5885 int err = 0; 5886 int i = 0; 5887 5888 /* disallow open during test */ 5889 5890 if (test_bit(__IGC_TESTING, &adapter->state)) { 5891 WARN_ON(resuming); 5892 return -EBUSY; 5893 } 5894 5895 if (!resuming) 5896 pm_runtime_get_sync(&pdev->dev); 5897 5898 netif_carrier_off(netdev); 5899 5900 /* allocate transmit descriptors */ 5901 err = igc_setup_all_tx_resources(adapter); 5902 if (err) 5903 goto err_setup_tx; 5904 5905 /* allocate receive descriptors */ 5906 err = igc_setup_all_rx_resources(adapter); 5907 if (err) 5908 goto err_setup_rx; 5909 5910 igc_power_up_link(adapter); 5911 5912 igc_configure(adapter); 5913 5914 err = igc_request_irq(adapter); 5915 if (err) 5916 goto err_req_irq; 5917 5918 /* Notify the stack of the actual queue counts. */ 5919 err = netif_set_real_num_tx_queues(netdev, adapter->num_tx_queues); 5920 if (err) 5921 goto err_set_queues; 5922 5923 err = netif_set_real_num_rx_queues(netdev, adapter->num_rx_queues); 5924 if (err) 5925 goto err_set_queues; 5926 5927 clear_bit(__IGC_DOWN, &adapter->state); 5928 5929 for (i = 0; i < adapter->num_q_vectors; i++) 5930 napi_enable(&adapter->q_vector[i]->napi); 5931 5932 /* Clear any pending interrupts. */ 5933 rd32(IGC_ICR); 5934 igc_irq_enable(adapter); 5935 5936 if (!resuming) 5937 pm_runtime_put(&pdev->dev); 5938 5939 netif_tx_start_all_queues(netdev); 5940 5941 /* start the watchdog. */ 5942 hw->mac.get_link_status = true; 5943 schedule_work(&adapter->watchdog_task); 5944 5945 return IGC_SUCCESS; 5946 5947 err_set_queues: 5948 igc_free_irq(adapter); 5949 err_req_irq: 5950 igc_release_hw_control(adapter); 5951 igc_power_down_phy_copper_base(&adapter->hw); 5952 igc_free_all_rx_resources(adapter); 5953 err_setup_rx: 5954 igc_free_all_tx_resources(adapter); 5955 err_setup_tx: 5956 igc_reset(adapter); 5957 if (!resuming) 5958 pm_runtime_put(&pdev->dev); 5959 5960 return err; 5961 } 5962 5963 int igc_open(struct net_device *netdev) 5964 { 5965 return __igc_open(netdev, false); 5966 } 5967 5968 /** 5969 * __igc_close - Disables a network interface 5970 * @netdev: network interface device structure 5971 * @suspending: boolean indicating the device is suspending 5972 * 5973 * Returns 0, this is not allowed to fail 5974 * 5975 * The close entry point is called when an interface is de-activated 5976 * by the OS. The hardware is still under the driver's control, but 5977 * needs to be disabled. A global MAC reset is issued to stop the 5978 * hardware, and all transmit and receive resources are freed. 5979 */ 5980 static int __igc_close(struct net_device *netdev, bool suspending) 5981 { 5982 struct igc_adapter *adapter = netdev_priv(netdev); 5983 struct pci_dev *pdev = adapter->pdev; 5984 5985 WARN_ON(test_bit(__IGC_RESETTING, &adapter->state)); 5986 5987 if (!suspending) 5988 pm_runtime_get_sync(&pdev->dev); 5989 5990 igc_down(adapter); 5991 5992 igc_release_hw_control(adapter); 5993 5994 igc_free_irq(adapter); 5995 5996 igc_free_all_tx_resources(adapter); 5997 igc_free_all_rx_resources(adapter); 5998 5999 if (!suspending) 6000 pm_runtime_put_sync(&pdev->dev); 6001 6002 return 0; 6003 } 6004 6005 int igc_close(struct net_device *netdev) 6006 { 6007 if (netif_device_present(netdev) || netdev->dismantle) 6008 return __igc_close(netdev, false); 6009 return 0; 6010 } 6011 6012 /** 6013 * igc_ioctl - Access the hwtstamp interface 6014 * @netdev: network interface device structure 6015 * @ifr: interface request data 6016 * @cmd: ioctl command 6017 **/ 6018 static int igc_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6019 { 6020 switch (cmd) { 6021 case SIOCGHWTSTAMP: 6022 return igc_ptp_get_ts_config(netdev, ifr); 6023 case SIOCSHWTSTAMP: 6024 return igc_ptp_set_ts_config(netdev, ifr); 6025 default: 6026 return -EOPNOTSUPP; 6027 } 6028 } 6029 6030 static int igc_save_launchtime_params(struct igc_adapter *adapter, int queue, 6031 bool enable) 6032 { 6033 struct igc_ring *ring; 6034 6035 if (queue < 0 || queue >= adapter->num_tx_queues) 6036 return -EINVAL; 6037 6038 ring = adapter->tx_ring[queue]; 6039 ring->launchtime_enable = enable; 6040 6041 return 0; 6042 } 6043 6044 static bool is_base_time_past(ktime_t base_time, const struct timespec64 *now) 6045 { 6046 struct timespec64 b; 6047 6048 b = ktime_to_timespec64(base_time); 6049 6050 return timespec64_compare(now, &b) > 0; 6051 } 6052 6053 static bool validate_schedule(struct igc_adapter *adapter, 6054 const struct tc_taprio_qopt_offload *qopt) 6055 { 6056 int queue_uses[IGC_MAX_TX_QUEUES] = { }; 6057 struct igc_hw *hw = &adapter->hw; 6058 struct timespec64 now; 6059 size_t n; 6060 6061 if (qopt->cycle_time_extension) 6062 return false; 6063 6064 igc_ptp_read(adapter, &now); 6065 6066 /* If we program the controller's BASET registers with a time 6067 * in the future, it will hold all the packets until that 6068 * time, causing a lot of TX Hangs, so to avoid that, we 6069 * reject schedules that would start in the future. 6070 * Note: Limitation above is no longer in i226. 6071 */ 6072 if (!is_base_time_past(qopt->base_time, &now) && 6073 igc_is_device_id_i225(hw)) 6074 return false; 6075 6076 for (n = 0; n < qopt->num_entries; n++) { 6077 const struct tc_taprio_sched_entry *e, *prev; 6078 int i; 6079 6080 prev = n ? &qopt->entries[n - 1] : NULL; 6081 e = &qopt->entries[n]; 6082 6083 /* i225 only supports "global" frame preemption 6084 * settings. 6085 */ 6086 if (e->command != TC_TAPRIO_CMD_SET_GATES) 6087 return false; 6088 6089 for (i = 0; i < adapter->num_tx_queues; i++) 6090 if (e->gate_mask & BIT(i)) { 6091 queue_uses[i]++; 6092 6093 /* There are limitations: A single queue cannot 6094 * be opened and closed multiple times per cycle 6095 * unless the gate stays open. Check for it. 6096 */ 6097 if (queue_uses[i] > 1 && 6098 !(prev->gate_mask & BIT(i))) 6099 return false; 6100 } 6101 } 6102 6103 return true; 6104 } 6105 6106 static int igc_tsn_enable_launchtime(struct igc_adapter *adapter, 6107 struct tc_etf_qopt_offload *qopt) 6108 { 6109 struct igc_hw *hw = &adapter->hw; 6110 int err; 6111 6112 if (hw->mac.type != igc_i225) 6113 return -EOPNOTSUPP; 6114 6115 err = igc_save_launchtime_params(adapter, qopt->queue, qopt->enable); 6116 if (err) 6117 return err; 6118 6119 return igc_tsn_offload_apply(adapter); 6120 } 6121 6122 static int igc_tsn_clear_schedule(struct igc_adapter *adapter) 6123 { 6124 int i; 6125 6126 adapter->base_time = 0; 6127 adapter->cycle_time = NSEC_PER_SEC; 6128 adapter->taprio_offload_enable = false; 6129 adapter->qbv_config_change_errors = 0; 6130 adapter->qbv_transition = false; 6131 adapter->qbv_count = 0; 6132 6133 for (i = 0; i < adapter->num_tx_queues; i++) { 6134 struct igc_ring *ring = adapter->tx_ring[i]; 6135 6136 ring->start_time = 0; 6137 ring->end_time = NSEC_PER_SEC; 6138 ring->max_sdu = 0; 6139 ring->oper_gate_closed = false; 6140 ring->admin_gate_closed = false; 6141 } 6142 6143 return 0; 6144 } 6145 6146 static int igc_save_qbv_schedule(struct igc_adapter *adapter, 6147 struct tc_taprio_qopt_offload *qopt) 6148 { 6149 bool queue_configured[IGC_MAX_TX_QUEUES] = { }; 6150 struct igc_hw *hw = &adapter->hw; 6151 u32 start_time = 0, end_time = 0; 6152 struct timespec64 now; 6153 size_t n; 6154 int i; 6155 6156 if (qopt->cmd == TAPRIO_CMD_DESTROY) 6157 return igc_tsn_clear_schedule(adapter); 6158 6159 if (qopt->cmd != TAPRIO_CMD_REPLACE) 6160 return -EOPNOTSUPP; 6161 6162 if (qopt->base_time < 0) 6163 return -ERANGE; 6164 6165 if (igc_is_device_id_i225(hw) && adapter->taprio_offload_enable) 6166 return -EALREADY; 6167 6168 if (!validate_schedule(adapter, qopt)) 6169 return -EINVAL; 6170 6171 adapter->cycle_time = qopt->cycle_time; 6172 adapter->base_time = qopt->base_time; 6173 adapter->taprio_offload_enable = true; 6174 6175 igc_ptp_read(adapter, &now); 6176 6177 for (n = 0; n < qopt->num_entries; n++) { 6178 struct tc_taprio_sched_entry *e = &qopt->entries[n]; 6179 6180 end_time += e->interval; 6181 6182 /* If any of the conditions below are true, we need to manually 6183 * control the end time of the cycle. 6184 * 1. Qbv users can specify a cycle time that is not equal 6185 * to the total GCL intervals. Hence, recalculation is 6186 * necessary here to exclude the time interval that 6187 * exceeds the cycle time. 6188 * 2. According to IEEE Std. 802.1Q-2018 section 8.6.9.2, 6189 * once the end of the list is reached, it will switch 6190 * to the END_OF_CYCLE state and leave the gates in the 6191 * same state until the next cycle is started. 6192 */ 6193 if (end_time > adapter->cycle_time || 6194 n + 1 == qopt->num_entries) 6195 end_time = adapter->cycle_time; 6196 6197 for (i = 0; i < adapter->num_tx_queues; i++) { 6198 struct igc_ring *ring = adapter->tx_ring[i]; 6199 6200 if (!(e->gate_mask & BIT(i))) 6201 continue; 6202 6203 /* Check whether a queue stays open for more than one 6204 * entry. If so, keep the start and advance the end 6205 * time. 6206 */ 6207 if (!queue_configured[i]) 6208 ring->start_time = start_time; 6209 ring->end_time = end_time; 6210 6211 if (ring->start_time >= adapter->cycle_time) 6212 queue_configured[i] = false; 6213 else 6214 queue_configured[i] = true; 6215 } 6216 6217 start_time += e->interval; 6218 } 6219 6220 /* Check whether a queue gets configured. 6221 * If not, set the start and end time to be end time. 6222 */ 6223 for (i = 0; i < adapter->num_tx_queues; i++) { 6224 struct igc_ring *ring = adapter->tx_ring[i]; 6225 6226 if (!is_base_time_past(qopt->base_time, &now)) { 6227 ring->admin_gate_closed = false; 6228 } else { 6229 ring->oper_gate_closed = false; 6230 ring->admin_gate_closed = false; 6231 } 6232 6233 if (!queue_configured[i]) { 6234 if (!is_base_time_past(qopt->base_time, &now)) 6235 ring->admin_gate_closed = true; 6236 else 6237 ring->oper_gate_closed = true; 6238 6239 ring->start_time = end_time; 6240 ring->end_time = end_time; 6241 } 6242 } 6243 6244 for (i = 0; i < adapter->num_tx_queues; i++) { 6245 struct igc_ring *ring = adapter->tx_ring[i]; 6246 struct net_device *dev = adapter->netdev; 6247 6248 if (qopt->max_sdu[i]) 6249 ring->max_sdu = qopt->max_sdu[i] + dev->hard_header_len - ETH_TLEN; 6250 else 6251 ring->max_sdu = 0; 6252 } 6253 6254 return 0; 6255 } 6256 6257 static int igc_tsn_enable_qbv_scheduling(struct igc_adapter *adapter, 6258 struct tc_taprio_qopt_offload *qopt) 6259 { 6260 struct igc_hw *hw = &adapter->hw; 6261 int err; 6262 6263 if (hw->mac.type != igc_i225) 6264 return -EOPNOTSUPP; 6265 6266 err = igc_save_qbv_schedule(adapter, qopt); 6267 if (err) 6268 return err; 6269 6270 return igc_tsn_offload_apply(adapter); 6271 } 6272 6273 static int igc_save_cbs_params(struct igc_adapter *adapter, int queue, 6274 bool enable, int idleslope, int sendslope, 6275 int hicredit, int locredit) 6276 { 6277 bool cbs_status[IGC_MAX_SR_QUEUES] = { false }; 6278 struct net_device *netdev = adapter->netdev; 6279 struct igc_ring *ring; 6280 int i; 6281 6282 /* i225 has two sets of credit-based shaper logic. 6283 * Supporting it only on the top two priority queues 6284 */ 6285 if (queue < 0 || queue > 1) 6286 return -EINVAL; 6287 6288 ring = adapter->tx_ring[queue]; 6289 6290 for (i = 0; i < IGC_MAX_SR_QUEUES; i++) 6291 if (adapter->tx_ring[i]) 6292 cbs_status[i] = adapter->tx_ring[i]->cbs_enable; 6293 6294 /* CBS should be enabled on the highest priority queue first in order 6295 * for the CBS algorithm to operate as intended. 6296 */ 6297 if (enable) { 6298 if (queue == 1 && !cbs_status[0]) { 6299 netdev_err(netdev, 6300 "Enabling CBS on queue1 before queue0\n"); 6301 return -EINVAL; 6302 } 6303 } else { 6304 if (queue == 0 && cbs_status[1]) { 6305 netdev_err(netdev, 6306 "Disabling CBS on queue0 before queue1\n"); 6307 return -EINVAL; 6308 } 6309 } 6310 6311 ring->cbs_enable = enable; 6312 ring->idleslope = idleslope; 6313 ring->sendslope = sendslope; 6314 ring->hicredit = hicredit; 6315 ring->locredit = locredit; 6316 6317 return 0; 6318 } 6319 6320 static int igc_tsn_enable_cbs(struct igc_adapter *adapter, 6321 struct tc_cbs_qopt_offload *qopt) 6322 { 6323 struct igc_hw *hw = &adapter->hw; 6324 int err; 6325 6326 if (hw->mac.type != igc_i225) 6327 return -EOPNOTSUPP; 6328 6329 if (qopt->queue < 0 || qopt->queue > 1) 6330 return -EINVAL; 6331 6332 err = igc_save_cbs_params(adapter, qopt->queue, qopt->enable, 6333 qopt->idleslope, qopt->sendslope, 6334 qopt->hicredit, qopt->locredit); 6335 if (err) 6336 return err; 6337 6338 return igc_tsn_offload_apply(adapter); 6339 } 6340 6341 static int igc_tc_query_caps(struct igc_adapter *adapter, 6342 struct tc_query_caps_base *base) 6343 { 6344 struct igc_hw *hw = &adapter->hw; 6345 6346 switch (base->type) { 6347 case TC_SETUP_QDISC_TAPRIO: { 6348 struct tc_taprio_caps *caps = base->caps; 6349 6350 caps->broken_mqprio = true; 6351 6352 if (hw->mac.type == igc_i225) { 6353 caps->supports_queue_max_sdu = true; 6354 caps->gate_mask_per_txq = true; 6355 } 6356 6357 return 0; 6358 } 6359 default: 6360 return -EOPNOTSUPP; 6361 } 6362 } 6363 6364 static int igc_setup_tc(struct net_device *dev, enum tc_setup_type type, 6365 void *type_data) 6366 { 6367 struct igc_adapter *adapter = netdev_priv(dev); 6368 6369 adapter->tc_setup_type = type; 6370 6371 switch (type) { 6372 case TC_QUERY_CAPS: 6373 return igc_tc_query_caps(adapter, type_data); 6374 case TC_SETUP_QDISC_TAPRIO: 6375 return igc_tsn_enable_qbv_scheduling(adapter, type_data); 6376 6377 case TC_SETUP_QDISC_ETF: 6378 return igc_tsn_enable_launchtime(adapter, type_data); 6379 6380 case TC_SETUP_QDISC_CBS: 6381 return igc_tsn_enable_cbs(adapter, type_data); 6382 6383 default: 6384 return -EOPNOTSUPP; 6385 } 6386 } 6387 6388 static int igc_bpf(struct net_device *dev, struct netdev_bpf *bpf) 6389 { 6390 struct igc_adapter *adapter = netdev_priv(dev); 6391 6392 switch (bpf->command) { 6393 case XDP_SETUP_PROG: 6394 return igc_xdp_set_prog(adapter, bpf->prog, bpf->extack); 6395 case XDP_SETUP_XSK_POOL: 6396 return igc_xdp_setup_pool(adapter, bpf->xsk.pool, 6397 bpf->xsk.queue_id); 6398 default: 6399 return -EOPNOTSUPP; 6400 } 6401 } 6402 6403 static int igc_xdp_xmit(struct net_device *dev, int num_frames, 6404 struct xdp_frame **frames, u32 flags) 6405 { 6406 struct igc_adapter *adapter = netdev_priv(dev); 6407 int cpu = smp_processor_id(); 6408 struct netdev_queue *nq; 6409 struct igc_ring *ring; 6410 int i, drops; 6411 6412 if (unlikely(test_bit(__IGC_DOWN, &adapter->state))) 6413 return -ENETDOWN; 6414 6415 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 6416 return -EINVAL; 6417 6418 ring = igc_xdp_get_tx_ring(adapter, cpu); 6419 nq = txring_txq(ring); 6420 6421 __netif_tx_lock(nq, cpu); 6422 6423 /* Avoid transmit queue timeout since we share it with the slow path */ 6424 txq_trans_cond_update(nq); 6425 6426 drops = 0; 6427 for (i = 0; i < num_frames; i++) { 6428 int err; 6429 struct xdp_frame *xdpf = frames[i]; 6430 6431 err = igc_xdp_init_tx_descriptor(ring, xdpf); 6432 if (err) { 6433 xdp_return_frame_rx_napi(xdpf); 6434 drops++; 6435 } 6436 } 6437 6438 if (flags & XDP_XMIT_FLUSH) 6439 igc_flush_tx_descriptors(ring); 6440 6441 __netif_tx_unlock(nq); 6442 6443 return num_frames - drops; 6444 } 6445 6446 static void igc_trigger_rxtxq_interrupt(struct igc_adapter *adapter, 6447 struct igc_q_vector *q_vector) 6448 { 6449 struct igc_hw *hw = &adapter->hw; 6450 u32 eics = 0; 6451 6452 eics |= q_vector->eims_value; 6453 wr32(IGC_EICS, eics); 6454 } 6455 6456 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags) 6457 { 6458 struct igc_adapter *adapter = netdev_priv(dev); 6459 struct igc_q_vector *q_vector; 6460 struct igc_ring *ring; 6461 6462 if (test_bit(__IGC_DOWN, &adapter->state)) 6463 return -ENETDOWN; 6464 6465 if (!igc_xdp_is_enabled(adapter)) 6466 return -ENXIO; 6467 6468 if (queue_id >= adapter->num_rx_queues) 6469 return -EINVAL; 6470 6471 ring = adapter->rx_ring[queue_id]; 6472 6473 if (!ring->xsk_pool) 6474 return -ENXIO; 6475 6476 q_vector = adapter->q_vector[queue_id]; 6477 if (!napi_if_scheduled_mark_missed(&q_vector->napi)) 6478 igc_trigger_rxtxq_interrupt(adapter, q_vector); 6479 6480 return 0; 6481 } 6482 6483 static const struct net_device_ops igc_netdev_ops = { 6484 .ndo_open = igc_open, 6485 .ndo_stop = igc_close, 6486 .ndo_start_xmit = igc_xmit_frame, 6487 .ndo_set_rx_mode = igc_set_rx_mode, 6488 .ndo_set_mac_address = igc_set_mac, 6489 .ndo_change_mtu = igc_change_mtu, 6490 .ndo_tx_timeout = igc_tx_timeout, 6491 .ndo_get_stats64 = igc_get_stats64, 6492 .ndo_fix_features = igc_fix_features, 6493 .ndo_set_features = igc_set_features, 6494 .ndo_features_check = igc_features_check, 6495 .ndo_eth_ioctl = igc_ioctl, 6496 .ndo_setup_tc = igc_setup_tc, 6497 .ndo_bpf = igc_bpf, 6498 .ndo_xdp_xmit = igc_xdp_xmit, 6499 .ndo_xsk_wakeup = igc_xsk_wakeup, 6500 }; 6501 6502 /* PCIe configuration access */ 6503 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value) 6504 { 6505 struct igc_adapter *adapter = hw->back; 6506 6507 pci_read_config_word(adapter->pdev, reg, value); 6508 } 6509 6510 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value) 6511 { 6512 struct igc_adapter *adapter = hw->back; 6513 6514 pci_write_config_word(adapter->pdev, reg, *value); 6515 } 6516 6517 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value) 6518 { 6519 struct igc_adapter *adapter = hw->back; 6520 6521 if (!pci_is_pcie(adapter->pdev)) 6522 return -IGC_ERR_CONFIG; 6523 6524 pcie_capability_read_word(adapter->pdev, reg, value); 6525 6526 return IGC_SUCCESS; 6527 } 6528 6529 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value) 6530 { 6531 struct igc_adapter *adapter = hw->back; 6532 6533 if (!pci_is_pcie(adapter->pdev)) 6534 return -IGC_ERR_CONFIG; 6535 6536 pcie_capability_write_word(adapter->pdev, reg, *value); 6537 6538 return IGC_SUCCESS; 6539 } 6540 6541 u32 igc_rd32(struct igc_hw *hw, u32 reg) 6542 { 6543 struct igc_adapter *igc = container_of(hw, struct igc_adapter, hw); 6544 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 6545 u32 value = 0; 6546 6547 if (IGC_REMOVED(hw_addr)) 6548 return ~value; 6549 6550 value = readl(&hw_addr[reg]); 6551 6552 /* reads should not return all F's */ 6553 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 6554 struct net_device *netdev = igc->netdev; 6555 6556 hw->hw_addr = NULL; 6557 netif_device_detach(netdev); 6558 netdev_err(netdev, "PCIe link lost, device now detached\n"); 6559 WARN(pci_device_is_present(igc->pdev), 6560 "igc: Failed to read reg 0x%x!\n", reg); 6561 } 6562 6563 return value; 6564 } 6565 6566 /* Mapping HW RSS Type to enum xdp_rss_hash_type */ 6567 static enum xdp_rss_hash_type igc_xdp_rss_type[IGC_RSS_TYPE_MAX_TABLE] = { 6568 [IGC_RSS_TYPE_NO_HASH] = XDP_RSS_TYPE_L2, 6569 [IGC_RSS_TYPE_HASH_TCP_IPV4] = XDP_RSS_TYPE_L4_IPV4_TCP, 6570 [IGC_RSS_TYPE_HASH_IPV4] = XDP_RSS_TYPE_L3_IPV4, 6571 [IGC_RSS_TYPE_HASH_TCP_IPV6] = XDP_RSS_TYPE_L4_IPV6_TCP, 6572 [IGC_RSS_TYPE_HASH_IPV6_EX] = XDP_RSS_TYPE_L3_IPV6_EX, 6573 [IGC_RSS_TYPE_HASH_IPV6] = XDP_RSS_TYPE_L3_IPV6, 6574 [IGC_RSS_TYPE_HASH_TCP_IPV6_EX] = XDP_RSS_TYPE_L4_IPV6_TCP_EX, 6575 [IGC_RSS_TYPE_HASH_UDP_IPV4] = XDP_RSS_TYPE_L4_IPV4_UDP, 6576 [IGC_RSS_TYPE_HASH_UDP_IPV6] = XDP_RSS_TYPE_L4_IPV6_UDP, 6577 [IGC_RSS_TYPE_HASH_UDP_IPV6_EX] = XDP_RSS_TYPE_L4_IPV6_UDP_EX, 6578 [10] = XDP_RSS_TYPE_NONE, /* RSS Type above 9 "Reserved" by HW */ 6579 [11] = XDP_RSS_TYPE_NONE, /* keep array sized for SW bit-mask */ 6580 [12] = XDP_RSS_TYPE_NONE, /* to handle future HW revisons */ 6581 [13] = XDP_RSS_TYPE_NONE, 6582 [14] = XDP_RSS_TYPE_NONE, 6583 [15] = XDP_RSS_TYPE_NONE, 6584 }; 6585 6586 static int igc_xdp_rx_hash(const struct xdp_md *_ctx, u32 *hash, 6587 enum xdp_rss_hash_type *rss_type) 6588 { 6589 const struct igc_xdp_buff *ctx = (void *)_ctx; 6590 6591 if (!(ctx->xdp.rxq->dev->features & NETIF_F_RXHASH)) 6592 return -ENODATA; 6593 6594 *hash = le32_to_cpu(ctx->rx_desc->wb.lower.hi_dword.rss); 6595 *rss_type = igc_xdp_rss_type[igc_rss_type(ctx->rx_desc)]; 6596 6597 return 0; 6598 } 6599 6600 static int igc_xdp_rx_timestamp(const struct xdp_md *_ctx, u64 *timestamp) 6601 { 6602 const struct igc_xdp_buff *ctx = (void *)_ctx; 6603 6604 if (igc_test_staterr(ctx->rx_desc, IGC_RXDADV_STAT_TSIP)) { 6605 *timestamp = ctx->rx_ts; 6606 6607 return 0; 6608 } 6609 6610 return -ENODATA; 6611 } 6612 6613 static const struct xdp_metadata_ops igc_xdp_metadata_ops = { 6614 .xmo_rx_hash = igc_xdp_rx_hash, 6615 .xmo_rx_timestamp = igc_xdp_rx_timestamp, 6616 }; 6617 6618 static enum hrtimer_restart igc_qbv_scheduling_timer(struct hrtimer *timer) 6619 { 6620 struct igc_adapter *adapter = container_of(timer, struct igc_adapter, 6621 hrtimer); 6622 unsigned int i; 6623 6624 adapter->qbv_transition = true; 6625 for (i = 0; i < adapter->num_tx_queues; i++) { 6626 struct igc_ring *tx_ring = adapter->tx_ring[i]; 6627 6628 if (tx_ring->admin_gate_closed) { 6629 tx_ring->admin_gate_closed = false; 6630 tx_ring->oper_gate_closed = true; 6631 } else { 6632 tx_ring->oper_gate_closed = false; 6633 } 6634 } 6635 adapter->qbv_transition = false; 6636 return HRTIMER_NORESTART; 6637 } 6638 6639 /** 6640 * igc_probe - Device Initialization Routine 6641 * @pdev: PCI device information struct 6642 * @ent: entry in igc_pci_tbl 6643 * 6644 * Returns 0 on success, negative on failure 6645 * 6646 * igc_probe initializes an adapter identified by a pci_dev structure. 6647 * The OS initialization, configuring the adapter private structure, 6648 * and a hardware reset occur. 6649 */ 6650 static int igc_probe(struct pci_dev *pdev, 6651 const struct pci_device_id *ent) 6652 { 6653 struct igc_adapter *adapter; 6654 struct net_device *netdev; 6655 struct igc_hw *hw; 6656 const struct igc_info *ei = igc_info_tbl[ent->driver_data]; 6657 int err; 6658 6659 err = pci_enable_device_mem(pdev); 6660 if (err) 6661 return err; 6662 6663 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 6664 if (err) { 6665 dev_err(&pdev->dev, 6666 "No usable DMA configuration, aborting\n"); 6667 goto err_dma; 6668 } 6669 6670 err = pci_request_mem_regions(pdev, igc_driver_name); 6671 if (err) 6672 goto err_pci_reg; 6673 6674 err = pci_enable_ptm(pdev, NULL); 6675 if (err < 0) 6676 dev_info(&pdev->dev, "PCIe PTM not supported by PCIe bus/controller\n"); 6677 6678 pci_set_master(pdev); 6679 6680 err = -ENOMEM; 6681 netdev = alloc_etherdev_mq(sizeof(struct igc_adapter), 6682 IGC_MAX_TX_QUEUES); 6683 6684 if (!netdev) 6685 goto err_alloc_etherdev; 6686 6687 SET_NETDEV_DEV(netdev, &pdev->dev); 6688 6689 pci_set_drvdata(pdev, netdev); 6690 adapter = netdev_priv(netdev); 6691 adapter->netdev = netdev; 6692 adapter->pdev = pdev; 6693 hw = &adapter->hw; 6694 hw->back = adapter; 6695 adapter->port_num = hw->bus.func; 6696 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 6697 6698 err = pci_save_state(pdev); 6699 if (err) 6700 goto err_ioremap; 6701 6702 err = -EIO; 6703 adapter->io_addr = ioremap(pci_resource_start(pdev, 0), 6704 pci_resource_len(pdev, 0)); 6705 if (!adapter->io_addr) 6706 goto err_ioremap; 6707 6708 /* hw->hw_addr can be zeroed, so use adapter->io_addr for unmap */ 6709 hw->hw_addr = adapter->io_addr; 6710 6711 netdev->netdev_ops = &igc_netdev_ops; 6712 netdev->xdp_metadata_ops = &igc_xdp_metadata_ops; 6713 igc_ethtool_set_ops(netdev); 6714 netdev->watchdog_timeo = 5 * HZ; 6715 6716 netdev->mem_start = pci_resource_start(pdev, 0); 6717 netdev->mem_end = pci_resource_end(pdev, 0); 6718 6719 /* PCI config space info */ 6720 hw->vendor_id = pdev->vendor; 6721 hw->device_id = pdev->device; 6722 hw->revision_id = pdev->revision; 6723 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6724 hw->subsystem_device_id = pdev->subsystem_device; 6725 6726 /* Copy the default MAC and PHY function pointers */ 6727 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 6728 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 6729 6730 /* Initialize skew-specific constants */ 6731 err = ei->get_invariants(hw); 6732 if (err) 6733 goto err_sw_init; 6734 6735 /* Add supported features to the features list*/ 6736 netdev->features |= NETIF_F_SG; 6737 netdev->features |= NETIF_F_TSO; 6738 netdev->features |= NETIF_F_TSO6; 6739 netdev->features |= NETIF_F_TSO_ECN; 6740 netdev->features |= NETIF_F_RXHASH; 6741 netdev->features |= NETIF_F_RXCSUM; 6742 netdev->features |= NETIF_F_HW_CSUM; 6743 netdev->features |= NETIF_F_SCTP_CRC; 6744 netdev->features |= NETIF_F_HW_TC; 6745 6746 #define IGC_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 6747 NETIF_F_GSO_GRE_CSUM | \ 6748 NETIF_F_GSO_IPXIP4 | \ 6749 NETIF_F_GSO_IPXIP6 | \ 6750 NETIF_F_GSO_UDP_TUNNEL | \ 6751 NETIF_F_GSO_UDP_TUNNEL_CSUM) 6752 6753 netdev->gso_partial_features = IGC_GSO_PARTIAL_FEATURES; 6754 netdev->features |= NETIF_F_GSO_PARTIAL | IGC_GSO_PARTIAL_FEATURES; 6755 6756 /* setup the private structure */ 6757 err = igc_sw_init(adapter); 6758 if (err) 6759 goto err_sw_init; 6760 6761 /* copy netdev features into list of user selectable features */ 6762 netdev->hw_features |= NETIF_F_NTUPLE; 6763 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 6764 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 6765 netdev->hw_features |= netdev->features; 6766 6767 netdev->features |= NETIF_F_HIGHDMA; 6768 6769 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 6770 netdev->mpls_features |= NETIF_F_HW_CSUM; 6771 netdev->hw_enc_features |= netdev->vlan_features; 6772 6773 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 6774 NETDEV_XDP_ACT_XSK_ZEROCOPY; 6775 6776 /* MTU range: 68 - 9216 */ 6777 netdev->min_mtu = ETH_MIN_MTU; 6778 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 6779 6780 /* before reading the NVM, reset the controller to put the device in a 6781 * known good starting state 6782 */ 6783 hw->mac.ops.reset_hw(hw); 6784 6785 if (igc_get_flash_presence_i225(hw)) { 6786 if (hw->nvm.ops.validate(hw) < 0) { 6787 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 6788 err = -EIO; 6789 goto err_eeprom; 6790 } 6791 } 6792 6793 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 6794 /* copy the MAC address out of the NVM */ 6795 if (hw->mac.ops.read_mac_addr(hw)) 6796 dev_err(&pdev->dev, "NVM Read Error\n"); 6797 } 6798 6799 eth_hw_addr_set(netdev, hw->mac.addr); 6800 6801 if (!is_valid_ether_addr(netdev->dev_addr)) { 6802 dev_err(&pdev->dev, "Invalid MAC Address\n"); 6803 err = -EIO; 6804 goto err_eeprom; 6805 } 6806 6807 /* configure RXPBSIZE and TXPBSIZE */ 6808 wr32(IGC_RXPBS, I225_RXPBSIZE_DEFAULT); 6809 wr32(IGC_TXPBS, I225_TXPBSIZE_DEFAULT); 6810 6811 timer_setup(&adapter->watchdog_timer, igc_watchdog, 0); 6812 timer_setup(&adapter->phy_info_timer, igc_update_phy_info, 0); 6813 6814 INIT_WORK(&adapter->reset_task, igc_reset_task); 6815 INIT_WORK(&adapter->watchdog_task, igc_watchdog_task); 6816 6817 hrtimer_init(&adapter->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 6818 adapter->hrtimer.function = &igc_qbv_scheduling_timer; 6819 6820 /* Initialize link properties that are user-changeable */ 6821 adapter->fc_autoneg = true; 6822 hw->mac.autoneg = true; 6823 hw->phy.autoneg_advertised = 0xaf; 6824 6825 hw->fc.requested_mode = igc_fc_default; 6826 hw->fc.current_mode = igc_fc_default; 6827 6828 /* By default, support wake on port A */ 6829 adapter->flags |= IGC_FLAG_WOL_SUPPORTED; 6830 6831 /* initialize the wol settings based on the eeprom settings */ 6832 if (adapter->flags & IGC_FLAG_WOL_SUPPORTED) 6833 adapter->wol |= IGC_WUFC_MAG; 6834 6835 device_set_wakeup_enable(&adapter->pdev->dev, 6836 adapter->flags & IGC_FLAG_WOL_SUPPORTED); 6837 6838 igc_ptp_init(adapter); 6839 6840 igc_tsn_clear_schedule(adapter); 6841 6842 /* reset the hardware with the new settings */ 6843 igc_reset(adapter); 6844 6845 /* let the f/w know that the h/w is now under the control of the 6846 * driver. 6847 */ 6848 igc_get_hw_control(adapter); 6849 6850 strncpy(netdev->name, "eth%d", IFNAMSIZ); 6851 err = register_netdev(netdev); 6852 if (err) 6853 goto err_register; 6854 6855 /* carrier off reporting is important to ethtool even BEFORE open */ 6856 netif_carrier_off(netdev); 6857 6858 /* Check if Media Autosense is enabled */ 6859 adapter->ei = *ei; 6860 6861 /* print pcie link status and MAC address */ 6862 pcie_print_link_status(pdev); 6863 netdev_info(netdev, "MAC: %pM\n", netdev->dev_addr); 6864 6865 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 6866 /* Disable EEE for internal PHY devices */ 6867 hw->dev_spec._base.eee_enable = false; 6868 adapter->flags &= ~IGC_FLAG_EEE; 6869 igc_set_eee_i225(hw, false, false, false); 6870 6871 pm_runtime_put_noidle(&pdev->dev); 6872 6873 return 0; 6874 6875 err_register: 6876 igc_release_hw_control(adapter); 6877 err_eeprom: 6878 if (!igc_check_reset_block(hw)) 6879 igc_reset_phy(hw); 6880 err_sw_init: 6881 igc_clear_interrupt_scheme(adapter); 6882 iounmap(adapter->io_addr); 6883 err_ioremap: 6884 free_netdev(netdev); 6885 err_alloc_etherdev: 6886 pci_release_mem_regions(pdev); 6887 err_pci_reg: 6888 err_dma: 6889 pci_disable_device(pdev); 6890 return err; 6891 } 6892 6893 /** 6894 * igc_remove - Device Removal Routine 6895 * @pdev: PCI device information struct 6896 * 6897 * igc_remove is called by the PCI subsystem to alert the driver 6898 * that it should release a PCI device. This could be caused by a 6899 * Hot-Plug event, or because the driver is going to be removed from 6900 * memory. 6901 */ 6902 static void igc_remove(struct pci_dev *pdev) 6903 { 6904 struct net_device *netdev = pci_get_drvdata(pdev); 6905 struct igc_adapter *adapter = netdev_priv(netdev); 6906 6907 pm_runtime_get_noresume(&pdev->dev); 6908 6909 igc_flush_nfc_rules(adapter); 6910 6911 igc_ptp_stop(adapter); 6912 6913 pci_disable_ptm(pdev); 6914 pci_clear_master(pdev); 6915 6916 set_bit(__IGC_DOWN, &adapter->state); 6917 6918 del_timer_sync(&adapter->watchdog_timer); 6919 del_timer_sync(&adapter->phy_info_timer); 6920 6921 cancel_work_sync(&adapter->reset_task); 6922 cancel_work_sync(&adapter->watchdog_task); 6923 hrtimer_cancel(&adapter->hrtimer); 6924 6925 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6926 * would have already happened in close and is redundant. 6927 */ 6928 igc_release_hw_control(adapter); 6929 unregister_netdev(netdev); 6930 6931 igc_clear_interrupt_scheme(adapter); 6932 pci_iounmap(pdev, adapter->io_addr); 6933 pci_release_mem_regions(pdev); 6934 6935 free_netdev(netdev); 6936 6937 pci_disable_device(pdev); 6938 } 6939 6940 static int __igc_shutdown(struct pci_dev *pdev, bool *enable_wake, 6941 bool runtime) 6942 { 6943 struct net_device *netdev = pci_get_drvdata(pdev); 6944 struct igc_adapter *adapter = netdev_priv(netdev); 6945 u32 wufc = runtime ? IGC_WUFC_LNKC : adapter->wol; 6946 struct igc_hw *hw = &adapter->hw; 6947 u32 ctrl, rctl, status; 6948 bool wake; 6949 6950 rtnl_lock(); 6951 netif_device_detach(netdev); 6952 6953 if (netif_running(netdev)) 6954 __igc_close(netdev, true); 6955 6956 igc_ptp_suspend(adapter); 6957 6958 igc_clear_interrupt_scheme(adapter); 6959 rtnl_unlock(); 6960 6961 status = rd32(IGC_STATUS); 6962 if (status & IGC_STATUS_LU) 6963 wufc &= ~IGC_WUFC_LNKC; 6964 6965 if (wufc) { 6966 igc_setup_rctl(adapter); 6967 igc_set_rx_mode(netdev); 6968 6969 /* turn on all-multi mode if wake on multicast is enabled */ 6970 if (wufc & IGC_WUFC_MC) { 6971 rctl = rd32(IGC_RCTL); 6972 rctl |= IGC_RCTL_MPE; 6973 wr32(IGC_RCTL, rctl); 6974 } 6975 6976 ctrl = rd32(IGC_CTRL); 6977 ctrl |= IGC_CTRL_ADVD3WUC; 6978 wr32(IGC_CTRL, ctrl); 6979 6980 /* Allow time for pending master requests to run */ 6981 igc_disable_pcie_master(hw); 6982 6983 wr32(IGC_WUC, IGC_WUC_PME_EN); 6984 wr32(IGC_WUFC, wufc); 6985 } else { 6986 wr32(IGC_WUC, 0); 6987 wr32(IGC_WUFC, 0); 6988 } 6989 6990 wake = wufc || adapter->en_mng_pt; 6991 if (!wake) 6992 igc_power_down_phy_copper_base(&adapter->hw); 6993 else 6994 igc_power_up_link(adapter); 6995 6996 if (enable_wake) 6997 *enable_wake = wake; 6998 6999 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7000 * would have already happened in close and is redundant. 7001 */ 7002 igc_release_hw_control(adapter); 7003 7004 pci_disable_device(pdev); 7005 7006 return 0; 7007 } 7008 7009 #ifdef CONFIG_PM 7010 static int __maybe_unused igc_runtime_suspend(struct device *dev) 7011 { 7012 return __igc_shutdown(to_pci_dev(dev), NULL, 1); 7013 } 7014 7015 static void igc_deliver_wake_packet(struct net_device *netdev) 7016 { 7017 struct igc_adapter *adapter = netdev_priv(netdev); 7018 struct igc_hw *hw = &adapter->hw; 7019 struct sk_buff *skb; 7020 u32 wupl; 7021 7022 wupl = rd32(IGC_WUPL) & IGC_WUPL_MASK; 7023 7024 /* WUPM stores only the first 128 bytes of the wake packet. 7025 * Read the packet only if we have the whole thing. 7026 */ 7027 if (wupl == 0 || wupl > IGC_WUPM_BYTES) 7028 return; 7029 7030 skb = netdev_alloc_skb_ip_align(netdev, IGC_WUPM_BYTES); 7031 if (!skb) 7032 return; 7033 7034 skb_put(skb, wupl); 7035 7036 /* Ensure reads are 32-bit aligned */ 7037 wupl = roundup(wupl, 4); 7038 7039 memcpy_fromio(skb->data, hw->hw_addr + IGC_WUPM_REG(0), wupl); 7040 7041 skb->protocol = eth_type_trans(skb, netdev); 7042 netif_rx(skb); 7043 } 7044 7045 static int __maybe_unused igc_resume(struct device *dev) 7046 { 7047 struct pci_dev *pdev = to_pci_dev(dev); 7048 struct net_device *netdev = pci_get_drvdata(pdev); 7049 struct igc_adapter *adapter = netdev_priv(netdev); 7050 struct igc_hw *hw = &adapter->hw; 7051 u32 err, val; 7052 7053 pci_set_power_state(pdev, PCI_D0); 7054 pci_restore_state(pdev); 7055 pci_save_state(pdev); 7056 7057 if (!pci_device_is_present(pdev)) 7058 return -ENODEV; 7059 err = pci_enable_device_mem(pdev); 7060 if (err) { 7061 netdev_err(netdev, "Cannot enable PCI device from suspend\n"); 7062 return err; 7063 } 7064 pci_set_master(pdev); 7065 7066 pci_enable_wake(pdev, PCI_D3hot, 0); 7067 pci_enable_wake(pdev, PCI_D3cold, 0); 7068 7069 if (igc_init_interrupt_scheme(adapter, true)) { 7070 netdev_err(netdev, "Unable to allocate memory for queues\n"); 7071 return -ENOMEM; 7072 } 7073 7074 igc_reset(adapter); 7075 7076 /* let the f/w know that the h/w is now under the control of the 7077 * driver. 7078 */ 7079 igc_get_hw_control(adapter); 7080 7081 val = rd32(IGC_WUS); 7082 if (val & WAKE_PKT_WUS) 7083 igc_deliver_wake_packet(netdev); 7084 7085 wr32(IGC_WUS, ~0); 7086 7087 rtnl_lock(); 7088 if (!err && netif_running(netdev)) 7089 err = __igc_open(netdev, true); 7090 7091 if (!err) 7092 netif_device_attach(netdev); 7093 rtnl_unlock(); 7094 7095 return err; 7096 } 7097 7098 static int __maybe_unused igc_runtime_resume(struct device *dev) 7099 { 7100 return igc_resume(dev); 7101 } 7102 7103 static int __maybe_unused igc_suspend(struct device *dev) 7104 { 7105 return __igc_shutdown(to_pci_dev(dev), NULL, 0); 7106 } 7107 7108 static int __maybe_unused igc_runtime_idle(struct device *dev) 7109 { 7110 struct net_device *netdev = dev_get_drvdata(dev); 7111 struct igc_adapter *adapter = netdev_priv(netdev); 7112 7113 if (!igc_has_link(adapter)) 7114 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 7115 7116 return -EBUSY; 7117 } 7118 #endif /* CONFIG_PM */ 7119 7120 static void igc_shutdown(struct pci_dev *pdev) 7121 { 7122 bool wake; 7123 7124 __igc_shutdown(pdev, &wake, 0); 7125 7126 if (system_state == SYSTEM_POWER_OFF) { 7127 pci_wake_from_d3(pdev, wake); 7128 pci_set_power_state(pdev, PCI_D3hot); 7129 } 7130 } 7131 7132 /** 7133 * igc_io_error_detected - called when PCI error is detected 7134 * @pdev: Pointer to PCI device 7135 * @state: The current PCI connection state 7136 * 7137 * This function is called after a PCI bus error affecting 7138 * this device has been detected. 7139 **/ 7140 static pci_ers_result_t igc_io_error_detected(struct pci_dev *pdev, 7141 pci_channel_state_t state) 7142 { 7143 struct net_device *netdev = pci_get_drvdata(pdev); 7144 struct igc_adapter *adapter = netdev_priv(netdev); 7145 7146 netif_device_detach(netdev); 7147 7148 if (state == pci_channel_io_perm_failure) 7149 return PCI_ERS_RESULT_DISCONNECT; 7150 7151 if (netif_running(netdev)) 7152 igc_down(adapter); 7153 pci_disable_device(pdev); 7154 7155 /* Request a slot reset. */ 7156 return PCI_ERS_RESULT_NEED_RESET; 7157 } 7158 7159 /** 7160 * igc_io_slot_reset - called after the PCI bus has been reset. 7161 * @pdev: Pointer to PCI device 7162 * 7163 * Restart the card from scratch, as if from a cold-boot. Implementation 7164 * resembles the first-half of the igc_resume routine. 7165 **/ 7166 static pci_ers_result_t igc_io_slot_reset(struct pci_dev *pdev) 7167 { 7168 struct net_device *netdev = pci_get_drvdata(pdev); 7169 struct igc_adapter *adapter = netdev_priv(netdev); 7170 struct igc_hw *hw = &adapter->hw; 7171 pci_ers_result_t result; 7172 7173 if (pci_enable_device_mem(pdev)) { 7174 netdev_err(netdev, "Could not re-enable PCI device after reset\n"); 7175 result = PCI_ERS_RESULT_DISCONNECT; 7176 } else { 7177 pci_set_master(pdev); 7178 pci_restore_state(pdev); 7179 pci_save_state(pdev); 7180 7181 pci_enable_wake(pdev, PCI_D3hot, 0); 7182 pci_enable_wake(pdev, PCI_D3cold, 0); 7183 7184 /* In case of PCI error, adapter loses its HW address 7185 * so we should re-assign it here. 7186 */ 7187 hw->hw_addr = adapter->io_addr; 7188 7189 igc_reset(adapter); 7190 wr32(IGC_WUS, ~0); 7191 result = PCI_ERS_RESULT_RECOVERED; 7192 } 7193 7194 return result; 7195 } 7196 7197 /** 7198 * igc_io_resume - called when traffic can start to flow again. 7199 * @pdev: Pointer to PCI device 7200 * 7201 * This callback is called when the error recovery driver tells us that 7202 * its OK to resume normal operation. Implementation resembles the 7203 * second-half of the igc_resume routine. 7204 */ 7205 static void igc_io_resume(struct pci_dev *pdev) 7206 { 7207 struct net_device *netdev = pci_get_drvdata(pdev); 7208 struct igc_adapter *adapter = netdev_priv(netdev); 7209 7210 rtnl_lock(); 7211 if (netif_running(netdev)) { 7212 if (igc_open(netdev)) { 7213 netdev_err(netdev, "igc_open failed after reset\n"); 7214 return; 7215 } 7216 } 7217 7218 netif_device_attach(netdev); 7219 7220 /* let the f/w know that the h/w is now under the control of the 7221 * driver. 7222 */ 7223 igc_get_hw_control(adapter); 7224 rtnl_unlock(); 7225 } 7226 7227 static const struct pci_error_handlers igc_err_handler = { 7228 .error_detected = igc_io_error_detected, 7229 .slot_reset = igc_io_slot_reset, 7230 .resume = igc_io_resume, 7231 }; 7232 7233 #ifdef CONFIG_PM 7234 static const struct dev_pm_ops igc_pm_ops = { 7235 SET_SYSTEM_SLEEP_PM_OPS(igc_suspend, igc_resume) 7236 SET_RUNTIME_PM_OPS(igc_runtime_suspend, igc_runtime_resume, 7237 igc_runtime_idle) 7238 }; 7239 #endif 7240 7241 static struct pci_driver igc_driver = { 7242 .name = igc_driver_name, 7243 .id_table = igc_pci_tbl, 7244 .probe = igc_probe, 7245 .remove = igc_remove, 7246 #ifdef CONFIG_PM 7247 .driver.pm = &igc_pm_ops, 7248 #endif 7249 .shutdown = igc_shutdown, 7250 .err_handler = &igc_err_handler, 7251 }; 7252 7253 /** 7254 * igc_reinit_queues - return error 7255 * @adapter: pointer to adapter structure 7256 */ 7257 int igc_reinit_queues(struct igc_adapter *adapter) 7258 { 7259 struct net_device *netdev = adapter->netdev; 7260 int err = 0; 7261 7262 if (netif_running(netdev)) 7263 igc_close(netdev); 7264 7265 igc_reset_interrupt_capability(adapter); 7266 7267 if (igc_init_interrupt_scheme(adapter, true)) { 7268 netdev_err(netdev, "Unable to allocate memory for queues\n"); 7269 return -ENOMEM; 7270 } 7271 7272 if (netif_running(netdev)) 7273 err = igc_open(netdev); 7274 7275 return err; 7276 } 7277 7278 /** 7279 * igc_get_hw_dev - return device 7280 * @hw: pointer to hardware structure 7281 * 7282 * used by hardware layer to print debugging information 7283 */ 7284 struct net_device *igc_get_hw_dev(struct igc_hw *hw) 7285 { 7286 struct igc_adapter *adapter = hw->back; 7287 7288 return adapter->netdev; 7289 } 7290 7291 static void igc_disable_rx_ring_hw(struct igc_ring *ring) 7292 { 7293 struct igc_hw *hw = &ring->q_vector->adapter->hw; 7294 u8 idx = ring->reg_idx; 7295 u32 rxdctl; 7296 7297 rxdctl = rd32(IGC_RXDCTL(idx)); 7298 rxdctl &= ~IGC_RXDCTL_QUEUE_ENABLE; 7299 rxdctl |= IGC_RXDCTL_SWFLUSH; 7300 wr32(IGC_RXDCTL(idx), rxdctl); 7301 } 7302 7303 void igc_disable_rx_ring(struct igc_ring *ring) 7304 { 7305 igc_disable_rx_ring_hw(ring); 7306 igc_clean_rx_ring(ring); 7307 } 7308 7309 void igc_enable_rx_ring(struct igc_ring *ring) 7310 { 7311 struct igc_adapter *adapter = ring->q_vector->adapter; 7312 7313 igc_configure_rx_ring(adapter, ring); 7314 7315 if (ring->xsk_pool) 7316 igc_alloc_rx_buffers_zc(ring, igc_desc_unused(ring)); 7317 else 7318 igc_alloc_rx_buffers(ring, igc_desc_unused(ring)); 7319 } 7320 7321 void igc_disable_tx_ring(struct igc_ring *ring) 7322 { 7323 igc_disable_tx_ring_hw(ring); 7324 igc_clean_tx_ring(ring); 7325 } 7326 7327 void igc_enable_tx_ring(struct igc_ring *ring) 7328 { 7329 struct igc_adapter *adapter = ring->q_vector->adapter; 7330 7331 igc_configure_tx_ring(adapter, ring); 7332 } 7333 7334 /** 7335 * igc_init_module - Driver Registration Routine 7336 * 7337 * igc_init_module is the first routine called when the driver is 7338 * loaded. All it does is register with the PCI subsystem. 7339 */ 7340 static int __init igc_init_module(void) 7341 { 7342 int ret; 7343 7344 pr_info("%s\n", igc_driver_string); 7345 pr_info("%s\n", igc_copyright); 7346 7347 ret = pci_register_driver(&igc_driver); 7348 return ret; 7349 } 7350 7351 module_init(igc_init_module); 7352 7353 /** 7354 * igc_exit_module - Driver Exit Cleanup Routine 7355 * 7356 * igc_exit_module is called just before the driver is removed 7357 * from memory. 7358 */ 7359 static void __exit igc_exit_module(void) 7360 { 7361 pci_unregister_driver(&igc_driver); 7362 } 7363 7364 module_exit(igc_exit_module); 7365 /* igc_main.c */ 7366