1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #include <linux/module.h> 5 #include <linux/types.h> 6 #include <linux/if_vlan.h> 7 #include <linux/tcp.h> 8 #include <linux/udp.h> 9 #include <linux/ip.h> 10 #include <linux/pm_runtime.h> 11 #include <net/pkt_sched.h> 12 #include <linux/bpf_trace.h> 13 #include <net/xdp_sock_drv.h> 14 #include <linux/pci.h> 15 16 #include <net/ipv6.h> 17 18 #include "igc.h" 19 #include "igc_hw.h" 20 #include "igc_tsn.h" 21 #include "igc_xdp.h" 22 23 #define DRV_SUMMARY "Intel(R) 2.5G Ethernet Linux Driver" 24 25 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 26 27 #define IGC_XDP_PASS 0 28 #define IGC_XDP_CONSUMED BIT(0) 29 #define IGC_XDP_TX BIT(1) 30 #define IGC_XDP_REDIRECT BIT(2) 31 32 static int debug = -1; 33 34 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 35 MODULE_DESCRIPTION(DRV_SUMMARY); 36 MODULE_LICENSE("GPL v2"); 37 module_param(debug, int, 0); 38 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 39 40 char igc_driver_name[] = "igc"; 41 static const char igc_driver_string[] = DRV_SUMMARY; 42 static const char igc_copyright[] = 43 "Copyright(c) 2018 Intel Corporation."; 44 45 static const struct igc_info *igc_info_tbl[] = { 46 [board_base] = &igc_base_info, 47 }; 48 49 static const struct pci_device_id igc_pci_tbl[] = { 50 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LM), board_base }, 51 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_V), board_base }, 52 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_I), board_base }, 53 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I220_V), board_base }, 54 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_K), board_base }, 55 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_K2), board_base }, 56 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_K), board_base }, 57 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LMVP), board_base }, 58 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_LMVP), board_base }, 59 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_IT), board_base }, 60 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_LM), board_base }, 61 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_V), board_base }, 62 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_IT), board_base }, 63 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I221_V), board_base }, 64 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_BLANK_NVM), board_base }, 65 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_BLANK_NVM), board_base }, 66 /* required last entry */ 67 {0, } 68 }; 69 70 MODULE_DEVICE_TABLE(pci, igc_pci_tbl); 71 72 enum latency_range { 73 lowest_latency = 0, 74 low_latency = 1, 75 bulk_latency = 2, 76 latency_invalid = 255 77 }; 78 79 void igc_reset(struct igc_adapter *adapter) 80 { 81 struct net_device *dev = adapter->netdev; 82 struct igc_hw *hw = &adapter->hw; 83 struct igc_fc_info *fc = &hw->fc; 84 u32 pba, hwm; 85 86 /* Repartition PBA for greater than 9k MTU if required */ 87 pba = IGC_PBA_34K; 88 89 /* flow control settings 90 * The high water mark must be low enough to fit one full frame 91 * after transmitting the pause frame. As such we must have enough 92 * space to allow for us to complete our current transmit and then 93 * receive the frame that is in progress from the link partner. 94 * Set it to: 95 * - the full Rx FIFO size minus one full Tx plus one full Rx frame 96 */ 97 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE); 98 99 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 100 fc->low_water = fc->high_water - 16; 101 fc->pause_time = 0xFFFF; 102 fc->send_xon = 1; 103 fc->current_mode = fc->requested_mode; 104 105 hw->mac.ops.reset_hw(hw); 106 107 if (hw->mac.ops.init_hw(hw)) 108 netdev_err(dev, "Error on hardware initialization\n"); 109 110 /* Re-establish EEE setting */ 111 igc_set_eee_i225(hw, true, true, true); 112 113 if (!netif_running(adapter->netdev)) 114 igc_power_down_phy_copper_base(&adapter->hw); 115 116 /* Enable HW to recognize an 802.1Q VLAN Ethernet packet */ 117 wr32(IGC_VET, ETH_P_8021Q); 118 119 /* Re-enable PTP, where applicable. */ 120 igc_ptp_reset(adapter); 121 122 /* Re-enable TSN offloading, where applicable. */ 123 igc_tsn_reset(adapter); 124 125 igc_get_phy_info(hw); 126 } 127 128 /** 129 * igc_power_up_link - Power up the phy link 130 * @adapter: address of board private structure 131 */ 132 static void igc_power_up_link(struct igc_adapter *adapter) 133 { 134 igc_reset_phy(&adapter->hw); 135 136 igc_power_up_phy_copper(&adapter->hw); 137 138 igc_setup_link(&adapter->hw); 139 } 140 141 /** 142 * igc_release_hw_control - release control of the h/w to f/w 143 * @adapter: address of board private structure 144 * 145 * igc_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 146 * For ASF and Pass Through versions of f/w this means that the 147 * driver is no longer loaded. 148 */ 149 static void igc_release_hw_control(struct igc_adapter *adapter) 150 { 151 struct igc_hw *hw = &adapter->hw; 152 u32 ctrl_ext; 153 154 if (!pci_device_is_present(adapter->pdev)) 155 return; 156 157 /* Let firmware take over control of h/w */ 158 ctrl_ext = rd32(IGC_CTRL_EXT); 159 wr32(IGC_CTRL_EXT, 160 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD); 161 } 162 163 /** 164 * igc_get_hw_control - get control of the h/w from f/w 165 * @adapter: address of board private structure 166 * 167 * igc_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 168 * For ASF and Pass Through versions of f/w this means that 169 * the driver is loaded. 170 */ 171 static void igc_get_hw_control(struct igc_adapter *adapter) 172 { 173 struct igc_hw *hw = &adapter->hw; 174 u32 ctrl_ext; 175 176 /* Let firmware know the driver has taken over */ 177 ctrl_ext = rd32(IGC_CTRL_EXT); 178 wr32(IGC_CTRL_EXT, 179 ctrl_ext | IGC_CTRL_EXT_DRV_LOAD); 180 } 181 182 static void igc_unmap_tx_buffer(struct device *dev, struct igc_tx_buffer *buf) 183 { 184 dma_unmap_single(dev, dma_unmap_addr(buf, dma), 185 dma_unmap_len(buf, len), DMA_TO_DEVICE); 186 187 dma_unmap_len_set(buf, len, 0); 188 } 189 190 /** 191 * igc_clean_tx_ring - Free Tx Buffers 192 * @tx_ring: ring to be cleaned 193 */ 194 static void igc_clean_tx_ring(struct igc_ring *tx_ring) 195 { 196 u16 i = tx_ring->next_to_clean; 197 struct igc_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 198 u32 xsk_frames = 0; 199 200 while (i != tx_ring->next_to_use) { 201 union igc_adv_tx_desc *eop_desc, *tx_desc; 202 203 switch (tx_buffer->type) { 204 case IGC_TX_BUFFER_TYPE_XSK: 205 xsk_frames++; 206 break; 207 case IGC_TX_BUFFER_TYPE_XDP: 208 xdp_return_frame(tx_buffer->xdpf); 209 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 210 break; 211 case IGC_TX_BUFFER_TYPE_SKB: 212 dev_kfree_skb_any(tx_buffer->skb); 213 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 214 break; 215 default: 216 netdev_warn_once(tx_ring->netdev, "Unknown Tx buffer type\n"); 217 break; 218 } 219 220 /* check for eop_desc to determine the end of the packet */ 221 eop_desc = tx_buffer->next_to_watch; 222 tx_desc = IGC_TX_DESC(tx_ring, i); 223 224 /* unmap remaining buffers */ 225 while (tx_desc != eop_desc) { 226 tx_buffer++; 227 tx_desc++; 228 i++; 229 if (unlikely(i == tx_ring->count)) { 230 i = 0; 231 tx_buffer = tx_ring->tx_buffer_info; 232 tx_desc = IGC_TX_DESC(tx_ring, 0); 233 } 234 235 /* unmap any remaining paged data */ 236 if (dma_unmap_len(tx_buffer, len)) 237 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 238 } 239 240 tx_buffer->next_to_watch = NULL; 241 242 /* move us one more past the eop_desc for start of next pkt */ 243 tx_buffer++; 244 i++; 245 if (unlikely(i == tx_ring->count)) { 246 i = 0; 247 tx_buffer = tx_ring->tx_buffer_info; 248 } 249 } 250 251 if (tx_ring->xsk_pool && xsk_frames) 252 xsk_tx_completed(tx_ring->xsk_pool, xsk_frames); 253 254 /* reset BQL for queue */ 255 netdev_tx_reset_queue(txring_txq(tx_ring)); 256 257 /* reset next_to_use and next_to_clean */ 258 tx_ring->next_to_use = 0; 259 tx_ring->next_to_clean = 0; 260 } 261 262 /** 263 * igc_free_tx_resources - Free Tx Resources per Queue 264 * @tx_ring: Tx descriptor ring for a specific queue 265 * 266 * Free all transmit software resources 267 */ 268 void igc_free_tx_resources(struct igc_ring *tx_ring) 269 { 270 igc_clean_tx_ring(tx_ring); 271 272 vfree(tx_ring->tx_buffer_info); 273 tx_ring->tx_buffer_info = NULL; 274 275 /* if not set, then don't free */ 276 if (!tx_ring->desc) 277 return; 278 279 dma_free_coherent(tx_ring->dev, tx_ring->size, 280 tx_ring->desc, tx_ring->dma); 281 282 tx_ring->desc = NULL; 283 } 284 285 /** 286 * igc_free_all_tx_resources - Free Tx Resources for All Queues 287 * @adapter: board private structure 288 * 289 * Free all transmit software resources 290 */ 291 static void igc_free_all_tx_resources(struct igc_adapter *adapter) 292 { 293 int i; 294 295 for (i = 0; i < adapter->num_tx_queues; i++) 296 igc_free_tx_resources(adapter->tx_ring[i]); 297 } 298 299 /** 300 * igc_clean_all_tx_rings - Free Tx Buffers for all queues 301 * @adapter: board private structure 302 */ 303 static void igc_clean_all_tx_rings(struct igc_adapter *adapter) 304 { 305 int i; 306 307 for (i = 0; i < adapter->num_tx_queues; i++) 308 if (adapter->tx_ring[i]) 309 igc_clean_tx_ring(adapter->tx_ring[i]); 310 } 311 312 /** 313 * igc_setup_tx_resources - allocate Tx resources (Descriptors) 314 * @tx_ring: tx descriptor ring (for a specific queue) to setup 315 * 316 * Return 0 on success, negative on failure 317 */ 318 int igc_setup_tx_resources(struct igc_ring *tx_ring) 319 { 320 struct net_device *ndev = tx_ring->netdev; 321 struct device *dev = tx_ring->dev; 322 int size = 0; 323 324 size = sizeof(struct igc_tx_buffer) * tx_ring->count; 325 tx_ring->tx_buffer_info = vzalloc(size); 326 if (!tx_ring->tx_buffer_info) 327 goto err; 328 329 /* round up to nearest 4K */ 330 tx_ring->size = tx_ring->count * sizeof(union igc_adv_tx_desc); 331 tx_ring->size = ALIGN(tx_ring->size, 4096); 332 333 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 334 &tx_ring->dma, GFP_KERNEL); 335 336 if (!tx_ring->desc) 337 goto err; 338 339 tx_ring->next_to_use = 0; 340 tx_ring->next_to_clean = 0; 341 342 return 0; 343 344 err: 345 vfree(tx_ring->tx_buffer_info); 346 netdev_err(ndev, "Unable to allocate memory for Tx descriptor ring\n"); 347 return -ENOMEM; 348 } 349 350 /** 351 * igc_setup_all_tx_resources - wrapper to allocate Tx resources for all queues 352 * @adapter: board private structure 353 * 354 * Return 0 on success, negative on failure 355 */ 356 static int igc_setup_all_tx_resources(struct igc_adapter *adapter) 357 { 358 struct net_device *dev = adapter->netdev; 359 int i, err = 0; 360 361 for (i = 0; i < adapter->num_tx_queues; i++) { 362 err = igc_setup_tx_resources(adapter->tx_ring[i]); 363 if (err) { 364 netdev_err(dev, "Error on Tx queue %u setup\n", i); 365 for (i--; i >= 0; i--) 366 igc_free_tx_resources(adapter->tx_ring[i]); 367 break; 368 } 369 } 370 371 return err; 372 } 373 374 static void igc_clean_rx_ring_page_shared(struct igc_ring *rx_ring) 375 { 376 u16 i = rx_ring->next_to_clean; 377 378 dev_kfree_skb(rx_ring->skb); 379 rx_ring->skb = NULL; 380 381 /* Free all the Rx ring sk_buffs */ 382 while (i != rx_ring->next_to_alloc) { 383 struct igc_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 384 385 /* Invalidate cache lines that may have been written to by 386 * device so that we avoid corrupting memory. 387 */ 388 dma_sync_single_range_for_cpu(rx_ring->dev, 389 buffer_info->dma, 390 buffer_info->page_offset, 391 igc_rx_bufsz(rx_ring), 392 DMA_FROM_DEVICE); 393 394 /* free resources associated with mapping */ 395 dma_unmap_page_attrs(rx_ring->dev, 396 buffer_info->dma, 397 igc_rx_pg_size(rx_ring), 398 DMA_FROM_DEVICE, 399 IGC_RX_DMA_ATTR); 400 __page_frag_cache_drain(buffer_info->page, 401 buffer_info->pagecnt_bias); 402 403 i++; 404 if (i == rx_ring->count) 405 i = 0; 406 } 407 } 408 409 static void igc_clean_rx_ring_xsk_pool(struct igc_ring *ring) 410 { 411 struct igc_rx_buffer *bi; 412 u16 i; 413 414 for (i = 0; i < ring->count; i++) { 415 bi = &ring->rx_buffer_info[i]; 416 if (!bi->xdp) 417 continue; 418 419 xsk_buff_free(bi->xdp); 420 bi->xdp = NULL; 421 } 422 } 423 424 /** 425 * igc_clean_rx_ring - Free Rx Buffers per Queue 426 * @ring: ring to free buffers from 427 */ 428 static void igc_clean_rx_ring(struct igc_ring *ring) 429 { 430 if (ring->xsk_pool) 431 igc_clean_rx_ring_xsk_pool(ring); 432 else 433 igc_clean_rx_ring_page_shared(ring); 434 435 clear_ring_uses_large_buffer(ring); 436 437 ring->next_to_alloc = 0; 438 ring->next_to_clean = 0; 439 ring->next_to_use = 0; 440 } 441 442 /** 443 * igc_clean_all_rx_rings - Free Rx Buffers for all queues 444 * @adapter: board private structure 445 */ 446 static void igc_clean_all_rx_rings(struct igc_adapter *adapter) 447 { 448 int i; 449 450 for (i = 0; i < adapter->num_rx_queues; i++) 451 if (adapter->rx_ring[i]) 452 igc_clean_rx_ring(adapter->rx_ring[i]); 453 } 454 455 /** 456 * igc_free_rx_resources - Free Rx Resources 457 * @rx_ring: ring to clean the resources from 458 * 459 * Free all receive software resources 460 */ 461 void igc_free_rx_resources(struct igc_ring *rx_ring) 462 { 463 igc_clean_rx_ring(rx_ring); 464 465 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 466 467 vfree(rx_ring->rx_buffer_info); 468 rx_ring->rx_buffer_info = NULL; 469 470 /* if not set, then don't free */ 471 if (!rx_ring->desc) 472 return; 473 474 dma_free_coherent(rx_ring->dev, rx_ring->size, 475 rx_ring->desc, rx_ring->dma); 476 477 rx_ring->desc = NULL; 478 } 479 480 /** 481 * igc_free_all_rx_resources - Free Rx Resources for All Queues 482 * @adapter: board private structure 483 * 484 * Free all receive software resources 485 */ 486 static void igc_free_all_rx_resources(struct igc_adapter *adapter) 487 { 488 int i; 489 490 for (i = 0; i < adapter->num_rx_queues; i++) 491 igc_free_rx_resources(adapter->rx_ring[i]); 492 } 493 494 /** 495 * igc_setup_rx_resources - allocate Rx resources (Descriptors) 496 * @rx_ring: rx descriptor ring (for a specific queue) to setup 497 * 498 * Returns 0 on success, negative on failure 499 */ 500 int igc_setup_rx_resources(struct igc_ring *rx_ring) 501 { 502 struct net_device *ndev = rx_ring->netdev; 503 struct device *dev = rx_ring->dev; 504 u8 index = rx_ring->queue_index; 505 int size, desc_len, res; 506 507 /* XDP RX-queue info */ 508 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 509 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 510 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, ndev, index, 511 rx_ring->q_vector->napi.napi_id); 512 if (res < 0) { 513 netdev_err(ndev, "Failed to register xdp_rxq index %u\n", 514 index); 515 return res; 516 } 517 518 size = sizeof(struct igc_rx_buffer) * rx_ring->count; 519 rx_ring->rx_buffer_info = vzalloc(size); 520 if (!rx_ring->rx_buffer_info) 521 goto err; 522 523 desc_len = sizeof(union igc_adv_rx_desc); 524 525 /* Round up to nearest 4K */ 526 rx_ring->size = rx_ring->count * desc_len; 527 rx_ring->size = ALIGN(rx_ring->size, 4096); 528 529 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 530 &rx_ring->dma, GFP_KERNEL); 531 532 if (!rx_ring->desc) 533 goto err; 534 535 rx_ring->next_to_alloc = 0; 536 rx_ring->next_to_clean = 0; 537 rx_ring->next_to_use = 0; 538 539 return 0; 540 541 err: 542 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 543 vfree(rx_ring->rx_buffer_info); 544 rx_ring->rx_buffer_info = NULL; 545 netdev_err(ndev, "Unable to allocate memory for Rx descriptor ring\n"); 546 return -ENOMEM; 547 } 548 549 /** 550 * igc_setup_all_rx_resources - wrapper to allocate Rx resources 551 * (Descriptors) for all queues 552 * @adapter: board private structure 553 * 554 * Return 0 on success, negative on failure 555 */ 556 static int igc_setup_all_rx_resources(struct igc_adapter *adapter) 557 { 558 struct net_device *dev = adapter->netdev; 559 int i, err = 0; 560 561 for (i = 0; i < adapter->num_rx_queues; i++) { 562 err = igc_setup_rx_resources(adapter->rx_ring[i]); 563 if (err) { 564 netdev_err(dev, "Error on Rx queue %u setup\n", i); 565 for (i--; i >= 0; i--) 566 igc_free_rx_resources(adapter->rx_ring[i]); 567 break; 568 } 569 } 570 571 return err; 572 } 573 574 static struct xsk_buff_pool *igc_get_xsk_pool(struct igc_adapter *adapter, 575 struct igc_ring *ring) 576 { 577 if (!igc_xdp_is_enabled(adapter) || 578 !test_bit(IGC_RING_FLAG_AF_XDP_ZC, &ring->flags)) 579 return NULL; 580 581 return xsk_get_pool_from_qid(ring->netdev, ring->queue_index); 582 } 583 584 /** 585 * igc_configure_rx_ring - Configure a receive ring after Reset 586 * @adapter: board private structure 587 * @ring: receive ring to be configured 588 * 589 * Configure the Rx unit of the MAC after a reset. 590 */ 591 static void igc_configure_rx_ring(struct igc_adapter *adapter, 592 struct igc_ring *ring) 593 { 594 struct igc_hw *hw = &adapter->hw; 595 union igc_adv_rx_desc *rx_desc; 596 int reg_idx = ring->reg_idx; 597 u32 srrctl = 0, rxdctl = 0; 598 u64 rdba = ring->dma; 599 u32 buf_size; 600 601 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 602 ring->xsk_pool = igc_get_xsk_pool(adapter, ring); 603 if (ring->xsk_pool) { 604 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 605 MEM_TYPE_XSK_BUFF_POOL, 606 NULL)); 607 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 608 } else { 609 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 610 MEM_TYPE_PAGE_SHARED, 611 NULL)); 612 } 613 614 if (igc_xdp_is_enabled(adapter)) 615 set_ring_uses_large_buffer(ring); 616 617 /* disable the queue */ 618 wr32(IGC_RXDCTL(reg_idx), 0); 619 620 /* Set DMA base address registers */ 621 wr32(IGC_RDBAL(reg_idx), 622 rdba & 0x00000000ffffffffULL); 623 wr32(IGC_RDBAH(reg_idx), rdba >> 32); 624 wr32(IGC_RDLEN(reg_idx), 625 ring->count * sizeof(union igc_adv_rx_desc)); 626 627 /* initialize head and tail */ 628 ring->tail = adapter->io_addr + IGC_RDT(reg_idx); 629 wr32(IGC_RDH(reg_idx), 0); 630 writel(0, ring->tail); 631 632 /* reset next-to- use/clean to place SW in sync with hardware */ 633 ring->next_to_clean = 0; 634 ring->next_to_use = 0; 635 636 if (ring->xsk_pool) 637 buf_size = xsk_pool_get_rx_frame_size(ring->xsk_pool); 638 else if (ring_uses_large_buffer(ring)) 639 buf_size = IGC_RXBUFFER_3072; 640 else 641 buf_size = IGC_RXBUFFER_2048; 642 643 srrctl = IGC_RX_HDR_LEN << IGC_SRRCTL_BSIZEHDRSIZE_SHIFT; 644 srrctl |= buf_size >> IGC_SRRCTL_BSIZEPKT_SHIFT; 645 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF; 646 647 wr32(IGC_SRRCTL(reg_idx), srrctl); 648 649 rxdctl |= IGC_RX_PTHRESH; 650 rxdctl |= IGC_RX_HTHRESH << 8; 651 rxdctl |= IGC_RX_WTHRESH << 16; 652 653 /* initialize rx_buffer_info */ 654 memset(ring->rx_buffer_info, 0, 655 sizeof(struct igc_rx_buffer) * ring->count); 656 657 /* initialize Rx descriptor 0 */ 658 rx_desc = IGC_RX_DESC(ring, 0); 659 rx_desc->wb.upper.length = 0; 660 661 /* enable receive descriptor fetching */ 662 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE; 663 664 wr32(IGC_RXDCTL(reg_idx), rxdctl); 665 } 666 667 /** 668 * igc_configure_rx - Configure receive Unit after Reset 669 * @adapter: board private structure 670 * 671 * Configure the Rx unit of the MAC after a reset. 672 */ 673 static void igc_configure_rx(struct igc_adapter *adapter) 674 { 675 int i; 676 677 /* Setup the HW Rx Head and Tail Descriptor Pointers and 678 * the Base and Length of the Rx Descriptor Ring 679 */ 680 for (i = 0; i < adapter->num_rx_queues; i++) 681 igc_configure_rx_ring(adapter, adapter->rx_ring[i]); 682 } 683 684 /** 685 * igc_configure_tx_ring - Configure transmit ring after Reset 686 * @adapter: board private structure 687 * @ring: tx ring to configure 688 * 689 * Configure a transmit ring after a reset. 690 */ 691 static void igc_configure_tx_ring(struct igc_adapter *adapter, 692 struct igc_ring *ring) 693 { 694 struct igc_hw *hw = &adapter->hw; 695 int reg_idx = ring->reg_idx; 696 u64 tdba = ring->dma; 697 u32 txdctl = 0; 698 699 ring->xsk_pool = igc_get_xsk_pool(adapter, ring); 700 701 /* disable the queue */ 702 wr32(IGC_TXDCTL(reg_idx), 0); 703 wrfl(); 704 mdelay(10); 705 706 wr32(IGC_TDLEN(reg_idx), 707 ring->count * sizeof(union igc_adv_tx_desc)); 708 wr32(IGC_TDBAL(reg_idx), 709 tdba & 0x00000000ffffffffULL); 710 wr32(IGC_TDBAH(reg_idx), tdba >> 32); 711 712 ring->tail = adapter->io_addr + IGC_TDT(reg_idx); 713 wr32(IGC_TDH(reg_idx), 0); 714 writel(0, ring->tail); 715 716 txdctl |= IGC_TX_PTHRESH; 717 txdctl |= IGC_TX_HTHRESH << 8; 718 txdctl |= IGC_TX_WTHRESH << 16; 719 720 txdctl |= IGC_TXDCTL_QUEUE_ENABLE; 721 wr32(IGC_TXDCTL(reg_idx), txdctl); 722 } 723 724 /** 725 * igc_configure_tx - Configure transmit Unit after Reset 726 * @adapter: board private structure 727 * 728 * Configure the Tx unit of the MAC after a reset. 729 */ 730 static void igc_configure_tx(struct igc_adapter *adapter) 731 { 732 int i; 733 734 for (i = 0; i < adapter->num_tx_queues; i++) 735 igc_configure_tx_ring(adapter, adapter->tx_ring[i]); 736 } 737 738 /** 739 * igc_setup_mrqc - configure the multiple receive queue control registers 740 * @adapter: Board private structure 741 */ 742 static void igc_setup_mrqc(struct igc_adapter *adapter) 743 { 744 struct igc_hw *hw = &adapter->hw; 745 u32 j, num_rx_queues; 746 u32 mrqc, rxcsum; 747 u32 rss_key[10]; 748 749 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 750 for (j = 0; j < 10; j++) 751 wr32(IGC_RSSRK(j), rss_key[j]); 752 753 num_rx_queues = adapter->rss_queues; 754 755 if (adapter->rss_indir_tbl_init != num_rx_queues) { 756 for (j = 0; j < IGC_RETA_SIZE; j++) 757 adapter->rss_indir_tbl[j] = 758 (j * num_rx_queues) / IGC_RETA_SIZE; 759 adapter->rss_indir_tbl_init = num_rx_queues; 760 } 761 igc_write_rss_indir_tbl(adapter); 762 763 /* Disable raw packet checksumming so that RSS hash is placed in 764 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 765 * offloads as they are enabled by default 766 */ 767 rxcsum = rd32(IGC_RXCSUM); 768 rxcsum |= IGC_RXCSUM_PCSD; 769 770 /* Enable Receive Checksum Offload for SCTP */ 771 rxcsum |= IGC_RXCSUM_CRCOFL; 772 773 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 774 wr32(IGC_RXCSUM, rxcsum); 775 776 /* Generate RSS hash based on packet types, TCP/UDP 777 * port numbers and/or IPv4/v6 src and dst addresses 778 */ 779 mrqc = IGC_MRQC_RSS_FIELD_IPV4 | 780 IGC_MRQC_RSS_FIELD_IPV4_TCP | 781 IGC_MRQC_RSS_FIELD_IPV6 | 782 IGC_MRQC_RSS_FIELD_IPV6_TCP | 783 IGC_MRQC_RSS_FIELD_IPV6_TCP_EX; 784 785 if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV4_UDP) 786 mrqc |= IGC_MRQC_RSS_FIELD_IPV4_UDP; 787 if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV6_UDP) 788 mrqc |= IGC_MRQC_RSS_FIELD_IPV6_UDP; 789 790 mrqc |= IGC_MRQC_ENABLE_RSS_MQ; 791 792 wr32(IGC_MRQC, mrqc); 793 } 794 795 /** 796 * igc_setup_rctl - configure the receive control registers 797 * @adapter: Board private structure 798 */ 799 static void igc_setup_rctl(struct igc_adapter *adapter) 800 { 801 struct igc_hw *hw = &adapter->hw; 802 u32 rctl; 803 804 rctl = rd32(IGC_RCTL); 805 806 rctl &= ~(3 << IGC_RCTL_MO_SHIFT); 807 rctl &= ~(IGC_RCTL_LBM_TCVR | IGC_RCTL_LBM_MAC); 808 809 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | IGC_RCTL_RDMTS_HALF | 810 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT); 811 812 /* enable stripping of CRC. Newer features require 813 * that the HW strips the CRC. 814 */ 815 rctl |= IGC_RCTL_SECRC; 816 817 /* disable store bad packets and clear size bits. */ 818 rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_SZ_256); 819 820 /* enable LPE to allow for reception of jumbo frames */ 821 rctl |= IGC_RCTL_LPE; 822 823 /* disable queue 0 to prevent tail write w/o re-config */ 824 wr32(IGC_RXDCTL(0), 0); 825 826 /* This is useful for sniffing bad packets. */ 827 if (adapter->netdev->features & NETIF_F_RXALL) { 828 /* UPE and MPE will be handled by normal PROMISC logic 829 * in set_rx_mode 830 */ 831 rctl |= (IGC_RCTL_SBP | /* Receive bad packets */ 832 IGC_RCTL_BAM | /* RX All Bcast Pkts */ 833 IGC_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 834 835 rctl &= ~(IGC_RCTL_DPF | /* Allow filtered pause */ 836 IGC_RCTL_CFIEN); /* Disable VLAN CFIEN Filter */ 837 } 838 839 wr32(IGC_RCTL, rctl); 840 } 841 842 /** 843 * igc_setup_tctl - configure the transmit control registers 844 * @adapter: Board private structure 845 */ 846 static void igc_setup_tctl(struct igc_adapter *adapter) 847 { 848 struct igc_hw *hw = &adapter->hw; 849 u32 tctl; 850 851 /* disable queue 0 which icould be enabled by default */ 852 wr32(IGC_TXDCTL(0), 0); 853 854 /* Program the Transmit Control Register */ 855 tctl = rd32(IGC_TCTL); 856 tctl &= ~IGC_TCTL_CT; 857 tctl |= IGC_TCTL_PSP | IGC_TCTL_RTLC | 858 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT); 859 860 /* Enable transmits */ 861 tctl |= IGC_TCTL_EN; 862 863 wr32(IGC_TCTL, tctl); 864 } 865 866 /** 867 * igc_set_mac_filter_hw() - Set MAC address filter in hardware 868 * @adapter: Pointer to adapter where the filter should be set 869 * @index: Filter index 870 * @type: MAC address filter type (source or destination) 871 * @addr: MAC address 872 * @queue: If non-negative, queue assignment feature is enabled and frames 873 * matching the filter are enqueued onto 'queue'. Otherwise, queue 874 * assignment is disabled. 875 */ 876 static void igc_set_mac_filter_hw(struct igc_adapter *adapter, int index, 877 enum igc_mac_filter_type type, 878 const u8 *addr, int queue) 879 { 880 struct net_device *dev = adapter->netdev; 881 struct igc_hw *hw = &adapter->hw; 882 u32 ral, rah; 883 884 if (WARN_ON(index >= hw->mac.rar_entry_count)) 885 return; 886 887 ral = le32_to_cpup((__le32 *)(addr)); 888 rah = le16_to_cpup((__le16 *)(addr + 4)); 889 890 if (type == IGC_MAC_FILTER_TYPE_SRC) { 891 rah &= ~IGC_RAH_ASEL_MASK; 892 rah |= IGC_RAH_ASEL_SRC_ADDR; 893 } 894 895 if (queue >= 0) { 896 rah &= ~IGC_RAH_QSEL_MASK; 897 rah |= (queue << IGC_RAH_QSEL_SHIFT); 898 rah |= IGC_RAH_QSEL_ENABLE; 899 } 900 901 rah |= IGC_RAH_AV; 902 903 wr32(IGC_RAL(index), ral); 904 wr32(IGC_RAH(index), rah); 905 906 netdev_dbg(dev, "MAC address filter set in HW: index %d", index); 907 } 908 909 /** 910 * igc_clear_mac_filter_hw() - Clear MAC address filter in hardware 911 * @adapter: Pointer to adapter where the filter should be cleared 912 * @index: Filter index 913 */ 914 static void igc_clear_mac_filter_hw(struct igc_adapter *adapter, int index) 915 { 916 struct net_device *dev = adapter->netdev; 917 struct igc_hw *hw = &adapter->hw; 918 919 if (WARN_ON(index >= hw->mac.rar_entry_count)) 920 return; 921 922 wr32(IGC_RAL(index), 0); 923 wr32(IGC_RAH(index), 0); 924 925 netdev_dbg(dev, "MAC address filter cleared in HW: index %d", index); 926 } 927 928 /* Set default MAC address for the PF in the first RAR entry */ 929 static void igc_set_default_mac_filter(struct igc_adapter *adapter) 930 { 931 struct net_device *dev = adapter->netdev; 932 u8 *addr = adapter->hw.mac.addr; 933 934 netdev_dbg(dev, "Set default MAC address filter: address %pM", addr); 935 936 igc_set_mac_filter_hw(adapter, 0, IGC_MAC_FILTER_TYPE_DST, addr, -1); 937 } 938 939 /** 940 * igc_set_mac - Change the Ethernet Address of the NIC 941 * @netdev: network interface device structure 942 * @p: pointer to an address structure 943 * 944 * Returns 0 on success, negative on failure 945 */ 946 static int igc_set_mac(struct net_device *netdev, void *p) 947 { 948 struct igc_adapter *adapter = netdev_priv(netdev); 949 struct igc_hw *hw = &adapter->hw; 950 struct sockaddr *addr = p; 951 952 if (!is_valid_ether_addr(addr->sa_data)) 953 return -EADDRNOTAVAIL; 954 955 eth_hw_addr_set(netdev, addr->sa_data); 956 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 957 958 /* set the correct pool for the new PF MAC address in entry 0 */ 959 igc_set_default_mac_filter(adapter); 960 961 return 0; 962 } 963 964 /** 965 * igc_write_mc_addr_list - write multicast addresses to MTA 966 * @netdev: network interface device structure 967 * 968 * Writes multicast address list to the MTA hash table. 969 * Returns: -ENOMEM on failure 970 * 0 on no addresses written 971 * X on writing X addresses to MTA 972 **/ 973 static int igc_write_mc_addr_list(struct net_device *netdev) 974 { 975 struct igc_adapter *adapter = netdev_priv(netdev); 976 struct igc_hw *hw = &adapter->hw; 977 struct netdev_hw_addr *ha; 978 u8 *mta_list; 979 int i; 980 981 if (netdev_mc_empty(netdev)) { 982 /* nothing to program, so clear mc list */ 983 igc_update_mc_addr_list(hw, NULL, 0); 984 return 0; 985 } 986 987 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC); 988 if (!mta_list) 989 return -ENOMEM; 990 991 /* The shared function expects a packed array of only addresses. */ 992 i = 0; 993 netdev_for_each_mc_addr(ha, netdev) 994 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 995 996 igc_update_mc_addr_list(hw, mta_list, i); 997 kfree(mta_list); 998 999 return netdev_mc_count(netdev); 1000 } 1001 1002 static __le32 igc_tx_launchtime(struct igc_ring *ring, ktime_t txtime, 1003 bool *first_flag, bool *insert_empty) 1004 { 1005 struct igc_adapter *adapter = netdev_priv(ring->netdev); 1006 ktime_t cycle_time = adapter->cycle_time; 1007 ktime_t base_time = adapter->base_time; 1008 ktime_t now = ktime_get_clocktai(); 1009 ktime_t baset_est, end_of_cycle; 1010 u32 launchtime; 1011 s64 n; 1012 1013 n = div64_s64(ktime_sub_ns(now, base_time), cycle_time); 1014 1015 baset_est = ktime_add_ns(base_time, cycle_time * (n)); 1016 end_of_cycle = ktime_add_ns(baset_est, cycle_time); 1017 1018 if (ktime_compare(txtime, end_of_cycle) >= 0) { 1019 if (baset_est != ring->last_ff_cycle) { 1020 *first_flag = true; 1021 ring->last_ff_cycle = baset_est; 1022 1023 if (ktime_compare(txtime, ring->last_tx_cycle) > 0) 1024 *insert_empty = true; 1025 } 1026 } 1027 1028 /* Introducing a window at end of cycle on which packets 1029 * potentially not honor launchtime. Window of 5us chosen 1030 * considering software update the tail pointer and packets 1031 * are dma'ed to packet buffer. 1032 */ 1033 if ((ktime_sub_ns(end_of_cycle, now) < 5 * NSEC_PER_USEC)) 1034 netdev_warn(ring->netdev, "Packet with txtime=%llu may not be honoured\n", 1035 txtime); 1036 1037 ring->last_tx_cycle = end_of_cycle; 1038 1039 launchtime = ktime_sub_ns(txtime, baset_est); 1040 if (launchtime > 0) 1041 div_s64_rem(launchtime, cycle_time, &launchtime); 1042 else 1043 launchtime = 0; 1044 1045 return cpu_to_le32(launchtime); 1046 } 1047 1048 static int igc_init_empty_frame(struct igc_ring *ring, 1049 struct igc_tx_buffer *buffer, 1050 struct sk_buff *skb) 1051 { 1052 unsigned int size; 1053 dma_addr_t dma; 1054 1055 size = skb_headlen(skb); 1056 1057 dma = dma_map_single(ring->dev, skb->data, size, DMA_TO_DEVICE); 1058 if (dma_mapping_error(ring->dev, dma)) { 1059 netdev_err_once(ring->netdev, "Failed to map DMA for TX\n"); 1060 return -ENOMEM; 1061 } 1062 1063 buffer->skb = skb; 1064 buffer->protocol = 0; 1065 buffer->bytecount = skb->len; 1066 buffer->gso_segs = 1; 1067 buffer->time_stamp = jiffies; 1068 dma_unmap_len_set(buffer, len, skb->len); 1069 dma_unmap_addr_set(buffer, dma, dma); 1070 1071 return 0; 1072 } 1073 1074 static int igc_init_tx_empty_descriptor(struct igc_ring *ring, 1075 struct sk_buff *skb, 1076 struct igc_tx_buffer *first) 1077 { 1078 union igc_adv_tx_desc *desc; 1079 u32 cmd_type, olinfo_status; 1080 int err; 1081 1082 if (!igc_desc_unused(ring)) 1083 return -EBUSY; 1084 1085 err = igc_init_empty_frame(ring, first, skb); 1086 if (err) 1087 return err; 1088 1089 cmd_type = IGC_ADVTXD_DTYP_DATA | IGC_ADVTXD_DCMD_DEXT | 1090 IGC_ADVTXD_DCMD_IFCS | IGC_TXD_DCMD | 1091 first->bytecount; 1092 olinfo_status = first->bytecount << IGC_ADVTXD_PAYLEN_SHIFT; 1093 1094 desc = IGC_TX_DESC(ring, ring->next_to_use); 1095 desc->read.cmd_type_len = cpu_to_le32(cmd_type); 1096 desc->read.olinfo_status = cpu_to_le32(olinfo_status); 1097 desc->read.buffer_addr = cpu_to_le64(dma_unmap_addr(first, dma)); 1098 1099 netdev_tx_sent_queue(txring_txq(ring), skb->len); 1100 1101 first->next_to_watch = desc; 1102 1103 ring->next_to_use++; 1104 if (ring->next_to_use == ring->count) 1105 ring->next_to_use = 0; 1106 1107 return 0; 1108 } 1109 1110 #define IGC_EMPTY_FRAME_SIZE 60 1111 1112 static void igc_tx_ctxtdesc(struct igc_ring *tx_ring, 1113 __le32 launch_time, bool first_flag, 1114 u32 vlan_macip_lens, u32 type_tucmd, 1115 u32 mss_l4len_idx) 1116 { 1117 struct igc_adv_tx_context_desc *context_desc; 1118 u16 i = tx_ring->next_to_use; 1119 1120 context_desc = IGC_TX_CTXTDESC(tx_ring, i); 1121 1122 i++; 1123 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 1124 1125 /* set bits to identify this as an advanced context descriptor */ 1126 type_tucmd |= IGC_TXD_CMD_DEXT | IGC_ADVTXD_DTYP_CTXT; 1127 1128 /* For i225, context index must be unique per ring. */ 1129 if (test_bit(IGC_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 1130 mss_l4len_idx |= tx_ring->reg_idx << 4; 1131 1132 if (first_flag) 1133 mss_l4len_idx |= IGC_ADVTXD_TSN_CNTX_FIRST; 1134 1135 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 1136 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 1137 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 1138 context_desc->launch_time = launch_time; 1139 } 1140 1141 static void igc_tx_csum(struct igc_ring *tx_ring, struct igc_tx_buffer *first, 1142 __le32 launch_time, bool first_flag) 1143 { 1144 struct sk_buff *skb = first->skb; 1145 u32 vlan_macip_lens = 0; 1146 u32 type_tucmd = 0; 1147 1148 if (skb->ip_summed != CHECKSUM_PARTIAL) { 1149 csum_failed: 1150 if (!(first->tx_flags & IGC_TX_FLAGS_VLAN) && 1151 !tx_ring->launchtime_enable) 1152 return; 1153 goto no_csum; 1154 } 1155 1156 switch (skb->csum_offset) { 1157 case offsetof(struct tcphdr, check): 1158 type_tucmd = IGC_ADVTXD_TUCMD_L4T_TCP; 1159 fallthrough; 1160 case offsetof(struct udphdr, check): 1161 break; 1162 case offsetof(struct sctphdr, checksum): 1163 /* validate that this is actually an SCTP request */ 1164 if (skb_csum_is_sctp(skb)) { 1165 type_tucmd = IGC_ADVTXD_TUCMD_L4T_SCTP; 1166 break; 1167 } 1168 fallthrough; 1169 default: 1170 skb_checksum_help(skb); 1171 goto csum_failed; 1172 } 1173 1174 /* update TX checksum flag */ 1175 first->tx_flags |= IGC_TX_FLAGS_CSUM; 1176 vlan_macip_lens = skb_checksum_start_offset(skb) - 1177 skb_network_offset(skb); 1178 no_csum: 1179 vlan_macip_lens |= skb_network_offset(skb) << IGC_ADVTXD_MACLEN_SHIFT; 1180 vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK; 1181 1182 igc_tx_ctxtdesc(tx_ring, launch_time, first_flag, 1183 vlan_macip_lens, type_tucmd, 0); 1184 } 1185 1186 static int __igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size) 1187 { 1188 struct net_device *netdev = tx_ring->netdev; 1189 1190 netif_stop_subqueue(netdev, tx_ring->queue_index); 1191 1192 /* memory barriier comment */ 1193 smp_mb(); 1194 1195 /* We need to check again in a case another CPU has just 1196 * made room available. 1197 */ 1198 if (igc_desc_unused(tx_ring) < size) 1199 return -EBUSY; 1200 1201 /* A reprieve! */ 1202 netif_wake_subqueue(netdev, tx_ring->queue_index); 1203 1204 u64_stats_update_begin(&tx_ring->tx_syncp2); 1205 tx_ring->tx_stats.restart_queue2++; 1206 u64_stats_update_end(&tx_ring->tx_syncp2); 1207 1208 return 0; 1209 } 1210 1211 static inline int igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size) 1212 { 1213 if (igc_desc_unused(tx_ring) >= size) 1214 return 0; 1215 return __igc_maybe_stop_tx(tx_ring, size); 1216 } 1217 1218 #define IGC_SET_FLAG(_input, _flag, _result) \ 1219 (((_flag) <= (_result)) ? \ 1220 ((u32)((_input) & (_flag)) * ((_result) / (_flag))) : \ 1221 ((u32)((_input) & (_flag)) / ((_flag) / (_result)))) 1222 1223 static u32 igc_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 1224 { 1225 /* set type for advanced descriptor with frame checksum insertion */ 1226 u32 cmd_type = IGC_ADVTXD_DTYP_DATA | 1227 IGC_ADVTXD_DCMD_DEXT | 1228 IGC_ADVTXD_DCMD_IFCS; 1229 1230 /* set HW vlan bit if vlan is present */ 1231 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_VLAN, 1232 IGC_ADVTXD_DCMD_VLE); 1233 1234 /* set segmentation bits for TSO */ 1235 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSO, 1236 (IGC_ADVTXD_DCMD_TSE)); 1237 1238 /* set timestamp bit if present */ 1239 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP, 1240 (IGC_ADVTXD_MAC_TSTAMP)); 1241 1242 /* insert frame checksum */ 1243 cmd_type ^= IGC_SET_FLAG(skb->no_fcs, 1, IGC_ADVTXD_DCMD_IFCS); 1244 1245 return cmd_type; 1246 } 1247 1248 static void igc_tx_olinfo_status(struct igc_ring *tx_ring, 1249 union igc_adv_tx_desc *tx_desc, 1250 u32 tx_flags, unsigned int paylen) 1251 { 1252 u32 olinfo_status = paylen << IGC_ADVTXD_PAYLEN_SHIFT; 1253 1254 /* insert L4 checksum */ 1255 olinfo_status |= (tx_flags & IGC_TX_FLAGS_CSUM) * 1256 ((IGC_TXD_POPTS_TXSM << 8) / 1257 IGC_TX_FLAGS_CSUM); 1258 1259 /* insert IPv4 checksum */ 1260 olinfo_status |= (tx_flags & IGC_TX_FLAGS_IPV4) * 1261 (((IGC_TXD_POPTS_IXSM << 8)) / 1262 IGC_TX_FLAGS_IPV4); 1263 1264 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 1265 } 1266 1267 static int igc_tx_map(struct igc_ring *tx_ring, 1268 struct igc_tx_buffer *first, 1269 const u8 hdr_len) 1270 { 1271 struct sk_buff *skb = first->skb; 1272 struct igc_tx_buffer *tx_buffer; 1273 union igc_adv_tx_desc *tx_desc; 1274 u32 tx_flags = first->tx_flags; 1275 skb_frag_t *frag; 1276 u16 i = tx_ring->next_to_use; 1277 unsigned int data_len, size; 1278 dma_addr_t dma; 1279 u32 cmd_type; 1280 1281 cmd_type = igc_tx_cmd_type(skb, tx_flags); 1282 tx_desc = IGC_TX_DESC(tx_ring, i); 1283 1284 igc_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 1285 1286 size = skb_headlen(skb); 1287 data_len = skb->data_len; 1288 1289 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 1290 1291 tx_buffer = first; 1292 1293 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 1294 if (dma_mapping_error(tx_ring->dev, dma)) 1295 goto dma_error; 1296 1297 /* record length, and DMA address */ 1298 dma_unmap_len_set(tx_buffer, len, size); 1299 dma_unmap_addr_set(tx_buffer, dma, dma); 1300 1301 tx_desc->read.buffer_addr = cpu_to_le64(dma); 1302 1303 while (unlikely(size > IGC_MAX_DATA_PER_TXD)) { 1304 tx_desc->read.cmd_type_len = 1305 cpu_to_le32(cmd_type ^ IGC_MAX_DATA_PER_TXD); 1306 1307 i++; 1308 tx_desc++; 1309 if (i == tx_ring->count) { 1310 tx_desc = IGC_TX_DESC(tx_ring, 0); 1311 i = 0; 1312 } 1313 tx_desc->read.olinfo_status = 0; 1314 1315 dma += IGC_MAX_DATA_PER_TXD; 1316 size -= IGC_MAX_DATA_PER_TXD; 1317 1318 tx_desc->read.buffer_addr = cpu_to_le64(dma); 1319 } 1320 1321 if (likely(!data_len)) 1322 break; 1323 1324 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 1325 1326 i++; 1327 tx_desc++; 1328 if (i == tx_ring->count) { 1329 tx_desc = IGC_TX_DESC(tx_ring, 0); 1330 i = 0; 1331 } 1332 tx_desc->read.olinfo_status = 0; 1333 1334 size = skb_frag_size(frag); 1335 data_len -= size; 1336 1337 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 1338 size, DMA_TO_DEVICE); 1339 1340 tx_buffer = &tx_ring->tx_buffer_info[i]; 1341 } 1342 1343 /* write last descriptor with RS and EOP bits */ 1344 cmd_type |= size | IGC_TXD_DCMD; 1345 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 1346 1347 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 1348 1349 /* set the timestamp */ 1350 first->time_stamp = jiffies; 1351 1352 skb_tx_timestamp(skb); 1353 1354 /* Force memory writes to complete before letting h/w know there 1355 * are new descriptors to fetch. (Only applicable for weak-ordered 1356 * memory model archs, such as IA-64). 1357 * 1358 * We also need this memory barrier to make certain all of the 1359 * status bits have been updated before next_to_watch is written. 1360 */ 1361 wmb(); 1362 1363 /* set next_to_watch value indicating a packet is present */ 1364 first->next_to_watch = tx_desc; 1365 1366 i++; 1367 if (i == tx_ring->count) 1368 i = 0; 1369 1370 tx_ring->next_to_use = i; 1371 1372 /* Make sure there is space in the ring for the next send. */ 1373 igc_maybe_stop_tx(tx_ring, DESC_NEEDED); 1374 1375 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 1376 writel(i, tx_ring->tail); 1377 } 1378 1379 return 0; 1380 dma_error: 1381 netdev_err(tx_ring->netdev, "TX DMA map failed\n"); 1382 tx_buffer = &tx_ring->tx_buffer_info[i]; 1383 1384 /* clear dma mappings for failed tx_buffer_info map */ 1385 while (tx_buffer != first) { 1386 if (dma_unmap_len(tx_buffer, len)) 1387 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 1388 1389 if (i-- == 0) 1390 i += tx_ring->count; 1391 tx_buffer = &tx_ring->tx_buffer_info[i]; 1392 } 1393 1394 if (dma_unmap_len(tx_buffer, len)) 1395 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 1396 1397 dev_kfree_skb_any(tx_buffer->skb); 1398 tx_buffer->skb = NULL; 1399 1400 tx_ring->next_to_use = i; 1401 1402 return -1; 1403 } 1404 1405 static int igc_tso(struct igc_ring *tx_ring, 1406 struct igc_tx_buffer *first, 1407 __le32 launch_time, bool first_flag, 1408 u8 *hdr_len) 1409 { 1410 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 1411 struct sk_buff *skb = first->skb; 1412 union { 1413 struct iphdr *v4; 1414 struct ipv6hdr *v6; 1415 unsigned char *hdr; 1416 } ip; 1417 union { 1418 struct tcphdr *tcp; 1419 struct udphdr *udp; 1420 unsigned char *hdr; 1421 } l4; 1422 u32 paylen, l4_offset; 1423 int err; 1424 1425 if (skb->ip_summed != CHECKSUM_PARTIAL) 1426 return 0; 1427 1428 if (!skb_is_gso(skb)) 1429 return 0; 1430 1431 err = skb_cow_head(skb, 0); 1432 if (err < 0) 1433 return err; 1434 1435 ip.hdr = skb_network_header(skb); 1436 l4.hdr = skb_checksum_start(skb); 1437 1438 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 1439 type_tucmd = IGC_ADVTXD_TUCMD_L4T_TCP; 1440 1441 /* initialize outer IP header fields */ 1442 if (ip.v4->version == 4) { 1443 unsigned char *csum_start = skb_checksum_start(skb); 1444 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 1445 1446 /* IP header will have to cancel out any data that 1447 * is not a part of the outer IP header 1448 */ 1449 ip.v4->check = csum_fold(csum_partial(trans_start, 1450 csum_start - trans_start, 1451 0)); 1452 type_tucmd |= IGC_ADVTXD_TUCMD_IPV4; 1453 1454 ip.v4->tot_len = 0; 1455 first->tx_flags |= IGC_TX_FLAGS_TSO | 1456 IGC_TX_FLAGS_CSUM | 1457 IGC_TX_FLAGS_IPV4; 1458 } else { 1459 ip.v6->payload_len = 0; 1460 first->tx_flags |= IGC_TX_FLAGS_TSO | 1461 IGC_TX_FLAGS_CSUM; 1462 } 1463 1464 /* determine offset of inner transport header */ 1465 l4_offset = l4.hdr - skb->data; 1466 1467 /* remove payload length from inner checksum */ 1468 paylen = skb->len - l4_offset; 1469 if (type_tucmd & IGC_ADVTXD_TUCMD_L4T_TCP) { 1470 /* compute length of segmentation header */ 1471 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 1472 csum_replace_by_diff(&l4.tcp->check, 1473 (__force __wsum)htonl(paylen)); 1474 } else { 1475 /* compute length of segmentation header */ 1476 *hdr_len = sizeof(*l4.udp) + l4_offset; 1477 csum_replace_by_diff(&l4.udp->check, 1478 (__force __wsum)htonl(paylen)); 1479 } 1480 1481 /* update gso size and bytecount with header size */ 1482 first->gso_segs = skb_shinfo(skb)->gso_segs; 1483 first->bytecount += (first->gso_segs - 1) * *hdr_len; 1484 1485 /* MSS L4LEN IDX */ 1486 mss_l4len_idx = (*hdr_len - l4_offset) << IGC_ADVTXD_L4LEN_SHIFT; 1487 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IGC_ADVTXD_MSS_SHIFT; 1488 1489 /* VLAN MACLEN IPLEN */ 1490 vlan_macip_lens = l4.hdr - ip.hdr; 1491 vlan_macip_lens |= (ip.hdr - skb->data) << IGC_ADVTXD_MACLEN_SHIFT; 1492 vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK; 1493 1494 igc_tx_ctxtdesc(tx_ring, launch_time, first_flag, 1495 vlan_macip_lens, type_tucmd, mss_l4len_idx); 1496 1497 return 1; 1498 } 1499 1500 static netdev_tx_t igc_xmit_frame_ring(struct sk_buff *skb, 1501 struct igc_ring *tx_ring) 1502 { 1503 struct igc_adapter *adapter = netdev_priv(tx_ring->netdev); 1504 bool first_flag = false, insert_empty = false; 1505 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 1506 __be16 protocol = vlan_get_protocol(skb); 1507 struct igc_tx_buffer *first; 1508 __le32 launch_time = 0; 1509 u32 tx_flags = 0; 1510 unsigned short f; 1511 ktime_t txtime; 1512 u8 hdr_len = 0; 1513 int tso = 0; 1514 1515 /* need: 1 descriptor per page * PAGE_SIZE/IGC_MAX_DATA_PER_TXD, 1516 * + 1 desc for skb_headlen/IGC_MAX_DATA_PER_TXD, 1517 * + 2 desc gap to keep tail from touching head, 1518 * + 1 desc for context descriptor, 1519 * otherwise try next time 1520 */ 1521 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 1522 count += TXD_USE_COUNT(skb_frag_size( 1523 &skb_shinfo(skb)->frags[f])); 1524 1525 if (igc_maybe_stop_tx(tx_ring, count + 5)) { 1526 /* this is a hard error */ 1527 return NETDEV_TX_BUSY; 1528 } 1529 1530 if (!tx_ring->launchtime_enable) 1531 goto done; 1532 1533 txtime = skb->tstamp; 1534 skb->tstamp = ktime_set(0, 0); 1535 launch_time = igc_tx_launchtime(tx_ring, txtime, &first_flag, &insert_empty); 1536 1537 if (insert_empty) { 1538 struct igc_tx_buffer *empty_info; 1539 struct sk_buff *empty; 1540 void *data; 1541 1542 empty_info = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 1543 empty = alloc_skb(IGC_EMPTY_FRAME_SIZE, GFP_ATOMIC); 1544 if (!empty) 1545 goto done; 1546 1547 data = skb_put(empty, IGC_EMPTY_FRAME_SIZE); 1548 memset(data, 0, IGC_EMPTY_FRAME_SIZE); 1549 1550 igc_tx_ctxtdesc(tx_ring, 0, false, 0, 0, 0); 1551 1552 if (igc_init_tx_empty_descriptor(tx_ring, 1553 empty, 1554 empty_info) < 0) 1555 dev_kfree_skb_any(empty); 1556 } 1557 1558 done: 1559 /* record the location of the first descriptor for this packet */ 1560 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 1561 first->type = IGC_TX_BUFFER_TYPE_SKB; 1562 first->skb = skb; 1563 first->bytecount = skb->len; 1564 first->gso_segs = 1; 1565 1566 if (tx_ring->max_sdu > 0) { 1567 u32 max_sdu = 0; 1568 1569 max_sdu = tx_ring->max_sdu + 1570 (skb_vlan_tagged(first->skb) ? VLAN_HLEN : 0); 1571 1572 if (first->bytecount > max_sdu) { 1573 adapter->stats.txdrop++; 1574 goto out_drop; 1575 } 1576 } 1577 1578 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 1579 /* FIXME: add support for retrieving timestamps from 1580 * the other timer registers before skipping the 1581 * timestamping request. 1582 */ 1583 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 1584 !test_and_set_bit_lock(__IGC_PTP_TX_IN_PROGRESS, 1585 &adapter->state)) { 1586 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1587 tx_flags |= IGC_TX_FLAGS_TSTAMP; 1588 1589 adapter->ptp_tx_skb = skb_get(skb); 1590 adapter->ptp_tx_start = jiffies; 1591 } else { 1592 adapter->tx_hwtstamp_skipped++; 1593 } 1594 } 1595 1596 if (skb_vlan_tag_present(skb)) { 1597 tx_flags |= IGC_TX_FLAGS_VLAN; 1598 tx_flags |= (skb_vlan_tag_get(skb) << IGC_TX_FLAGS_VLAN_SHIFT); 1599 } 1600 1601 /* record initial flags and protocol */ 1602 first->tx_flags = tx_flags; 1603 first->protocol = protocol; 1604 1605 tso = igc_tso(tx_ring, first, launch_time, first_flag, &hdr_len); 1606 if (tso < 0) 1607 goto out_drop; 1608 else if (!tso) 1609 igc_tx_csum(tx_ring, first, launch_time, first_flag); 1610 1611 igc_tx_map(tx_ring, first, hdr_len); 1612 1613 return NETDEV_TX_OK; 1614 1615 out_drop: 1616 dev_kfree_skb_any(first->skb); 1617 first->skb = NULL; 1618 1619 return NETDEV_TX_OK; 1620 } 1621 1622 static inline struct igc_ring *igc_tx_queue_mapping(struct igc_adapter *adapter, 1623 struct sk_buff *skb) 1624 { 1625 unsigned int r_idx = skb->queue_mapping; 1626 1627 if (r_idx >= adapter->num_tx_queues) 1628 r_idx = r_idx % adapter->num_tx_queues; 1629 1630 return adapter->tx_ring[r_idx]; 1631 } 1632 1633 static netdev_tx_t igc_xmit_frame(struct sk_buff *skb, 1634 struct net_device *netdev) 1635 { 1636 struct igc_adapter *adapter = netdev_priv(netdev); 1637 1638 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 1639 * in order to meet this minimum size requirement. 1640 */ 1641 if (skb->len < 17) { 1642 if (skb_padto(skb, 17)) 1643 return NETDEV_TX_OK; 1644 skb->len = 17; 1645 } 1646 1647 return igc_xmit_frame_ring(skb, igc_tx_queue_mapping(adapter, skb)); 1648 } 1649 1650 static void igc_rx_checksum(struct igc_ring *ring, 1651 union igc_adv_rx_desc *rx_desc, 1652 struct sk_buff *skb) 1653 { 1654 skb_checksum_none_assert(skb); 1655 1656 /* Ignore Checksum bit is set */ 1657 if (igc_test_staterr(rx_desc, IGC_RXD_STAT_IXSM)) 1658 return; 1659 1660 /* Rx checksum disabled via ethtool */ 1661 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1662 return; 1663 1664 /* TCP/UDP checksum error bit is set */ 1665 if (igc_test_staterr(rx_desc, 1666 IGC_RXDEXT_STATERR_L4E | 1667 IGC_RXDEXT_STATERR_IPE)) { 1668 /* work around errata with sctp packets where the TCPE aka 1669 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 1670 * packets (aka let the stack check the crc32c) 1671 */ 1672 if (!(skb->len == 60 && 1673 test_bit(IGC_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 1674 u64_stats_update_begin(&ring->rx_syncp); 1675 ring->rx_stats.csum_err++; 1676 u64_stats_update_end(&ring->rx_syncp); 1677 } 1678 /* let the stack verify checksum errors */ 1679 return; 1680 } 1681 /* It must be a TCP or UDP packet with a valid checksum */ 1682 if (igc_test_staterr(rx_desc, IGC_RXD_STAT_TCPCS | 1683 IGC_RXD_STAT_UDPCS)) 1684 skb->ip_summed = CHECKSUM_UNNECESSARY; 1685 1686 netdev_dbg(ring->netdev, "cksum success: bits %08X\n", 1687 le32_to_cpu(rx_desc->wb.upper.status_error)); 1688 } 1689 1690 static inline void igc_rx_hash(struct igc_ring *ring, 1691 union igc_adv_rx_desc *rx_desc, 1692 struct sk_buff *skb) 1693 { 1694 if (ring->netdev->features & NETIF_F_RXHASH) 1695 skb_set_hash(skb, 1696 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1697 PKT_HASH_TYPE_L3); 1698 } 1699 1700 static void igc_rx_vlan(struct igc_ring *rx_ring, 1701 union igc_adv_rx_desc *rx_desc, 1702 struct sk_buff *skb) 1703 { 1704 struct net_device *dev = rx_ring->netdev; 1705 u16 vid; 1706 1707 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1708 igc_test_staterr(rx_desc, IGC_RXD_STAT_VP)) { 1709 if (igc_test_staterr(rx_desc, IGC_RXDEXT_STATERR_LB) && 1710 test_bit(IGC_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 1711 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan); 1712 else 1713 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1714 1715 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1716 } 1717 } 1718 1719 /** 1720 * igc_process_skb_fields - Populate skb header fields from Rx descriptor 1721 * @rx_ring: rx descriptor ring packet is being transacted on 1722 * @rx_desc: pointer to the EOP Rx descriptor 1723 * @skb: pointer to current skb being populated 1724 * 1725 * This function checks the ring, descriptor, and packet information in order 1726 * to populate the hash, checksum, VLAN, protocol, and other fields within the 1727 * skb. 1728 */ 1729 static void igc_process_skb_fields(struct igc_ring *rx_ring, 1730 union igc_adv_rx_desc *rx_desc, 1731 struct sk_buff *skb) 1732 { 1733 igc_rx_hash(rx_ring, rx_desc, skb); 1734 1735 igc_rx_checksum(rx_ring, rx_desc, skb); 1736 1737 igc_rx_vlan(rx_ring, rx_desc, skb); 1738 1739 skb_record_rx_queue(skb, rx_ring->queue_index); 1740 1741 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 1742 } 1743 1744 static void igc_vlan_mode(struct net_device *netdev, netdev_features_t features) 1745 { 1746 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 1747 struct igc_adapter *adapter = netdev_priv(netdev); 1748 struct igc_hw *hw = &adapter->hw; 1749 u32 ctrl; 1750 1751 ctrl = rd32(IGC_CTRL); 1752 1753 if (enable) { 1754 /* enable VLAN tag insert/strip */ 1755 ctrl |= IGC_CTRL_VME; 1756 } else { 1757 /* disable VLAN tag insert/strip */ 1758 ctrl &= ~IGC_CTRL_VME; 1759 } 1760 wr32(IGC_CTRL, ctrl); 1761 } 1762 1763 static void igc_restore_vlan(struct igc_adapter *adapter) 1764 { 1765 igc_vlan_mode(adapter->netdev, adapter->netdev->features); 1766 } 1767 1768 static struct igc_rx_buffer *igc_get_rx_buffer(struct igc_ring *rx_ring, 1769 const unsigned int size, 1770 int *rx_buffer_pgcnt) 1771 { 1772 struct igc_rx_buffer *rx_buffer; 1773 1774 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 1775 *rx_buffer_pgcnt = 1776 #if (PAGE_SIZE < 8192) 1777 page_count(rx_buffer->page); 1778 #else 1779 0; 1780 #endif 1781 prefetchw(rx_buffer->page); 1782 1783 /* we are reusing so sync this buffer for CPU use */ 1784 dma_sync_single_range_for_cpu(rx_ring->dev, 1785 rx_buffer->dma, 1786 rx_buffer->page_offset, 1787 size, 1788 DMA_FROM_DEVICE); 1789 1790 rx_buffer->pagecnt_bias--; 1791 1792 return rx_buffer; 1793 } 1794 1795 static void igc_rx_buffer_flip(struct igc_rx_buffer *buffer, 1796 unsigned int truesize) 1797 { 1798 #if (PAGE_SIZE < 8192) 1799 buffer->page_offset ^= truesize; 1800 #else 1801 buffer->page_offset += truesize; 1802 #endif 1803 } 1804 1805 static unsigned int igc_get_rx_frame_truesize(struct igc_ring *ring, 1806 unsigned int size) 1807 { 1808 unsigned int truesize; 1809 1810 #if (PAGE_SIZE < 8192) 1811 truesize = igc_rx_pg_size(ring) / 2; 1812 #else 1813 truesize = ring_uses_build_skb(ring) ? 1814 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1815 SKB_DATA_ALIGN(IGC_SKB_PAD + size) : 1816 SKB_DATA_ALIGN(size); 1817 #endif 1818 return truesize; 1819 } 1820 1821 /** 1822 * igc_add_rx_frag - Add contents of Rx buffer to sk_buff 1823 * @rx_ring: rx descriptor ring to transact packets on 1824 * @rx_buffer: buffer containing page to add 1825 * @skb: sk_buff to place the data into 1826 * @size: size of buffer to be added 1827 * 1828 * This function will add the data contained in rx_buffer->page to the skb. 1829 */ 1830 static void igc_add_rx_frag(struct igc_ring *rx_ring, 1831 struct igc_rx_buffer *rx_buffer, 1832 struct sk_buff *skb, 1833 unsigned int size) 1834 { 1835 unsigned int truesize; 1836 1837 #if (PAGE_SIZE < 8192) 1838 truesize = igc_rx_pg_size(rx_ring) / 2; 1839 #else 1840 truesize = ring_uses_build_skb(rx_ring) ? 1841 SKB_DATA_ALIGN(IGC_SKB_PAD + size) : 1842 SKB_DATA_ALIGN(size); 1843 #endif 1844 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 1845 rx_buffer->page_offset, size, truesize); 1846 1847 igc_rx_buffer_flip(rx_buffer, truesize); 1848 } 1849 1850 static struct sk_buff *igc_build_skb(struct igc_ring *rx_ring, 1851 struct igc_rx_buffer *rx_buffer, 1852 struct xdp_buff *xdp) 1853 { 1854 unsigned int size = xdp->data_end - xdp->data; 1855 unsigned int truesize = igc_get_rx_frame_truesize(rx_ring, size); 1856 unsigned int metasize = xdp->data - xdp->data_meta; 1857 struct sk_buff *skb; 1858 1859 /* prefetch first cache line of first page */ 1860 net_prefetch(xdp->data_meta); 1861 1862 /* build an skb around the page buffer */ 1863 skb = napi_build_skb(xdp->data_hard_start, truesize); 1864 if (unlikely(!skb)) 1865 return NULL; 1866 1867 /* update pointers within the skb to store the data */ 1868 skb_reserve(skb, xdp->data - xdp->data_hard_start); 1869 __skb_put(skb, size); 1870 if (metasize) 1871 skb_metadata_set(skb, metasize); 1872 1873 igc_rx_buffer_flip(rx_buffer, truesize); 1874 return skb; 1875 } 1876 1877 static struct sk_buff *igc_construct_skb(struct igc_ring *rx_ring, 1878 struct igc_rx_buffer *rx_buffer, 1879 struct xdp_buff *xdp, 1880 ktime_t timestamp) 1881 { 1882 unsigned int metasize = xdp->data - xdp->data_meta; 1883 unsigned int size = xdp->data_end - xdp->data; 1884 unsigned int truesize = igc_get_rx_frame_truesize(rx_ring, size); 1885 void *va = xdp->data; 1886 unsigned int headlen; 1887 struct sk_buff *skb; 1888 1889 /* prefetch first cache line of first page */ 1890 net_prefetch(xdp->data_meta); 1891 1892 /* allocate a skb to store the frags */ 1893 skb = napi_alloc_skb(&rx_ring->q_vector->napi, 1894 IGC_RX_HDR_LEN + metasize); 1895 if (unlikely(!skb)) 1896 return NULL; 1897 1898 if (timestamp) 1899 skb_hwtstamps(skb)->hwtstamp = timestamp; 1900 1901 /* Determine available headroom for copy */ 1902 headlen = size; 1903 if (headlen > IGC_RX_HDR_LEN) 1904 headlen = eth_get_headlen(skb->dev, va, IGC_RX_HDR_LEN); 1905 1906 /* align pull length to size of long to optimize memcpy performance */ 1907 memcpy(__skb_put(skb, headlen + metasize), xdp->data_meta, 1908 ALIGN(headlen + metasize, sizeof(long))); 1909 1910 if (metasize) { 1911 skb_metadata_set(skb, metasize); 1912 __skb_pull(skb, metasize); 1913 } 1914 1915 /* update all of the pointers */ 1916 size -= headlen; 1917 if (size) { 1918 skb_add_rx_frag(skb, 0, rx_buffer->page, 1919 (va + headlen) - page_address(rx_buffer->page), 1920 size, truesize); 1921 igc_rx_buffer_flip(rx_buffer, truesize); 1922 } else { 1923 rx_buffer->pagecnt_bias++; 1924 } 1925 1926 return skb; 1927 } 1928 1929 /** 1930 * igc_reuse_rx_page - page flip buffer and store it back on the ring 1931 * @rx_ring: rx descriptor ring to store buffers on 1932 * @old_buff: donor buffer to have page reused 1933 * 1934 * Synchronizes page for reuse by the adapter 1935 */ 1936 static void igc_reuse_rx_page(struct igc_ring *rx_ring, 1937 struct igc_rx_buffer *old_buff) 1938 { 1939 u16 nta = rx_ring->next_to_alloc; 1940 struct igc_rx_buffer *new_buff; 1941 1942 new_buff = &rx_ring->rx_buffer_info[nta]; 1943 1944 /* update, and store next to alloc */ 1945 nta++; 1946 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1947 1948 /* Transfer page from old buffer to new buffer. 1949 * Move each member individually to avoid possible store 1950 * forwarding stalls. 1951 */ 1952 new_buff->dma = old_buff->dma; 1953 new_buff->page = old_buff->page; 1954 new_buff->page_offset = old_buff->page_offset; 1955 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1956 } 1957 1958 static bool igc_can_reuse_rx_page(struct igc_rx_buffer *rx_buffer, 1959 int rx_buffer_pgcnt) 1960 { 1961 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1962 struct page *page = rx_buffer->page; 1963 1964 /* avoid re-using remote and pfmemalloc pages */ 1965 if (!dev_page_is_reusable(page)) 1966 return false; 1967 1968 #if (PAGE_SIZE < 8192) 1969 /* if we are only owner of page we can reuse it */ 1970 if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1)) 1971 return false; 1972 #else 1973 #define IGC_LAST_OFFSET \ 1974 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGC_RXBUFFER_2048) 1975 1976 if (rx_buffer->page_offset > IGC_LAST_OFFSET) 1977 return false; 1978 #endif 1979 1980 /* If we have drained the page fragment pool we need to update 1981 * the pagecnt_bias and page count so that we fully restock the 1982 * number of references the driver holds. 1983 */ 1984 if (unlikely(pagecnt_bias == 1)) { 1985 page_ref_add(page, USHRT_MAX - 1); 1986 rx_buffer->pagecnt_bias = USHRT_MAX; 1987 } 1988 1989 return true; 1990 } 1991 1992 /** 1993 * igc_is_non_eop - process handling of non-EOP buffers 1994 * @rx_ring: Rx ring being processed 1995 * @rx_desc: Rx descriptor for current buffer 1996 * 1997 * This function updates next to clean. If the buffer is an EOP buffer 1998 * this function exits returning false, otherwise it will place the 1999 * sk_buff in the next buffer to be chained and return true indicating 2000 * that this is in fact a non-EOP buffer. 2001 */ 2002 static bool igc_is_non_eop(struct igc_ring *rx_ring, 2003 union igc_adv_rx_desc *rx_desc) 2004 { 2005 u32 ntc = rx_ring->next_to_clean + 1; 2006 2007 /* fetch, update, and store next to clean */ 2008 ntc = (ntc < rx_ring->count) ? ntc : 0; 2009 rx_ring->next_to_clean = ntc; 2010 2011 prefetch(IGC_RX_DESC(rx_ring, ntc)); 2012 2013 if (likely(igc_test_staterr(rx_desc, IGC_RXD_STAT_EOP))) 2014 return false; 2015 2016 return true; 2017 } 2018 2019 /** 2020 * igc_cleanup_headers - Correct corrupted or empty headers 2021 * @rx_ring: rx descriptor ring packet is being transacted on 2022 * @rx_desc: pointer to the EOP Rx descriptor 2023 * @skb: pointer to current skb being fixed 2024 * 2025 * Address the case where we are pulling data in on pages only 2026 * and as such no data is present in the skb header. 2027 * 2028 * In addition if skb is not at least 60 bytes we need to pad it so that 2029 * it is large enough to qualify as a valid Ethernet frame. 2030 * 2031 * Returns true if an error was encountered and skb was freed. 2032 */ 2033 static bool igc_cleanup_headers(struct igc_ring *rx_ring, 2034 union igc_adv_rx_desc *rx_desc, 2035 struct sk_buff *skb) 2036 { 2037 /* XDP packets use error pointer so abort at this point */ 2038 if (IS_ERR(skb)) 2039 return true; 2040 2041 if (unlikely(igc_test_staterr(rx_desc, IGC_RXDEXT_STATERR_RXE))) { 2042 struct net_device *netdev = rx_ring->netdev; 2043 2044 if (!(netdev->features & NETIF_F_RXALL)) { 2045 dev_kfree_skb_any(skb); 2046 return true; 2047 } 2048 } 2049 2050 /* if eth_skb_pad returns an error the skb was freed */ 2051 if (eth_skb_pad(skb)) 2052 return true; 2053 2054 return false; 2055 } 2056 2057 static void igc_put_rx_buffer(struct igc_ring *rx_ring, 2058 struct igc_rx_buffer *rx_buffer, 2059 int rx_buffer_pgcnt) 2060 { 2061 if (igc_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) { 2062 /* hand second half of page back to the ring */ 2063 igc_reuse_rx_page(rx_ring, rx_buffer); 2064 } else { 2065 /* We are not reusing the buffer so unmap it and free 2066 * any references we are holding to it 2067 */ 2068 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2069 igc_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 2070 IGC_RX_DMA_ATTR); 2071 __page_frag_cache_drain(rx_buffer->page, 2072 rx_buffer->pagecnt_bias); 2073 } 2074 2075 /* clear contents of rx_buffer */ 2076 rx_buffer->page = NULL; 2077 } 2078 2079 static inline unsigned int igc_rx_offset(struct igc_ring *rx_ring) 2080 { 2081 struct igc_adapter *adapter = rx_ring->q_vector->adapter; 2082 2083 if (ring_uses_build_skb(rx_ring)) 2084 return IGC_SKB_PAD; 2085 if (igc_xdp_is_enabled(adapter)) 2086 return XDP_PACKET_HEADROOM; 2087 2088 return 0; 2089 } 2090 2091 static bool igc_alloc_mapped_page(struct igc_ring *rx_ring, 2092 struct igc_rx_buffer *bi) 2093 { 2094 struct page *page = bi->page; 2095 dma_addr_t dma; 2096 2097 /* since we are recycling buffers we should seldom need to alloc */ 2098 if (likely(page)) 2099 return true; 2100 2101 /* alloc new page for storage */ 2102 page = dev_alloc_pages(igc_rx_pg_order(rx_ring)); 2103 if (unlikely(!page)) { 2104 rx_ring->rx_stats.alloc_failed++; 2105 return false; 2106 } 2107 2108 /* map page for use */ 2109 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 2110 igc_rx_pg_size(rx_ring), 2111 DMA_FROM_DEVICE, 2112 IGC_RX_DMA_ATTR); 2113 2114 /* if mapping failed free memory back to system since 2115 * there isn't much point in holding memory we can't use 2116 */ 2117 if (dma_mapping_error(rx_ring->dev, dma)) { 2118 __free_page(page); 2119 2120 rx_ring->rx_stats.alloc_failed++; 2121 return false; 2122 } 2123 2124 bi->dma = dma; 2125 bi->page = page; 2126 bi->page_offset = igc_rx_offset(rx_ring); 2127 page_ref_add(page, USHRT_MAX - 1); 2128 bi->pagecnt_bias = USHRT_MAX; 2129 2130 return true; 2131 } 2132 2133 /** 2134 * igc_alloc_rx_buffers - Replace used receive buffers; packet split 2135 * @rx_ring: rx descriptor ring 2136 * @cleaned_count: number of buffers to clean 2137 */ 2138 static void igc_alloc_rx_buffers(struct igc_ring *rx_ring, u16 cleaned_count) 2139 { 2140 union igc_adv_rx_desc *rx_desc; 2141 u16 i = rx_ring->next_to_use; 2142 struct igc_rx_buffer *bi; 2143 u16 bufsz; 2144 2145 /* nothing to do */ 2146 if (!cleaned_count) 2147 return; 2148 2149 rx_desc = IGC_RX_DESC(rx_ring, i); 2150 bi = &rx_ring->rx_buffer_info[i]; 2151 i -= rx_ring->count; 2152 2153 bufsz = igc_rx_bufsz(rx_ring); 2154 2155 do { 2156 if (!igc_alloc_mapped_page(rx_ring, bi)) 2157 break; 2158 2159 /* sync the buffer for use by the device */ 2160 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 2161 bi->page_offset, bufsz, 2162 DMA_FROM_DEVICE); 2163 2164 /* Refresh the desc even if buffer_addrs didn't change 2165 * because each write-back erases this info. 2166 */ 2167 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 2168 2169 rx_desc++; 2170 bi++; 2171 i++; 2172 if (unlikely(!i)) { 2173 rx_desc = IGC_RX_DESC(rx_ring, 0); 2174 bi = rx_ring->rx_buffer_info; 2175 i -= rx_ring->count; 2176 } 2177 2178 /* clear the length for the next_to_use descriptor */ 2179 rx_desc->wb.upper.length = 0; 2180 2181 cleaned_count--; 2182 } while (cleaned_count); 2183 2184 i += rx_ring->count; 2185 2186 if (rx_ring->next_to_use != i) { 2187 /* record the next descriptor to use */ 2188 rx_ring->next_to_use = i; 2189 2190 /* update next to alloc since we have filled the ring */ 2191 rx_ring->next_to_alloc = i; 2192 2193 /* Force memory writes to complete before letting h/w 2194 * know there are new descriptors to fetch. (Only 2195 * applicable for weak-ordered memory model archs, 2196 * such as IA-64). 2197 */ 2198 wmb(); 2199 writel(i, rx_ring->tail); 2200 } 2201 } 2202 2203 static bool igc_alloc_rx_buffers_zc(struct igc_ring *ring, u16 count) 2204 { 2205 union igc_adv_rx_desc *desc; 2206 u16 i = ring->next_to_use; 2207 struct igc_rx_buffer *bi; 2208 dma_addr_t dma; 2209 bool ok = true; 2210 2211 if (!count) 2212 return ok; 2213 2214 desc = IGC_RX_DESC(ring, i); 2215 bi = &ring->rx_buffer_info[i]; 2216 i -= ring->count; 2217 2218 do { 2219 bi->xdp = xsk_buff_alloc(ring->xsk_pool); 2220 if (!bi->xdp) { 2221 ok = false; 2222 break; 2223 } 2224 2225 dma = xsk_buff_xdp_get_dma(bi->xdp); 2226 desc->read.pkt_addr = cpu_to_le64(dma); 2227 2228 desc++; 2229 bi++; 2230 i++; 2231 if (unlikely(!i)) { 2232 desc = IGC_RX_DESC(ring, 0); 2233 bi = ring->rx_buffer_info; 2234 i -= ring->count; 2235 } 2236 2237 /* Clear the length for the next_to_use descriptor. */ 2238 desc->wb.upper.length = 0; 2239 2240 count--; 2241 } while (count); 2242 2243 i += ring->count; 2244 2245 if (ring->next_to_use != i) { 2246 ring->next_to_use = i; 2247 2248 /* Force memory writes to complete before letting h/w 2249 * know there are new descriptors to fetch. (Only 2250 * applicable for weak-ordered memory model archs, 2251 * such as IA-64). 2252 */ 2253 wmb(); 2254 writel(i, ring->tail); 2255 } 2256 2257 return ok; 2258 } 2259 2260 /* This function requires __netif_tx_lock is held by the caller. */ 2261 static int igc_xdp_init_tx_descriptor(struct igc_ring *ring, 2262 struct xdp_frame *xdpf) 2263 { 2264 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 2265 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 2266 u16 count, index = ring->next_to_use; 2267 struct igc_tx_buffer *head = &ring->tx_buffer_info[index]; 2268 struct igc_tx_buffer *buffer = head; 2269 union igc_adv_tx_desc *desc = IGC_TX_DESC(ring, index); 2270 u32 olinfo_status, len = xdpf->len, cmd_type; 2271 void *data = xdpf->data; 2272 u16 i; 2273 2274 count = TXD_USE_COUNT(len); 2275 for (i = 0; i < nr_frags; i++) 2276 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i])); 2277 2278 if (igc_maybe_stop_tx(ring, count + 3)) { 2279 /* this is a hard error */ 2280 return -EBUSY; 2281 } 2282 2283 i = 0; 2284 head->bytecount = xdp_get_frame_len(xdpf); 2285 head->type = IGC_TX_BUFFER_TYPE_XDP; 2286 head->gso_segs = 1; 2287 head->xdpf = xdpf; 2288 2289 olinfo_status = head->bytecount << IGC_ADVTXD_PAYLEN_SHIFT; 2290 desc->read.olinfo_status = cpu_to_le32(olinfo_status); 2291 2292 for (;;) { 2293 dma_addr_t dma; 2294 2295 dma = dma_map_single(ring->dev, data, len, DMA_TO_DEVICE); 2296 if (dma_mapping_error(ring->dev, dma)) { 2297 netdev_err_once(ring->netdev, 2298 "Failed to map DMA for TX\n"); 2299 goto unmap; 2300 } 2301 2302 dma_unmap_len_set(buffer, len, len); 2303 dma_unmap_addr_set(buffer, dma, dma); 2304 2305 cmd_type = IGC_ADVTXD_DTYP_DATA | IGC_ADVTXD_DCMD_DEXT | 2306 IGC_ADVTXD_DCMD_IFCS | len; 2307 2308 desc->read.cmd_type_len = cpu_to_le32(cmd_type); 2309 desc->read.buffer_addr = cpu_to_le64(dma); 2310 2311 buffer->protocol = 0; 2312 2313 if (++index == ring->count) 2314 index = 0; 2315 2316 if (i == nr_frags) 2317 break; 2318 2319 buffer = &ring->tx_buffer_info[index]; 2320 desc = IGC_TX_DESC(ring, index); 2321 desc->read.olinfo_status = 0; 2322 2323 data = skb_frag_address(&sinfo->frags[i]); 2324 len = skb_frag_size(&sinfo->frags[i]); 2325 i++; 2326 } 2327 desc->read.cmd_type_len |= cpu_to_le32(IGC_TXD_DCMD); 2328 2329 netdev_tx_sent_queue(txring_txq(ring), head->bytecount); 2330 /* set the timestamp */ 2331 head->time_stamp = jiffies; 2332 /* set next_to_watch value indicating a packet is present */ 2333 head->next_to_watch = desc; 2334 ring->next_to_use = index; 2335 2336 return 0; 2337 2338 unmap: 2339 for (;;) { 2340 buffer = &ring->tx_buffer_info[index]; 2341 if (dma_unmap_len(buffer, len)) 2342 dma_unmap_page(ring->dev, 2343 dma_unmap_addr(buffer, dma), 2344 dma_unmap_len(buffer, len), 2345 DMA_TO_DEVICE); 2346 dma_unmap_len_set(buffer, len, 0); 2347 if (buffer == head) 2348 break; 2349 2350 if (!index) 2351 index += ring->count; 2352 index--; 2353 } 2354 2355 return -ENOMEM; 2356 } 2357 2358 static struct igc_ring *igc_xdp_get_tx_ring(struct igc_adapter *adapter, 2359 int cpu) 2360 { 2361 int index = cpu; 2362 2363 if (unlikely(index < 0)) 2364 index = 0; 2365 2366 while (index >= adapter->num_tx_queues) 2367 index -= adapter->num_tx_queues; 2368 2369 return adapter->tx_ring[index]; 2370 } 2371 2372 static int igc_xdp_xmit_back(struct igc_adapter *adapter, struct xdp_buff *xdp) 2373 { 2374 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 2375 int cpu = smp_processor_id(); 2376 struct netdev_queue *nq; 2377 struct igc_ring *ring; 2378 int res; 2379 2380 if (unlikely(!xdpf)) 2381 return -EFAULT; 2382 2383 ring = igc_xdp_get_tx_ring(adapter, cpu); 2384 nq = txring_txq(ring); 2385 2386 __netif_tx_lock(nq, cpu); 2387 res = igc_xdp_init_tx_descriptor(ring, xdpf); 2388 __netif_tx_unlock(nq); 2389 return res; 2390 } 2391 2392 /* This function assumes rcu_read_lock() is held by the caller. */ 2393 static int __igc_xdp_run_prog(struct igc_adapter *adapter, 2394 struct bpf_prog *prog, 2395 struct xdp_buff *xdp) 2396 { 2397 u32 act = bpf_prog_run_xdp(prog, xdp); 2398 2399 switch (act) { 2400 case XDP_PASS: 2401 return IGC_XDP_PASS; 2402 case XDP_TX: 2403 if (igc_xdp_xmit_back(adapter, xdp) < 0) 2404 goto out_failure; 2405 return IGC_XDP_TX; 2406 case XDP_REDIRECT: 2407 if (xdp_do_redirect(adapter->netdev, xdp, prog) < 0) 2408 goto out_failure; 2409 return IGC_XDP_REDIRECT; 2410 break; 2411 default: 2412 bpf_warn_invalid_xdp_action(adapter->netdev, prog, act); 2413 fallthrough; 2414 case XDP_ABORTED: 2415 out_failure: 2416 trace_xdp_exception(adapter->netdev, prog, act); 2417 fallthrough; 2418 case XDP_DROP: 2419 return IGC_XDP_CONSUMED; 2420 } 2421 } 2422 2423 static struct sk_buff *igc_xdp_run_prog(struct igc_adapter *adapter, 2424 struct xdp_buff *xdp) 2425 { 2426 struct bpf_prog *prog; 2427 int res; 2428 2429 prog = READ_ONCE(adapter->xdp_prog); 2430 if (!prog) { 2431 res = IGC_XDP_PASS; 2432 goto out; 2433 } 2434 2435 res = __igc_xdp_run_prog(adapter, prog, xdp); 2436 2437 out: 2438 return ERR_PTR(-res); 2439 } 2440 2441 /* This function assumes __netif_tx_lock is held by the caller. */ 2442 static void igc_flush_tx_descriptors(struct igc_ring *ring) 2443 { 2444 /* Once tail pointer is updated, hardware can fetch the descriptors 2445 * any time so we issue a write membar here to ensure all memory 2446 * writes are complete before the tail pointer is updated. 2447 */ 2448 wmb(); 2449 writel(ring->next_to_use, ring->tail); 2450 } 2451 2452 static void igc_finalize_xdp(struct igc_adapter *adapter, int status) 2453 { 2454 int cpu = smp_processor_id(); 2455 struct netdev_queue *nq; 2456 struct igc_ring *ring; 2457 2458 if (status & IGC_XDP_TX) { 2459 ring = igc_xdp_get_tx_ring(adapter, cpu); 2460 nq = txring_txq(ring); 2461 2462 __netif_tx_lock(nq, cpu); 2463 igc_flush_tx_descriptors(ring); 2464 __netif_tx_unlock(nq); 2465 } 2466 2467 if (status & IGC_XDP_REDIRECT) 2468 xdp_do_flush(); 2469 } 2470 2471 static void igc_update_rx_stats(struct igc_q_vector *q_vector, 2472 unsigned int packets, unsigned int bytes) 2473 { 2474 struct igc_ring *ring = q_vector->rx.ring; 2475 2476 u64_stats_update_begin(&ring->rx_syncp); 2477 ring->rx_stats.packets += packets; 2478 ring->rx_stats.bytes += bytes; 2479 u64_stats_update_end(&ring->rx_syncp); 2480 2481 q_vector->rx.total_packets += packets; 2482 q_vector->rx.total_bytes += bytes; 2483 } 2484 2485 static int igc_clean_rx_irq(struct igc_q_vector *q_vector, const int budget) 2486 { 2487 unsigned int total_bytes = 0, total_packets = 0; 2488 struct igc_adapter *adapter = q_vector->adapter; 2489 struct igc_ring *rx_ring = q_vector->rx.ring; 2490 struct sk_buff *skb = rx_ring->skb; 2491 u16 cleaned_count = igc_desc_unused(rx_ring); 2492 int xdp_status = 0, rx_buffer_pgcnt; 2493 2494 while (likely(total_packets < budget)) { 2495 union igc_adv_rx_desc *rx_desc; 2496 struct igc_rx_buffer *rx_buffer; 2497 unsigned int size, truesize; 2498 ktime_t timestamp = 0; 2499 struct xdp_buff xdp; 2500 int pkt_offset = 0; 2501 void *pktbuf; 2502 2503 /* return some buffers to hardware, one at a time is too slow */ 2504 if (cleaned_count >= IGC_RX_BUFFER_WRITE) { 2505 igc_alloc_rx_buffers(rx_ring, cleaned_count); 2506 cleaned_count = 0; 2507 } 2508 2509 rx_desc = IGC_RX_DESC(rx_ring, rx_ring->next_to_clean); 2510 size = le16_to_cpu(rx_desc->wb.upper.length); 2511 if (!size) 2512 break; 2513 2514 /* This memory barrier is needed to keep us from reading 2515 * any other fields out of the rx_desc until we know the 2516 * descriptor has been written back 2517 */ 2518 dma_rmb(); 2519 2520 rx_buffer = igc_get_rx_buffer(rx_ring, size, &rx_buffer_pgcnt); 2521 truesize = igc_get_rx_frame_truesize(rx_ring, size); 2522 2523 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset; 2524 2525 if (igc_test_staterr(rx_desc, IGC_RXDADV_STAT_TSIP)) { 2526 timestamp = igc_ptp_rx_pktstamp(q_vector->adapter, 2527 pktbuf); 2528 pkt_offset = IGC_TS_HDR_LEN; 2529 size -= IGC_TS_HDR_LEN; 2530 } 2531 2532 if (!skb) { 2533 xdp_init_buff(&xdp, truesize, &rx_ring->xdp_rxq); 2534 xdp_prepare_buff(&xdp, pktbuf - igc_rx_offset(rx_ring), 2535 igc_rx_offset(rx_ring) + pkt_offset, 2536 size, true); 2537 xdp_buff_clear_frags_flag(&xdp); 2538 2539 skb = igc_xdp_run_prog(adapter, &xdp); 2540 } 2541 2542 if (IS_ERR(skb)) { 2543 unsigned int xdp_res = -PTR_ERR(skb); 2544 2545 switch (xdp_res) { 2546 case IGC_XDP_CONSUMED: 2547 rx_buffer->pagecnt_bias++; 2548 break; 2549 case IGC_XDP_TX: 2550 case IGC_XDP_REDIRECT: 2551 igc_rx_buffer_flip(rx_buffer, truesize); 2552 xdp_status |= xdp_res; 2553 break; 2554 } 2555 2556 total_packets++; 2557 total_bytes += size; 2558 } else if (skb) 2559 igc_add_rx_frag(rx_ring, rx_buffer, skb, size); 2560 else if (ring_uses_build_skb(rx_ring)) 2561 skb = igc_build_skb(rx_ring, rx_buffer, &xdp); 2562 else 2563 skb = igc_construct_skb(rx_ring, rx_buffer, &xdp, 2564 timestamp); 2565 2566 /* exit if we failed to retrieve a buffer */ 2567 if (!skb) { 2568 rx_ring->rx_stats.alloc_failed++; 2569 rx_buffer->pagecnt_bias++; 2570 break; 2571 } 2572 2573 igc_put_rx_buffer(rx_ring, rx_buffer, rx_buffer_pgcnt); 2574 cleaned_count++; 2575 2576 /* fetch next buffer in frame if non-eop */ 2577 if (igc_is_non_eop(rx_ring, rx_desc)) 2578 continue; 2579 2580 /* verify the packet layout is correct */ 2581 if (igc_cleanup_headers(rx_ring, rx_desc, skb)) { 2582 skb = NULL; 2583 continue; 2584 } 2585 2586 /* probably a little skewed due to removing CRC */ 2587 total_bytes += skb->len; 2588 2589 /* populate checksum, VLAN, and protocol */ 2590 igc_process_skb_fields(rx_ring, rx_desc, skb); 2591 2592 napi_gro_receive(&q_vector->napi, skb); 2593 2594 /* reset skb pointer */ 2595 skb = NULL; 2596 2597 /* update budget accounting */ 2598 total_packets++; 2599 } 2600 2601 if (xdp_status) 2602 igc_finalize_xdp(adapter, xdp_status); 2603 2604 /* place incomplete frames back on ring for completion */ 2605 rx_ring->skb = skb; 2606 2607 igc_update_rx_stats(q_vector, total_packets, total_bytes); 2608 2609 if (cleaned_count) 2610 igc_alloc_rx_buffers(rx_ring, cleaned_count); 2611 2612 return total_packets; 2613 } 2614 2615 static struct sk_buff *igc_construct_skb_zc(struct igc_ring *ring, 2616 struct xdp_buff *xdp) 2617 { 2618 unsigned int totalsize = xdp->data_end - xdp->data_meta; 2619 unsigned int metasize = xdp->data - xdp->data_meta; 2620 struct sk_buff *skb; 2621 2622 net_prefetch(xdp->data_meta); 2623 2624 skb = __napi_alloc_skb(&ring->q_vector->napi, totalsize, 2625 GFP_ATOMIC | __GFP_NOWARN); 2626 if (unlikely(!skb)) 2627 return NULL; 2628 2629 memcpy(__skb_put(skb, totalsize), xdp->data_meta, 2630 ALIGN(totalsize, sizeof(long))); 2631 2632 if (metasize) { 2633 skb_metadata_set(skb, metasize); 2634 __skb_pull(skb, metasize); 2635 } 2636 2637 return skb; 2638 } 2639 2640 static void igc_dispatch_skb_zc(struct igc_q_vector *q_vector, 2641 union igc_adv_rx_desc *desc, 2642 struct xdp_buff *xdp, 2643 ktime_t timestamp) 2644 { 2645 struct igc_ring *ring = q_vector->rx.ring; 2646 struct sk_buff *skb; 2647 2648 skb = igc_construct_skb_zc(ring, xdp); 2649 if (!skb) { 2650 ring->rx_stats.alloc_failed++; 2651 return; 2652 } 2653 2654 if (timestamp) 2655 skb_hwtstamps(skb)->hwtstamp = timestamp; 2656 2657 if (igc_cleanup_headers(ring, desc, skb)) 2658 return; 2659 2660 igc_process_skb_fields(ring, desc, skb); 2661 napi_gro_receive(&q_vector->napi, skb); 2662 } 2663 2664 static int igc_clean_rx_irq_zc(struct igc_q_vector *q_vector, const int budget) 2665 { 2666 struct igc_adapter *adapter = q_vector->adapter; 2667 struct igc_ring *ring = q_vector->rx.ring; 2668 u16 cleaned_count = igc_desc_unused(ring); 2669 int total_bytes = 0, total_packets = 0; 2670 u16 ntc = ring->next_to_clean; 2671 struct bpf_prog *prog; 2672 bool failure = false; 2673 int xdp_status = 0; 2674 2675 rcu_read_lock(); 2676 2677 prog = READ_ONCE(adapter->xdp_prog); 2678 2679 while (likely(total_packets < budget)) { 2680 union igc_adv_rx_desc *desc; 2681 struct igc_rx_buffer *bi; 2682 ktime_t timestamp = 0; 2683 unsigned int size; 2684 int res; 2685 2686 desc = IGC_RX_DESC(ring, ntc); 2687 size = le16_to_cpu(desc->wb.upper.length); 2688 if (!size) 2689 break; 2690 2691 /* This memory barrier is needed to keep us from reading 2692 * any other fields out of the rx_desc until we know the 2693 * descriptor has been written back 2694 */ 2695 dma_rmb(); 2696 2697 bi = &ring->rx_buffer_info[ntc]; 2698 2699 if (igc_test_staterr(desc, IGC_RXDADV_STAT_TSIP)) { 2700 timestamp = igc_ptp_rx_pktstamp(q_vector->adapter, 2701 bi->xdp->data); 2702 2703 bi->xdp->data += IGC_TS_HDR_LEN; 2704 2705 /* HW timestamp has been copied into local variable. Metadata 2706 * length when XDP program is called should be 0. 2707 */ 2708 bi->xdp->data_meta += IGC_TS_HDR_LEN; 2709 size -= IGC_TS_HDR_LEN; 2710 } 2711 2712 bi->xdp->data_end = bi->xdp->data + size; 2713 xsk_buff_dma_sync_for_cpu(bi->xdp, ring->xsk_pool); 2714 2715 res = __igc_xdp_run_prog(adapter, prog, bi->xdp); 2716 switch (res) { 2717 case IGC_XDP_PASS: 2718 igc_dispatch_skb_zc(q_vector, desc, bi->xdp, timestamp); 2719 fallthrough; 2720 case IGC_XDP_CONSUMED: 2721 xsk_buff_free(bi->xdp); 2722 break; 2723 case IGC_XDP_TX: 2724 case IGC_XDP_REDIRECT: 2725 xdp_status |= res; 2726 break; 2727 } 2728 2729 bi->xdp = NULL; 2730 total_bytes += size; 2731 total_packets++; 2732 cleaned_count++; 2733 ntc++; 2734 if (ntc == ring->count) 2735 ntc = 0; 2736 } 2737 2738 ring->next_to_clean = ntc; 2739 rcu_read_unlock(); 2740 2741 if (cleaned_count >= IGC_RX_BUFFER_WRITE) 2742 failure = !igc_alloc_rx_buffers_zc(ring, cleaned_count); 2743 2744 if (xdp_status) 2745 igc_finalize_xdp(adapter, xdp_status); 2746 2747 igc_update_rx_stats(q_vector, total_packets, total_bytes); 2748 2749 if (xsk_uses_need_wakeup(ring->xsk_pool)) { 2750 if (failure || ring->next_to_clean == ring->next_to_use) 2751 xsk_set_rx_need_wakeup(ring->xsk_pool); 2752 else 2753 xsk_clear_rx_need_wakeup(ring->xsk_pool); 2754 return total_packets; 2755 } 2756 2757 return failure ? budget : total_packets; 2758 } 2759 2760 static void igc_update_tx_stats(struct igc_q_vector *q_vector, 2761 unsigned int packets, unsigned int bytes) 2762 { 2763 struct igc_ring *ring = q_vector->tx.ring; 2764 2765 u64_stats_update_begin(&ring->tx_syncp); 2766 ring->tx_stats.bytes += bytes; 2767 ring->tx_stats.packets += packets; 2768 u64_stats_update_end(&ring->tx_syncp); 2769 2770 q_vector->tx.total_bytes += bytes; 2771 q_vector->tx.total_packets += packets; 2772 } 2773 2774 static void igc_xdp_xmit_zc(struct igc_ring *ring) 2775 { 2776 struct xsk_buff_pool *pool = ring->xsk_pool; 2777 struct netdev_queue *nq = txring_txq(ring); 2778 union igc_adv_tx_desc *tx_desc = NULL; 2779 int cpu = smp_processor_id(); 2780 u16 ntu = ring->next_to_use; 2781 struct xdp_desc xdp_desc; 2782 u16 budget; 2783 2784 if (!netif_carrier_ok(ring->netdev)) 2785 return; 2786 2787 __netif_tx_lock(nq, cpu); 2788 2789 budget = igc_desc_unused(ring); 2790 2791 while (xsk_tx_peek_desc(pool, &xdp_desc) && budget--) { 2792 u32 cmd_type, olinfo_status; 2793 struct igc_tx_buffer *bi; 2794 dma_addr_t dma; 2795 2796 cmd_type = IGC_ADVTXD_DTYP_DATA | IGC_ADVTXD_DCMD_DEXT | 2797 IGC_ADVTXD_DCMD_IFCS | IGC_TXD_DCMD | 2798 xdp_desc.len; 2799 olinfo_status = xdp_desc.len << IGC_ADVTXD_PAYLEN_SHIFT; 2800 2801 dma = xsk_buff_raw_get_dma(pool, xdp_desc.addr); 2802 xsk_buff_raw_dma_sync_for_device(pool, dma, xdp_desc.len); 2803 2804 tx_desc = IGC_TX_DESC(ring, ntu); 2805 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 2806 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 2807 tx_desc->read.buffer_addr = cpu_to_le64(dma); 2808 2809 bi = &ring->tx_buffer_info[ntu]; 2810 bi->type = IGC_TX_BUFFER_TYPE_XSK; 2811 bi->protocol = 0; 2812 bi->bytecount = xdp_desc.len; 2813 bi->gso_segs = 1; 2814 bi->time_stamp = jiffies; 2815 bi->next_to_watch = tx_desc; 2816 2817 netdev_tx_sent_queue(txring_txq(ring), xdp_desc.len); 2818 2819 ntu++; 2820 if (ntu == ring->count) 2821 ntu = 0; 2822 } 2823 2824 ring->next_to_use = ntu; 2825 if (tx_desc) { 2826 igc_flush_tx_descriptors(ring); 2827 xsk_tx_release(pool); 2828 } 2829 2830 __netif_tx_unlock(nq); 2831 } 2832 2833 /** 2834 * igc_clean_tx_irq - Reclaim resources after transmit completes 2835 * @q_vector: pointer to q_vector containing needed info 2836 * @napi_budget: Used to determine if we are in netpoll 2837 * 2838 * returns true if ring is completely cleaned 2839 */ 2840 static bool igc_clean_tx_irq(struct igc_q_vector *q_vector, int napi_budget) 2841 { 2842 struct igc_adapter *adapter = q_vector->adapter; 2843 unsigned int total_bytes = 0, total_packets = 0; 2844 unsigned int budget = q_vector->tx.work_limit; 2845 struct igc_ring *tx_ring = q_vector->tx.ring; 2846 unsigned int i = tx_ring->next_to_clean; 2847 struct igc_tx_buffer *tx_buffer; 2848 union igc_adv_tx_desc *tx_desc; 2849 u32 xsk_frames = 0; 2850 2851 if (test_bit(__IGC_DOWN, &adapter->state)) 2852 return true; 2853 2854 tx_buffer = &tx_ring->tx_buffer_info[i]; 2855 tx_desc = IGC_TX_DESC(tx_ring, i); 2856 i -= tx_ring->count; 2857 2858 do { 2859 union igc_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 2860 2861 /* if next_to_watch is not set then there is no work pending */ 2862 if (!eop_desc) 2863 break; 2864 2865 /* prevent any other reads prior to eop_desc */ 2866 smp_rmb(); 2867 2868 /* if DD is not set pending work has not been completed */ 2869 if (!(eop_desc->wb.status & cpu_to_le32(IGC_TXD_STAT_DD))) 2870 break; 2871 2872 /* clear next_to_watch to prevent false hangs */ 2873 tx_buffer->next_to_watch = NULL; 2874 2875 /* update the statistics for this packet */ 2876 total_bytes += tx_buffer->bytecount; 2877 total_packets += tx_buffer->gso_segs; 2878 2879 switch (tx_buffer->type) { 2880 case IGC_TX_BUFFER_TYPE_XSK: 2881 xsk_frames++; 2882 break; 2883 case IGC_TX_BUFFER_TYPE_XDP: 2884 xdp_return_frame(tx_buffer->xdpf); 2885 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 2886 break; 2887 case IGC_TX_BUFFER_TYPE_SKB: 2888 napi_consume_skb(tx_buffer->skb, napi_budget); 2889 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 2890 break; 2891 default: 2892 netdev_warn_once(tx_ring->netdev, "Unknown Tx buffer type\n"); 2893 break; 2894 } 2895 2896 /* clear last DMA location and unmap remaining buffers */ 2897 while (tx_desc != eop_desc) { 2898 tx_buffer++; 2899 tx_desc++; 2900 i++; 2901 if (unlikely(!i)) { 2902 i -= tx_ring->count; 2903 tx_buffer = tx_ring->tx_buffer_info; 2904 tx_desc = IGC_TX_DESC(tx_ring, 0); 2905 } 2906 2907 /* unmap any remaining paged data */ 2908 if (dma_unmap_len(tx_buffer, len)) 2909 igc_unmap_tx_buffer(tx_ring->dev, tx_buffer); 2910 } 2911 2912 /* move us one more past the eop_desc for start of next pkt */ 2913 tx_buffer++; 2914 tx_desc++; 2915 i++; 2916 if (unlikely(!i)) { 2917 i -= tx_ring->count; 2918 tx_buffer = tx_ring->tx_buffer_info; 2919 tx_desc = IGC_TX_DESC(tx_ring, 0); 2920 } 2921 2922 /* issue prefetch for next Tx descriptor */ 2923 prefetch(tx_desc); 2924 2925 /* update budget accounting */ 2926 budget--; 2927 } while (likely(budget)); 2928 2929 netdev_tx_completed_queue(txring_txq(tx_ring), 2930 total_packets, total_bytes); 2931 2932 i += tx_ring->count; 2933 tx_ring->next_to_clean = i; 2934 2935 igc_update_tx_stats(q_vector, total_packets, total_bytes); 2936 2937 if (tx_ring->xsk_pool) { 2938 if (xsk_frames) 2939 xsk_tx_completed(tx_ring->xsk_pool, xsk_frames); 2940 if (xsk_uses_need_wakeup(tx_ring->xsk_pool)) 2941 xsk_set_tx_need_wakeup(tx_ring->xsk_pool); 2942 igc_xdp_xmit_zc(tx_ring); 2943 } 2944 2945 if (test_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 2946 struct igc_hw *hw = &adapter->hw; 2947 2948 /* Detect a transmit hang in hardware, this serializes the 2949 * check with the clearing of time_stamp and movement of i 2950 */ 2951 clear_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 2952 if (tx_buffer->next_to_watch && 2953 time_after(jiffies, tx_buffer->time_stamp + 2954 (adapter->tx_timeout_factor * HZ)) && 2955 !(rd32(IGC_STATUS) & IGC_STATUS_TXOFF) && 2956 (rd32(IGC_TDH(tx_ring->reg_idx)) != 2957 readl(tx_ring->tail))) { 2958 /* detected Tx unit hang */ 2959 netdev_err(tx_ring->netdev, 2960 "Detected Tx Unit Hang\n" 2961 " Tx Queue <%d>\n" 2962 " TDH <%x>\n" 2963 " TDT <%x>\n" 2964 " next_to_use <%x>\n" 2965 " next_to_clean <%x>\n" 2966 "buffer_info[next_to_clean]\n" 2967 " time_stamp <%lx>\n" 2968 " next_to_watch <%p>\n" 2969 " jiffies <%lx>\n" 2970 " desc.status <%x>\n", 2971 tx_ring->queue_index, 2972 rd32(IGC_TDH(tx_ring->reg_idx)), 2973 readl(tx_ring->tail), 2974 tx_ring->next_to_use, 2975 tx_ring->next_to_clean, 2976 tx_buffer->time_stamp, 2977 tx_buffer->next_to_watch, 2978 jiffies, 2979 tx_buffer->next_to_watch->wb.status); 2980 netif_stop_subqueue(tx_ring->netdev, 2981 tx_ring->queue_index); 2982 2983 /* we are about to reset, no point in enabling stuff */ 2984 return true; 2985 } 2986 } 2987 2988 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 2989 if (unlikely(total_packets && 2990 netif_carrier_ok(tx_ring->netdev) && 2991 igc_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 2992 /* Make sure that anybody stopping the queue after this 2993 * sees the new next_to_clean. 2994 */ 2995 smp_mb(); 2996 if (__netif_subqueue_stopped(tx_ring->netdev, 2997 tx_ring->queue_index) && 2998 !(test_bit(__IGC_DOWN, &adapter->state))) { 2999 netif_wake_subqueue(tx_ring->netdev, 3000 tx_ring->queue_index); 3001 3002 u64_stats_update_begin(&tx_ring->tx_syncp); 3003 tx_ring->tx_stats.restart_queue++; 3004 u64_stats_update_end(&tx_ring->tx_syncp); 3005 } 3006 } 3007 3008 return !!budget; 3009 } 3010 3011 static int igc_find_mac_filter(struct igc_adapter *adapter, 3012 enum igc_mac_filter_type type, const u8 *addr) 3013 { 3014 struct igc_hw *hw = &adapter->hw; 3015 int max_entries = hw->mac.rar_entry_count; 3016 u32 ral, rah; 3017 int i; 3018 3019 for (i = 0; i < max_entries; i++) { 3020 ral = rd32(IGC_RAL(i)); 3021 rah = rd32(IGC_RAH(i)); 3022 3023 if (!(rah & IGC_RAH_AV)) 3024 continue; 3025 if (!!(rah & IGC_RAH_ASEL_SRC_ADDR) != type) 3026 continue; 3027 if ((rah & IGC_RAH_RAH_MASK) != 3028 le16_to_cpup((__le16 *)(addr + 4))) 3029 continue; 3030 if (ral != le32_to_cpup((__le32 *)(addr))) 3031 continue; 3032 3033 return i; 3034 } 3035 3036 return -1; 3037 } 3038 3039 static int igc_get_avail_mac_filter_slot(struct igc_adapter *adapter) 3040 { 3041 struct igc_hw *hw = &adapter->hw; 3042 int max_entries = hw->mac.rar_entry_count; 3043 u32 rah; 3044 int i; 3045 3046 for (i = 0; i < max_entries; i++) { 3047 rah = rd32(IGC_RAH(i)); 3048 3049 if (!(rah & IGC_RAH_AV)) 3050 return i; 3051 } 3052 3053 return -1; 3054 } 3055 3056 /** 3057 * igc_add_mac_filter() - Add MAC address filter 3058 * @adapter: Pointer to adapter where the filter should be added 3059 * @type: MAC address filter type (source or destination) 3060 * @addr: MAC address 3061 * @queue: If non-negative, queue assignment feature is enabled and frames 3062 * matching the filter are enqueued onto 'queue'. Otherwise, queue 3063 * assignment is disabled. 3064 * 3065 * Return: 0 in case of success, negative errno code otherwise. 3066 */ 3067 static int igc_add_mac_filter(struct igc_adapter *adapter, 3068 enum igc_mac_filter_type type, const u8 *addr, 3069 int queue) 3070 { 3071 struct net_device *dev = adapter->netdev; 3072 int index; 3073 3074 index = igc_find_mac_filter(adapter, type, addr); 3075 if (index >= 0) 3076 goto update_filter; 3077 3078 index = igc_get_avail_mac_filter_slot(adapter); 3079 if (index < 0) 3080 return -ENOSPC; 3081 3082 netdev_dbg(dev, "Add MAC address filter: index %d type %s address %pM queue %d\n", 3083 index, type == IGC_MAC_FILTER_TYPE_DST ? "dst" : "src", 3084 addr, queue); 3085 3086 update_filter: 3087 igc_set_mac_filter_hw(adapter, index, type, addr, queue); 3088 return 0; 3089 } 3090 3091 /** 3092 * igc_del_mac_filter() - Delete MAC address filter 3093 * @adapter: Pointer to adapter where the filter should be deleted from 3094 * @type: MAC address filter type (source or destination) 3095 * @addr: MAC address 3096 */ 3097 static void igc_del_mac_filter(struct igc_adapter *adapter, 3098 enum igc_mac_filter_type type, const u8 *addr) 3099 { 3100 struct net_device *dev = adapter->netdev; 3101 int index; 3102 3103 index = igc_find_mac_filter(adapter, type, addr); 3104 if (index < 0) 3105 return; 3106 3107 if (index == 0) { 3108 /* If this is the default filter, we don't actually delete it. 3109 * We just reset to its default value i.e. disable queue 3110 * assignment. 3111 */ 3112 netdev_dbg(dev, "Disable default MAC filter queue assignment"); 3113 3114 igc_set_mac_filter_hw(adapter, 0, type, addr, -1); 3115 } else { 3116 netdev_dbg(dev, "Delete MAC address filter: index %d type %s address %pM\n", 3117 index, 3118 type == IGC_MAC_FILTER_TYPE_DST ? "dst" : "src", 3119 addr); 3120 3121 igc_clear_mac_filter_hw(adapter, index); 3122 } 3123 } 3124 3125 /** 3126 * igc_add_vlan_prio_filter() - Add VLAN priority filter 3127 * @adapter: Pointer to adapter where the filter should be added 3128 * @prio: VLAN priority value 3129 * @queue: Queue number which matching frames are assigned to 3130 * 3131 * Return: 0 in case of success, negative errno code otherwise. 3132 */ 3133 static int igc_add_vlan_prio_filter(struct igc_adapter *adapter, int prio, 3134 int queue) 3135 { 3136 struct net_device *dev = adapter->netdev; 3137 struct igc_hw *hw = &adapter->hw; 3138 u32 vlanpqf; 3139 3140 vlanpqf = rd32(IGC_VLANPQF); 3141 3142 if (vlanpqf & IGC_VLANPQF_VALID(prio)) { 3143 netdev_dbg(dev, "VLAN priority filter already in use\n"); 3144 return -EEXIST; 3145 } 3146 3147 vlanpqf |= IGC_VLANPQF_QSEL(prio, queue); 3148 vlanpqf |= IGC_VLANPQF_VALID(prio); 3149 3150 wr32(IGC_VLANPQF, vlanpqf); 3151 3152 netdev_dbg(dev, "Add VLAN priority filter: prio %d queue %d\n", 3153 prio, queue); 3154 return 0; 3155 } 3156 3157 /** 3158 * igc_del_vlan_prio_filter() - Delete VLAN priority filter 3159 * @adapter: Pointer to adapter where the filter should be deleted from 3160 * @prio: VLAN priority value 3161 */ 3162 static void igc_del_vlan_prio_filter(struct igc_adapter *adapter, int prio) 3163 { 3164 struct igc_hw *hw = &adapter->hw; 3165 u32 vlanpqf; 3166 3167 vlanpqf = rd32(IGC_VLANPQF); 3168 3169 vlanpqf &= ~IGC_VLANPQF_VALID(prio); 3170 vlanpqf &= ~IGC_VLANPQF_QSEL(prio, IGC_VLANPQF_QUEUE_MASK); 3171 3172 wr32(IGC_VLANPQF, vlanpqf); 3173 3174 netdev_dbg(adapter->netdev, "Delete VLAN priority filter: prio %d\n", 3175 prio); 3176 } 3177 3178 static int igc_get_avail_etype_filter_slot(struct igc_adapter *adapter) 3179 { 3180 struct igc_hw *hw = &adapter->hw; 3181 int i; 3182 3183 for (i = 0; i < MAX_ETYPE_FILTER; i++) { 3184 u32 etqf = rd32(IGC_ETQF(i)); 3185 3186 if (!(etqf & IGC_ETQF_FILTER_ENABLE)) 3187 return i; 3188 } 3189 3190 return -1; 3191 } 3192 3193 /** 3194 * igc_add_etype_filter() - Add ethertype filter 3195 * @adapter: Pointer to adapter where the filter should be added 3196 * @etype: Ethertype value 3197 * @queue: If non-negative, queue assignment feature is enabled and frames 3198 * matching the filter are enqueued onto 'queue'. Otherwise, queue 3199 * assignment is disabled. 3200 * 3201 * Return: 0 in case of success, negative errno code otherwise. 3202 */ 3203 static int igc_add_etype_filter(struct igc_adapter *adapter, u16 etype, 3204 int queue) 3205 { 3206 struct igc_hw *hw = &adapter->hw; 3207 int index; 3208 u32 etqf; 3209 3210 index = igc_get_avail_etype_filter_slot(adapter); 3211 if (index < 0) 3212 return -ENOSPC; 3213 3214 etqf = rd32(IGC_ETQF(index)); 3215 3216 etqf &= ~IGC_ETQF_ETYPE_MASK; 3217 etqf |= etype; 3218 3219 if (queue >= 0) { 3220 etqf &= ~IGC_ETQF_QUEUE_MASK; 3221 etqf |= (queue << IGC_ETQF_QUEUE_SHIFT); 3222 etqf |= IGC_ETQF_QUEUE_ENABLE; 3223 } 3224 3225 etqf |= IGC_ETQF_FILTER_ENABLE; 3226 3227 wr32(IGC_ETQF(index), etqf); 3228 3229 netdev_dbg(adapter->netdev, "Add ethertype filter: etype %04x queue %d\n", 3230 etype, queue); 3231 return 0; 3232 } 3233 3234 static int igc_find_etype_filter(struct igc_adapter *adapter, u16 etype) 3235 { 3236 struct igc_hw *hw = &adapter->hw; 3237 int i; 3238 3239 for (i = 0; i < MAX_ETYPE_FILTER; i++) { 3240 u32 etqf = rd32(IGC_ETQF(i)); 3241 3242 if ((etqf & IGC_ETQF_ETYPE_MASK) == etype) 3243 return i; 3244 } 3245 3246 return -1; 3247 } 3248 3249 /** 3250 * igc_del_etype_filter() - Delete ethertype filter 3251 * @adapter: Pointer to adapter where the filter should be deleted from 3252 * @etype: Ethertype value 3253 */ 3254 static void igc_del_etype_filter(struct igc_adapter *adapter, u16 etype) 3255 { 3256 struct igc_hw *hw = &adapter->hw; 3257 int index; 3258 3259 index = igc_find_etype_filter(adapter, etype); 3260 if (index < 0) 3261 return; 3262 3263 wr32(IGC_ETQF(index), 0); 3264 3265 netdev_dbg(adapter->netdev, "Delete ethertype filter: etype %04x\n", 3266 etype); 3267 } 3268 3269 static int igc_flex_filter_select(struct igc_adapter *adapter, 3270 struct igc_flex_filter *input, 3271 u32 *fhft) 3272 { 3273 struct igc_hw *hw = &adapter->hw; 3274 u8 fhft_index; 3275 u32 fhftsl; 3276 3277 if (input->index >= MAX_FLEX_FILTER) { 3278 dev_err(&adapter->pdev->dev, "Wrong Flex Filter index selected!\n"); 3279 return -EINVAL; 3280 } 3281 3282 /* Indirect table select register */ 3283 fhftsl = rd32(IGC_FHFTSL); 3284 fhftsl &= ~IGC_FHFTSL_FTSL_MASK; 3285 switch (input->index) { 3286 case 0 ... 7: 3287 fhftsl |= 0x00; 3288 break; 3289 case 8 ... 15: 3290 fhftsl |= 0x01; 3291 break; 3292 case 16 ... 23: 3293 fhftsl |= 0x02; 3294 break; 3295 case 24 ... 31: 3296 fhftsl |= 0x03; 3297 break; 3298 } 3299 wr32(IGC_FHFTSL, fhftsl); 3300 3301 /* Normalize index down to host table register */ 3302 fhft_index = input->index % 8; 3303 3304 *fhft = (fhft_index < 4) ? IGC_FHFT(fhft_index) : 3305 IGC_FHFT_EXT(fhft_index - 4); 3306 3307 return 0; 3308 } 3309 3310 static int igc_write_flex_filter_ll(struct igc_adapter *adapter, 3311 struct igc_flex_filter *input) 3312 { 3313 struct device *dev = &adapter->pdev->dev; 3314 struct igc_hw *hw = &adapter->hw; 3315 u8 *data = input->data; 3316 u8 *mask = input->mask; 3317 u32 queuing; 3318 u32 fhft; 3319 u32 wufc; 3320 int ret; 3321 int i; 3322 3323 /* Length has to be aligned to 8. Otherwise the filter will fail. Bail 3324 * out early to avoid surprises later. 3325 */ 3326 if (input->length % 8 != 0) { 3327 dev_err(dev, "The length of a flex filter has to be 8 byte aligned!\n"); 3328 return -EINVAL; 3329 } 3330 3331 /* Select corresponding flex filter register and get base for host table. */ 3332 ret = igc_flex_filter_select(adapter, input, &fhft); 3333 if (ret) 3334 return ret; 3335 3336 /* When adding a filter globally disable flex filter feature. That is 3337 * recommended within the datasheet. 3338 */ 3339 wufc = rd32(IGC_WUFC); 3340 wufc &= ~IGC_WUFC_FLEX_HQ; 3341 wr32(IGC_WUFC, wufc); 3342 3343 /* Configure filter */ 3344 queuing = input->length & IGC_FHFT_LENGTH_MASK; 3345 queuing |= (input->rx_queue << IGC_FHFT_QUEUE_SHIFT) & IGC_FHFT_QUEUE_MASK; 3346 queuing |= (input->prio << IGC_FHFT_PRIO_SHIFT) & IGC_FHFT_PRIO_MASK; 3347 3348 if (input->immediate_irq) 3349 queuing |= IGC_FHFT_IMM_INT; 3350 3351 if (input->drop) 3352 queuing |= IGC_FHFT_DROP; 3353 3354 wr32(fhft + 0xFC, queuing); 3355 3356 /* Write data (128 byte) and mask (128 bit) */ 3357 for (i = 0; i < 16; ++i) { 3358 const size_t data_idx = i * 8; 3359 const size_t row_idx = i * 16; 3360 u32 dw0 = 3361 (data[data_idx + 0] << 0) | 3362 (data[data_idx + 1] << 8) | 3363 (data[data_idx + 2] << 16) | 3364 (data[data_idx + 3] << 24); 3365 u32 dw1 = 3366 (data[data_idx + 4] << 0) | 3367 (data[data_idx + 5] << 8) | 3368 (data[data_idx + 6] << 16) | 3369 (data[data_idx + 7] << 24); 3370 u32 tmp; 3371 3372 /* Write row: dw0, dw1 and mask */ 3373 wr32(fhft + row_idx, dw0); 3374 wr32(fhft + row_idx + 4, dw1); 3375 3376 /* mask is only valid for MASK(7, 0) */ 3377 tmp = rd32(fhft + row_idx + 8); 3378 tmp &= ~GENMASK(7, 0); 3379 tmp |= mask[i]; 3380 wr32(fhft + row_idx + 8, tmp); 3381 } 3382 3383 /* Enable filter. */ 3384 wufc |= IGC_WUFC_FLEX_HQ; 3385 if (input->index > 8) { 3386 /* Filter 0-7 are enabled via WUFC. The other 24 filters are not. */ 3387 u32 wufc_ext = rd32(IGC_WUFC_EXT); 3388 3389 wufc_ext |= (IGC_WUFC_EXT_FLX8 << (input->index - 8)); 3390 3391 wr32(IGC_WUFC_EXT, wufc_ext); 3392 } else { 3393 wufc |= (IGC_WUFC_FLX0 << input->index); 3394 } 3395 wr32(IGC_WUFC, wufc); 3396 3397 dev_dbg(&adapter->pdev->dev, "Added flex filter %u to HW.\n", 3398 input->index); 3399 3400 return 0; 3401 } 3402 3403 static void igc_flex_filter_add_field(struct igc_flex_filter *flex, 3404 const void *src, unsigned int offset, 3405 size_t len, const void *mask) 3406 { 3407 int i; 3408 3409 /* data */ 3410 memcpy(&flex->data[offset], src, len); 3411 3412 /* mask */ 3413 for (i = 0; i < len; ++i) { 3414 const unsigned int idx = i + offset; 3415 const u8 *ptr = mask; 3416 3417 if (mask) { 3418 if (ptr[i] & 0xff) 3419 flex->mask[idx / 8] |= BIT(idx % 8); 3420 3421 continue; 3422 } 3423 3424 flex->mask[idx / 8] |= BIT(idx % 8); 3425 } 3426 } 3427 3428 static int igc_find_avail_flex_filter_slot(struct igc_adapter *adapter) 3429 { 3430 struct igc_hw *hw = &adapter->hw; 3431 u32 wufc, wufc_ext; 3432 int i; 3433 3434 wufc = rd32(IGC_WUFC); 3435 wufc_ext = rd32(IGC_WUFC_EXT); 3436 3437 for (i = 0; i < MAX_FLEX_FILTER; i++) { 3438 if (i < 8) { 3439 if (!(wufc & (IGC_WUFC_FLX0 << i))) 3440 return i; 3441 } else { 3442 if (!(wufc_ext & (IGC_WUFC_EXT_FLX8 << (i - 8)))) 3443 return i; 3444 } 3445 } 3446 3447 return -ENOSPC; 3448 } 3449 3450 static bool igc_flex_filter_in_use(struct igc_adapter *adapter) 3451 { 3452 struct igc_hw *hw = &adapter->hw; 3453 u32 wufc, wufc_ext; 3454 3455 wufc = rd32(IGC_WUFC); 3456 wufc_ext = rd32(IGC_WUFC_EXT); 3457 3458 if (wufc & IGC_WUFC_FILTER_MASK) 3459 return true; 3460 3461 if (wufc_ext & IGC_WUFC_EXT_FILTER_MASK) 3462 return true; 3463 3464 return false; 3465 } 3466 3467 static int igc_add_flex_filter(struct igc_adapter *adapter, 3468 struct igc_nfc_rule *rule) 3469 { 3470 struct igc_flex_filter flex = { }; 3471 struct igc_nfc_filter *filter = &rule->filter; 3472 unsigned int eth_offset, user_offset; 3473 int ret, index; 3474 bool vlan; 3475 3476 index = igc_find_avail_flex_filter_slot(adapter); 3477 if (index < 0) 3478 return -ENOSPC; 3479 3480 /* Construct the flex filter: 3481 * -> dest_mac [6] 3482 * -> src_mac [6] 3483 * -> tpid [2] 3484 * -> vlan tci [2] 3485 * -> ether type [2] 3486 * -> user data [8] 3487 * -> = 26 bytes => 32 length 3488 */ 3489 flex.index = index; 3490 flex.length = 32; 3491 flex.rx_queue = rule->action; 3492 3493 vlan = rule->filter.vlan_tci || rule->filter.vlan_etype; 3494 eth_offset = vlan ? 16 : 12; 3495 user_offset = vlan ? 18 : 14; 3496 3497 /* Add destination MAC */ 3498 if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR) 3499 igc_flex_filter_add_field(&flex, &filter->dst_addr, 0, 3500 ETH_ALEN, NULL); 3501 3502 /* Add source MAC */ 3503 if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR) 3504 igc_flex_filter_add_field(&flex, &filter->src_addr, 6, 3505 ETH_ALEN, NULL); 3506 3507 /* Add VLAN etype */ 3508 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_ETYPE) 3509 igc_flex_filter_add_field(&flex, &filter->vlan_etype, 12, 3510 sizeof(filter->vlan_etype), 3511 NULL); 3512 3513 /* Add VLAN TCI */ 3514 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) 3515 igc_flex_filter_add_field(&flex, &filter->vlan_tci, 14, 3516 sizeof(filter->vlan_tci), NULL); 3517 3518 /* Add Ether type */ 3519 if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) { 3520 __be16 etype = cpu_to_be16(filter->etype); 3521 3522 igc_flex_filter_add_field(&flex, &etype, eth_offset, 3523 sizeof(etype), NULL); 3524 } 3525 3526 /* Add user data */ 3527 if (rule->filter.match_flags & IGC_FILTER_FLAG_USER_DATA) 3528 igc_flex_filter_add_field(&flex, &filter->user_data, 3529 user_offset, 3530 sizeof(filter->user_data), 3531 filter->user_mask); 3532 3533 /* Add it down to the hardware and enable it. */ 3534 ret = igc_write_flex_filter_ll(adapter, &flex); 3535 if (ret) 3536 return ret; 3537 3538 filter->flex_index = index; 3539 3540 return 0; 3541 } 3542 3543 static void igc_del_flex_filter(struct igc_adapter *adapter, 3544 u16 reg_index) 3545 { 3546 struct igc_hw *hw = &adapter->hw; 3547 u32 wufc; 3548 3549 /* Just disable the filter. The filter table itself is kept 3550 * intact. Another flex_filter_add() should override the "old" data 3551 * then. 3552 */ 3553 if (reg_index > 8) { 3554 u32 wufc_ext = rd32(IGC_WUFC_EXT); 3555 3556 wufc_ext &= ~(IGC_WUFC_EXT_FLX8 << (reg_index - 8)); 3557 wr32(IGC_WUFC_EXT, wufc_ext); 3558 } else { 3559 wufc = rd32(IGC_WUFC); 3560 3561 wufc &= ~(IGC_WUFC_FLX0 << reg_index); 3562 wr32(IGC_WUFC, wufc); 3563 } 3564 3565 if (igc_flex_filter_in_use(adapter)) 3566 return; 3567 3568 /* No filters are in use, we may disable flex filters */ 3569 wufc = rd32(IGC_WUFC); 3570 wufc &= ~IGC_WUFC_FLEX_HQ; 3571 wr32(IGC_WUFC, wufc); 3572 } 3573 3574 static int igc_enable_nfc_rule(struct igc_adapter *adapter, 3575 struct igc_nfc_rule *rule) 3576 { 3577 int err; 3578 3579 if (rule->flex) { 3580 return igc_add_flex_filter(adapter, rule); 3581 } 3582 3583 if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) { 3584 err = igc_add_etype_filter(adapter, rule->filter.etype, 3585 rule->action); 3586 if (err) 3587 return err; 3588 } 3589 3590 if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR) { 3591 err = igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_SRC, 3592 rule->filter.src_addr, rule->action); 3593 if (err) 3594 return err; 3595 } 3596 3597 if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR) { 3598 err = igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, 3599 rule->filter.dst_addr, rule->action); 3600 if (err) 3601 return err; 3602 } 3603 3604 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) { 3605 int prio = (rule->filter.vlan_tci & VLAN_PRIO_MASK) >> 3606 VLAN_PRIO_SHIFT; 3607 3608 err = igc_add_vlan_prio_filter(adapter, prio, rule->action); 3609 if (err) 3610 return err; 3611 } 3612 3613 return 0; 3614 } 3615 3616 static void igc_disable_nfc_rule(struct igc_adapter *adapter, 3617 const struct igc_nfc_rule *rule) 3618 { 3619 if (rule->flex) { 3620 igc_del_flex_filter(adapter, rule->filter.flex_index); 3621 return; 3622 } 3623 3624 if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) 3625 igc_del_etype_filter(adapter, rule->filter.etype); 3626 3627 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) { 3628 int prio = (rule->filter.vlan_tci & VLAN_PRIO_MASK) >> 3629 VLAN_PRIO_SHIFT; 3630 3631 igc_del_vlan_prio_filter(adapter, prio); 3632 } 3633 3634 if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR) 3635 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_SRC, 3636 rule->filter.src_addr); 3637 3638 if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR) 3639 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, 3640 rule->filter.dst_addr); 3641 } 3642 3643 /** 3644 * igc_get_nfc_rule() - Get NFC rule 3645 * @adapter: Pointer to adapter 3646 * @location: Rule location 3647 * 3648 * Context: Expects adapter->nfc_rule_lock to be held by caller. 3649 * 3650 * Return: Pointer to NFC rule at @location. If not found, NULL. 3651 */ 3652 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter, 3653 u32 location) 3654 { 3655 struct igc_nfc_rule *rule; 3656 3657 list_for_each_entry(rule, &adapter->nfc_rule_list, list) { 3658 if (rule->location == location) 3659 return rule; 3660 if (rule->location > location) 3661 break; 3662 } 3663 3664 return NULL; 3665 } 3666 3667 /** 3668 * igc_del_nfc_rule() - Delete NFC rule 3669 * @adapter: Pointer to adapter 3670 * @rule: Pointer to rule to be deleted 3671 * 3672 * Disable NFC rule in hardware and delete it from adapter. 3673 * 3674 * Context: Expects adapter->nfc_rule_lock to be held by caller. 3675 */ 3676 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule) 3677 { 3678 igc_disable_nfc_rule(adapter, rule); 3679 3680 list_del(&rule->list); 3681 adapter->nfc_rule_count--; 3682 3683 kfree(rule); 3684 } 3685 3686 static void igc_flush_nfc_rules(struct igc_adapter *adapter) 3687 { 3688 struct igc_nfc_rule *rule, *tmp; 3689 3690 mutex_lock(&adapter->nfc_rule_lock); 3691 3692 list_for_each_entry_safe(rule, tmp, &adapter->nfc_rule_list, list) 3693 igc_del_nfc_rule(adapter, rule); 3694 3695 mutex_unlock(&adapter->nfc_rule_lock); 3696 } 3697 3698 /** 3699 * igc_add_nfc_rule() - Add NFC rule 3700 * @adapter: Pointer to adapter 3701 * @rule: Pointer to rule to be added 3702 * 3703 * Enable NFC rule in hardware and add it to adapter. 3704 * 3705 * Context: Expects adapter->nfc_rule_lock to be held by caller. 3706 * 3707 * Return: 0 on success, negative errno on failure. 3708 */ 3709 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule) 3710 { 3711 struct igc_nfc_rule *pred, *cur; 3712 int err; 3713 3714 err = igc_enable_nfc_rule(adapter, rule); 3715 if (err) 3716 return err; 3717 3718 pred = NULL; 3719 list_for_each_entry(cur, &adapter->nfc_rule_list, list) { 3720 if (cur->location >= rule->location) 3721 break; 3722 pred = cur; 3723 } 3724 3725 list_add(&rule->list, pred ? &pred->list : &adapter->nfc_rule_list); 3726 adapter->nfc_rule_count++; 3727 return 0; 3728 } 3729 3730 static void igc_restore_nfc_rules(struct igc_adapter *adapter) 3731 { 3732 struct igc_nfc_rule *rule; 3733 3734 mutex_lock(&adapter->nfc_rule_lock); 3735 3736 list_for_each_entry_reverse(rule, &adapter->nfc_rule_list, list) 3737 igc_enable_nfc_rule(adapter, rule); 3738 3739 mutex_unlock(&adapter->nfc_rule_lock); 3740 } 3741 3742 static int igc_uc_sync(struct net_device *netdev, const unsigned char *addr) 3743 { 3744 struct igc_adapter *adapter = netdev_priv(netdev); 3745 3746 return igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, addr, -1); 3747 } 3748 3749 static int igc_uc_unsync(struct net_device *netdev, const unsigned char *addr) 3750 { 3751 struct igc_adapter *adapter = netdev_priv(netdev); 3752 3753 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, addr); 3754 return 0; 3755 } 3756 3757 /** 3758 * igc_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 3759 * @netdev: network interface device structure 3760 * 3761 * The set_rx_mode entry point is called whenever the unicast or multicast 3762 * address lists or the network interface flags are updated. This routine is 3763 * responsible for configuring the hardware for proper unicast, multicast, 3764 * promiscuous mode, and all-multi behavior. 3765 */ 3766 static void igc_set_rx_mode(struct net_device *netdev) 3767 { 3768 struct igc_adapter *adapter = netdev_priv(netdev); 3769 struct igc_hw *hw = &adapter->hw; 3770 u32 rctl = 0, rlpml = MAX_JUMBO_FRAME_SIZE; 3771 int count; 3772 3773 /* Check for Promiscuous and All Multicast modes */ 3774 if (netdev->flags & IFF_PROMISC) { 3775 rctl |= IGC_RCTL_UPE | IGC_RCTL_MPE; 3776 } else { 3777 if (netdev->flags & IFF_ALLMULTI) { 3778 rctl |= IGC_RCTL_MPE; 3779 } else { 3780 /* Write addresses to the MTA, if the attempt fails 3781 * then we should just turn on promiscuous mode so 3782 * that we can at least receive multicast traffic 3783 */ 3784 count = igc_write_mc_addr_list(netdev); 3785 if (count < 0) 3786 rctl |= IGC_RCTL_MPE; 3787 } 3788 } 3789 3790 /* Write addresses to available RAR registers, if there is not 3791 * sufficient space to store all the addresses then enable 3792 * unicast promiscuous mode 3793 */ 3794 if (__dev_uc_sync(netdev, igc_uc_sync, igc_uc_unsync)) 3795 rctl |= IGC_RCTL_UPE; 3796 3797 /* update state of unicast and multicast */ 3798 rctl |= rd32(IGC_RCTL) & ~(IGC_RCTL_UPE | IGC_RCTL_MPE); 3799 wr32(IGC_RCTL, rctl); 3800 3801 #if (PAGE_SIZE < 8192) 3802 if (adapter->max_frame_size <= IGC_MAX_FRAME_BUILD_SKB) 3803 rlpml = IGC_MAX_FRAME_BUILD_SKB; 3804 #endif 3805 wr32(IGC_RLPML, rlpml); 3806 } 3807 3808 /** 3809 * igc_configure - configure the hardware for RX and TX 3810 * @adapter: private board structure 3811 */ 3812 static void igc_configure(struct igc_adapter *adapter) 3813 { 3814 struct net_device *netdev = adapter->netdev; 3815 int i = 0; 3816 3817 igc_get_hw_control(adapter); 3818 igc_set_rx_mode(netdev); 3819 3820 igc_restore_vlan(adapter); 3821 3822 igc_setup_tctl(adapter); 3823 igc_setup_mrqc(adapter); 3824 igc_setup_rctl(adapter); 3825 3826 igc_set_default_mac_filter(adapter); 3827 igc_restore_nfc_rules(adapter); 3828 3829 igc_configure_tx(adapter); 3830 igc_configure_rx(adapter); 3831 3832 igc_rx_fifo_flush_base(&adapter->hw); 3833 3834 /* call igc_desc_unused which always leaves 3835 * at least 1 descriptor unused to make sure 3836 * next_to_use != next_to_clean 3837 */ 3838 for (i = 0; i < adapter->num_rx_queues; i++) { 3839 struct igc_ring *ring = adapter->rx_ring[i]; 3840 3841 if (ring->xsk_pool) 3842 igc_alloc_rx_buffers_zc(ring, igc_desc_unused(ring)); 3843 else 3844 igc_alloc_rx_buffers(ring, igc_desc_unused(ring)); 3845 } 3846 } 3847 3848 /** 3849 * igc_write_ivar - configure ivar for given MSI-X vector 3850 * @hw: pointer to the HW structure 3851 * @msix_vector: vector number we are allocating to a given ring 3852 * @index: row index of IVAR register to write within IVAR table 3853 * @offset: column offset of in IVAR, should be multiple of 8 3854 * 3855 * The IVAR table consists of 2 columns, 3856 * each containing an cause allocation for an Rx and Tx ring, and a 3857 * variable number of rows depending on the number of queues supported. 3858 */ 3859 static void igc_write_ivar(struct igc_hw *hw, int msix_vector, 3860 int index, int offset) 3861 { 3862 u32 ivar = array_rd32(IGC_IVAR0, index); 3863 3864 /* clear any bits that are currently set */ 3865 ivar &= ~((u32)0xFF << offset); 3866 3867 /* write vector and valid bit */ 3868 ivar |= (msix_vector | IGC_IVAR_VALID) << offset; 3869 3870 array_wr32(IGC_IVAR0, index, ivar); 3871 } 3872 3873 static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector) 3874 { 3875 struct igc_adapter *adapter = q_vector->adapter; 3876 struct igc_hw *hw = &adapter->hw; 3877 int rx_queue = IGC_N0_QUEUE; 3878 int tx_queue = IGC_N0_QUEUE; 3879 3880 if (q_vector->rx.ring) 3881 rx_queue = q_vector->rx.ring->reg_idx; 3882 if (q_vector->tx.ring) 3883 tx_queue = q_vector->tx.ring->reg_idx; 3884 3885 switch (hw->mac.type) { 3886 case igc_i225: 3887 if (rx_queue > IGC_N0_QUEUE) 3888 igc_write_ivar(hw, msix_vector, 3889 rx_queue >> 1, 3890 (rx_queue & 0x1) << 4); 3891 if (tx_queue > IGC_N0_QUEUE) 3892 igc_write_ivar(hw, msix_vector, 3893 tx_queue >> 1, 3894 ((tx_queue & 0x1) << 4) + 8); 3895 q_vector->eims_value = BIT(msix_vector); 3896 break; 3897 default: 3898 WARN_ONCE(hw->mac.type != igc_i225, "Wrong MAC type\n"); 3899 break; 3900 } 3901 3902 /* add q_vector eims value to global eims_enable_mask */ 3903 adapter->eims_enable_mask |= q_vector->eims_value; 3904 3905 /* configure q_vector to set itr on first interrupt */ 3906 q_vector->set_itr = 1; 3907 } 3908 3909 /** 3910 * igc_configure_msix - Configure MSI-X hardware 3911 * @adapter: Pointer to adapter structure 3912 * 3913 * igc_configure_msix sets up the hardware to properly 3914 * generate MSI-X interrupts. 3915 */ 3916 static void igc_configure_msix(struct igc_adapter *adapter) 3917 { 3918 struct igc_hw *hw = &adapter->hw; 3919 int i, vector = 0; 3920 u32 tmp; 3921 3922 adapter->eims_enable_mask = 0; 3923 3924 /* set vector for other causes, i.e. link changes */ 3925 switch (hw->mac.type) { 3926 case igc_i225: 3927 /* Turn on MSI-X capability first, or our settings 3928 * won't stick. And it will take days to debug. 3929 */ 3930 wr32(IGC_GPIE, IGC_GPIE_MSIX_MODE | 3931 IGC_GPIE_PBA | IGC_GPIE_EIAME | 3932 IGC_GPIE_NSICR); 3933 3934 /* enable msix_other interrupt */ 3935 adapter->eims_other = BIT(vector); 3936 tmp = (vector++ | IGC_IVAR_VALID) << 8; 3937 3938 wr32(IGC_IVAR_MISC, tmp); 3939 break; 3940 default: 3941 /* do nothing, since nothing else supports MSI-X */ 3942 break; 3943 } /* switch (hw->mac.type) */ 3944 3945 adapter->eims_enable_mask |= adapter->eims_other; 3946 3947 for (i = 0; i < adapter->num_q_vectors; i++) 3948 igc_assign_vector(adapter->q_vector[i], vector++); 3949 3950 wrfl(); 3951 } 3952 3953 /** 3954 * igc_irq_enable - Enable default interrupt generation settings 3955 * @adapter: board private structure 3956 */ 3957 static void igc_irq_enable(struct igc_adapter *adapter) 3958 { 3959 struct igc_hw *hw = &adapter->hw; 3960 3961 if (adapter->msix_entries) { 3962 u32 ims = IGC_IMS_LSC | IGC_IMS_DOUTSYNC | IGC_IMS_DRSTA; 3963 u32 regval = rd32(IGC_EIAC); 3964 3965 wr32(IGC_EIAC, regval | adapter->eims_enable_mask); 3966 regval = rd32(IGC_EIAM); 3967 wr32(IGC_EIAM, regval | adapter->eims_enable_mask); 3968 wr32(IGC_EIMS, adapter->eims_enable_mask); 3969 wr32(IGC_IMS, ims); 3970 } else { 3971 wr32(IGC_IMS, IMS_ENABLE_MASK | IGC_IMS_DRSTA); 3972 wr32(IGC_IAM, IMS_ENABLE_MASK | IGC_IMS_DRSTA); 3973 } 3974 } 3975 3976 /** 3977 * igc_irq_disable - Mask off interrupt generation on the NIC 3978 * @adapter: board private structure 3979 */ 3980 static void igc_irq_disable(struct igc_adapter *adapter) 3981 { 3982 struct igc_hw *hw = &adapter->hw; 3983 3984 if (adapter->msix_entries) { 3985 u32 regval = rd32(IGC_EIAM); 3986 3987 wr32(IGC_EIAM, regval & ~adapter->eims_enable_mask); 3988 wr32(IGC_EIMC, adapter->eims_enable_mask); 3989 regval = rd32(IGC_EIAC); 3990 wr32(IGC_EIAC, regval & ~adapter->eims_enable_mask); 3991 } 3992 3993 wr32(IGC_IAM, 0); 3994 wr32(IGC_IMC, ~0); 3995 wrfl(); 3996 3997 if (adapter->msix_entries) { 3998 int vector = 0, i; 3999 4000 synchronize_irq(adapter->msix_entries[vector++].vector); 4001 4002 for (i = 0; i < adapter->num_q_vectors; i++) 4003 synchronize_irq(adapter->msix_entries[vector++].vector); 4004 } else { 4005 synchronize_irq(adapter->pdev->irq); 4006 } 4007 } 4008 4009 void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 4010 const u32 max_rss_queues) 4011 { 4012 /* Determine if we need to pair queues. */ 4013 /* If rss_queues > half of max_rss_queues, pair the queues in 4014 * order to conserve interrupts due to limited supply. 4015 */ 4016 if (adapter->rss_queues > (max_rss_queues / 2)) 4017 adapter->flags |= IGC_FLAG_QUEUE_PAIRS; 4018 else 4019 adapter->flags &= ~IGC_FLAG_QUEUE_PAIRS; 4020 } 4021 4022 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter) 4023 { 4024 return IGC_MAX_RX_QUEUES; 4025 } 4026 4027 static void igc_init_queue_configuration(struct igc_adapter *adapter) 4028 { 4029 u32 max_rss_queues; 4030 4031 max_rss_queues = igc_get_max_rss_queues(adapter); 4032 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 4033 4034 igc_set_flag_queue_pairs(adapter, max_rss_queues); 4035 } 4036 4037 /** 4038 * igc_reset_q_vector - Reset config for interrupt vector 4039 * @adapter: board private structure to initialize 4040 * @v_idx: Index of vector to be reset 4041 * 4042 * If NAPI is enabled it will delete any references to the 4043 * NAPI struct. This is preparation for igc_free_q_vector. 4044 */ 4045 static void igc_reset_q_vector(struct igc_adapter *adapter, int v_idx) 4046 { 4047 struct igc_q_vector *q_vector = adapter->q_vector[v_idx]; 4048 4049 /* if we're coming from igc_set_interrupt_capability, the vectors are 4050 * not yet allocated 4051 */ 4052 if (!q_vector) 4053 return; 4054 4055 if (q_vector->tx.ring) 4056 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 4057 4058 if (q_vector->rx.ring) 4059 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 4060 4061 netif_napi_del(&q_vector->napi); 4062 } 4063 4064 /** 4065 * igc_free_q_vector - Free memory allocated for specific interrupt vector 4066 * @adapter: board private structure to initialize 4067 * @v_idx: Index of vector to be freed 4068 * 4069 * This function frees the memory allocated to the q_vector. 4070 */ 4071 static void igc_free_q_vector(struct igc_adapter *adapter, int v_idx) 4072 { 4073 struct igc_q_vector *q_vector = adapter->q_vector[v_idx]; 4074 4075 adapter->q_vector[v_idx] = NULL; 4076 4077 /* igc_get_stats64() might access the rings on this vector, 4078 * we must wait a grace period before freeing it. 4079 */ 4080 if (q_vector) 4081 kfree_rcu(q_vector, rcu); 4082 } 4083 4084 /** 4085 * igc_free_q_vectors - Free memory allocated for interrupt vectors 4086 * @adapter: board private structure to initialize 4087 * 4088 * This function frees the memory allocated to the q_vectors. In addition if 4089 * NAPI is enabled it will delete any references to the NAPI struct prior 4090 * to freeing the q_vector. 4091 */ 4092 static void igc_free_q_vectors(struct igc_adapter *adapter) 4093 { 4094 int v_idx = adapter->num_q_vectors; 4095 4096 adapter->num_tx_queues = 0; 4097 adapter->num_rx_queues = 0; 4098 adapter->num_q_vectors = 0; 4099 4100 while (v_idx--) { 4101 igc_reset_q_vector(adapter, v_idx); 4102 igc_free_q_vector(adapter, v_idx); 4103 } 4104 } 4105 4106 /** 4107 * igc_update_itr - update the dynamic ITR value based on statistics 4108 * @q_vector: pointer to q_vector 4109 * @ring_container: ring info to update the itr for 4110 * 4111 * Stores a new ITR value based on packets and byte 4112 * counts during the last interrupt. The advantage of per interrupt 4113 * computation is faster updates and more accurate ITR for the current 4114 * traffic pattern. Constants in this function were computed 4115 * based on theoretical maximum wire speed and thresholds were set based 4116 * on testing data as well as attempting to minimize response time 4117 * while increasing bulk throughput. 4118 * NOTE: These calculations are only valid when operating in a single- 4119 * queue environment. 4120 */ 4121 static void igc_update_itr(struct igc_q_vector *q_vector, 4122 struct igc_ring_container *ring_container) 4123 { 4124 unsigned int packets = ring_container->total_packets; 4125 unsigned int bytes = ring_container->total_bytes; 4126 u8 itrval = ring_container->itr; 4127 4128 /* no packets, exit with status unchanged */ 4129 if (packets == 0) 4130 return; 4131 4132 switch (itrval) { 4133 case lowest_latency: 4134 /* handle TSO and jumbo frames */ 4135 if (bytes / packets > 8000) 4136 itrval = bulk_latency; 4137 else if ((packets < 5) && (bytes > 512)) 4138 itrval = low_latency; 4139 break; 4140 case low_latency: /* 50 usec aka 20000 ints/s */ 4141 if (bytes > 10000) { 4142 /* this if handles the TSO accounting */ 4143 if (bytes / packets > 8000) 4144 itrval = bulk_latency; 4145 else if ((packets < 10) || ((bytes / packets) > 1200)) 4146 itrval = bulk_latency; 4147 else if ((packets > 35)) 4148 itrval = lowest_latency; 4149 } else if (bytes / packets > 2000) { 4150 itrval = bulk_latency; 4151 } else if (packets <= 2 && bytes < 512) { 4152 itrval = lowest_latency; 4153 } 4154 break; 4155 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4156 if (bytes > 25000) { 4157 if (packets > 35) 4158 itrval = low_latency; 4159 } else if (bytes < 1500) { 4160 itrval = low_latency; 4161 } 4162 break; 4163 } 4164 4165 /* clear work counters since we have the values we need */ 4166 ring_container->total_bytes = 0; 4167 ring_container->total_packets = 0; 4168 4169 /* write updated itr to ring container */ 4170 ring_container->itr = itrval; 4171 } 4172 4173 static void igc_set_itr(struct igc_q_vector *q_vector) 4174 { 4175 struct igc_adapter *adapter = q_vector->adapter; 4176 u32 new_itr = q_vector->itr_val; 4177 u8 current_itr = 0; 4178 4179 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4180 switch (adapter->link_speed) { 4181 case SPEED_10: 4182 case SPEED_100: 4183 current_itr = 0; 4184 new_itr = IGC_4K_ITR; 4185 goto set_itr_now; 4186 default: 4187 break; 4188 } 4189 4190 igc_update_itr(q_vector, &q_vector->tx); 4191 igc_update_itr(q_vector, &q_vector->rx); 4192 4193 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4194 4195 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4196 if (current_itr == lowest_latency && 4197 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4198 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4199 current_itr = low_latency; 4200 4201 switch (current_itr) { 4202 /* counts and packets in update_itr are dependent on these numbers */ 4203 case lowest_latency: 4204 new_itr = IGC_70K_ITR; /* 70,000 ints/sec */ 4205 break; 4206 case low_latency: 4207 new_itr = IGC_20K_ITR; /* 20,000 ints/sec */ 4208 break; 4209 case bulk_latency: 4210 new_itr = IGC_4K_ITR; /* 4,000 ints/sec */ 4211 break; 4212 default: 4213 break; 4214 } 4215 4216 set_itr_now: 4217 if (new_itr != q_vector->itr_val) { 4218 /* this attempts to bias the interrupt rate towards Bulk 4219 * by adding intermediate steps when interrupt rate is 4220 * increasing 4221 */ 4222 new_itr = new_itr > q_vector->itr_val ? 4223 max((new_itr * q_vector->itr_val) / 4224 (new_itr + (q_vector->itr_val >> 2)), 4225 new_itr) : new_itr; 4226 /* Don't write the value here; it resets the adapter's 4227 * internal timer, and causes us to delay far longer than 4228 * we should between interrupts. Instead, we write the ITR 4229 * value at the beginning of the next interrupt so the timing 4230 * ends up being correct. 4231 */ 4232 q_vector->itr_val = new_itr; 4233 q_vector->set_itr = 1; 4234 } 4235 } 4236 4237 static void igc_reset_interrupt_capability(struct igc_adapter *adapter) 4238 { 4239 int v_idx = adapter->num_q_vectors; 4240 4241 if (adapter->msix_entries) { 4242 pci_disable_msix(adapter->pdev); 4243 kfree(adapter->msix_entries); 4244 adapter->msix_entries = NULL; 4245 } else if (adapter->flags & IGC_FLAG_HAS_MSI) { 4246 pci_disable_msi(adapter->pdev); 4247 } 4248 4249 while (v_idx--) 4250 igc_reset_q_vector(adapter, v_idx); 4251 } 4252 4253 /** 4254 * igc_set_interrupt_capability - set MSI or MSI-X if supported 4255 * @adapter: Pointer to adapter structure 4256 * @msix: boolean value for MSI-X capability 4257 * 4258 * Attempt to configure interrupts using the best available 4259 * capabilities of the hardware and kernel. 4260 */ 4261 static void igc_set_interrupt_capability(struct igc_adapter *adapter, 4262 bool msix) 4263 { 4264 int numvecs, i; 4265 int err; 4266 4267 if (!msix) 4268 goto msi_only; 4269 adapter->flags |= IGC_FLAG_HAS_MSIX; 4270 4271 /* Number of supported queues. */ 4272 adapter->num_rx_queues = adapter->rss_queues; 4273 4274 adapter->num_tx_queues = adapter->rss_queues; 4275 4276 /* start with one vector for every Rx queue */ 4277 numvecs = adapter->num_rx_queues; 4278 4279 /* if Tx handler is separate add 1 for every Tx queue */ 4280 if (!(adapter->flags & IGC_FLAG_QUEUE_PAIRS)) 4281 numvecs += adapter->num_tx_queues; 4282 4283 /* store the number of vectors reserved for queues */ 4284 adapter->num_q_vectors = numvecs; 4285 4286 /* add 1 vector for link status interrupts */ 4287 numvecs++; 4288 4289 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), 4290 GFP_KERNEL); 4291 4292 if (!adapter->msix_entries) 4293 return; 4294 4295 /* populate entry values */ 4296 for (i = 0; i < numvecs; i++) 4297 adapter->msix_entries[i].entry = i; 4298 4299 err = pci_enable_msix_range(adapter->pdev, 4300 adapter->msix_entries, 4301 numvecs, 4302 numvecs); 4303 if (err > 0) 4304 return; 4305 4306 kfree(adapter->msix_entries); 4307 adapter->msix_entries = NULL; 4308 4309 igc_reset_interrupt_capability(adapter); 4310 4311 msi_only: 4312 adapter->flags &= ~IGC_FLAG_HAS_MSIX; 4313 4314 adapter->rss_queues = 1; 4315 adapter->flags |= IGC_FLAG_QUEUE_PAIRS; 4316 adapter->num_rx_queues = 1; 4317 adapter->num_tx_queues = 1; 4318 adapter->num_q_vectors = 1; 4319 if (!pci_enable_msi(adapter->pdev)) 4320 adapter->flags |= IGC_FLAG_HAS_MSI; 4321 } 4322 4323 /** 4324 * igc_update_ring_itr - update the dynamic ITR value based on packet size 4325 * @q_vector: pointer to q_vector 4326 * 4327 * Stores a new ITR value based on strictly on packet size. This 4328 * algorithm is less sophisticated than that used in igc_update_itr, 4329 * due to the difficulty of synchronizing statistics across multiple 4330 * receive rings. The divisors and thresholds used by this function 4331 * were determined based on theoretical maximum wire speed and testing 4332 * data, in order to minimize response time while increasing bulk 4333 * throughput. 4334 * NOTE: This function is called only when operating in a multiqueue 4335 * receive environment. 4336 */ 4337 static void igc_update_ring_itr(struct igc_q_vector *q_vector) 4338 { 4339 struct igc_adapter *adapter = q_vector->adapter; 4340 int new_val = q_vector->itr_val; 4341 int avg_wire_size = 0; 4342 unsigned int packets; 4343 4344 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4345 * ints/sec - ITR timer value of 120 ticks. 4346 */ 4347 switch (adapter->link_speed) { 4348 case SPEED_10: 4349 case SPEED_100: 4350 new_val = IGC_4K_ITR; 4351 goto set_itr_val; 4352 default: 4353 break; 4354 } 4355 4356 packets = q_vector->rx.total_packets; 4357 if (packets) 4358 avg_wire_size = q_vector->rx.total_bytes / packets; 4359 4360 packets = q_vector->tx.total_packets; 4361 if (packets) 4362 avg_wire_size = max_t(u32, avg_wire_size, 4363 q_vector->tx.total_bytes / packets); 4364 4365 /* if avg_wire_size isn't set no work was done */ 4366 if (!avg_wire_size) 4367 goto clear_counts; 4368 4369 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4370 avg_wire_size += 24; 4371 4372 /* Don't starve jumbo frames */ 4373 avg_wire_size = min(avg_wire_size, 3000); 4374 4375 /* Give a little boost to mid-size frames */ 4376 if (avg_wire_size > 300 && avg_wire_size < 1200) 4377 new_val = avg_wire_size / 3; 4378 else 4379 new_val = avg_wire_size / 2; 4380 4381 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4382 if (new_val < IGC_20K_ITR && 4383 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4384 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4385 new_val = IGC_20K_ITR; 4386 4387 set_itr_val: 4388 if (new_val != q_vector->itr_val) { 4389 q_vector->itr_val = new_val; 4390 q_vector->set_itr = 1; 4391 } 4392 clear_counts: 4393 q_vector->rx.total_bytes = 0; 4394 q_vector->rx.total_packets = 0; 4395 q_vector->tx.total_bytes = 0; 4396 q_vector->tx.total_packets = 0; 4397 } 4398 4399 static void igc_ring_irq_enable(struct igc_q_vector *q_vector) 4400 { 4401 struct igc_adapter *adapter = q_vector->adapter; 4402 struct igc_hw *hw = &adapter->hw; 4403 4404 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 4405 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 4406 if (adapter->num_q_vectors == 1) 4407 igc_set_itr(q_vector); 4408 else 4409 igc_update_ring_itr(q_vector); 4410 } 4411 4412 if (!test_bit(__IGC_DOWN, &adapter->state)) { 4413 if (adapter->msix_entries) 4414 wr32(IGC_EIMS, q_vector->eims_value); 4415 else 4416 igc_irq_enable(adapter); 4417 } 4418 } 4419 4420 static void igc_add_ring(struct igc_ring *ring, 4421 struct igc_ring_container *head) 4422 { 4423 head->ring = ring; 4424 head->count++; 4425 } 4426 4427 /** 4428 * igc_cache_ring_register - Descriptor ring to register mapping 4429 * @adapter: board private structure to initialize 4430 * 4431 * Once we know the feature-set enabled for the device, we'll cache 4432 * the register offset the descriptor ring is assigned to. 4433 */ 4434 static void igc_cache_ring_register(struct igc_adapter *adapter) 4435 { 4436 int i = 0, j = 0; 4437 4438 switch (adapter->hw.mac.type) { 4439 case igc_i225: 4440 default: 4441 for (; i < adapter->num_rx_queues; i++) 4442 adapter->rx_ring[i]->reg_idx = i; 4443 for (; j < adapter->num_tx_queues; j++) 4444 adapter->tx_ring[j]->reg_idx = j; 4445 break; 4446 } 4447 } 4448 4449 /** 4450 * igc_poll - NAPI Rx polling callback 4451 * @napi: napi polling structure 4452 * @budget: count of how many packets we should handle 4453 */ 4454 static int igc_poll(struct napi_struct *napi, int budget) 4455 { 4456 struct igc_q_vector *q_vector = container_of(napi, 4457 struct igc_q_vector, 4458 napi); 4459 struct igc_ring *rx_ring = q_vector->rx.ring; 4460 bool clean_complete = true; 4461 int work_done = 0; 4462 4463 if (q_vector->tx.ring) 4464 clean_complete = igc_clean_tx_irq(q_vector, budget); 4465 4466 if (rx_ring) { 4467 int cleaned = rx_ring->xsk_pool ? 4468 igc_clean_rx_irq_zc(q_vector, budget) : 4469 igc_clean_rx_irq(q_vector, budget); 4470 4471 work_done += cleaned; 4472 if (cleaned >= budget) 4473 clean_complete = false; 4474 } 4475 4476 /* If all work not completed, return budget and keep polling */ 4477 if (!clean_complete) 4478 return budget; 4479 4480 /* Exit the polling mode, but don't re-enable interrupts if stack might 4481 * poll us due to busy-polling 4482 */ 4483 if (likely(napi_complete_done(napi, work_done))) 4484 igc_ring_irq_enable(q_vector); 4485 4486 return min(work_done, budget - 1); 4487 } 4488 4489 /** 4490 * igc_alloc_q_vector - Allocate memory for a single interrupt vector 4491 * @adapter: board private structure to initialize 4492 * @v_count: q_vectors allocated on adapter, used for ring interleaving 4493 * @v_idx: index of vector in adapter struct 4494 * @txr_count: total number of Tx rings to allocate 4495 * @txr_idx: index of first Tx ring to allocate 4496 * @rxr_count: total number of Rx rings to allocate 4497 * @rxr_idx: index of first Rx ring to allocate 4498 * 4499 * We allocate one q_vector. If allocation fails we return -ENOMEM. 4500 */ 4501 static int igc_alloc_q_vector(struct igc_adapter *adapter, 4502 unsigned int v_count, unsigned int v_idx, 4503 unsigned int txr_count, unsigned int txr_idx, 4504 unsigned int rxr_count, unsigned int rxr_idx) 4505 { 4506 struct igc_q_vector *q_vector; 4507 struct igc_ring *ring; 4508 int ring_count; 4509 4510 /* igc only supports 1 Tx and/or 1 Rx queue per vector */ 4511 if (txr_count > 1 || rxr_count > 1) 4512 return -ENOMEM; 4513 4514 ring_count = txr_count + rxr_count; 4515 4516 /* allocate q_vector and rings */ 4517 q_vector = adapter->q_vector[v_idx]; 4518 if (!q_vector) 4519 q_vector = kzalloc(struct_size(q_vector, ring, ring_count), 4520 GFP_KERNEL); 4521 else 4522 memset(q_vector, 0, struct_size(q_vector, ring, ring_count)); 4523 if (!q_vector) 4524 return -ENOMEM; 4525 4526 /* initialize NAPI */ 4527 netif_napi_add(adapter->netdev, &q_vector->napi, igc_poll); 4528 4529 /* tie q_vector and adapter together */ 4530 adapter->q_vector[v_idx] = q_vector; 4531 q_vector->adapter = adapter; 4532 4533 /* initialize work limits */ 4534 q_vector->tx.work_limit = adapter->tx_work_limit; 4535 4536 /* initialize ITR configuration */ 4537 q_vector->itr_register = adapter->io_addr + IGC_EITR(0); 4538 q_vector->itr_val = IGC_START_ITR; 4539 4540 /* initialize pointer to rings */ 4541 ring = q_vector->ring; 4542 4543 /* initialize ITR */ 4544 if (rxr_count) { 4545 /* rx or rx/tx vector */ 4546 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 4547 q_vector->itr_val = adapter->rx_itr_setting; 4548 } else { 4549 /* tx only vector */ 4550 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 4551 q_vector->itr_val = adapter->tx_itr_setting; 4552 } 4553 4554 if (txr_count) { 4555 /* assign generic ring traits */ 4556 ring->dev = &adapter->pdev->dev; 4557 ring->netdev = adapter->netdev; 4558 4559 /* configure backlink on ring */ 4560 ring->q_vector = q_vector; 4561 4562 /* update q_vector Tx values */ 4563 igc_add_ring(ring, &q_vector->tx); 4564 4565 /* apply Tx specific ring traits */ 4566 ring->count = adapter->tx_ring_count; 4567 ring->queue_index = txr_idx; 4568 4569 /* assign ring to adapter */ 4570 adapter->tx_ring[txr_idx] = ring; 4571 4572 /* push pointer to next ring */ 4573 ring++; 4574 } 4575 4576 if (rxr_count) { 4577 /* assign generic ring traits */ 4578 ring->dev = &adapter->pdev->dev; 4579 ring->netdev = adapter->netdev; 4580 4581 /* configure backlink on ring */ 4582 ring->q_vector = q_vector; 4583 4584 /* update q_vector Rx values */ 4585 igc_add_ring(ring, &q_vector->rx); 4586 4587 /* apply Rx specific ring traits */ 4588 ring->count = adapter->rx_ring_count; 4589 ring->queue_index = rxr_idx; 4590 4591 /* assign ring to adapter */ 4592 adapter->rx_ring[rxr_idx] = ring; 4593 } 4594 4595 return 0; 4596 } 4597 4598 /** 4599 * igc_alloc_q_vectors - Allocate memory for interrupt vectors 4600 * @adapter: board private structure to initialize 4601 * 4602 * We allocate one q_vector per queue interrupt. If allocation fails we 4603 * return -ENOMEM. 4604 */ 4605 static int igc_alloc_q_vectors(struct igc_adapter *adapter) 4606 { 4607 int rxr_remaining = adapter->num_rx_queues; 4608 int txr_remaining = adapter->num_tx_queues; 4609 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 4610 int q_vectors = adapter->num_q_vectors; 4611 int err; 4612 4613 if (q_vectors >= (rxr_remaining + txr_remaining)) { 4614 for (; rxr_remaining; v_idx++) { 4615 err = igc_alloc_q_vector(adapter, q_vectors, v_idx, 4616 0, 0, 1, rxr_idx); 4617 4618 if (err) 4619 goto err_out; 4620 4621 /* update counts and index */ 4622 rxr_remaining--; 4623 rxr_idx++; 4624 } 4625 } 4626 4627 for (; v_idx < q_vectors; v_idx++) { 4628 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 4629 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 4630 4631 err = igc_alloc_q_vector(adapter, q_vectors, v_idx, 4632 tqpv, txr_idx, rqpv, rxr_idx); 4633 4634 if (err) 4635 goto err_out; 4636 4637 /* update counts and index */ 4638 rxr_remaining -= rqpv; 4639 txr_remaining -= tqpv; 4640 rxr_idx++; 4641 txr_idx++; 4642 } 4643 4644 return 0; 4645 4646 err_out: 4647 adapter->num_tx_queues = 0; 4648 adapter->num_rx_queues = 0; 4649 adapter->num_q_vectors = 0; 4650 4651 while (v_idx--) 4652 igc_free_q_vector(adapter, v_idx); 4653 4654 return -ENOMEM; 4655 } 4656 4657 /** 4658 * igc_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 4659 * @adapter: Pointer to adapter structure 4660 * @msix: boolean for MSI-X capability 4661 * 4662 * This function initializes the interrupts and allocates all of the queues. 4663 */ 4664 static int igc_init_interrupt_scheme(struct igc_adapter *adapter, bool msix) 4665 { 4666 struct net_device *dev = adapter->netdev; 4667 int err = 0; 4668 4669 igc_set_interrupt_capability(adapter, msix); 4670 4671 err = igc_alloc_q_vectors(adapter); 4672 if (err) { 4673 netdev_err(dev, "Unable to allocate memory for vectors\n"); 4674 goto err_alloc_q_vectors; 4675 } 4676 4677 igc_cache_ring_register(adapter); 4678 4679 return 0; 4680 4681 err_alloc_q_vectors: 4682 igc_reset_interrupt_capability(adapter); 4683 return err; 4684 } 4685 4686 /** 4687 * igc_sw_init - Initialize general software structures (struct igc_adapter) 4688 * @adapter: board private structure to initialize 4689 * 4690 * igc_sw_init initializes the Adapter private data structure. 4691 * Fields are initialized based on PCI device information and 4692 * OS network device settings (MTU size). 4693 */ 4694 static int igc_sw_init(struct igc_adapter *adapter) 4695 { 4696 struct net_device *netdev = adapter->netdev; 4697 struct pci_dev *pdev = adapter->pdev; 4698 struct igc_hw *hw = &adapter->hw; 4699 4700 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 4701 4702 /* set default ring sizes */ 4703 adapter->tx_ring_count = IGC_DEFAULT_TXD; 4704 adapter->rx_ring_count = IGC_DEFAULT_RXD; 4705 4706 /* set default ITR values */ 4707 adapter->rx_itr_setting = IGC_DEFAULT_ITR; 4708 adapter->tx_itr_setting = IGC_DEFAULT_ITR; 4709 4710 /* set default work limits */ 4711 adapter->tx_work_limit = IGC_DEFAULT_TX_WORK; 4712 4713 /* adjust max frame to be at least the size of a standard frame */ 4714 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 4715 VLAN_HLEN; 4716 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4717 4718 mutex_init(&adapter->nfc_rule_lock); 4719 INIT_LIST_HEAD(&adapter->nfc_rule_list); 4720 adapter->nfc_rule_count = 0; 4721 4722 spin_lock_init(&adapter->stats64_lock); 4723 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4724 adapter->flags |= IGC_FLAG_HAS_MSIX; 4725 4726 igc_init_queue_configuration(adapter); 4727 4728 /* This call may decrease the number of queues */ 4729 if (igc_init_interrupt_scheme(adapter, true)) { 4730 netdev_err(netdev, "Unable to allocate memory for queues\n"); 4731 return -ENOMEM; 4732 } 4733 4734 /* Explicitly disable IRQ since the NIC can be in any state. */ 4735 igc_irq_disable(adapter); 4736 4737 set_bit(__IGC_DOWN, &adapter->state); 4738 4739 return 0; 4740 } 4741 4742 /** 4743 * igc_up - Open the interface and prepare it to handle traffic 4744 * @adapter: board private structure 4745 */ 4746 void igc_up(struct igc_adapter *adapter) 4747 { 4748 struct igc_hw *hw = &adapter->hw; 4749 int i = 0; 4750 4751 /* hardware has been reset, we need to reload some things */ 4752 igc_configure(adapter); 4753 4754 clear_bit(__IGC_DOWN, &adapter->state); 4755 4756 for (i = 0; i < adapter->num_q_vectors; i++) 4757 napi_enable(&adapter->q_vector[i]->napi); 4758 4759 if (adapter->msix_entries) 4760 igc_configure_msix(adapter); 4761 else 4762 igc_assign_vector(adapter->q_vector[0], 0); 4763 4764 /* Clear any pending interrupts. */ 4765 rd32(IGC_ICR); 4766 igc_irq_enable(adapter); 4767 4768 netif_tx_start_all_queues(adapter->netdev); 4769 4770 /* start the watchdog. */ 4771 hw->mac.get_link_status = true; 4772 schedule_work(&adapter->watchdog_task); 4773 } 4774 4775 /** 4776 * igc_update_stats - Update the board statistics counters 4777 * @adapter: board private structure 4778 */ 4779 void igc_update_stats(struct igc_adapter *adapter) 4780 { 4781 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 4782 struct pci_dev *pdev = adapter->pdev; 4783 struct igc_hw *hw = &adapter->hw; 4784 u64 _bytes, _packets; 4785 u64 bytes, packets; 4786 unsigned int start; 4787 u32 mpc; 4788 int i; 4789 4790 /* Prevent stats update while adapter is being reset, or if the pci 4791 * connection is down. 4792 */ 4793 if (adapter->link_speed == 0) 4794 return; 4795 if (pci_channel_offline(pdev)) 4796 return; 4797 4798 packets = 0; 4799 bytes = 0; 4800 4801 rcu_read_lock(); 4802 for (i = 0; i < adapter->num_rx_queues; i++) { 4803 struct igc_ring *ring = adapter->rx_ring[i]; 4804 u32 rqdpc = rd32(IGC_RQDPC(i)); 4805 4806 if (hw->mac.type >= igc_i225) 4807 wr32(IGC_RQDPC(i), 0); 4808 4809 if (rqdpc) { 4810 ring->rx_stats.drops += rqdpc; 4811 net_stats->rx_fifo_errors += rqdpc; 4812 } 4813 4814 do { 4815 start = u64_stats_fetch_begin(&ring->rx_syncp); 4816 _bytes = ring->rx_stats.bytes; 4817 _packets = ring->rx_stats.packets; 4818 } while (u64_stats_fetch_retry(&ring->rx_syncp, start)); 4819 bytes += _bytes; 4820 packets += _packets; 4821 } 4822 4823 net_stats->rx_bytes = bytes; 4824 net_stats->rx_packets = packets; 4825 4826 packets = 0; 4827 bytes = 0; 4828 for (i = 0; i < adapter->num_tx_queues; i++) { 4829 struct igc_ring *ring = adapter->tx_ring[i]; 4830 4831 do { 4832 start = u64_stats_fetch_begin(&ring->tx_syncp); 4833 _bytes = ring->tx_stats.bytes; 4834 _packets = ring->tx_stats.packets; 4835 } while (u64_stats_fetch_retry(&ring->tx_syncp, start)); 4836 bytes += _bytes; 4837 packets += _packets; 4838 } 4839 net_stats->tx_bytes = bytes; 4840 net_stats->tx_packets = packets; 4841 rcu_read_unlock(); 4842 4843 /* read stats registers */ 4844 adapter->stats.crcerrs += rd32(IGC_CRCERRS); 4845 adapter->stats.gprc += rd32(IGC_GPRC); 4846 adapter->stats.gorc += rd32(IGC_GORCL); 4847 rd32(IGC_GORCH); /* clear GORCL */ 4848 adapter->stats.bprc += rd32(IGC_BPRC); 4849 adapter->stats.mprc += rd32(IGC_MPRC); 4850 adapter->stats.roc += rd32(IGC_ROC); 4851 4852 adapter->stats.prc64 += rd32(IGC_PRC64); 4853 adapter->stats.prc127 += rd32(IGC_PRC127); 4854 adapter->stats.prc255 += rd32(IGC_PRC255); 4855 adapter->stats.prc511 += rd32(IGC_PRC511); 4856 adapter->stats.prc1023 += rd32(IGC_PRC1023); 4857 adapter->stats.prc1522 += rd32(IGC_PRC1522); 4858 adapter->stats.tlpic += rd32(IGC_TLPIC); 4859 adapter->stats.rlpic += rd32(IGC_RLPIC); 4860 adapter->stats.hgptc += rd32(IGC_HGPTC); 4861 4862 mpc = rd32(IGC_MPC); 4863 adapter->stats.mpc += mpc; 4864 net_stats->rx_fifo_errors += mpc; 4865 adapter->stats.scc += rd32(IGC_SCC); 4866 adapter->stats.ecol += rd32(IGC_ECOL); 4867 adapter->stats.mcc += rd32(IGC_MCC); 4868 adapter->stats.latecol += rd32(IGC_LATECOL); 4869 adapter->stats.dc += rd32(IGC_DC); 4870 adapter->stats.rlec += rd32(IGC_RLEC); 4871 adapter->stats.xonrxc += rd32(IGC_XONRXC); 4872 adapter->stats.xontxc += rd32(IGC_XONTXC); 4873 adapter->stats.xoffrxc += rd32(IGC_XOFFRXC); 4874 adapter->stats.xofftxc += rd32(IGC_XOFFTXC); 4875 adapter->stats.fcruc += rd32(IGC_FCRUC); 4876 adapter->stats.gptc += rd32(IGC_GPTC); 4877 adapter->stats.gotc += rd32(IGC_GOTCL); 4878 rd32(IGC_GOTCH); /* clear GOTCL */ 4879 adapter->stats.rnbc += rd32(IGC_RNBC); 4880 adapter->stats.ruc += rd32(IGC_RUC); 4881 adapter->stats.rfc += rd32(IGC_RFC); 4882 adapter->stats.rjc += rd32(IGC_RJC); 4883 adapter->stats.tor += rd32(IGC_TORH); 4884 adapter->stats.tot += rd32(IGC_TOTH); 4885 adapter->stats.tpr += rd32(IGC_TPR); 4886 4887 adapter->stats.ptc64 += rd32(IGC_PTC64); 4888 adapter->stats.ptc127 += rd32(IGC_PTC127); 4889 adapter->stats.ptc255 += rd32(IGC_PTC255); 4890 adapter->stats.ptc511 += rd32(IGC_PTC511); 4891 adapter->stats.ptc1023 += rd32(IGC_PTC1023); 4892 adapter->stats.ptc1522 += rd32(IGC_PTC1522); 4893 4894 adapter->stats.mptc += rd32(IGC_MPTC); 4895 adapter->stats.bptc += rd32(IGC_BPTC); 4896 4897 adapter->stats.tpt += rd32(IGC_TPT); 4898 adapter->stats.colc += rd32(IGC_COLC); 4899 adapter->stats.colc += rd32(IGC_RERC); 4900 4901 adapter->stats.algnerrc += rd32(IGC_ALGNERRC); 4902 4903 adapter->stats.tsctc += rd32(IGC_TSCTC); 4904 4905 adapter->stats.iac += rd32(IGC_IAC); 4906 4907 /* Fill out the OS statistics structure */ 4908 net_stats->multicast = adapter->stats.mprc; 4909 net_stats->collisions = adapter->stats.colc; 4910 4911 /* Rx Errors */ 4912 4913 /* RLEC on some newer hardware can be incorrect so build 4914 * our own version based on RUC and ROC 4915 */ 4916 net_stats->rx_errors = adapter->stats.rxerrc + 4917 adapter->stats.crcerrs + adapter->stats.algnerrc + 4918 adapter->stats.ruc + adapter->stats.roc + 4919 adapter->stats.cexterr; 4920 net_stats->rx_length_errors = adapter->stats.ruc + 4921 adapter->stats.roc; 4922 net_stats->rx_crc_errors = adapter->stats.crcerrs; 4923 net_stats->rx_frame_errors = adapter->stats.algnerrc; 4924 net_stats->rx_missed_errors = adapter->stats.mpc; 4925 4926 /* Tx Errors */ 4927 net_stats->tx_errors = adapter->stats.ecol + 4928 adapter->stats.latecol; 4929 net_stats->tx_aborted_errors = adapter->stats.ecol; 4930 net_stats->tx_window_errors = adapter->stats.latecol; 4931 net_stats->tx_carrier_errors = adapter->stats.tncrs; 4932 4933 /* Tx Dropped */ 4934 net_stats->tx_dropped = adapter->stats.txdrop; 4935 4936 /* Management Stats */ 4937 adapter->stats.mgptc += rd32(IGC_MGTPTC); 4938 adapter->stats.mgprc += rd32(IGC_MGTPRC); 4939 adapter->stats.mgpdc += rd32(IGC_MGTPDC); 4940 } 4941 4942 /** 4943 * igc_down - Close the interface 4944 * @adapter: board private structure 4945 */ 4946 void igc_down(struct igc_adapter *adapter) 4947 { 4948 struct net_device *netdev = adapter->netdev; 4949 struct igc_hw *hw = &adapter->hw; 4950 u32 tctl, rctl; 4951 int i = 0; 4952 4953 set_bit(__IGC_DOWN, &adapter->state); 4954 4955 igc_ptp_suspend(adapter); 4956 4957 if (pci_device_is_present(adapter->pdev)) { 4958 /* disable receives in the hardware */ 4959 rctl = rd32(IGC_RCTL); 4960 wr32(IGC_RCTL, rctl & ~IGC_RCTL_EN); 4961 /* flush and sleep below */ 4962 } 4963 /* set trans_start so we don't get spurious watchdogs during reset */ 4964 netif_trans_update(netdev); 4965 4966 netif_carrier_off(netdev); 4967 netif_tx_stop_all_queues(netdev); 4968 4969 if (pci_device_is_present(adapter->pdev)) { 4970 /* disable transmits in the hardware */ 4971 tctl = rd32(IGC_TCTL); 4972 tctl &= ~IGC_TCTL_EN; 4973 wr32(IGC_TCTL, tctl); 4974 /* flush both disables and wait for them to finish */ 4975 wrfl(); 4976 usleep_range(10000, 20000); 4977 4978 igc_irq_disable(adapter); 4979 } 4980 4981 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE; 4982 4983 for (i = 0; i < adapter->num_q_vectors; i++) { 4984 if (adapter->q_vector[i]) { 4985 napi_synchronize(&adapter->q_vector[i]->napi); 4986 napi_disable(&adapter->q_vector[i]->napi); 4987 } 4988 } 4989 4990 del_timer_sync(&adapter->watchdog_timer); 4991 del_timer_sync(&adapter->phy_info_timer); 4992 4993 /* record the stats before reset*/ 4994 spin_lock(&adapter->stats64_lock); 4995 igc_update_stats(adapter); 4996 spin_unlock(&adapter->stats64_lock); 4997 4998 adapter->link_speed = 0; 4999 adapter->link_duplex = 0; 5000 5001 if (!pci_channel_offline(adapter->pdev)) 5002 igc_reset(adapter); 5003 5004 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 5005 adapter->flags &= ~IGC_FLAG_VLAN_PROMISC; 5006 5007 igc_clean_all_tx_rings(adapter); 5008 igc_clean_all_rx_rings(adapter); 5009 } 5010 5011 void igc_reinit_locked(struct igc_adapter *adapter) 5012 { 5013 while (test_and_set_bit(__IGC_RESETTING, &adapter->state)) 5014 usleep_range(1000, 2000); 5015 igc_down(adapter); 5016 igc_up(adapter); 5017 clear_bit(__IGC_RESETTING, &adapter->state); 5018 } 5019 5020 static void igc_reset_task(struct work_struct *work) 5021 { 5022 struct igc_adapter *adapter; 5023 5024 adapter = container_of(work, struct igc_adapter, reset_task); 5025 5026 rtnl_lock(); 5027 /* If we're already down or resetting, just bail */ 5028 if (test_bit(__IGC_DOWN, &adapter->state) || 5029 test_bit(__IGC_RESETTING, &adapter->state)) { 5030 rtnl_unlock(); 5031 return; 5032 } 5033 5034 igc_rings_dump(adapter); 5035 igc_regs_dump(adapter); 5036 netdev_err(adapter->netdev, "Reset adapter\n"); 5037 igc_reinit_locked(adapter); 5038 rtnl_unlock(); 5039 } 5040 5041 /** 5042 * igc_change_mtu - Change the Maximum Transfer Unit 5043 * @netdev: network interface device structure 5044 * @new_mtu: new value for maximum frame size 5045 * 5046 * Returns 0 on success, negative on failure 5047 */ 5048 static int igc_change_mtu(struct net_device *netdev, int new_mtu) 5049 { 5050 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5051 struct igc_adapter *adapter = netdev_priv(netdev); 5052 5053 if (igc_xdp_is_enabled(adapter) && new_mtu > ETH_DATA_LEN) { 5054 netdev_dbg(netdev, "Jumbo frames not supported with XDP"); 5055 return -EINVAL; 5056 } 5057 5058 /* adjust max frame to be at least the size of a standard frame */ 5059 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5060 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5061 5062 while (test_and_set_bit(__IGC_RESETTING, &adapter->state)) 5063 usleep_range(1000, 2000); 5064 5065 /* igc_down has a dependency on max_frame_size */ 5066 adapter->max_frame_size = max_frame; 5067 5068 if (netif_running(netdev)) 5069 igc_down(adapter); 5070 5071 netdev_dbg(netdev, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 5072 netdev->mtu = new_mtu; 5073 5074 if (netif_running(netdev)) 5075 igc_up(adapter); 5076 else 5077 igc_reset(adapter); 5078 5079 clear_bit(__IGC_RESETTING, &adapter->state); 5080 5081 return 0; 5082 } 5083 5084 /** 5085 * igc_tx_timeout - Respond to a Tx Hang 5086 * @netdev: network interface device structure 5087 * @txqueue: queue number that timed out 5088 **/ 5089 static void igc_tx_timeout(struct net_device *netdev, 5090 unsigned int __always_unused txqueue) 5091 { 5092 struct igc_adapter *adapter = netdev_priv(netdev); 5093 struct igc_hw *hw = &adapter->hw; 5094 5095 /* Do the reset outside of interrupt context */ 5096 adapter->tx_timeout_count++; 5097 schedule_work(&adapter->reset_task); 5098 wr32(IGC_EICS, 5099 (adapter->eims_enable_mask & ~adapter->eims_other)); 5100 } 5101 5102 /** 5103 * igc_get_stats64 - Get System Network Statistics 5104 * @netdev: network interface device structure 5105 * @stats: rtnl_link_stats64 pointer 5106 * 5107 * Returns the address of the device statistics structure. 5108 * The statistics are updated here and also from the timer callback. 5109 */ 5110 static void igc_get_stats64(struct net_device *netdev, 5111 struct rtnl_link_stats64 *stats) 5112 { 5113 struct igc_adapter *adapter = netdev_priv(netdev); 5114 5115 spin_lock(&adapter->stats64_lock); 5116 if (!test_bit(__IGC_RESETTING, &adapter->state)) 5117 igc_update_stats(adapter); 5118 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5119 spin_unlock(&adapter->stats64_lock); 5120 } 5121 5122 static netdev_features_t igc_fix_features(struct net_device *netdev, 5123 netdev_features_t features) 5124 { 5125 /* Since there is no support for separate Rx/Tx vlan accel 5126 * enable/disable make sure Tx flag is always in same state as Rx. 5127 */ 5128 if (features & NETIF_F_HW_VLAN_CTAG_RX) 5129 features |= NETIF_F_HW_VLAN_CTAG_TX; 5130 else 5131 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 5132 5133 return features; 5134 } 5135 5136 static int igc_set_features(struct net_device *netdev, 5137 netdev_features_t features) 5138 { 5139 netdev_features_t changed = netdev->features ^ features; 5140 struct igc_adapter *adapter = netdev_priv(netdev); 5141 5142 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 5143 igc_vlan_mode(netdev, features); 5144 5145 /* Add VLAN support */ 5146 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 5147 return 0; 5148 5149 if (!(features & NETIF_F_NTUPLE)) 5150 igc_flush_nfc_rules(adapter); 5151 5152 netdev->features = features; 5153 5154 if (netif_running(netdev)) 5155 igc_reinit_locked(adapter); 5156 else 5157 igc_reset(adapter); 5158 5159 return 1; 5160 } 5161 5162 static netdev_features_t 5163 igc_features_check(struct sk_buff *skb, struct net_device *dev, 5164 netdev_features_t features) 5165 { 5166 unsigned int network_hdr_len, mac_hdr_len; 5167 5168 /* Make certain the headers can be described by a context descriptor */ 5169 mac_hdr_len = skb_network_header(skb) - skb->data; 5170 if (unlikely(mac_hdr_len > IGC_MAX_MAC_HDR_LEN)) 5171 return features & ~(NETIF_F_HW_CSUM | 5172 NETIF_F_SCTP_CRC | 5173 NETIF_F_HW_VLAN_CTAG_TX | 5174 NETIF_F_TSO | 5175 NETIF_F_TSO6); 5176 5177 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 5178 if (unlikely(network_hdr_len > IGC_MAX_NETWORK_HDR_LEN)) 5179 return features & ~(NETIF_F_HW_CSUM | 5180 NETIF_F_SCTP_CRC | 5181 NETIF_F_TSO | 5182 NETIF_F_TSO6); 5183 5184 /* We can only support IPv4 TSO in tunnels if we can mangle the 5185 * inner IP ID field, so strip TSO if MANGLEID is not supported. 5186 */ 5187 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 5188 features &= ~NETIF_F_TSO; 5189 5190 return features; 5191 } 5192 5193 static void igc_tsync_interrupt(struct igc_adapter *adapter) 5194 { 5195 u32 ack, tsauxc, sec, nsec, tsicr; 5196 struct igc_hw *hw = &adapter->hw; 5197 struct ptp_clock_event event; 5198 struct timespec64 ts; 5199 5200 tsicr = rd32(IGC_TSICR); 5201 ack = 0; 5202 5203 if (tsicr & IGC_TSICR_SYS_WRAP) { 5204 event.type = PTP_CLOCK_PPS; 5205 if (adapter->ptp_caps.pps) 5206 ptp_clock_event(adapter->ptp_clock, &event); 5207 ack |= IGC_TSICR_SYS_WRAP; 5208 } 5209 5210 if (tsicr & IGC_TSICR_TXTS) { 5211 /* retrieve hardware timestamp */ 5212 schedule_work(&adapter->ptp_tx_work); 5213 ack |= IGC_TSICR_TXTS; 5214 } 5215 5216 if (tsicr & IGC_TSICR_TT0) { 5217 spin_lock(&adapter->tmreg_lock); 5218 ts = timespec64_add(adapter->perout[0].start, 5219 adapter->perout[0].period); 5220 wr32(IGC_TRGTTIML0, ts.tv_nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0); 5221 wr32(IGC_TRGTTIMH0, (u32)ts.tv_sec); 5222 tsauxc = rd32(IGC_TSAUXC); 5223 tsauxc |= IGC_TSAUXC_EN_TT0; 5224 wr32(IGC_TSAUXC, tsauxc); 5225 adapter->perout[0].start = ts; 5226 spin_unlock(&adapter->tmreg_lock); 5227 ack |= IGC_TSICR_TT0; 5228 } 5229 5230 if (tsicr & IGC_TSICR_TT1) { 5231 spin_lock(&adapter->tmreg_lock); 5232 ts = timespec64_add(adapter->perout[1].start, 5233 adapter->perout[1].period); 5234 wr32(IGC_TRGTTIML1, ts.tv_nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0); 5235 wr32(IGC_TRGTTIMH1, (u32)ts.tv_sec); 5236 tsauxc = rd32(IGC_TSAUXC); 5237 tsauxc |= IGC_TSAUXC_EN_TT1; 5238 wr32(IGC_TSAUXC, tsauxc); 5239 adapter->perout[1].start = ts; 5240 spin_unlock(&adapter->tmreg_lock); 5241 ack |= IGC_TSICR_TT1; 5242 } 5243 5244 if (tsicr & IGC_TSICR_AUTT0) { 5245 nsec = rd32(IGC_AUXSTMPL0); 5246 sec = rd32(IGC_AUXSTMPH0); 5247 event.type = PTP_CLOCK_EXTTS; 5248 event.index = 0; 5249 event.timestamp = sec * NSEC_PER_SEC + nsec; 5250 ptp_clock_event(adapter->ptp_clock, &event); 5251 ack |= IGC_TSICR_AUTT0; 5252 } 5253 5254 if (tsicr & IGC_TSICR_AUTT1) { 5255 nsec = rd32(IGC_AUXSTMPL1); 5256 sec = rd32(IGC_AUXSTMPH1); 5257 event.type = PTP_CLOCK_EXTTS; 5258 event.index = 1; 5259 event.timestamp = sec * NSEC_PER_SEC + nsec; 5260 ptp_clock_event(adapter->ptp_clock, &event); 5261 ack |= IGC_TSICR_AUTT1; 5262 } 5263 5264 /* acknowledge the interrupts */ 5265 wr32(IGC_TSICR, ack); 5266 } 5267 5268 /** 5269 * igc_msix_other - msix other interrupt handler 5270 * @irq: interrupt number 5271 * @data: pointer to a q_vector 5272 */ 5273 static irqreturn_t igc_msix_other(int irq, void *data) 5274 { 5275 struct igc_adapter *adapter = data; 5276 struct igc_hw *hw = &adapter->hw; 5277 u32 icr = rd32(IGC_ICR); 5278 5279 /* reading ICR causes bit 31 of EICR to be cleared */ 5280 if (icr & IGC_ICR_DRSTA) 5281 schedule_work(&adapter->reset_task); 5282 5283 if (icr & IGC_ICR_DOUTSYNC) { 5284 /* HW is reporting DMA is out of sync */ 5285 adapter->stats.doosync++; 5286 } 5287 5288 if (icr & IGC_ICR_LSC) { 5289 hw->mac.get_link_status = true; 5290 /* guard against interrupt when we're going down */ 5291 if (!test_bit(__IGC_DOWN, &adapter->state)) 5292 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5293 } 5294 5295 if (icr & IGC_ICR_TS) 5296 igc_tsync_interrupt(adapter); 5297 5298 wr32(IGC_EIMS, adapter->eims_other); 5299 5300 return IRQ_HANDLED; 5301 } 5302 5303 static void igc_write_itr(struct igc_q_vector *q_vector) 5304 { 5305 u32 itr_val = q_vector->itr_val & IGC_QVECTOR_MASK; 5306 5307 if (!q_vector->set_itr) 5308 return; 5309 5310 if (!itr_val) 5311 itr_val = IGC_ITR_VAL_MASK; 5312 5313 itr_val |= IGC_EITR_CNT_IGNR; 5314 5315 writel(itr_val, q_vector->itr_register); 5316 q_vector->set_itr = 0; 5317 } 5318 5319 static irqreturn_t igc_msix_ring(int irq, void *data) 5320 { 5321 struct igc_q_vector *q_vector = data; 5322 5323 /* Write the ITR value calculated from the previous interrupt. */ 5324 igc_write_itr(q_vector); 5325 5326 napi_schedule(&q_vector->napi); 5327 5328 return IRQ_HANDLED; 5329 } 5330 5331 /** 5332 * igc_request_msix - Initialize MSI-X interrupts 5333 * @adapter: Pointer to adapter structure 5334 * 5335 * igc_request_msix allocates MSI-X vectors and requests interrupts from the 5336 * kernel. 5337 */ 5338 static int igc_request_msix(struct igc_adapter *adapter) 5339 { 5340 unsigned int num_q_vectors = adapter->num_q_vectors; 5341 int i = 0, err = 0, vector = 0, free_vector = 0; 5342 struct net_device *netdev = adapter->netdev; 5343 5344 err = request_irq(adapter->msix_entries[vector].vector, 5345 &igc_msix_other, 0, netdev->name, adapter); 5346 if (err) 5347 goto err_out; 5348 5349 if (num_q_vectors > MAX_Q_VECTORS) { 5350 num_q_vectors = MAX_Q_VECTORS; 5351 dev_warn(&adapter->pdev->dev, 5352 "The number of queue vectors (%d) is higher than max allowed (%d)\n", 5353 adapter->num_q_vectors, MAX_Q_VECTORS); 5354 } 5355 for (i = 0; i < num_q_vectors; i++) { 5356 struct igc_q_vector *q_vector = adapter->q_vector[i]; 5357 5358 vector++; 5359 5360 q_vector->itr_register = adapter->io_addr + IGC_EITR(vector); 5361 5362 if (q_vector->rx.ring && q_vector->tx.ring) 5363 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 5364 q_vector->rx.ring->queue_index); 5365 else if (q_vector->tx.ring) 5366 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 5367 q_vector->tx.ring->queue_index); 5368 else if (q_vector->rx.ring) 5369 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 5370 q_vector->rx.ring->queue_index); 5371 else 5372 sprintf(q_vector->name, "%s-unused", netdev->name); 5373 5374 err = request_irq(adapter->msix_entries[vector].vector, 5375 igc_msix_ring, 0, q_vector->name, 5376 q_vector); 5377 if (err) 5378 goto err_free; 5379 } 5380 5381 igc_configure_msix(adapter); 5382 return 0; 5383 5384 err_free: 5385 /* free already assigned IRQs */ 5386 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 5387 5388 vector--; 5389 for (i = 0; i < vector; i++) { 5390 free_irq(adapter->msix_entries[free_vector++].vector, 5391 adapter->q_vector[i]); 5392 } 5393 err_out: 5394 return err; 5395 } 5396 5397 /** 5398 * igc_clear_interrupt_scheme - reset the device to a state of no interrupts 5399 * @adapter: Pointer to adapter structure 5400 * 5401 * This function resets the device so that it has 0 rx queues, tx queues, and 5402 * MSI-X interrupts allocated. 5403 */ 5404 static void igc_clear_interrupt_scheme(struct igc_adapter *adapter) 5405 { 5406 igc_free_q_vectors(adapter); 5407 igc_reset_interrupt_capability(adapter); 5408 } 5409 5410 /* Need to wait a few seconds after link up to get diagnostic information from 5411 * the phy 5412 */ 5413 static void igc_update_phy_info(struct timer_list *t) 5414 { 5415 struct igc_adapter *adapter = from_timer(adapter, t, phy_info_timer); 5416 5417 igc_get_phy_info(&adapter->hw); 5418 } 5419 5420 /** 5421 * igc_has_link - check shared code for link and determine up/down 5422 * @adapter: pointer to driver private info 5423 */ 5424 bool igc_has_link(struct igc_adapter *adapter) 5425 { 5426 struct igc_hw *hw = &adapter->hw; 5427 bool link_active = false; 5428 5429 /* get_link_status is set on LSC (link status) interrupt or 5430 * rx sequence error interrupt. get_link_status will stay 5431 * false until the igc_check_for_link establishes link 5432 * for copper adapters ONLY 5433 */ 5434 if (!hw->mac.get_link_status) 5435 return true; 5436 hw->mac.ops.check_for_link(hw); 5437 link_active = !hw->mac.get_link_status; 5438 5439 if (hw->mac.type == igc_i225) { 5440 if (!netif_carrier_ok(adapter->netdev)) { 5441 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE; 5442 } else if (!(adapter->flags & IGC_FLAG_NEED_LINK_UPDATE)) { 5443 adapter->flags |= IGC_FLAG_NEED_LINK_UPDATE; 5444 adapter->link_check_timeout = jiffies; 5445 } 5446 } 5447 5448 return link_active; 5449 } 5450 5451 /** 5452 * igc_watchdog - Timer Call-back 5453 * @t: timer for the watchdog 5454 */ 5455 static void igc_watchdog(struct timer_list *t) 5456 { 5457 struct igc_adapter *adapter = from_timer(adapter, t, watchdog_timer); 5458 /* Do the rest outside of interrupt context */ 5459 schedule_work(&adapter->watchdog_task); 5460 } 5461 5462 static void igc_watchdog_task(struct work_struct *work) 5463 { 5464 struct igc_adapter *adapter = container_of(work, 5465 struct igc_adapter, 5466 watchdog_task); 5467 struct net_device *netdev = adapter->netdev; 5468 struct igc_hw *hw = &adapter->hw; 5469 struct igc_phy_info *phy = &hw->phy; 5470 u16 phy_data, retry_count = 20; 5471 u32 link; 5472 int i; 5473 5474 link = igc_has_link(adapter); 5475 5476 if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE) { 5477 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 5478 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE; 5479 else 5480 link = false; 5481 } 5482 5483 if (link) { 5484 /* Cancel scheduled suspend requests. */ 5485 pm_runtime_resume(netdev->dev.parent); 5486 5487 if (!netif_carrier_ok(netdev)) { 5488 u32 ctrl; 5489 5490 hw->mac.ops.get_speed_and_duplex(hw, 5491 &adapter->link_speed, 5492 &adapter->link_duplex); 5493 5494 ctrl = rd32(IGC_CTRL); 5495 /* Link status message must follow this format */ 5496 netdev_info(netdev, 5497 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 5498 adapter->link_speed, 5499 adapter->link_duplex == FULL_DUPLEX ? 5500 "Full" : "Half", 5501 (ctrl & IGC_CTRL_TFCE) && 5502 (ctrl & IGC_CTRL_RFCE) ? "RX/TX" : 5503 (ctrl & IGC_CTRL_RFCE) ? "RX" : 5504 (ctrl & IGC_CTRL_TFCE) ? "TX" : "None"); 5505 5506 /* disable EEE if enabled */ 5507 if ((adapter->flags & IGC_FLAG_EEE) && 5508 adapter->link_duplex == HALF_DUPLEX) { 5509 netdev_info(netdev, 5510 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex\n"); 5511 adapter->hw.dev_spec._base.eee_enable = false; 5512 adapter->flags &= ~IGC_FLAG_EEE; 5513 } 5514 5515 /* check if SmartSpeed worked */ 5516 igc_check_downshift(hw); 5517 if (phy->speed_downgraded) 5518 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 5519 5520 /* adjust timeout factor according to speed/duplex */ 5521 adapter->tx_timeout_factor = 1; 5522 switch (adapter->link_speed) { 5523 case SPEED_10: 5524 adapter->tx_timeout_factor = 14; 5525 break; 5526 case SPEED_100: 5527 case SPEED_1000: 5528 case SPEED_2500: 5529 adapter->tx_timeout_factor = 1; 5530 break; 5531 } 5532 5533 /* Once the launch time has been set on the wire, there 5534 * is a delay before the link speed can be determined 5535 * based on link-up activity. Write into the register 5536 * as soon as we know the correct link speed. 5537 */ 5538 igc_tsn_adjust_txtime_offset(adapter); 5539 5540 if (adapter->link_speed != SPEED_1000) 5541 goto no_wait; 5542 5543 /* wait for Remote receiver status OK */ 5544 retry_read_status: 5545 if (!igc_read_phy_reg(hw, PHY_1000T_STATUS, 5546 &phy_data)) { 5547 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 5548 retry_count) { 5549 msleep(100); 5550 retry_count--; 5551 goto retry_read_status; 5552 } else if (!retry_count) { 5553 netdev_err(netdev, "exceed max 2 second\n"); 5554 } 5555 } else { 5556 netdev_err(netdev, "read 1000Base-T Status Reg\n"); 5557 } 5558 no_wait: 5559 netif_carrier_on(netdev); 5560 5561 /* link state has changed, schedule phy info update */ 5562 if (!test_bit(__IGC_DOWN, &adapter->state)) 5563 mod_timer(&adapter->phy_info_timer, 5564 round_jiffies(jiffies + 2 * HZ)); 5565 } 5566 } else { 5567 if (netif_carrier_ok(netdev)) { 5568 adapter->link_speed = 0; 5569 adapter->link_duplex = 0; 5570 5571 /* Links status message must follow this format */ 5572 netdev_info(netdev, "NIC Link is Down\n"); 5573 netif_carrier_off(netdev); 5574 5575 /* link state has changed, schedule phy info update */ 5576 if (!test_bit(__IGC_DOWN, &adapter->state)) 5577 mod_timer(&adapter->phy_info_timer, 5578 round_jiffies(jiffies + 2 * HZ)); 5579 5580 pm_schedule_suspend(netdev->dev.parent, 5581 MSEC_PER_SEC * 5); 5582 } 5583 } 5584 5585 spin_lock(&adapter->stats64_lock); 5586 igc_update_stats(adapter); 5587 spin_unlock(&adapter->stats64_lock); 5588 5589 for (i = 0; i < adapter->num_tx_queues; i++) { 5590 struct igc_ring *tx_ring = adapter->tx_ring[i]; 5591 5592 if (!netif_carrier_ok(netdev)) { 5593 /* We've lost link, so the controller stops DMA, 5594 * but we've got queued Tx work that's never going 5595 * to get done, so reset controller to flush Tx. 5596 * (Do the reset outside of interrupt context). 5597 */ 5598 if (igc_desc_unused(tx_ring) + 1 < tx_ring->count) { 5599 adapter->tx_timeout_count++; 5600 schedule_work(&adapter->reset_task); 5601 /* return immediately since reset is imminent */ 5602 return; 5603 } 5604 } 5605 5606 /* Force detection of hung controller every watchdog period */ 5607 set_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5608 } 5609 5610 /* Cause software interrupt to ensure Rx ring is cleaned */ 5611 if (adapter->flags & IGC_FLAG_HAS_MSIX) { 5612 u32 eics = 0; 5613 5614 for (i = 0; i < adapter->num_q_vectors; i++) 5615 eics |= adapter->q_vector[i]->eims_value; 5616 wr32(IGC_EICS, eics); 5617 } else { 5618 wr32(IGC_ICS, IGC_ICS_RXDMT0); 5619 } 5620 5621 igc_ptp_tx_hang(adapter); 5622 5623 /* Reset the timer */ 5624 if (!test_bit(__IGC_DOWN, &adapter->state)) { 5625 if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE) 5626 mod_timer(&adapter->watchdog_timer, 5627 round_jiffies(jiffies + HZ)); 5628 else 5629 mod_timer(&adapter->watchdog_timer, 5630 round_jiffies(jiffies + 2 * HZ)); 5631 } 5632 } 5633 5634 /** 5635 * igc_intr_msi - Interrupt Handler 5636 * @irq: interrupt number 5637 * @data: pointer to a network interface device structure 5638 */ 5639 static irqreturn_t igc_intr_msi(int irq, void *data) 5640 { 5641 struct igc_adapter *adapter = data; 5642 struct igc_q_vector *q_vector = adapter->q_vector[0]; 5643 struct igc_hw *hw = &adapter->hw; 5644 /* read ICR disables interrupts using IAM */ 5645 u32 icr = rd32(IGC_ICR); 5646 5647 igc_write_itr(q_vector); 5648 5649 if (icr & IGC_ICR_DRSTA) 5650 schedule_work(&adapter->reset_task); 5651 5652 if (icr & IGC_ICR_DOUTSYNC) { 5653 /* HW is reporting DMA is out of sync */ 5654 adapter->stats.doosync++; 5655 } 5656 5657 if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) { 5658 hw->mac.get_link_status = true; 5659 if (!test_bit(__IGC_DOWN, &adapter->state)) 5660 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5661 } 5662 5663 if (icr & IGC_ICR_TS) 5664 igc_tsync_interrupt(adapter); 5665 5666 napi_schedule(&q_vector->napi); 5667 5668 return IRQ_HANDLED; 5669 } 5670 5671 /** 5672 * igc_intr - Legacy Interrupt Handler 5673 * @irq: interrupt number 5674 * @data: pointer to a network interface device structure 5675 */ 5676 static irqreturn_t igc_intr(int irq, void *data) 5677 { 5678 struct igc_adapter *adapter = data; 5679 struct igc_q_vector *q_vector = adapter->q_vector[0]; 5680 struct igc_hw *hw = &adapter->hw; 5681 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 5682 * need for the IMC write 5683 */ 5684 u32 icr = rd32(IGC_ICR); 5685 5686 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 5687 * not set, then the adapter didn't send an interrupt 5688 */ 5689 if (!(icr & IGC_ICR_INT_ASSERTED)) 5690 return IRQ_NONE; 5691 5692 igc_write_itr(q_vector); 5693 5694 if (icr & IGC_ICR_DRSTA) 5695 schedule_work(&adapter->reset_task); 5696 5697 if (icr & IGC_ICR_DOUTSYNC) { 5698 /* HW is reporting DMA is out of sync */ 5699 adapter->stats.doosync++; 5700 } 5701 5702 if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) { 5703 hw->mac.get_link_status = true; 5704 /* guard against interrupt when we're going down */ 5705 if (!test_bit(__IGC_DOWN, &adapter->state)) 5706 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5707 } 5708 5709 if (icr & IGC_ICR_TS) 5710 igc_tsync_interrupt(adapter); 5711 5712 napi_schedule(&q_vector->napi); 5713 5714 return IRQ_HANDLED; 5715 } 5716 5717 static void igc_free_irq(struct igc_adapter *adapter) 5718 { 5719 if (adapter->msix_entries) { 5720 int vector = 0, i; 5721 5722 free_irq(adapter->msix_entries[vector++].vector, adapter); 5723 5724 for (i = 0; i < adapter->num_q_vectors; i++) 5725 free_irq(adapter->msix_entries[vector++].vector, 5726 adapter->q_vector[i]); 5727 } else { 5728 free_irq(adapter->pdev->irq, adapter); 5729 } 5730 } 5731 5732 /** 5733 * igc_request_irq - initialize interrupts 5734 * @adapter: Pointer to adapter structure 5735 * 5736 * Attempts to configure interrupts using the best available 5737 * capabilities of the hardware and kernel. 5738 */ 5739 static int igc_request_irq(struct igc_adapter *adapter) 5740 { 5741 struct net_device *netdev = adapter->netdev; 5742 struct pci_dev *pdev = adapter->pdev; 5743 int err = 0; 5744 5745 if (adapter->flags & IGC_FLAG_HAS_MSIX) { 5746 err = igc_request_msix(adapter); 5747 if (!err) 5748 goto request_done; 5749 /* fall back to MSI */ 5750 igc_free_all_tx_resources(adapter); 5751 igc_free_all_rx_resources(adapter); 5752 5753 igc_clear_interrupt_scheme(adapter); 5754 err = igc_init_interrupt_scheme(adapter, false); 5755 if (err) 5756 goto request_done; 5757 igc_setup_all_tx_resources(adapter); 5758 igc_setup_all_rx_resources(adapter); 5759 igc_configure(adapter); 5760 } 5761 5762 igc_assign_vector(adapter->q_vector[0], 0); 5763 5764 if (adapter->flags & IGC_FLAG_HAS_MSI) { 5765 err = request_irq(pdev->irq, &igc_intr_msi, 0, 5766 netdev->name, adapter); 5767 if (!err) 5768 goto request_done; 5769 5770 /* fall back to legacy interrupts */ 5771 igc_reset_interrupt_capability(adapter); 5772 adapter->flags &= ~IGC_FLAG_HAS_MSI; 5773 } 5774 5775 err = request_irq(pdev->irq, &igc_intr, IRQF_SHARED, 5776 netdev->name, adapter); 5777 5778 if (err) 5779 netdev_err(netdev, "Error %d getting interrupt\n", err); 5780 5781 request_done: 5782 return err; 5783 } 5784 5785 /** 5786 * __igc_open - Called when a network interface is made active 5787 * @netdev: network interface device structure 5788 * @resuming: boolean indicating if the device is resuming 5789 * 5790 * Returns 0 on success, negative value on failure 5791 * 5792 * The open entry point is called when a network interface is made 5793 * active by the system (IFF_UP). At this point all resources needed 5794 * for transmit and receive operations are allocated, the interrupt 5795 * handler is registered with the OS, the watchdog timer is started, 5796 * and the stack is notified that the interface is ready. 5797 */ 5798 static int __igc_open(struct net_device *netdev, bool resuming) 5799 { 5800 struct igc_adapter *adapter = netdev_priv(netdev); 5801 struct pci_dev *pdev = adapter->pdev; 5802 struct igc_hw *hw = &adapter->hw; 5803 int err = 0; 5804 int i = 0; 5805 5806 /* disallow open during test */ 5807 5808 if (test_bit(__IGC_TESTING, &adapter->state)) { 5809 WARN_ON(resuming); 5810 return -EBUSY; 5811 } 5812 5813 if (!resuming) 5814 pm_runtime_get_sync(&pdev->dev); 5815 5816 netif_carrier_off(netdev); 5817 5818 /* allocate transmit descriptors */ 5819 err = igc_setup_all_tx_resources(adapter); 5820 if (err) 5821 goto err_setup_tx; 5822 5823 /* allocate receive descriptors */ 5824 err = igc_setup_all_rx_resources(adapter); 5825 if (err) 5826 goto err_setup_rx; 5827 5828 igc_power_up_link(adapter); 5829 5830 igc_configure(adapter); 5831 5832 err = igc_request_irq(adapter); 5833 if (err) 5834 goto err_req_irq; 5835 5836 /* Notify the stack of the actual queue counts. */ 5837 err = netif_set_real_num_tx_queues(netdev, adapter->num_tx_queues); 5838 if (err) 5839 goto err_set_queues; 5840 5841 err = netif_set_real_num_rx_queues(netdev, adapter->num_rx_queues); 5842 if (err) 5843 goto err_set_queues; 5844 5845 clear_bit(__IGC_DOWN, &adapter->state); 5846 5847 for (i = 0; i < adapter->num_q_vectors; i++) 5848 napi_enable(&adapter->q_vector[i]->napi); 5849 5850 /* Clear any pending interrupts. */ 5851 rd32(IGC_ICR); 5852 igc_irq_enable(adapter); 5853 5854 if (!resuming) 5855 pm_runtime_put(&pdev->dev); 5856 5857 netif_tx_start_all_queues(netdev); 5858 5859 /* start the watchdog. */ 5860 hw->mac.get_link_status = true; 5861 schedule_work(&adapter->watchdog_task); 5862 5863 return IGC_SUCCESS; 5864 5865 err_set_queues: 5866 igc_free_irq(adapter); 5867 err_req_irq: 5868 igc_release_hw_control(adapter); 5869 igc_power_down_phy_copper_base(&adapter->hw); 5870 igc_free_all_rx_resources(adapter); 5871 err_setup_rx: 5872 igc_free_all_tx_resources(adapter); 5873 err_setup_tx: 5874 igc_reset(adapter); 5875 if (!resuming) 5876 pm_runtime_put(&pdev->dev); 5877 5878 return err; 5879 } 5880 5881 int igc_open(struct net_device *netdev) 5882 { 5883 return __igc_open(netdev, false); 5884 } 5885 5886 /** 5887 * __igc_close - Disables a network interface 5888 * @netdev: network interface device structure 5889 * @suspending: boolean indicating the device is suspending 5890 * 5891 * Returns 0, this is not allowed to fail 5892 * 5893 * The close entry point is called when an interface is de-activated 5894 * by the OS. The hardware is still under the driver's control, but 5895 * needs to be disabled. A global MAC reset is issued to stop the 5896 * hardware, and all transmit and receive resources are freed. 5897 */ 5898 static int __igc_close(struct net_device *netdev, bool suspending) 5899 { 5900 struct igc_adapter *adapter = netdev_priv(netdev); 5901 struct pci_dev *pdev = adapter->pdev; 5902 5903 WARN_ON(test_bit(__IGC_RESETTING, &adapter->state)); 5904 5905 if (!suspending) 5906 pm_runtime_get_sync(&pdev->dev); 5907 5908 igc_down(adapter); 5909 5910 igc_release_hw_control(adapter); 5911 5912 igc_free_irq(adapter); 5913 5914 igc_free_all_tx_resources(adapter); 5915 igc_free_all_rx_resources(adapter); 5916 5917 if (!suspending) 5918 pm_runtime_put_sync(&pdev->dev); 5919 5920 return 0; 5921 } 5922 5923 int igc_close(struct net_device *netdev) 5924 { 5925 if (netif_device_present(netdev) || netdev->dismantle) 5926 return __igc_close(netdev, false); 5927 return 0; 5928 } 5929 5930 /** 5931 * igc_ioctl - Access the hwtstamp interface 5932 * @netdev: network interface device structure 5933 * @ifr: interface request data 5934 * @cmd: ioctl command 5935 **/ 5936 static int igc_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 5937 { 5938 switch (cmd) { 5939 case SIOCGHWTSTAMP: 5940 return igc_ptp_get_ts_config(netdev, ifr); 5941 case SIOCSHWTSTAMP: 5942 return igc_ptp_set_ts_config(netdev, ifr); 5943 default: 5944 return -EOPNOTSUPP; 5945 } 5946 } 5947 5948 static int igc_save_launchtime_params(struct igc_adapter *adapter, int queue, 5949 bool enable) 5950 { 5951 struct igc_ring *ring; 5952 5953 if (queue < 0 || queue >= adapter->num_tx_queues) 5954 return -EINVAL; 5955 5956 ring = adapter->tx_ring[queue]; 5957 ring->launchtime_enable = enable; 5958 5959 return 0; 5960 } 5961 5962 static bool is_base_time_past(ktime_t base_time, const struct timespec64 *now) 5963 { 5964 struct timespec64 b; 5965 5966 b = ktime_to_timespec64(base_time); 5967 5968 return timespec64_compare(now, &b) > 0; 5969 } 5970 5971 static bool validate_schedule(struct igc_adapter *adapter, 5972 const struct tc_taprio_qopt_offload *qopt) 5973 { 5974 int queue_uses[IGC_MAX_TX_QUEUES] = { }; 5975 struct igc_hw *hw = &adapter->hw; 5976 struct timespec64 now; 5977 size_t n; 5978 5979 if (qopt->cycle_time_extension) 5980 return false; 5981 5982 igc_ptp_read(adapter, &now); 5983 5984 /* If we program the controller's BASET registers with a time 5985 * in the future, it will hold all the packets until that 5986 * time, causing a lot of TX Hangs, so to avoid that, we 5987 * reject schedules that would start in the future. 5988 * Note: Limitation above is no longer in i226. 5989 */ 5990 if (!is_base_time_past(qopt->base_time, &now) && 5991 igc_is_device_id_i225(hw)) 5992 return false; 5993 5994 for (n = 0; n < qopt->num_entries; n++) { 5995 const struct tc_taprio_sched_entry *e, *prev; 5996 int i; 5997 5998 prev = n ? &qopt->entries[n - 1] : NULL; 5999 e = &qopt->entries[n]; 6000 6001 /* i225 only supports "global" frame preemption 6002 * settings. 6003 */ 6004 if (e->command != TC_TAPRIO_CMD_SET_GATES) 6005 return false; 6006 6007 for (i = 0; i < adapter->num_tx_queues; i++) 6008 if (e->gate_mask & BIT(i)) { 6009 queue_uses[i]++; 6010 6011 /* There are limitations: A single queue cannot 6012 * be opened and closed multiple times per cycle 6013 * unless the gate stays open. Check for it. 6014 */ 6015 if (queue_uses[i] > 1 && 6016 !(prev->gate_mask & BIT(i))) 6017 return false; 6018 } 6019 } 6020 6021 return true; 6022 } 6023 6024 static int igc_tsn_enable_launchtime(struct igc_adapter *adapter, 6025 struct tc_etf_qopt_offload *qopt) 6026 { 6027 struct igc_hw *hw = &adapter->hw; 6028 int err; 6029 6030 if (hw->mac.type != igc_i225) 6031 return -EOPNOTSUPP; 6032 6033 err = igc_save_launchtime_params(adapter, qopt->queue, qopt->enable); 6034 if (err) 6035 return err; 6036 6037 return igc_tsn_offload_apply(adapter); 6038 } 6039 6040 static int igc_tsn_clear_schedule(struct igc_adapter *adapter) 6041 { 6042 int i; 6043 6044 adapter->base_time = 0; 6045 adapter->cycle_time = NSEC_PER_SEC; 6046 adapter->qbv_config_change_errors = 0; 6047 6048 for (i = 0; i < adapter->num_tx_queues; i++) { 6049 struct igc_ring *ring = adapter->tx_ring[i]; 6050 6051 ring->start_time = 0; 6052 ring->end_time = NSEC_PER_SEC; 6053 ring->max_sdu = 0; 6054 } 6055 6056 return 0; 6057 } 6058 6059 static int igc_save_qbv_schedule(struct igc_adapter *adapter, 6060 struct tc_taprio_qopt_offload *qopt) 6061 { 6062 bool queue_configured[IGC_MAX_TX_QUEUES] = { }; 6063 struct igc_hw *hw = &adapter->hw; 6064 u32 start_time = 0, end_time = 0; 6065 size_t n; 6066 int i; 6067 6068 adapter->qbv_enable = qopt->enable; 6069 6070 if (!qopt->enable) 6071 return igc_tsn_clear_schedule(adapter); 6072 6073 if (qopt->base_time < 0) 6074 return -ERANGE; 6075 6076 if (igc_is_device_id_i225(hw) && adapter->base_time) 6077 return -EALREADY; 6078 6079 if (!validate_schedule(adapter, qopt)) 6080 return -EINVAL; 6081 6082 adapter->cycle_time = qopt->cycle_time; 6083 adapter->base_time = qopt->base_time; 6084 6085 for (n = 0; n < qopt->num_entries; n++) { 6086 struct tc_taprio_sched_entry *e = &qopt->entries[n]; 6087 6088 end_time += e->interval; 6089 6090 /* If any of the conditions below are true, we need to manually 6091 * control the end time of the cycle. 6092 * 1. Qbv users can specify a cycle time that is not equal 6093 * to the total GCL intervals. Hence, recalculation is 6094 * necessary here to exclude the time interval that 6095 * exceeds the cycle time. 6096 * 2. According to IEEE Std. 802.1Q-2018 section 8.6.9.2, 6097 * once the end of the list is reached, it will switch 6098 * to the END_OF_CYCLE state and leave the gates in the 6099 * same state until the next cycle is started. 6100 */ 6101 if (end_time > adapter->cycle_time || 6102 n + 1 == qopt->num_entries) 6103 end_time = adapter->cycle_time; 6104 6105 for (i = 0; i < adapter->num_tx_queues; i++) { 6106 struct igc_ring *ring = adapter->tx_ring[i]; 6107 6108 if (!(e->gate_mask & BIT(i))) 6109 continue; 6110 6111 /* Check whether a queue stays open for more than one 6112 * entry. If so, keep the start and advance the end 6113 * time. 6114 */ 6115 if (!queue_configured[i]) 6116 ring->start_time = start_time; 6117 ring->end_time = end_time; 6118 6119 queue_configured[i] = true; 6120 } 6121 6122 start_time += e->interval; 6123 } 6124 6125 /* Check whether a queue gets configured. 6126 * If not, set the start and end time to be end time. 6127 */ 6128 for (i = 0; i < adapter->num_tx_queues; i++) { 6129 if (!queue_configured[i]) { 6130 struct igc_ring *ring = adapter->tx_ring[i]; 6131 6132 ring->start_time = end_time; 6133 ring->end_time = end_time; 6134 } 6135 } 6136 6137 for (i = 0; i < adapter->num_tx_queues; i++) { 6138 struct igc_ring *ring = adapter->tx_ring[i]; 6139 struct net_device *dev = adapter->netdev; 6140 6141 if (qopt->max_sdu[i]) 6142 ring->max_sdu = qopt->max_sdu[i] + dev->hard_header_len; 6143 else 6144 ring->max_sdu = 0; 6145 } 6146 6147 return 0; 6148 } 6149 6150 static int igc_tsn_enable_qbv_scheduling(struct igc_adapter *adapter, 6151 struct tc_taprio_qopt_offload *qopt) 6152 { 6153 struct igc_hw *hw = &adapter->hw; 6154 int err; 6155 6156 if (hw->mac.type != igc_i225) 6157 return -EOPNOTSUPP; 6158 6159 err = igc_save_qbv_schedule(adapter, qopt); 6160 if (err) 6161 return err; 6162 6163 return igc_tsn_offload_apply(adapter); 6164 } 6165 6166 static int igc_save_cbs_params(struct igc_adapter *adapter, int queue, 6167 bool enable, int idleslope, int sendslope, 6168 int hicredit, int locredit) 6169 { 6170 bool cbs_status[IGC_MAX_SR_QUEUES] = { false }; 6171 struct net_device *netdev = adapter->netdev; 6172 struct igc_ring *ring; 6173 int i; 6174 6175 /* i225 has two sets of credit-based shaper logic. 6176 * Supporting it only on the top two priority queues 6177 */ 6178 if (queue < 0 || queue > 1) 6179 return -EINVAL; 6180 6181 ring = adapter->tx_ring[queue]; 6182 6183 for (i = 0; i < IGC_MAX_SR_QUEUES; i++) 6184 if (adapter->tx_ring[i]) 6185 cbs_status[i] = adapter->tx_ring[i]->cbs_enable; 6186 6187 /* CBS should be enabled on the highest priority queue first in order 6188 * for the CBS algorithm to operate as intended. 6189 */ 6190 if (enable) { 6191 if (queue == 1 && !cbs_status[0]) { 6192 netdev_err(netdev, 6193 "Enabling CBS on queue1 before queue0\n"); 6194 return -EINVAL; 6195 } 6196 } else { 6197 if (queue == 0 && cbs_status[1]) { 6198 netdev_err(netdev, 6199 "Disabling CBS on queue0 before queue1\n"); 6200 return -EINVAL; 6201 } 6202 } 6203 6204 ring->cbs_enable = enable; 6205 ring->idleslope = idleslope; 6206 ring->sendslope = sendslope; 6207 ring->hicredit = hicredit; 6208 ring->locredit = locredit; 6209 6210 return 0; 6211 } 6212 6213 static int igc_tsn_enable_cbs(struct igc_adapter *adapter, 6214 struct tc_cbs_qopt_offload *qopt) 6215 { 6216 struct igc_hw *hw = &adapter->hw; 6217 int err; 6218 6219 if (hw->mac.type != igc_i225) 6220 return -EOPNOTSUPP; 6221 6222 if (qopt->queue < 0 || qopt->queue > 1) 6223 return -EINVAL; 6224 6225 err = igc_save_cbs_params(adapter, qopt->queue, qopt->enable, 6226 qopt->idleslope, qopt->sendslope, 6227 qopt->hicredit, qopt->locredit); 6228 if (err) 6229 return err; 6230 6231 return igc_tsn_offload_apply(adapter); 6232 } 6233 6234 static int igc_tc_query_caps(struct igc_adapter *adapter, 6235 struct tc_query_caps_base *base) 6236 { 6237 struct igc_hw *hw = &adapter->hw; 6238 6239 switch (base->type) { 6240 case TC_SETUP_QDISC_TAPRIO: { 6241 struct tc_taprio_caps *caps = base->caps; 6242 6243 caps->broken_mqprio = true; 6244 6245 if (hw->mac.type == igc_i225) { 6246 caps->supports_queue_max_sdu = true; 6247 caps->gate_mask_per_txq = true; 6248 } 6249 6250 return 0; 6251 } 6252 default: 6253 return -EOPNOTSUPP; 6254 } 6255 } 6256 6257 static int igc_setup_tc(struct net_device *dev, enum tc_setup_type type, 6258 void *type_data) 6259 { 6260 struct igc_adapter *adapter = netdev_priv(dev); 6261 6262 switch (type) { 6263 case TC_QUERY_CAPS: 6264 return igc_tc_query_caps(adapter, type_data); 6265 case TC_SETUP_QDISC_TAPRIO: 6266 return igc_tsn_enable_qbv_scheduling(adapter, type_data); 6267 6268 case TC_SETUP_QDISC_ETF: 6269 return igc_tsn_enable_launchtime(adapter, type_data); 6270 6271 case TC_SETUP_QDISC_CBS: 6272 return igc_tsn_enable_cbs(adapter, type_data); 6273 6274 default: 6275 return -EOPNOTSUPP; 6276 } 6277 } 6278 6279 static int igc_bpf(struct net_device *dev, struct netdev_bpf *bpf) 6280 { 6281 struct igc_adapter *adapter = netdev_priv(dev); 6282 6283 switch (bpf->command) { 6284 case XDP_SETUP_PROG: 6285 return igc_xdp_set_prog(adapter, bpf->prog, bpf->extack); 6286 case XDP_SETUP_XSK_POOL: 6287 return igc_xdp_setup_pool(adapter, bpf->xsk.pool, 6288 bpf->xsk.queue_id); 6289 default: 6290 return -EOPNOTSUPP; 6291 } 6292 } 6293 6294 static int igc_xdp_xmit(struct net_device *dev, int num_frames, 6295 struct xdp_frame **frames, u32 flags) 6296 { 6297 struct igc_adapter *adapter = netdev_priv(dev); 6298 int cpu = smp_processor_id(); 6299 struct netdev_queue *nq; 6300 struct igc_ring *ring; 6301 int i, drops; 6302 6303 if (unlikely(test_bit(__IGC_DOWN, &adapter->state))) 6304 return -ENETDOWN; 6305 6306 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 6307 return -EINVAL; 6308 6309 ring = igc_xdp_get_tx_ring(adapter, cpu); 6310 nq = txring_txq(ring); 6311 6312 __netif_tx_lock(nq, cpu); 6313 6314 drops = 0; 6315 for (i = 0; i < num_frames; i++) { 6316 int err; 6317 struct xdp_frame *xdpf = frames[i]; 6318 6319 err = igc_xdp_init_tx_descriptor(ring, xdpf); 6320 if (err) { 6321 xdp_return_frame_rx_napi(xdpf); 6322 drops++; 6323 } 6324 } 6325 6326 if (flags & XDP_XMIT_FLUSH) 6327 igc_flush_tx_descriptors(ring); 6328 6329 __netif_tx_unlock(nq); 6330 6331 return num_frames - drops; 6332 } 6333 6334 static void igc_trigger_rxtxq_interrupt(struct igc_adapter *adapter, 6335 struct igc_q_vector *q_vector) 6336 { 6337 struct igc_hw *hw = &adapter->hw; 6338 u32 eics = 0; 6339 6340 eics |= q_vector->eims_value; 6341 wr32(IGC_EICS, eics); 6342 } 6343 6344 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags) 6345 { 6346 struct igc_adapter *adapter = netdev_priv(dev); 6347 struct igc_q_vector *q_vector; 6348 struct igc_ring *ring; 6349 6350 if (test_bit(__IGC_DOWN, &adapter->state)) 6351 return -ENETDOWN; 6352 6353 if (!igc_xdp_is_enabled(adapter)) 6354 return -ENXIO; 6355 6356 if (queue_id >= adapter->num_rx_queues) 6357 return -EINVAL; 6358 6359 ring = adapter->rx_ring[queue_id]; 6360 6361 if (!ring->xsk_pool) 6362 return -ENXIO; 6363 6364 q_vector = adapter->q_vector[queue_id]; 6365 if (!napi_if_scheduled_mark_missed(&q_vector->napi)) 6366 igc_trigger_rxtxq_interrupt(adapter, q_vector); 6367 6368 return 0; 6369 } 6370 6371 static const struct net_device_ops igc_netdev_ops = { 6372 .ndo_open = igc_open, 6373 .ndo_stop = igc_close, 6374 .ndo_start_xmit = igc_xmit_frame, 6375 .ndo_set_rx_mode = igc_set_rx_mode, 6376 .ndo_set_mac_address = igc_set_mac, 6377 .ndo_change_mtu = igc_change_mtu, 6378 .ndo_tx_timeout = igc_tx_timeout, 6379 .ndo_get_stats64 = igc_get_stats64, 6380 .ndo_fix_features = igc_fix_features, 6381 .ndo_set_features = igc_set_features, 6382 .ndo_features_check = igc_features_check, 6383 .ndo_eth_ioctl = igc_ioctl, 6384 .ndo_setup_tc = igc_setup_tc, 6385 .ndo_bpf = igc_bpf, 6386 .ndo_xdp_xmit = igc_xdp_xmit, 6387 .ndo_xsk_wakeup = igc_xsk_wakeup, 6388 }; 6389 6390 /* PCIe configuration access */ 6391 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value) 6392 { 6393 struct igc_adapter *adapter = hw->back; 6394 6395 pci_read_config_word(adapter->pdev, reg, value); 6396 } 6397 6398 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value) 6399 { 6400 struct igc_adapter *adapter = hw->back; 6401 6402 pci_write_config_word(adapter->pdev, reg, *value); 6403 } 6404 6405 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value) 6406 { 6407 struct igc_adapter *adapter = hw->back; 6408 6409 if (!pci_is_pcie(adapter->pdev)) 6410 return -IGC_ERR_CONFIG; 6411 6412 pcie_capability_read_word(adapter->pdev, reg, value); 6413 6414 return IGC_SUCCESS; 6415 } 6416 6417 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value) 6418 { 6419 struct igc_adapter *adapter = hw->back; 6420 6421 if (!pci_is_pcie(adapter->pdev)) 6422 return -IGC_ERR_CONFIG; 6423 6424 pcie_capability_write_word(adapter->pdev, reg, *value); 6425 6426 return IGC_SUCCESS; 6427 } 6428 6429 u32 igc_rd32(struct igc_hw *hw, u32 reg) 6430 { 6431 struct igc_adapter *igc = container_of(hw, struct igc_adapter, hw); 6432 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 6433 u32 value = 0; 6434 6435 if (IGC_REMOVED(hw_addr)) 6436 return ~value; 6437 6438 value = readl(&hw_addr[reg]); 6439 6440 /* reads should not return all F's */ 6441 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 6442 struct net_device *netdev = igc->netdev; 6443 6444 hw->hw_addr = NULL; 6445 netif_device_detach(netdev); 6446 netdev_err(netdev, "PCIe link lost, device now detached\n"); 6447 WARN(pci_device_is_present(igc->pdev), 6448 "igc: Failed to read reg 0x%x!\n", reg); 6449 } 6450 6451 return value; 6452 } 6453 6454 /** 6455 * igc_probe - Device Initialization Routine 6456 * @pdev: PCI device information struct 6457 * @ent: entry in igc_pci_tbl 6458 * 6459 * Returns 0 on success, negative on failure 6460 * 6461 * igc_probe initializes an adapter identified by a pci_dev structure. 6462 * The OS initialization, configuring the adapter private structure, 6463 * and a hardware reset occur. 6464 */ 6465 static int igc_probe(struct pci_dev *pdev, 6466 const struct pci_device_id *ent) 6467 { 6468 struct igc_adapter *adapter; 6469 struct net_device *netdev; 6470 struct igc_hw *hw; 6471 const struct igc_info *ei = igc_info_tbl[ent->driver_data]; 6472 int err; 6473 6474 err = pci_enable_device_mem(pdev); 6475 if (err) 6476 return err; 6477 6478 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 6479 if (err) { 6480 dev_err(&pdev->dev, 6481 "No usable DMA configuration, aborting\n"); 6482 goto err_dma; 6483 } 6484 6485 err = pci_request_mem_regions(pdev, igc_driver_name); 6486 if (err) 6487 goto err_pci_reg; 6488 6489 err = pci_enable_ptm(pdev, NULL); 6490 if (err < 0) 6491 dev_info(&pdev->dev, "PCIe PTM not supported by PCIe bus/controller\n"); 6492 6493 pci_set_master(pdev); 6494 6495 err = -ENOMEM; 6496 netdev = alloc_etherdev_mq(sizeof(struct igc_adapter), 6497 IGC_MAX_TX_QUEUES); 6498 6499 if (!netdev) 6500 goto err_alloc_etherdev; 6501 6502 SET_NETDEV_DEV(netdev, &pdev->dev); 6503 6504 pci_set_drvdata(pdev, netdev); 6505 adapter = netdev_priv(netdev); 6506 adapter->netdev = netdev; 6507 adapter->pdev = pdev; 6508 hw = &adapter->hw; 6509 hw->back = adapter; 6510 adapter->port_num = hw->bus.func; 6511 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 6512 6513 err = pci_save_state(pdev); 6514 if (err) 6515 goto err_ioremap; 6516 6517 err = -EIO; 6518 adapter->io_addr = ioremap(pci_resource_start(pdev, 0), 6519 pci_resource_len(pdev, 0)); 6520 if (!adapter->io_addr) 6521 goto err_ioremap; 6522 6523 /* hw->hw_addr can be zeroed, so use adapter->io_addr for unmap */ 6524 hw->hw_addr = adapter->io_addr; 6525 6526 netdev->netdev_ops = &igc_netdev_ops; 6527 igc_ethtool_set_ops(netdev); 6528 netdev->watchdog_timeo = 5 * HZ; 6529 6530 netdev->mem_start = pci_resource_start(pdev, 0); 6531 netdev->mem_end = pci_resource_end(pdev, 0); 6532 6533 /* PCI config space info */ 6534 hw->vendor_id = pdev->vendor; 6535 hw->device_id = pdev->device; 6536 hw->revision_id = pdev->revision; 6537 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6538 hw->subsystem_device_id = pdev->subsystem_device; 6539 6540 /* Copy the default MAC and PHY function pointers */ 6541 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 6542 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 6543 6544 /* Initialize skew-specific constants */ 6545 err = ei->get_invariants(hw); 6546 if (err) 6547 goto err_sw_init; 6548 6549 /* Add supported features to the features list*/ 6550 netdev->features |= NETIF_F_SG; 6551 netdev->features |= NETIF_F_TSO; 6552 netdev->features |= NETIF_F_TSO6; 6553 netdev->features |= NETIF_F_TSO_ECN; 6554 netdev->features |= NETIF_F_RXCSUM; 6555 netdev->features |= NETIF_F_HW_CSUM; 6556 netdev->features |= NETIF_F_SCTP_CRC; 6557 netdev->features |= NETIF_F_HW_TC; 6558 6559 #define IGC_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 6560 NETIF_F_GSO_GRE_CSUM | \ 6561 NETIF_F_GSO_IPXIP4 | \ 6562 NETIF_F_GSO_IPXIP6 | \ 6563 NETIF_F_GSO_UDP_TUNNEL | \ 6564 NETIF_F_GSO_UDP_TUNNEL_CSUM) 6565 6566 netdev->gso_partial_features = IGC_GSO_PARTIAL_FEATURES; 6567 netdev->features |= NETIF_F_GSO_PARTIAL | IGC_GSO_PARTIAL_FEATURES; 6568 6569 /* setup the private structure */ 6570 err = igc_sw_init(adapter); 6571 if (err) 6572 goto err_sw_init; 6573 6574 /* copy netdev features into list of user selectable features */ 6575 netdev->hw_features |= NETIF_F_NTUPLE; 6576 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 6577 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 6578 netdev->hw_features |= netdev->features; 6579 6580 netdev->features |= NETIF_F_HIGHDMA; 6581 6582 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 6583 netdev->mpls_features |= NETIF_F_HW_CSUM; 6584 netdev->hw_enc_features |= netdev->vlan_features; 6585 6586 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 6587 NETDEV_XDP_ACT_XSK_ZEROCOPY; 6588 6589 /* MTU range: 68 - 9216 */ 6590 netdev->min_mtu = ETH_MIN_MTU; 6591 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 6592 6593 /* before reading the NVM, reset the controller to put the device in a 6594 * known good starting state 6595 */ 6596 hw->mac.ops.reset_hw(hw); 6597 6598 if (igc_get_flash_presence_i225(hw)) { 6599 if (hw->nvm.ops.validate(hw) < 0) { 6600 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 6601 err = -EIO; 6602 goto err_eeprom; 6603 } 6604 } 6605 6606 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 6607 /* copy the MAC address out of the NVM */ 6608 if (hw->mac.ops.read_mac_addr(hw)) 6609 dev_err(&pdev->dev, "NVM Read Error\n"); 6610 } 6611 6612 eth_hw_addr_set(netdev, hw->mac.addr); 6613 6614 if (!is_valid_ether_addr(netdev->dev_addr)) { 6615 dev_err(&pdev->dev, "Invalid MAC Address\n"); 6616 err = -EIO; 6617 goto err_eeprom; 6618 } 6619 6620 /* configure RXPBSIZE and TXPBSIZE */ 6621 wr32(IGC_RXPBS, I225_RXPBSIZE_DEFAULT); 6622 wr32(IGC_TXPBS, I225_TXPBSIZE_DEFAULT); 6623 6624 timer_setup(&adapter->watchdog_timer, igc_watchdog, 0); 6625 timer_setup(&adapter->phy_info_timer, igc_update_phy_info, 0); 6626 6627 INIT_WORK(&adapter->reset_task, igc_reset_task); 6628 INIT_WORK(&adapter->watchdog_task, igc_watchdog_task); 6629 6630 /* Initialize link properties that are user-changeable */ 6631 adapter->fc_autoneg = true; 6632 hw->mac.autoneg = true; 6633 hw->phy.autoneg_advertised = 0xaf; 6634 6635 hw->fc.requested_mode = igc_fc_default; 6636 hw->fc.current_mode = igc_fc_default; 6637 6638 /* By default, support wake on port A */ 6639 adapter->flags |= IGC_FLAG_WOL_SUPPORTED; 6640 6641 /* initialize the wol settings based on the eeprom settings */ 6642 if (adapter->flags & IGC_FLAG_WOL_SUPPORTED) 6643 adapter->wol |= IGC_WUFC_MAG; 6644 6645 device_set_wakeup_enable(&adapter->pdev->dev, 6646 adapter->flags & IGC_FLAG_WOL_SUPPORTED); 6647 6648 igc_ptp_init(adapter); 6649 6650 igc_tsn_clear_schedule(adapter); 6651 6652 /* reset the hardware with the new settings */ 6653 igc_reset(adapter); 6654 6655 /* let the f/w know that the h/w is now under the control of the 6656 * driver. 6657 */ 6658 igc_get_hw_control(adapter); 6659 6660 strncpy(netdev->name, "eth%d", IFNAMSIZ); 6661 err = register_netdev(netdev); 6662 if (err) 6663 goto err_register; 6664 6665 /* carrier off reporting is important to ethtool even BEFORE open */ 6666 netif_carrier_off(netdev); 6667 6668 /* Check if Media Autosense is enabled */ 6669 adapter->ei = *ei; 6670 6671 /* print pcie link status and MAC address */ 6672 pcie_print_link_status(pdev); 6673 netdev_info(netdev, "MAC: %pM\n", netdev->dev_addr); 6674 6675 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 6676 /* Disable EEE for internal PHY devices */ 6677 hw->dev_spec._base.eee_enable = false; 6678 adapter->flags &= ~IGC_FLAG_EEE; 6679 igc_set_eee_i225(hw, false, false, false); 6680 6681 pm_runtime_put_noidle(&pdev->dev); 6682 6683 return 0; 6684 6685 err_register: 6686 igc_release_hw_control(adapter); 6687 err_eeprom: 6688 if (!igc_check_reset_block(hw)) 6689 igc_reset_phy(hw); 6690 err_sw_init: 6691 igc_clear_interrupt_scheme(adapter); 6692 iounmap(adapter->io_addr); 6693 err_ioremap: 6694 free_netdev(netdev); 6695 err_alloc_etherdev: 6696 pci_release_mem_regions(pdev); 6697 err_pci_reg: 6698 err_dma: 6699 pci_disable_device(pdev); 6700 return err; 6701 } 6702 6703 /** 6704 * igc_remove - Device Removal Routine 6705 * @pdev: PCI device information struct 6706 * 6707 * igc_remove is called by the PCI subsystem to alert the driver 6708 * that it should release a PCI device. This could be caused by a 6709 * Hot-Plug event, or because the driver is going to be removed from 6710 * memory. 6711 */ 6712 static void igc_remove(struct pci_dev *pdev) 6713 { 6714 struct net_device *netdev = pci_get_drvdata(pdev); 6715 struct igc_adapter *adapter = netdev_priv(netdev); 6716 6717 pm_runtime_get_noresume(&pdev->dev); 6718 6719 igc_flush_nfc_rules(adapter); 6720 6721 igc_ptp_stop(adapter); 6722 6723 set_bit(__IGC_DOWN, &adapter->state); 6724 6725 del_timer_sync(&adapter->watchdog_timer); 6726 del_timer_sync(&adapter->phy_info_timer); 6727 6728 cancel_work_sync(&adapter->reset_task); 6729 cancel_work_sync(&adapter->watchdog_task); 6730 6731 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6732 * would have already happened in close and is redundant. 6733 */ 6734 igc_release_hw_control(adapter); 6735 unregister_netdev(netdev); 6736 6737 igc_clear_interrupt_scheme(adapter); 6738 pci_iounmap(pdev, adapter->io_addr); 6739 pci_release_mem_regions(pdev); 6740 6741 free_netdev(netdev); 6742 6743 pci_disable_device(pdev); 6744 } 6745 6746 static int __igc_shutdown(struct pci_dev *pdev, bool *enable_wake, 6747 bool runtime) 6748 { 6749 struct net_device *netdev = pci_get_drvdata(pdev); 6750 struct igc_adapter *adapter = netdev_priv(netdev); 6751 u32 wufc = runtime ? IGC_WUFC_LNKC : adapter->wol; 6752 struct igc_hw *hw = &adapter->hw; 6753 u32 ctrl, rctl, status; 6754 bool wake; 6755 6756 rtnl_lock(); 6757 netif_device_detach(netdev); 6758 6759 if (netif_running(netdev)) 6760 __igc_close(netdev, true); 6761 6762 igc_ptp_suspend(adapter); 6763 6764 igc_clear_interrupt_scheme(adapter); 6765 rtnl_unlock(); 6766 6767 status = rd32(IGC_STATUS); 6768 if (status & IGC_STATUS_LU) 6769 wufc &= ~IGC_WUFC_LNKC; 6770 6771 if (wufc) { 6772 igc_setup_rctl(adapter); 6773 igc_set_rx_mode(netdev); 6774 6775 /* turn on all-multi mode if wake on multicast is enabled */ 6776 if (wufc & IGC_WUFC_MC) { 6777 rctl = rd32(IGC_RCTL); 6778 rctl |= IGC_RCTL_MPE; 6779 wr32(IGC_RCTL, rctl); 6780 } 6781 6782 ctrl = rd32(IGC_CTRL); 6783 ctrl |= IGC_CTRL_ADVD3WUC; 6784 wr32(IGC_CTRL, ctrl); 6785 6786 /* Allow time for pending master requests to run */ 6787 igc_disable_pcie_master(hw); 6788 6789 wr32(IGC_WUC, IGC_WUC_PME_EN); 6790 wr32(IGC_WUFC, wufc); 6791 } else { 6792 wr32(IGC_WUC, 0); 6793 wr32(IGC_WUFC, 0); 6794 } 6795 6796 wake = wufc || adapter->en_mng_pt; 6797 if (!wake) 6798 igc_power_down_phy_copper_base(&adapter->hw); 6799 else 6800 igc_power_up_link(adapter); 6801 6802 if (enable_wake) 6803 *enable_wake = wake; 6804 6805 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6806 * would have already happened in close and is redundant. 6807 */ 6808 igc_release_hw_control(adapter); 6809 6810 pci_disable_device(pdev); 6811 6812 return 0; 6813 } 6814 6815 #ifdef CONFIG_PM 6816 static int __maybe_unused igc_runtime_suspend(struct device *dev) 6817 { 6818 return __igc_shutdown(to_pci_dev(dev), NULL, 1); 6819 } 6820 6821 static void igc_deliver_wake_packet(struct net_device *netdev) 6822 { 6823 struct igc_adapter *adapter = netdev_priv(netdev); 6824 struct igc_hw *hw = &adapter->hw; 6825 struct sk_buff *skb; 6826 u32 wupl; 6827 6828 wupl = rd32(IGC_WUPL) & IGC_WUPL_MASK; 6829 6830 /* WUPM stores only the first 128 bytes of the wake packet. 6831 * Read the packet only if we have the whole thing. 6832 */ 6833 if (wupl == 0 || wupl > IGC_WUPM_BYTES) 6834 return; 6835 6836 skb = netdev_alloc_skb_ip_align(netdev, IGC_WUPM_BYTES); 6837 if (!skb) 6838 return; 6839 6840 skb_put(skb, wupl); 6841 6842 /* Ensure reads are 32-bit aligned */ 6843 wupl = roundup(wupl, 4); 6844 6845 memcpy_fromio(skb->data, hw->hw_addr + IGC_WUPM_REG(0), wupl); 6846 6847 skb->protocol = eth_type_trans(skb, netdev); 6848 netif_rx(skb); 6849 } 6850 6851 static int __maybe_unused igc_resume(struct device *dev) 6852 { 6853 struct pci_dev *pdev = to_pci_dev(dev); 6854 struct net_device *netdev = pci_get_drvdata(pdev); 6855 struct igc_adapter *adapter = netdev_priv(netdev); 6856 struct igc_hw *hw = &adapter->hw; 6857 u32 err, val; 6858 6859 pci_set_power_state(pdev, PCI_D0); 6860 pci_restore_state(pdev); 6861 pci_save_state(pdev); 6862 6863 if (!pci_device_is_present(pdev)) 6864 return -ENODEV; 6865 err = pci_enable_device_mem(pdev); 6866 if (err) { 6867 netdev_err(netdev, "Cannot enable PCI device from suspend\n"); 6868 return err; 6869 } 6870 pci_set_master(pdev); 6871 6872 pci_enable_wake(pdev, PCI_D3hot, 0); 6873 pci_enable_wake(pdev, PCI_D3cold, 0); 6874 6875 if (igc_init_interrupt_scheme(adapter, true)) { 6876 netdev_err(netdev, "Unable to allocate memory for queues\n"); 6877 return -ENOMEM; 6878 } 6879 6880 igc_reset(adapter); 6881 6882 /* let the f/w know that the h/w is now under the control of the 6883 * driver. 6884 */ 6885 igc_get_hw_control(adapter); 6886 6887 val = rd32(IGC_WUS); 6888 if (val & WAKE_PKT_WUS) 6889 igc_deliver_wake_packet(netdev); 6890 6891 wr32(IGC_WUS, ~0); 6892 6893 rtnl_lock(); 6894 if (!err && netif_running(netdev)) 6895 err = __igc_open(netdev, true); 6896 6897 if (!err) 6898 netif_device_attach(netdev); 6899 rtnl_unlock(); 6900 6901 return err; 6902 } 6903 6904 static int __maybe_unused igc_runtime_resume(struct device *dev) 6905 { 6906 return igc_resume(dev); 6907 } 6908 6909 static int __maybe_unused igc_suspend(struct device *dev) 6910 { 6911 return __igc_shutdown(to_pci_dev(dev), NULL, 0); 6912 } 6913 6914 static int __maybe_unused igc_runtime_idle(struct device *dev) 6915 { 6916 struct net_device *netdev = dev_get_drvdata(dev); 6917 struct igc_adapter *adapter = netdev_priv(netdev); 6918 6919 if (!igc_has_link(adapter)) 6920 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 6921 6922 return -EBUSY; 6923 } 6924 #endif /* CONFIG_PM */ 6925 6926 static void igc_shutdown(struct pci_dev *pdev) 6927 { 6928 bool wake; 6929 6930 __igc_shutdown(pdev, &wake, 0); 6931 6932 if (system_state == SYSTEM_POWER_OFF) { 6933 pci_wake_from_d3(pdev, wake); 6934 pci_set_power_state(pdev, PCI_D3hot); 6935 } 6936 } 6937 6938 /** 6939 * igc_io_error_detected - called when PCI error is detected 6940 * @pdev: Pointer to PCI device 6941 * @state: The current PCI connection state 6942 * 6943 * This function is called after a PCI bus error affecting 6944 * this device has been detected. 6945 **/ 6946 static pci_ers_result_t igc_io_error_detected(struct pci_dev *pdev, 6947 pci_channel_state_t state) 6948 { 6949 struct net_device *netdev = pci_get_drvdata(pdev); 6950 struct igc_adapter *adapter = netdev_priv(netdev); 6951 6952 netif_device_detach(netdev); 6953 6954 if (state == pci_channel_io_perm_failure) 6955 return PCI_ERS_RESULT_DISCONNECT; 6956 6957 if (netif_running(netdev)) 6958 igc_down(adapter); 6959 pci_disable_device(pdev); 6960 6961 /* Request a slot reset. */ 6962 return PCI_ERS_RESULT_NEED_RESET; 6963 } 6964 6965 /** 6966 * igc_io_slot_reset - called after the PCI bus has been reset. 6967 * @pdev: Pointer to PCI device 6968 * 6969 * Restart the card from scratch, as if from a cold-boot. Implementation 6970 * resembles the first-half of the igc_resume routine. 6971 **/ 6972 static pci_ers_result_t igc_io_slot_reset(struct pci_dev *pdev) 6973 { 6974 struct net_device *netdev = pci_get_drvdata(pdev); 6975 struct igc_adapter *adapter = netdev_priv(netdev); 6976 struct igc_hw *hw = &adapter->hw; 6977 pci_ers_result_t result; 6978 6979 if (pci_enable_device_mem(pdev)) { 6980 netdev_err(netdev, "Could not re-enable PCI device after reset\n"); 6981 result = PCI_ERS_RESULT_DISCONNECT; 6982 } else { 6983 pci_set_master(pdev); 6984 pci_restore_state(pdev); 6985 pci_save_state(pdev); 6986 6987 pci_enable_wake(pdev, PCI_D3hot, 0); 6988 pci_enable_wake(pdev, PCI_D3cold, 0); 6989 6990 /* In case of PCI error, adapter loses its HW address 6991 * so we should re-assign it here. 6992 */ 6993 hw->hw_addr = adapter->io_addr; 6994 6995 igc_reset(adapter); 6996 wr32(IGC_WUS, ~0); 6997 result = PCI_ERS_RESULT_RECOVERED; 6998 } 6999 7000 return result; 7001 } 7002 7003 /** 7004 * igc_io_resume - called when traffic can start to flow again. 7005 * @pdev: Pointer to PCI device 7006 * 7007 * This callback is called when the error recovery driver tells us that 7008 * its OK to resume normal operation. Implementation resembles the 7009 * second-half of the igc_resume routine. 7010 */ 7011 static void igc_io_resume(struct pci_dev *pdev) 7012 { 7013 struct net_device *netdev = pci_get_drvdata(pdev); 7014 struct igc_adapter *adapter = netdev_priv(netdev); 7015 7016 rtnl_lock(); 7017 if (netif_running(netdev)) { 7018 if (igc_open(netdev)) { 7019 netdev_err(netdev, "igc_open failed after reset\n"); 7020 return; 7021 } 7022 } 7023 7024 netif_device_attach(netdev); 7025 7026 /* let the f/w know that the h/w is now under the control of the 7027 * driver. 7028 */ 7029 igc_get_hw_control(adapter); 7030 rtnl_unlock(); 7031 } 7032 7033 static const struct pci_error_handlers igc_err_handler = { 7034 .error_detected = igc_io_error_detected, 7035 .slot_reset = igc_io_slot_reset, 7036 .resume = igc_io_resume, 7037 }; 7038 7039 #ifdef CONFIG_PM 7040 static const struct dev_pm_ops igc_pm_ops = { 7041 SET_SYSTEM_SLEEP_PM_OPS(igc_suspend, igc_resume) 7042 SET_RUNTIME_PM_OPS(igc_runtime_suspend, igc_runtime_resume, 7043 igc_runtime_idle) 7044 }; 7045 #endif 7046 7047 static struct pci_driver igc_driver = { 7048 .name = igc_driver_name, 7049 .id_table = igc_pci_tbl, 7050 .probe = igc_probe, 7051 .remove = igc_remove, 7052 #ifdef CONFIG_PM 7053 .driver.pm = &igc_pm_ops, 7054 #endif 7055 .shutdown = igc_shutdown, 7056 .err_handler = &igc_err_handler, 7057 }; 7058 7059 /** 7060 * igc_reinit_queues - return error 7061 * @adapter: pointer to adapter structure 7062 */ 7063 int igc_reinit_queues(struct igc_adapter *adapter) 7064 { 7065 struct net_device *netdev = adapter->netdev; 7066 int err = 0; 7067 7068 if (netif_running(netdev)) 7069 igc_close(netdev); 7070 7071 igc_reset_interrupt_capability(adapter); 7072 7073 if (igc_init_interrupt_scheme(adapter, true)) { 7074 netdev_err(netdev, "Unable to allocate memory for queues\n"); 7075 return -ENOMEM; 7076 } 7077 7078 if (netif_running(netdev)) 7079 err = igc_open(netdev); 7080 7081 return err; 7082 } 7083 7084 /** 7085 * igc_get_hw_dev - return device 7086 * @hw: pointer to hardware structure 7087 * 7088 * used by hardware layer to print debugging information 7089 */ 7090 struct net_device *igc_get_hw_dev(struct igc_hw *hw) 7091 { 7092 struct igc_adapter *adapter = hw->back; 7093 7094 return adapter->netdev; 7095 } 7096 7097 static void igc_disable_rx_ring_hw(struct igc_ring *ring) 7098 { 7099 struct igc_hw *hw = &ring->q_vector->adapter->hw; 7100 u8 idx = ring->reg_idx; 7101 u32 rxdctl; 7102 7103 rxdctl = rd32(IGC_RXDCTL(idx)); 7104 rxdctl &= ~IGC_RXDCTL_QUEUE_ENABLE; 7105 rxdctl |= IGC_RXDCTL_SWFLUSH; 7106 wr32(IGC_RXDCTL(idx), rxdctl); 7107 } 7108 7109 void igc_disable_rx_ring(struct igc_ring *ring) 7110 { 7111 igc_disable_rx_ring_hw(ring); 7112 igc_clean_rx_ring(ring); 7113 } 7114 7115 void igc_enable_rx_ring(struct igc_ring *ring) 7116 { 7117 struct igc_adapter *adapter = ring->q_vector->adapter; 7118 7119 igc_configure_rx_ring(adapter, ring); 7120 7121 if (ring->xsk_pool) 7122 igc_alloc_rx_buffers_zc(ring, igc_desc_unused(ring)); 7123 else 7124 igc_alloc_rx_buffers(ring, igc_desc_unused(ring)); 7125 } 7126 7127 static void igc_disable_tx_ring_hw(struct igc_ring *ring) 7128 { 7129 struct igc_hw *hw = &ring->q_vector->adapter->hw; 7130 u8 idx = ring->reg_idx; 7131 u32 txdctl; 7132 7133 txdctl = rd32(IGC_TXDCTL(idx)); 7134 txdctl &= ~IGC_TXDCTL_QUEUE_ENABLE; 7135 txdctl |= IGC_TXDCTL_SWFLUSH; 7136 wr32(IGC_TXDCTL(idx), txdctl); 7137 } 7138 7139 void igc_disable_tx_ring(struct igc_ring *ring) 7140 { 7141 igc_disable_tx_ring_hw(ring); 7142 igc_clean_tx_ring(ring); 7143 } 7144 7145 void igc_enable_tx_ring(struct igc_ring *ring) 7146 { 7147 struct igc_adapter *adapter = ring->q_vector->adapter; 7148 7149 igc_configure_tx_ring(adapter, ring); 7150 } 7151 7152 /** 7153 * igc_init_module - Driver Registration Routine 7154 * 7155 * igc_init_module is the first routine called when the driver is 7156 * loaded. All it does is register with the PCI subsystem. 7157 */ 7158 static int __init igc_init_module(void) 7159 { 7160 int ret; 7161 7162 pr_info("%s\n", igc_driver_string); 7163 pr_info("%s\n", igc_copyright); 7164 7165 ret = pci_register_driver(&igc_driver); 7166 return ret; 7167 } 7168 7169 module_init(igc_init_module); 7170 7171 /** 7172 * igc_exit_module - Driver Exit Cleanup Routine 7173 * 7174 * igc_exit_module is called just before the driver is removed 7175 * from memory. 7176 */ 7177 static void __exit igc_exit_module(void) 7178 { 7179 pci_unregister_driver(&igc_driver); 7180 } 7181 7182 module_exit(igc_exit_module); 7183 /* igc_main.c */ 7184