1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #include <linux/module.h> 5 #include <linux/types.h> 6 #include <linux/if_vlan.h> 7 #include <linux/aer.h> 8 9 #include "igc.h" 10 #include "igc_hw.h" 11 12 #define DRV_VERSION "0.0.1-k" 13 #define DRV_SUMMARY "Intel(R) 2.5G Ethernet Linux Driver" 14 15 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 16 17 static int debug = -1; 18 19 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 20 MODULE_DESCRIPTION(DRV_SUMMARY); 21 MODULE_LICENSE("GPL v2"); 22 MODULE_VERSION(DRV_VERSION); 23 module_param(debug, int, 0); 24 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 25 26 char igc_driver_name[] = "igc"; 27 char igc_driver_version[] = DRV_VERSION; 28 static const char igc_driver_string[] = DRV_SUMMARY; 29 static const char igc_copyright[] = 30 "Copyright(c) 2018 Intel Corporation."; 31 32 static const struct igc_info *igc_info_tbl[] = { 33 [board_base] = &igc_base_info, 34 }; 35 36 static const struct pci_device_id igc_pci_tbl[] = { 37 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LM), board_base }, 38 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_V), board_base }, 39 /* required last entry */ 40 {0, } 41 }; 42 43 MODULE_DEVICE_TABLE(pci, igc_pci_tbl); 44 45 /* forward declaration */ 46 static void igc_clean_tx_ring(struct igc_ring *tx_ring); 47 static int igc_sw_init(struct igc_adapter *); 48 static void igc_configure(struct igc_adapter *adapter); 49 static void igc_power_down_link(struct igc_adapter *adapter); 50 static void igc_set_default_mac_filter(struct igc_adapter *adapter); 51 static void igc_set_rx_mode(struct net_device *netdev); 52 static void igc_write_itr(struct igc_q_vector *q_vector); 53 static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector); 54 static void igc_free_q_vector(struct igc_adapter *adapter, int v_idx); 55 static void igc_set_interrupt_capability(struct igc_adapter *adapter, 56 bool msix); 57 static void igc_free_q_vectors(struct igc_adapter *adapter); 58 static void igc_irq_disable(struct igc_adapter *adapter); 59 static void igc_irq_enable(struct igc_adapter *adapter); 60 static void igc_configure_msix(struct igc_adapter *adapter); 61 static bool igc_alloc_mapped_page(struct igc_ring *rx_ring, 62 struct igc_rx_buffer *bi); 63 64 enum latency_range { 65 lowest_latency = 0, 66 low_latency = 1, 67 bulk_latency = 2, 68 latency_invalid = 255 69 }; 70 71 void igc_reset(struct igc_adapter *adapter) 72 { 73 struct pci_dev *pdev = adapter->pdev; 74 struct igc_hw *hw = &adapter->hw; 75 76 hw->mac.ops.reset_hw(hw); 77 78 if (hw->mac.ops.init_hw(hw)) 79 dev_err(&pdev->dev, "Hardware Error\n"); 80 81 if (!netif_running(adapter->netdev)) 82 igc_power_down_link(adapter); 83 84 igc_get_phy_info(hw); 85 } 86 87 /** 88 * igc_power_up_link - Power up the phy/serdes link 89 * @adapter: address of board private structure 90 */ 91 static void igc_power_up_link(struct igc_adapter *adapter) 92 { 93 igc_reset_phy(&adapter->hw); 94 95 if (adapter->hw.phy.media_type == igc_media_type_copper) 96 igc_power_up_phy_copper(&adapter->hw); 97 98 igc_setup_link(&adapter->hw); 99 } 100 101 /** 102 * igc_power_down_link - Power down the phy/serdes link 103 * @adapter: address of board private structure 104 */ 105 static void igc_power_down_link(struct igc_adapter *adapter) 106 { 107 if (adapter->hw.phy.media_type == igc_media_type_copper) 108 igc_power_down_phy_copper_base(&adapter->hw); 109 } 110 111 /** 112 * igc_release_hw_control - release control of the h/w to f/w 113 * @adapter: address of board private structure 114 * 115 * igc_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 116 * For ASF and Pass Through versions of f/w this means that the 117 * driver is no longer loaded. 118 */ 119 static void igc_release_hw_control(struct igc_adapter *adapter) 120 { 121 struct igc_hw *hw = &adapter->hw; 122 u32 ctrl_ext; 123 124 /* Let firmware take over control of h/w */ 125 ctrl_ext = rd32(IGC_CTRL_EXT); 126 wr32(IGC_CTRL_EXT, 127 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD); 128 } 129 130 /** 131 * igc_get_hw_control - get control of the h/w from f/w 132 * @adapter: address of board private structure 133 * 134 * igc_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 135 * For ASF and Pass Through versions of f/w this means that 136 * the driver is loaded. 137 */ 138 static void igc_get_hw_control(struct igc_adapter *adapter) 139 { 140 struct igc_hw *hw = &adapter->hw; 141 u32 ctrl_ext; 142 143 /* Let firmware know the driver has taken over */ 144 ctrl_ext = rd32(IGC_CTRL_EXT); 145 wr32(IGC_CTRL_EXT, 146 ctrl_ext | IGC_CTRL_EXT_DRV_LOAD); 147 } 148 149 /** 150 * igc_free_tx_resources - Free Tx Resources per Queue 151 * @tx_ring: Tx descriptor ring for a specific queue 152 * 153 * Free all transmit software resources 154 */ 155 void igc_free_tx_resources(struct igc_ring *tx_ring) 156 { 157 igc_clean_tx_ring(tx_ring); 158 159 vfree(tx_ring->tx_buffer_info); 160 tx_ring->tx_buffer_info = NULL; 161 162 /* if not set, then don't free */ 163 if (!tx_ring->desc) 164 return; 165 166 dma_free_coherent(tx_ring->dev, tx_ring->size, 167 tx_ring->desc, tx_ring->dma); 168 169 tx_ring->desc = NULL; 170 } 171 172 /** 173 * igc_free_all_tx_resources - Free Tx Resources for All Queues 174 * @adapter: board private structure 175 * 176 * Free all transmit software resources 177 */ 178 static void igc_free_all_tx_resources(struct igc_adapter *adapter) 179 { 180 int i; 181 182 for (i = 0; i < adapter->num_tx_queues; i++) 183 igc_free_tx_resources(adapter->tx_ring[i]); 184 } 185 186 /** 187 * igc_clean_tx_ring - Free Tx Buffers 188 * @tx_ring: ring to be cleaned 189 */ 190 static void igc_clean_tx_ring(struct igc_ring *tx_ring) 191 { 192 u16 i = tx_ring->next_to_clean; 193 struct igc_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 194 195 while (i != tx_ring->next_to_use) { 196 union igc_adv_tx_desc *eop_desc, *tx_desc; 197 198 /* Free all the Tx ring sk_buffs */ 199 dev_kfree_skb_any(tx_buffer->skb); 200 201 /* unmap skb header data */ 202 dma_unmap_single(tx_ring->dev, 203 dma_unmap_addr(tx_buffer, dma), 204 dma_unmap_len(tx_buffer, len), 205 DMA_TO_DEVICE); 206 207 /* check for eop_desc to determine the end of the packet */ 208 eop_desc = tx_buffer->next_to_watch; 209 tx_desc = IGC_TX_DESC(tx_ring, i); 210 211 /* unmap remaining buffers */ 212 while (tx_desc != eop_desc) { 213 tx_buffer++; 214 tx_desc++; 215 i++; 216 if (unlikely(i == tx_ring->count)) { 217 i = 0; 218 tx_buffer = tx_ring->tx_buffer_info; 219 tx_desc = IGC_TX_DESC(tx_ring, 0); 220 } 221 222 /* unmap any remaining paged data */ 223 if (dma_unmap_len(tx_buffer, len)) 224 dma_unmap_page(tx_ring->dev, 225 dma_unmap_addr(tx_buffer, dma), 226 dma_unmap_len(tx_buffer, len), 227 DMA_TO_DEVICE); 228 } 229 230 /* move us one more past the eop_desc for start of next pkt */ 231 tx_buffer++; 232 i++; 233 if (unlikely(i == tx_ring->count)) { 234 i = 0; 235 tx_buffer = tx_ring->tx_buffer_info; 236 } 237 } 238 239 /* reset BQL for queue */ 240 netdev_tx_reset_queue(txring_txq(tx_ring)); 241 242 /* reset next_to_use and next_to_clean */ 243 tx_ring->next_to_use = 0; 244 tx_ring->next_to_clean = 0; 245 } 246 247 /** 248 * igc_clean_all_tx_rings - Free Tx Buffers for all queues 249 * @adapter: board private structure 250 */ 251 static void igc_clean_all_tx_rings(struct igc_adapter *adapter) 252 { 253 int i; 254 255 for (i = 0; i < adapter->num_tx_queues; i++) 256 if (adapter->tx_ring[i]) 257 igc_clean_tx_ring(adapter->tx_ring[i]); 258 } 259 260 /** 261 * igc_setup_tx_resources - allocate Tx resources (Descriptors) 262 * @tx_ring: tx descriptor ring (for a specific queue) to setup 263 * 264 * Return 0 on success, negative on failure 265 */ 266 int igc_setup_tx_resources(struct igc_ring *tx_ring) 267 { 268 struct device *dev = tx_ring->dev; 269 int size = 0; 270 271 size = sizeof(struct igc_tx_buffer) * tx_ring->count; 272 tx_ring->tx_buffer_info = vzalloc(size); 273 if (!tx_ring->tx_buffer_info) 274 goto err; 275 276 /* round up to nearest 4K */ 277 tx_ring->size = tx_ring->count * sizeof(union igc_adv_tx_desc); 278 tx_ring->size = ALIGN(tx_ring->size, 4096); 279 280 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 281 &tx_ring->dma, GFP_KERNEL); 282 283 if (!tx_ring->desc) 284 goto err; 285 286 tx_ring->next_to_use = 0; 287 tx_ring->next_to_clean = 0; 288 289 return 0; 290 291 err: 292 vfree(tx_ring->tx_buffer_info); 293 dev_err(dev, 294 "Unable to allocate memory for the transmit descriptor ring\n"); 295 return -ENOMEM; 296 } 297 298 /** 299 * igc_setup_all_tx_resources - wrapper to allocate Tx resources for all queues 300 * @adapter: board private structure 301 * 302 * Return 0 on success, negative on failure 303 */ 304 static int igc_setup_all_tx_resources(struct igc_adapter *adapter) 305 { 306 struct pci_dev *pdev = adapter->pdev; 307 int i, err = 0; 308 309 for (i = 0; i < adapter->num_tx_queues; i++) { 310 err = igc_setup_tx_resources(adapter->tx_ring[i]); 311 if (err) { 312 dev_err(&pdev->dev, 313 "Allocation for Tx Queue %u failed\n", i); 314 for (i--; i >= 0; i--) 315 igc_free_tx_resources(adapter->tx_ring[i]); 316 break; 317 } 318 } 319 320 return err; 321 } 322 323 /** 324 * igc_clean_rx_ring - Free Rx Buffers per Queue 325 * @rx_ring: ring to free buffers from 326 */ 327 static void igc_clean_rx_ring(struct igc_ring *rx_ring) 328 { 329 u16 i = rx_ring->next_to_clean; 330 331 if (rx_ring->skb) 332 dev_kfree_skb(rx_ring->skb); 333 rx_ring->skb = NULL; 334 335 /* Free all the Rx ring sk_buffs */ 336 while (i != rx_ring->next_to_alloc) { 337 struct igc_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 338 339 /* Invalidate cache lines that may have been written to by 340 * device so that we avoid corrupting memory. 341 */ 342 dma_sync_single_range_for_cpu(rx_ring->dev, 343 buffer_info->dma, 344 buffer_info->page_offset, 345 igc_rx_bufsz(rx_ring), 346 DMA_FROM_DEVICE); 347 348 /* free resources associated with mapping */ 349 dma_unmap_page_attrs(rx_ring->dev, 350 buffer_info->dma, 351 igc_rx_pg_size(rx_ring), 352 DMA_FROM_DEVICE, 353 IGC_RX_DMA_ATTR); 354 __page_frag_cache_drain(buffer_info->page, 355 buffer_info->pagecnt_bias); 356 357 i++; 358 if (i == rx_ring->count) 359 i = 0; 360 } 361 362 rx_ring->next_to_alloc = 0; 363 rx_ring->next_to_clean = 0; 364 rx_ring->next_to_use = 0; 365 } 366 367 /** 368 * igc_clean_all_rx_rings - Free Rx Buffers for all queues 369 * @adapter: board private structure 370 */ 371 static void igc_clean_all_rx_rings(struct igc_adapter *adapter) 372 { 373 int i; 374 375 for (i = 0; i < adapter->num_rx_queues; i++) 376 if (adapter->rx_ring[i]) 377 igc_clean_rx_ring(adapter->rx_ring[i]); 378 } 379 380 /** 381 * igc_free_rx_resources - Free Rx Resources 382 * @rx_ring: ring to clean the resources from 383 * 384 * Free all receive software resources 385 */ 386 void igc_free_rx_resources(struct igc_ring *rx_ring) 387 { 388 igc_clean_rx_ring(rx_ring); 389 390 vfree(rx_ring->rx_buffer_info); 391 rx_ring->rx_buffer_info = NULL; 392 393 /* if not set, then don't free */ 394 if (!rx_ring->desc) 395 return; 396 397 dma_free_coherent(rx_ring->dev, rx_ring->size, 398 rx_ring->desc, rx_ring->dma); 399 400 rx_ring->desc = NULL; 401 } 402 403 /** 404 * igc_free_all_rx_resources - Free Rx Resources for All Queues 405 * @adapter: board private structure 406 * 407 * Free all receive software resources 408 */ 409 static void igc_free_all_rx_resources(struct igc_adapter *adapter) 410 { 411 int i; 412 413 for (i = 0; i < adapter->num_rx_queues; i++) 414 igc_free_rx_resources(adapter->rx_ring[i]); 415 } 416 417 /** 418 * igc_setup_rx_resources - allocate Rx resources (Descriptors) 419 * @rx_ring: rx descriptor ring (for a specific queue) to setup 420 * 421 * Returns 0 on success, negative on failure 422 */ 423 int igc_setup_rx_resources(struct igc_ring *rx_ring) 424 { 425 struct device *dev = rx_ring->dev; 426 int size, desc_len; 427 428 size = sizeof(struct igc_rx_buffer) * rx_ring->count; 429 rx_ring->rx_buffer_info = vzalloc(size); 430 if (!rx_ring->rx_buffer_info) 431 goto err; 432 433 desc_len = sizeof(union igc_adv_rx_desc); 434 435 /* Round up to nearest 4K */ 436 rx_ring->size = rx_ring->count * desc_len; 437 rx_ring->size = ALIGN(rx_ring->size, 4096); 438 439 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 440 &rx_ring->dma, GFP_KERNEL); 441 442 if (!rx_ring->desc) 443 goto err; 444 445 rx_ring->next_to_alloc = 0; 446 rx_ring->next_to_clean = 0; 447 rx_ring->next_to_use = 0; 448 449 return 0; 450 451 err: 452 vfree(rx_ring->rx_buffer_info); 453 rx_ring->rx_buffer_info = NULL; 454 dev_err(dev, 455 "Unable to allocate memory for the receive descriptor ring\n"); 456 return -ENOMEM; 457 } 458 459 /** 460 * igc_setup_all_rx_resources - wrapper to allocate Rx resources 461 * (Descriptors) for all queues 462 * @adapter: board private structure 463 * 464 * Return 0 on success, negative on failure 465 */ 466 static int igc_setup_all_rx_resources(struct igc_adapter *adapter) 467 { 468 struct pci_dev *pdev = adapter->pdev; 469 int i, err = 0; 470 471 for (i = 0; i < adapter->num_rx_queues; i++) { 472 err = igc_setup_rx_resources(adapter->rx_ring[i]); 473 if (err) { 474 dev_err(&pdev->dev, 475 "Allocation for Rx Queue %u failed\n", i); 476 for (i--; i >= 0; i--) 477 igc_free_rx_resources(adapter->rx_ring[i]); 478 break; 479 } 480 } 481 482 return err; 483 } 484 485 /** 486 * igc_configure_rx_ring - Configure a receive ring after Reset 487 * @adapter: board private structure 488 * @ring: receive ring to be configured 489 * 490 * Configure the Rx unit of the MAC after a reset. 491 */ 492 static void igc_configure_rx_ring(struct igc_adapter *adapter, 493 struct igc_ring *ring) 494 { 495 struct igc_hw *hw = &adapter->hw; 496 union igc_adv_rx_desc *rx_desc; 497 int reg_idx = ring->reg_idx; 498 u32 srrctl = 0, rxdctl = 0; 499 u64 rdba = ring->dma; 500 501 /* disable the queue */ 502 wr32(IGC_RXDCTL(reg_idx), 0); 503 504 /* Set DMA base address registers */ 505 wr32(IGC_RDBAL(reg_idx), 506 rdba & 0x00000000ffffffffULL); 507 wr32(IGC_RDBAH(reg_idx), rdba >> 32); 508 wr32(IGC_RDLEN(reg_idx), 509 ring->count * sizeof(union igc_adv_rx_desc)); 510 511 /* initialize head and tail */ 512 ring->tail = adapter->io_addr + IGC_RDT(reg_idx); 513 wr32(IGC_RDH(reg_idx), 0); 514 writel(0, ring->tail); 515 516 /* reset next-to- use/clean to place SW in sync with hardware */ 517 ring->next_to_clean = 0; 518 ring->next_to_use = 0; 519 520 /* set descriptor configuration */ 521 srrctl = IGC_RX_HDR_LEN << IGC_SRRCTL_BSIZEHDRSIZE_SHIFT; 522 if (ring_uses_large_buffer(ring)) 523 srrctl |= IGC_RXBUFFER_3072 >> IGC_SRRCTL_BSIZEPKT_SHIFT; 524 else 525 srrctl |= IGC_RXBUFFER_2048 >> IGC_SRRCTL_BSIZEPKT_SHIFT; 526 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF; 527 528 wr32(IGC_SRRCTL(reg_idx), srrctl); 529 530 rxdctl |= IGC_RX_PTHRESH; 531 rxdctl |= IGC_RX_HTHRESH << 8; 532 rxdctl |= IGC_RX_WTHRESH << 16; 533 534 /* initialize rx_buffer_info */ 535 memset(ring->rx_buffer_info, 0, 536 sizeof(struct igc_rx_buffer) * ring->count); 537 538 /* initialize Rx descriptor 0 */ 539 rx_desc = IGC_RX_DESC(ring, 0); 540 rx_desc->wb.upper.length = 0; 541 542 /* enable receive descriptor fetching */ 543 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE; 544 545 wr32(IGC_RXDCTL(reg_idx), rxdctl); 546 } 547 548 /** 549 * igc_configure_rx - Configure receive Unit after Reset 550 * @adapter: board private structure 551 * 552 * Configure the Rx unit of the MAC after a reset. 553 */ 554 static void igc_configure_rx(struct igc_adapter *adapter) 555 { 556 int i; 557 558 /* Setup the HW Rx Head and Tail Descriptor Pointers and 559 * the Base and Length of the Rx Descriptor Ring 560 */ 561 for (i = 0; i < adapter->num_rx_queues; i++) 562 igc_configure_rx_ring(adapter, adapter->rx_ring[i]); 563 } 564 565 /** 566 * igc_configure_tx_ring - Configure transmit ring after Reset 567 * @adapter: board private structure 568 * @ring: tx ring to configure 569 * 570 * Configure a transmit ring after a reset. 571 */ 572 static void igc_configure_tx_ring(struct igc_adapter *adapter, 573 struct igc_ring *ring) 574 { 575 struct igc_hw *hw = &adapter->hw; 576 int reg_idx = ring->reg_idx; 577 u64 tdba = ring->dma; 578 u32 txdctl = 0; 579 580 /* disable the queue */ 581 wr32(IGC_TXDCTL(reg_idx), 0); 582 wrfl(); 583 mdelay(10); 584 585 wr32(IGC_TDLEN(reg_idx), 586 ring->count * sizeof(union igc_adv_tx_desc)); 587 wr32(IGC_TDBAL(reg_idx), 588 tdba & 0x00000000ffffffffULL); 589 wr32(IGC_TDBAH(reg_idx), tdba >> 32); 590 591 ring->tail = adapter->io_addr + IGC_TDT(reg_idx); 592 wr32(IGC_TDH(reg_idx), 0); 593 writel(0, ring->tail); 594 595 txdctl |= IGC_TX_PTHRESH; 596 txdctl |= IGC_TX_HTHRESH << 8; 597 txdctl |= IGC_TX_WTHRESH << 16; 598 599 txdctl |= IGC_TXDCTL_QUEUE_ENABLE; 600 wr32(IGC_TXDCTL(reg_idx), txdctl); 601 } 602 603 /** 604 * igc_configure_tx - Configure transmit Unit after Reset 605 * @adapter: board private structure 606 * 607 * Configure the Tx unit of the MAC after a reset. 608 */ 609 static void igc_configure_tx(struct igc_adapter *adapter) 610 { 611 int i; 612 613 for (i = 0; i < adapter->num_tx_queues; i++) 614 igc_configure_tx_ring(adapter, adapter->tx_ring[i]); 615 } 616 617 /** 618 * igc_setup_mrqc - configure the multiple receive queue control registers 619 * @adapter: Board private structure 620 */ 621 static void igc_setup_mrqc(struct igc_adapter *adapter) 622 { 623 struct igc_hw *hw = &adapter->hw; 624 u32 j, num_rx_queues; 625 u32 mrqc, rxcsum; 626 u32 rss_key[10]; 627 628 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 629 for (j = 0; j < 10; j++) 630 wr32(IGC_RSSRK(j), rss_key[j]); 631 632 num_rx_queues = adapter->rss_queues; 633 634 if (adapter->rss_indir_tbl_init != num_rx_queues) { 635 for (j = 0; j < IGC_RETA_SIZE; j++) 636 adapter->rss_indir_tbl[j] = 637 (j * num_rx_queues) / IGC_RETA_SIZE; 638 adapter->rss_indir_tbl_init = num_rx_queues; 639 } 640 igc_write_rss_indir_tbl(adapter); 641 642 /* Disable raw packet checksumming so that RSS hash is placed in 643 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 644 * offloads as they are enabled by default 645 */ 646 rxcsum = rd32(IGC_RXCSUM); 647 rxcsum |= IGC_RXCSUM_PCSD; 648 649 /* Enable Receive Checksum Offload for SCTP */ 650 rxcsum |= IGC_RXCSUM_CRCOFL; 651 652 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 653 wr32(IGC_RXCSUM, rxcsum); 654 655 /* Generate RSS hash based on packet types, TCP/UDP 656 * port numbers and/or IPv4/v6 src and dst addresses 657 */ 658 mrqc = IGC_MRQC_RSS_FIELD_IPV4 | 659 IGC_MRQC_RSS_FIELD_IPV4_TCP | 660 IGC_MRQC_RSS_FIELD_IPV6 | 661 IGC_MRQC_RSS_FIELD_IPV6_TCP | 662 IGC_MRQC_RSS_FIELD_IPV6_TCP_EX; 663 664 if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV4_UDP) 665 mrqc |= IGC_MRQC_RSS_FIELD_IPV4_UDP; 666 if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV6_UDP) 667 mrqc |= IGC_MRQC_RSS_FIELD_IPV6_UDP; 668 669 mrqc |= IGC_MRQC_ENABLE_RSS_MQ; 670 671 wr32(IGC_MRQC, mrqc); 672 } 673 674 /** 675 * igc_setup_rctl - configure the receive control registers 676 * @adapter: Board private structure 677 */ 678 static void igc_setup_rctl(struct igc_adapter *adapter) 679 { 680 struct igc_hw *hw = &adapter->hw; 681 u32 rctl; 682 683 rctl = rd32(IGC_RCTL); 684 685 rctl &= ~(3 << IGC_RCTL_MO_SHIFT); 686 rctl &= ~(IGC_RCTL_LBM_TCVR | IGC_RCTL_LBM_MAC); 687 688 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | IGC_RCTL_RDMTS_HALF | 689 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT); 690 691 /* enable stripping of CRC. Newer features require 692 * that the HW strips the CRC. 693 */ 694 rctl |= IGC_RCTL_SECRC; 695 696 /* disable store bad packets and clear size bits. */ 697 rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_SZ_256); 698 699 /* enable LPE to allow for reception of jumbo frames */ 700 rctl |= IGC_RCTL_LPE; 701 702 /* disable queue 0 to prevent tail write w/o re-config */ 703 wr32(IGC_RXDCTL(0), 0); 704 705 /* This is useful for sniffing bad packets. */ 706 if (adapter->netdev->features & NETIF_F_RXALL) { 707 /* UPE and MPE will be handled by normal PROMISC logic 708 * in set_rx_mode 709 */ 710 rctl |= (IGC_RCTL_SBP | /* Receive bad packets */ 711 IGC_RCTL_BAM | /* RX All Bcast Pkts */ 712 IGC_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 713 714 rctl &= ~(IGC_RCTL_DPF | /* Allow filtered pause */ 715 IGC_RCTL_CFIEN); /* Disable VLAN CFIEN Filter */ 716 } 717 718 wr32(IGC_RCTL, rctl); 719 } 720 721 /** 722 * igc_setup_tctl - configure the transmit control registers 723 * @adapter: Board private structure 724 */ 725 static void igc_setup_tctl(struct igc_adapter *adapter) 726 { 727 struct igc_hw *hw = &adapter->hw; 728 u32 tctl; 729 730 /* disable queue 0 which icould be enabled by default */ 731 wr32(IGC_TXDCTL(0), 0); 732 733 /* Program the Transmit Control Register */ 734 tctl = rd32(IGC_TCTL); 735 tctl &= ~IGC_TCTL_CT; 736 tctl |= IGC_TCTL_PSP | IGC_TCTL_RTLC | 737 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT); 738 739 /* Enable transmits */ 740 tctl |= IGC_TCTL_EN; 741 742 wr32(IGC_TCTL, tctl); 743 } 744 745 /** 746 * igc_set_mac - Change the Ethernet Address of the NIC 747 * @netdev: network interface device structure 748 * @p: pointer to an address structure 749 * 750 * Returns 0 on success, negative on failure 751 */ 752 static int igc_set_mac(struct net_device *netdev, void *p) 753 { 754 struct igc_adapter *adapter = netdev_priv(netdev); 755 struct igc_hw *hw = &adapter->hw; 756 struct sockaddr *addr = p; 757 758 if (!is_valid_ether_addr(addr->sa_data)) 759 return -EADDRNOTAVAIL; 760 761 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 762 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 763 764 /* set the correct pool for the new PF MAC address in entry 0 */ 765 igc_set_default_mac_filter(adapter); 766 767 return 0; 768 } 769 770 static void igc_tx_csum(struct igc_ring *tx_ring, struct igc_tx_buffer *first) 771 { 772 } 773 774 static int __igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size) 775 { 776 struct net_device *netdev = tx_ring->netdev; 777 778 netif_stop_subqueue(netdev, tx_ring->queue_index); 779 780 /* memory barriier comment */ 781 smp_mb(); 782 783 /* We need to check again in a case another CPU has just 784 * made room available. 785 */ 786 if (igc_desc_unused(tx_ring) < size) 787 return -EBUSY; 788 789 /* A reprieve! */ 790 netif_wake_subqueue(netdev, tx_ring->queue_index); 791 792 u64_stats_update_begin(&tx_ring->tx_syncp2); 793 tx_ring->tx_stats.restart_queue2++; 794 u64_stats_update_end(&tx_ring->tx_syncp2); 795 796 return 0; 797 } 798 799 static inline int igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size) 800 { 801 if (igc_desc_unused(tx_ring) >= size) 802 return 0; 803 return __igc_maybe_stop_tx(tx_ring, size); 804 } 805 806 static u32 igc_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 807 { 808 /* set type for advanced descriptor with frame checksum insertion */ 809 u32 cmd_type = IGC_ADVTXD_DTYP_DATA | 810 IGC_ADVTXD_DCMD_DEXT | 811 IGC_ADVTXD_DCMD_IFCS; 812 813 return cmd_type; 814 } 815 816 static void igc_tx_olinfo_status(struct igc_ring *tx_ring, 817 union igc_adv_tx_desc *tx_desc, 818 u32 tx_flags, unsigned int paylen) 819 { 820 u32 olinfo_status = paylen << IGC_ADVTXD_PAYLEN_SHIFT; 821 822 /* insert L4 checksum */ 823 olinfo_status |= (tx_flags & IGC_TX_FLAGS_CSUM) * 824 ((IGC_TXD_POPTS_TXSM << 8) / 825 IGC_TX_FLAGS_CSUM); 826 827 /* insert IPv4 checksum */ 828 olinfo_status |= (tx_flags & IGC_TX_FLAGS_IPV4) * 829 (((IGC_TXD_POPTS_IXSM << 8)) / 830 IGC_TX_FLAGS_IPV4); 831 832 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 833 } 834 835 static int igc_tx_map(struct igc_ring *tx_ring, 836 struct igc_tx_buffer *first, 837 const u8 hdr_len) 838 { 839 struct sk_buff *skb = first->skb; 840 struct igc_tx_buffer *tx_buffer; 841 union igc_adv_tx_desc *tx_desc; 842 u32 tx_flags = first->tx_flags; 843 struct skb_frag_struct *frag; 844 u16 i = tx_ring->next_to_use; 845 unsigned int data_len, size; 846 dma_addr_t dma; 847 u32 cmd_type = igc_tx_cmd_type(skb, tx_flags); 848 849 tx_desc = IGC_TX_DESC(tx_ring, i); 850 851 igc_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 852 853 size = skb_headlen(skb); 854 data_len = skb->data_len; 855 856 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 857 858 tx_buffer = first; 859 860 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 861 if (dma_mapping_error(tx_ring->dev, dma)) 862 goto dma_error; 863 864 /* record length, and DMA address */ 865 dma_unmap_len_set(tx_buffer, len, size); 866 dma_unmap_addr_set(tx_buffer, dma, dma); 867 868 tx_desc->read.buffer_addr = cpu_to_le64(dma); 869 870 while (unlikely(size > IGC_MAX_DATA_PER_TXD)) { 871 tx_desc->read.cmd_type_len = 872 cpu_to_le32(cmd_type ^ IGC_MAX_DATA_PER_TXD); 873 874 i++; 875 tx_desc++; 876 if (i == tx_ring->count) { 877 tx_desc = IGC_TX_DESC(tx_ring, 0); 878 i = 0; 879 } 880 tx_desc->read.olinfo_status = 0; 881 882 dma += IGC_MAX_DATA_PER_TXD; 883 size -= IGC_MAX_DATA_PER_TXD; 884 885 tx_desc->read.buffer_addr = cpu_to_le64(dma); 886 } 887 888 if (likely(!data_len)) 889 break; 890 891 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 892 893 i++; 894 tx_desc++; 895 if (i == tx_ring->count) { 896 tx_desc = IGC_TX_DESC(tx_ring, 0); 897 i = 0; 898 } 899 tx_desc->read.olinfo_status = 0; 900 901 size = skb_frag_size(frag); 902 data_len -= size; 903 904 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 905 size, DMA_TO_DEVICE); 906 907 tx_buffer = &tx_ring->tx_buffer_info[i]; 908 } 909 910 /* write last descriptor with RS and EOP bits */ 911 cmd_type |= size | IGC_TXD_DCMD; 912 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 913 914 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 915 916 /* set the timestamp */ 917 first->time_stamp = jiffies; 918 919 skb_tx_timestamp(skb); 920 921 /* Force memory writes to complete before letting h/w know there 922 * are new descriptors to fetch. (Only applicable for weak-ordered 923 * memory model archs, such as IA-64). 924 * 925 * We also need this memory barrier to make certain all of the 926 * status bits have been updated before next_to_watch is written. 927 */ 928 wmb(); 929 930 /* set next_to_watch value indicating a packet is present */ 931 first->next_to_watch = tx_desc; 932 933 i++; 934 if (i == tx_ring->count) 935 i = 0; 936 937 tx_ring->next_to_use = i; 938 939 /* Make sure there is space in the ring for the next send. */ 940 igc_maybe_stop_tx(tx_ring, DESC_NEEDED); 941 942 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 943 writel(i, tx_ring->tail); 944 } 945 946 return 0; 947 dma_error: 948 dev_err(tx_ring->dev, "TX DMA map failed\n"); 949 tx_buffer = &tx_ring->tx_buffer_info[i]; 950 951 /* clear dma mappings for failed tx_buffer_info map */ 952 while (tx_buffer != first) { 953 if (dma_unmap_len(tx_buffer, len)) 954 dma_unmap_page(tx_ring->dev, 955 dma_unmap_addr(tx_buffer, dma), 956 dma_unmap_len(tx_buffer, len), 957 DMA_TO_DEVICE); 958 dma_unmap_len_set(tx_buffer, len, 0); 959 960 if (i-- == 0) 961 i += tx_ring->count; 962 tx_buffer = &tx_ring->tx_buffer_info[i]; 963 } 964 965 if (dma_unmap_len(tx_buffer, len)) 966 dma_unmap_single(tx_ring->dev, 967 dma_unmap_addr(tx_buffer, dma), 968 dma_unmap_len(tx_buffer, len), 969 DMA_TO_DEVICE); 970 dma_unmap_len_set(tx_buffer, len, 0); 971 972 dev_kfree_skb_any(tx_buffer->skb); 973 tx_buffer->skb = NULL; 974 975 tx_ring->next_to_use = i; 976 977 return -1; 978 } 979 980 static netdev_tx_t igc_xmit_frame_ring(struct sk_buff *skb, 981 struct igc_ring *tx_ring) 982 { 983 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 984 __be16 protocol = vlan_get_protocol(skb); 985 struct igc_tx_buffer *first; 986 u32 tx_flags = 0; 987 unsigned short f; 988 u8 hdr_len = 0; 989 990 /* need: 1 descriptor per page * PAGE_SIZE/IGC_MAX_DATA_PER_TXD, 991 * + 1 desc for skb_headlen/IGC_MAX_DATA_PER_TXD, 992 * + 2 desc gap to keep tail from touching head, 993 * + 1 desc for context descriptor, 994 * otherwise try next time 995 */ 996 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 997 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 998 999 if (igc_maybe_stop_tx(tx_ring, count + 3)) { 1000 /* this is a hard error */ 1001 return NETDEV_TX_BUSY; 1002 } 1003 1004 /* record the location of the first descriptor for this packet */ 1005 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 1006 first->skb = skb; 1007 first->bytecount = skb->len; 1008 first->gso_segs = 1; 1009 1010 /* record initial flags and protocol */ 1011 first->tx_flags = tx_flags; 1012 first->protocol = protocol; 1013 1014 igc_tx_csum(tx_ring, first); 1015 1016 igc_tx_map(tx_ring, first, hdr_len); 1017 1018 return NETDEV_TX_OK; 1019 } 1020 1021 static inline struct igc_ring *igc_tx_queue_mapping(struct igc_adapter *adapter, 1022 struct sk_buff *skb) 1023 { 1024 unsigned int r_idx = skb->queue_mapping; 1025 1026 if (r_idx >= adapter->num_tx_queues) 1027 r_idx = r_idx % adapter->num_tx_queues; 1028 1029 return adapter->tx_ring[r_idx]; 1030 } 1031 1032 static netdev_tx_t igc_xmit_frame(struct sk_buff *skb, 1033 struct net_device *netdev) 1034 { 1035 struct igc_adapter *adapter = netdev_priv(netdev); 1036 1037 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 1038 * in order to meet this minimum size requirement. 1039 */ 1040 if (skb->len < 17) { 1041 if (skb_padto(skb, 17)) 1042 return NETDEV_TX_OK; 1043 skb->len = 17; 1044 } 1045 1046 return igc_xmit_frame_ring(skb, igc_tx_queue_mapping(adapter, skb)); 1047 } 1048 1049 static inline void igc_rx_hash(struct igc_ring *ring, 1050 union igc_adv_rx_desc *rx_desc, 1051 struct sk_buff *skb) 1052 { 1053 if (ring->netdev->features & NETIF_F_RXHASH) 1054 skb_set_hash(skb, 1055 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1056 PKT_HASH_TYPE_L3); 1057 } 1058 1059 /** 1060 * igc_process_skb_fields - Populate skb header fields from Rx descriptor 1061 * @rx_ring: rx descriptor ring packet is being transacted on 1062 * @rx_desc: pointer to the EOP Rx descriptor 1063 * @skb: pointer to current skb being populated 1064 * 1065 * This function checks the ring, descriptor, and packet information in 1066 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1067 * other fields within the skb. 1068 */ 1069 static void igc_process_skb_fields(struct igc_ring *rx_ring, 1070 union igc_adv_rx_desc *rx_desc, 1071 struct sk_buff *skb) 1072 { 1073 igc_rx_hash(rx_ring, rx_desc, skb); 1074 1075 skb_record_rx_queue(skb, rx_ring->queue_index); 1076 1077 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 1078 } 1079 1080 static struct igc_rx_buffer *igc_get_rx_buffer(struct igc_ring *rx_ring, 1081 const unsigned int size) 1082 { 1083 struct igc_rx_buffer *rx_buffer; 1084 1085 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 1086 prefetchw(rx_buffer->page); 1087 1088 /* we are reusing so sync this buffer for CPU use */ 1089 dma_sync_single_range_for_cpu(rx_ring->dev, 1090 rx_buffer->dma, 1091 rx_buffer->page_offset, 1092 size, 1093 DMA_FROM_DEVICE); 1094 1095 rx_buffer->pagecnt_bias--; 1096 1097 return rx_buffer; 1098 } 1099 1100 /** 1101 * igc_add_rx_frag - Add contents of Rx buffer to sk_buff 1102 * @rx_ring: rx descriptor ring to transact packets on 1103 * @rx_buffer: buffer containing page to add 1104 * @skb: sk_buff to place the data into 1105 * @size: size of buffer to be added 1106 * 1107 * This function will add the data contained in rx_buffer->page to the skb. 1108 */ 1109 static void igc_add_rx_frag(struct igc_ring *rx_ring, 1110 struct igc_rx_buffer *rx_buffer, 1111 struct sk_buff *skb, 1112 unsigned int size) 1113 { 1114 #if (PAGE_SIZE < 8192) 1115 unsigned int truesize = igc_rx_pg_size(rx_ring) / 2; 1116 1117 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 1118 rx_buffer->page_offset, size, truesize); 1119 rx_buffer->page_offset ^= truesize; 1120 #else 1121 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 1122 SKB_DATA_ALIGN(IGC_SKB_PAD + size) : 1123 SKB_DATA_ALIGN(size); 1124 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 1125 rx_buffer->page_offset, size, truesize); 1126 rx_buffer->page_offset += truesize; 1127 #endif 1128 } 1129 1130 static struct sk_buff *igc_build_skb(struct igc_ring *rx_ring, 1131 struct igc_rx_buffer *rx_buffer, 1132 union igc_adv_rx_desc *rx_desc, 1133 unsigned int size) 1134 { 1135 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 1136 #if (PAGE_SIZE < 8192) 1137 unsigned int truesize = igc_rx_pg_size(rx_ring) / 2; 1138 #else 1139 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1140 SKB_DATA_ALIGN(IGC_SKB_PAD + size); 1141 #endif 1142 struct sk_buff *skb; 1143 1144 /* prefetch first cache line of first page */ 1145 prefetch(va); 1146 #if L1_CACHE_BYTES < 128 1147 prefetch(va + L1_CACHE_BYTES); 1148 #endif 1149 1150 /* build an skb around the page buffer */ 1151 skb = build_skb(va - IGC_SKB_PAD, truesize); 1152 if (unlikely(!skb)) 1153 return NULL; 1154 1155 /* update pointers within the skb to store the data */ 1156 skb_reserve(skb, IGC_SKB_PAD); 1157 __skb_put(skb, size); 1158 1159 /* update buffer offset */ 1160 #if (PAGE_SIZE < 8192) 1161 rx_buffer->page_offset ^= truesize; 1162 #else 1163 rx_buffer->page_offset += truesize; 1164 #endif 1165 1166 return skb; 1167 } 1168 1169 static struct sk_buff *igc_construct_skb(struct igc_ring *rx_ring, 1170 struct igc_rx_buffer *rx_buffer, 1171 union igc_adv_rx_desc *rx_desc, 1172 unsigned int size) 1173 { 1174 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 1175 #if (PAGE_SIZE < 8192) 1176 unsigned int truesize = igc_rx_pg_size(rx_ring) / 2; 1177 #else 1178 unsigned int truesize = SKB_DATA_ALIGN(size); 1179 #endif 1180 unsigned int headlen; 1181 struct sk_buff *skb; 1182 1183 /* prefetch first cache line of first page */ 1184 prefetch(va); 1185 #if L1_CACHE_BYTES < 128 1186 prefetch(va + L1_CACHE_BYTES); 1187 #endif 1188 1189 /* allocate a skb to store the frags */ 1190 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGC_RX_HDR_LEN); 1191 if (unlikely(!skb)) 1192 return NULL; 1193 1194 /* Determine available headroom for copy */ 1195 headlen = size; 1196 if (headlen > IGC_RX_HDR_LEN) 1197 headlen = eth_get_headlen(skb->dev, va, IGC_RX_HDR_LEN); 1198 1199 /* align pull length to size of long to optimize memcpy performance */ 1200 memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long))); 1201 1202 /* update all of the pointers */ 1203 size -= headlen; 1204 if (size) { 1205 skb_add_rx_frag(skb, 0, rx_buffer->page, 1206 (va + headlen) - page_address(rx_buffer->page), 1207 size, truesize); 1208 #if (PAGE_SIZE < 8192) 1209 rx_buffer->page_offset ^= truesize; 1210 #else 1211 rx_buffer->page_offset += truesize; 1212 #endif 1213 } else { 1214 rx_buffer->pagecnt_bias++; 1215 } 1216 1217 return skb; 1218 } 1219 1220 /** 1221 * igc_reuse_rx_page - page flip buffer and store it back on the ring 1222 * @rx_ring: rx descriptor ring to store buffers on 1223 * @old_buff: donor buffer to have page reused 1224 * 1225 * Synchronizes page for reuse by the adapter 1226 */ 1227 static void igc_reuse_rx_page(struct igc_ring *rx_ring, 1228 struct igc_rx_buffer *old_buff) 1229 { 1230 u16 nta = rx_ring->next_to_alloc; 1231 struct igc_rx_buffer *new_buff; 1232 1233 new_buff = &rx_ring->rx_buffer_info[nta]; 1234 1235 /* update, and store next to alloc */ 1236 nta++; 1237 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1238 1239 /* Transfer page from old buffer to new buffer. 1240 * Move each member individually to avoid possible store 1241 * forwarding stalls. 1242 */ 1243 new_buff->dma = old_buff->dma; 1244 new_buff->page = old_buff->page; 1245 new_buff->page_offset = old_buff->page_offset; 1246 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1247 } 1248 1249 static inline bool igc_page_is_reserved(struct page *page) 1250 { 1251 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 1252 } 1253 1254 static bool igc_can_reuse_rx_page(struct igc_rx_buffer *rx_buffer) 1255 { 1256 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1257 struct page *page = rx_buffer->page; 1258 1259 /* avoid re-using remote pages */ 1260 if (unlikely(igc_page_is_reserved(page))) 1261 return false; 1262 1263 #if (PAGE_SIZE < 8192) 1264 /* if we are only owner of page we can reuse it */ 1265 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 1266 return false; 1267 #else 1268 #define IGC_LAST_OFFSET \ 1269 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGC_RXBUFFER_2048) 1270 1271 if (rx_buffer->page_offset > IGC_LAST_OFFSET) 1272 return false; 1273 #endif 1274 1275 /* If we have drained the page fragment pool we need to update 1276 * the pagecnt_bias and page count so that we fully restock the 1277 * number of references the driver holds. 1278 */ 1279 if (unlikely(!pagecnt_bias)) { 1280 page_ref_add(page, USHRT_MAX); 1281 rx_buffer->pagecnt_bias = USHRT_MAX; 1282 } 1283 1284 return true; 1285 } 1286 1287 /** 1288 * igc_is_non_eop - process handling of non-EOP buffers 1289 * @rx_ring: Rx ring being processed 1290 * @rx_desc: Rx descriptor for current buffer 1291 * @skb: current socket buffer containing buffer in progress 1292 * 1293 * This function updates next to clean. If the buffer is an EOP buffer 1294 * this function exits returning false, otherwise it will place the 1295 * sk_buff in the next buffer to be chained and return true indicating 1296 * that this is in fact a non-EOP buffer. 1297 */ 1298 static bool igc_is_non_eop(struct igc_ring *rx_ring, 1299 union igc_adv_rx_desc *rx_desc) 1300 { 1301 u32 ntc = rx_ring->next_to_clean + 1; 1302 1303 /* fetch, update, and store next to clean */ 1304 ntc = (ntc < rx_ring->count) ? ntc : 0; 1305 rx_ring->next_to_clean = ntc; 1306 1307 prefetch(IGC_RX_DESC(rx_ring, ntc)); 1308 1309 if (likely(igc_test_staterr(rx_desc, IGC_RXD_STAT_EOP))) 1310 return false; 1311 1312 return true; 1313 } 1314 1315 /** 1316 * igc_cleanup_headers - Correct corrupted or empty headers 1317 * @rx_ring: rx descriptor ring packet is being transacted on 1318 * @rx_desc: pointer to the EOP Rx descriptor 1319 * @skb: pointer to current skb being fixed 1320 * 1321 * Address the case where we are pulling data in on pages only 1322 * and as such no data is present in the skb header. 1323 * 1324 * In addition if skb is not at least 60 bytes we need to pad it so that 1325 * it is large enough to qualify as a valid Ethernet frame. 1326 * 1327 * Returns true if an error was encountered and skb was freed. 1328 */ 1329 static bool igc_cleanup_headers(struct igc_ring *rx_ring, 1330 union igc_adv_rx_desc *rx_desc, 1331 struct sk_buff *skb) 1332 { 1333 if (unlikely((igc_test_staterr(rx_desc, 1334 IGC_RXDEXT_ERR_FRAME_ERR_MASK)))) { 1335 struct net_device *netdev = rx_ring->netdev; 1336 1337 if (!(netdev->features & NETIF_F_RXALL)) { 1338 dev_kfree_skb_any(skb); 1339 return true; 1340 } 1341 } 1342 1343 /* if eth_skb_pad returns an error the skb was freed */ 1344 if (eth_skb_pad(skb)) 1345 return true; 1346 1347 return false; 1348 } 1349 1350 static void igc_put_rx_buffer(struct igc_ring *rx_ring, 1351 struct igc_rx_buffer *rx_buffer) 1352 { 1353 if (igc_can_reuse_rx_page(rx_buffer)) { 1354 /* hand second half of page back to the ring */ 1355 igc_reuse_rx_page(rx_ring, rx_buffer); 1356 } else { 1357 /* We are not reusing the buffer so unmap it and free 1358 * any references we are holding to it 1359 */ 1360 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 1361 igc_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 1362 IGC_RX_DMA_ATTR); 1363 __page_frag_cache_drain(rx_buffer->page, 1364 rx_buffer->pagecnt_bias); 1365 } 1366 1367 /* clear contents of rx_buffer */ 1368 rx_buffer->page = NULL; 1369 } 1370 1371 /** 1372 * igc_alloc_rx_buffers - Replace used receive buffers; packet split 1373 * @adapter: address of board private structure 1374 */ 1375 static void igc_alloc_rx_buffers(struct igc_ring *rx_ring, u16 cleaned_count) 1376 { 1377 union igc_adv_rx_desc *rx_desc; 1378 u16 i = rx_ring->next_to_use; 1379 struct igc_rx_buffer *bi; 1380 u16 bufsz; 1381 1382 /* nothing to do */ 1383 if (!cleaned_count) 1384 return; 1385 1386 rx_desc = IGC_RX_DESC(rx_ring, i); 1387 bi = &rx_ring->rx_buffer_info[i]; 1388 i -= rx_ring->count; 1389 1390 bufsz = igc_rx_bufsz(rx_ring); 1391 1392 do { 1393 if (!igc_alloc_mapped_page(rx_ring, bi)) 1394 break; 1395 1396 /* sync the buffer for use by the device */ 1397 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1398 bi->page_offset, bufsz, 1399 DMA_FROM_DEVICE); 1400 1401 /* Refresh the desc even if buffer_addrs didn't change 1402 * because each write-back erases this info. 1403 */ 1404 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1405 1406 rx_desc++; 1407 bi++; 1408 i++; 1409 if (unlikely(!i)) { 1410 rx_desc = IGC_RX_DESC(rx_ring, 0); 1411 bi = rx_ring->rx_buffer_info; 1412 i -= rx_ring->count; 1413 } 1414 1415 /* clear the length for the next_to_use descriptor */ 1416 rx_desc->wb.upper.length = 0; 1417 1418 cleaned_count--; 1419 } while (cleaned_count); 1420 1421 i += rx_ring->count; 1422 1423 if (rx_ring->next_to_use != i) { 1424 /* record the next descriptor to use */ 1425 rx_ring->next_to_use = i; 1426 1427 /* update next to alloc since we have filled the ring */ 1428 rx_ring->next_to_alloc = i; 1429 1430 /* Force memory writes to complete before letting h/w 1431 * know there are new descriptors to fetch. (Only 1432 * applicable for weak-ordered memory model archs, 1433 * such as IA-64). 1434 */ 1435 wmb(); 1436 writel(i, rx_ring->tail); 1437 } 1438 } 1439 1440 static int igc_clean_rx_irq(struct igc_q_vector *q_vector, const int budget) 1441 { 1442 unsigned int total_bytes = 0, total_packets = 0; 1443 struct igc_ring *rx_ring = q_vector->rx.ring; 1444 struct sk_buff *skb = rx_ring->skb; 1445 u16 cleaned_count = igc_desc_unused(rx_ring); 1446 1447 while (likely(total_packets < budget)) { 1448 union igc_adv_rx_desc *rx_desc; 1449 struct igc_rx_buffer *rx_buffer; 1450 unsigned int size; 1451 1452 /* return some buffers to hardware, one at a time is too slow */ 1453 if (cleaned_count >= IGC_RX_BUFFER_WRITE) { 1454 igc_alloc_rx_buffers(rx_ring, cleaned_count); 1455 cleaned_count = 0; 1456 } 1457 1458 rx_desc = IGC_RX_DESC(rx_ring, rx_ring->next_to_clean); 1459 size = le16_to_cpu(rx_desc->wb.upper.length); 1460 if (!size) 1461 break; 1462 1463 /* This memory barrier is needed to keep us from reading 1464 * any other fields out of the rx_desc until we know the 1465 * descriptor has been written back 1466 */ 1467 dma_rmb(); 1468 1469 rx_buffer = igc_get_rx_buffer(rx_ring, size); 1470 1471 /* retrieve a buffer from the ring */ 1472 if (skb) 1473 igc_add_rx_frag(rx_ring, rx_buffer, skb, size); 1474 else if (ring_uses_build_skb(rx_ring)) 1475 skb = igc_build_skb(rx_ring, rx_buffer, rx_desc, size); 1476 else 1477 skb = igc_construct_skb(rx_ring, rx_buffer, 1478 rx_desc, size); 1479 1480 /* exit if we failed to retrieve a buffer */ 1481 if (!skb) { 1482 rx_ring->rx_stats.alloc_failed++; 1483 rx_buffer->pagecnt_bias++; 1484 break; 1485 } 1486 1487 igc_put_rx_buffer(rx_ring, rx_buffer); 1488 cleaned_count++; 1489 1490 /* fetch next buffer in frame if non-eop */ 1491 if (igc_is_non_eop(rx_ring, rx_desc)) 1492 continue; 1493 1494 /* verify the packet layout is correct */ 1495 if (igc_cleanup_headers(rx_ring, rx_desc, skb)) { 1496 skb = NULL; 1497 continue; 1498 } 1499 1500 /* probably a little skewed due to removing CRC */ 1501 total_bytes += skb->len; 1502 1503 /* populate checksum, timestamp, VLAN, and protocol */ 1504 igc_process_skb_fields(rx_ring, rx_desc, skb); 1505 1506 napi_gro_receive(&q_vector->napi, skb); 1507 1508 /* reset skb pointer */ 1509 skb = NULL; 1510 1511 /* update budget accounting */ 1512 total_packets++; 1513 } 1514 1515 /* place incomplete frames back on ring for completion */ 1516 rx_ring->skb = skb; 1517 1518 u64_stats_update_begin(&rx_ring->rx_syncp); 1519 rx_ring->rx_stats.packets += total_packets; 1520 rx_ring->rx_stats.bytes += total_bytes; 1521 u64_stats_update_end(&rx_ring->rx_syncp); 1522 q_vector->rx.total_packets += total_packets; 1523 q_vector->rx.total_bytes += total_bytes; 1524 1525 if (cleaned_count) 1526 igc_alloc_rx_buffers(rx_ring, cleaned_count); 1527 1528 return total_packets; 1529 } 1530 1531 static inline unsigned int igc_rx_offset(struct igc_ring *rx_ring) 1532 { 1533 return ring_uses_build_skb(rx_ring) ? IGC_SKB_PAD : 0; 1534 } 1535 1536 static bool igc_alloc_mapped_page(struct igc_ring *rx_ring, 1537 struct igc_rx_buffer *bi) 1538 { 1539 struct page *page = bi->page; 1540 dma_addr_t dma; 1541 1542 /* since we are recycling buffers we should seldom need to alloc */ 1543 if (likely(page)) 1544 return true; 1545 1546 /* alloc new page for storage */ 1547 page = dev_alloc_pages(igc_rx_pg_order(rx_ring)); 1548 if (unlikely(!page)) { 1549 rx_ring->rx_stats.alloc_failed++; 1550 return false; 1551 } 1552 1553 /* map page for use */ 1554 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1555 igc_rx_pg_size(rx_ring), 1556 DMA_FROM_DEVICE, 1557 IGC_RX_DMA_ATTR); 1558 1559 /* if mapping failed free memory back to system since 1560 * there isn't much point in holding memory we can't use 1561 */ 1562 if (dma_mapping_error(rx_ring->dev, dma)) { 1563 __free_page(page); 1564 1565 rx_ring->rx_stats.alloc_failed++; 1566 return false; 1567 } 1568 1569 bi->dma = dma; 1570 bi->page = page; 1571 bi->page_offset = igc_rx_offset(rx_ring); 1572 bi->pagecnt_bias = 1; 1573 1574 return true; 1575 } 1576 1577 /** 1578 * igc_clean_tx_irq - Reclaim resources after transmit completes 1579 * @q_vector: pointer to q_vector containing needed info 1580 * @napi_budget: Used to determine if we are in netpoll 1581 * 1582 * returns true if ring is completely cleaned 1583 */ 1584 static bool igc_clean_tx_irq(struct igc_q_vector *q_vector, int napi_budget) 1585 { 1586 struct igc_adapter *adapter = q_vector->adapter; 1587 unsigned int total_bytes = 0, total_packets = 0; 1588 unsigned int budget = q_vector->tx.work_limit; 1589 struct igc_ring *tx_ring = q_vector->tx.ring; 1590 unsigned int i = tx_ring->next_to_clean; 1591 struct igc_tx_buffer *tx_buffer; 1592 union igc_adv_tx_desc *tx_desc; 1593 1594 if (test_bit(__IGC_DOWN, &adapter->state)) 1595 return true; 1596 1597 tx_buffer = &tx_ring->tx_buffer_info[i]; 1598 tx_desc = IGC_TX_DESC(tx_ring, i); 1599 i -= tx_ring->count; 1600 1601 do { 1602 union igc_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1603 1604 /* if next_to_watch is not set then there is no work pending */ 1605 if (!eop_desc) 1606 break; 1607 1608 /* prevent any other reads prior to eop_desc */ 1609 smp_rmb(); 1610 1611 /* if DD is not set pending work has not been completed */ 1612 if (!(eop_desc->wb.status & cpu_to_le32(IGC_TXD_STAT_DD))) 1613 break; 1614 1615 /* clear next_to_watch to prevent false hangs */ 1616 tx_buffer->next_to_watch = NULL; 1617 1618 /* update the statistics for this packet */ 1619 total_bytes += tx_buffer->bytecount; 1620 total_packets += tx_buffer->gso_segs; 1621 1622 /* free the skb */ 1623 napi_consume_skb(tx_buffer->skb, napi_budget); 1624 1625 /* unmap skb header data */ 1626 dma_unmap_single(tx_ring->dev, 1627 dma_unmap_addr(tx_buffer, dma), 1628 dma_unmap_len(tx_buffer, len), 1629 DMA_TO_DEVICE); 1630 1631 /* clear tx_buffer data */ 1632 dma_unmap_len_set(tx_buffer, len, 0); 1633 1634 /* clear last DMA location and unmap remaining buffers */ 1635 while (tx_desc != eop_desc) { 1636 tx_buffer++; 1637 tx_desc++; 1638 i++; 1639 if (unlikely(!i)) { 1640 i -= tx_ring->count; 1641 tx_buffer = tx_ring->tx_buffer_info; 1642 tx_desc = IGC_TX_DESC(tx_ring, 0); 1643 } 1644 1645 /* unmap any remaining paged data */ 1646 if (dma_unmap_len(tx_buffer, len)) { 1647 dma_unmap_page(tx_ring->dev, 1648 dma_unmap_addr(tx_buffer, dma), 1649 dma_unmap_len(tx_buffer, len), 1650 DMA_TO_DEVICE); 1651 dma_unmap_len_set(tx_buffer, len, 0); 1652 } 1653 } 1654 1655 /* move us one more past the eop_desc for start of next pkt */ 1656 tx_buffer++; 1657 tx_desc++; 1658 i++; 1659 if (unlikely(!i)) { 1660 i -= tx_ring->count; 1661 tx_buffer = tx_ring->tx_buffer_info; 1662 tx_desc = IGC_TX_DESC(tx_ring, 0); 1663 } 1664 1665 /* issue prefetch for next Tx descriptor */ 1666 prefetch(tx_desc); 1667 1668 /* update budget accounting */ 1669 budget--; 1670 } while (likely(budget)); 1671 1672 netdev_tx_completed_queue(txring_txq(tx_ring), 1673 total_packets, total_bytes); 1674 1675 i += tx_ring->count; 1676 tx_ring->next_to_clean = i; 1677 u64_stats_update_begin(&tx_ring->tx_syncp); 1678 tx_ring->tx_stats.bytes += total_bytes; 1679 tx_ring->tx_stats.packets += total_packets; 1680 u64_stats_update_end(&tx_ring->tx_syncp); 1681 q_vector->tx.total_bytes += total_bytes; 1682 q_vector->tx.total_packets += total_packets; 1683 1684 if (test_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 1685 struct igc_hw *hw = &adapter->hw; 1686 1687 /* Detect a transmit hang in hardware, this serializes the 1688 * check with the clearing of time_stamp and movement of i 1689 */ 1690 clear_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 1691 if (tx_buffer->next_to_watch && 1692 time_after(jiffies, tx_buffer->time_stamp + 1693 (adapter->tx_timeout_factor * HZ)) && 1694 !(rd32(IGC_STATUS) & IGC_STATUS_TXOFF)) { 1695 /* detected Tx unit hang */ 1696 dev_err(tx_ring->dev, 1697 "Detected Tx Unit Hang\n" 1698 " Tx Queue <%d>\n" 1699 " TDH <%x>\n" 1700 " TDT <%x>\n" 1701 " next_to_use <%x>\n" 1702 " next_to_clean <%x>\n" 1703 "buffer_info[next_to_clean]\n" 1704 " time_stamp <%lx>\n" 1705 " next_to_watch <%p>\n" 1706 " jiffies <%lx>\n" 1707 " desc.status <%x>\n", 1708 tx_ring->queue_index, 1709 rd32(IGC_TDH(tx_ring->reg_idx)), 1710 readl(tx_ring->tail), 1711 tx_ring->next_to_use, 1712 tx_ring->next_to_clean, 1713 tx_buffer->time_stamp, 1714 tx_buffer->next_to_watch, 1715 jiffies, 1716 tx_buffer->next_to_watch->wb.status); 1717 netif_stop_subqueue(tx_ring->netdev, 1718 tx_ring->queue_index); 1719 1720 /* we are about to reset, no point in enabling stuff */ 1721 return true; 1722 } 1723 } 1724 1725 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1726 if (unlikely(total_packets && 1727 netif_carrier_ok(tx_ring->netdev) && 1728 igc_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 1729 /* Make sure that anybody stopping the queue after this 1730 * sees the new next_to_clean. 1731 */ 1732 smp_mb(); 1733 if (__netif_subqueue_stopped(tx_ring->netdev, 1734 tx_ring->queue_index) && 1735 !(test_bit(__IGC_DOWN, &adapter->state))) { 1736 netif_wake_subqueue(tx_ring->netdev, 1737 tx_ring->queue_index); 1738 1739 u64_stats_update_begin(&tx_ring->tx_syncp); 1740 tx_ring->tx_stats.restart_queue++; 1741 u64_stats_update_end(&tx_ring->tx_syncp); 1742 } 1743 } 1744 1745 return !!budget; 1746 } 1747 1748 /** 1749 * igc_up - Open the interface and prepare it to handle traffic 1750 * @adapter: board private structure 1751 */ 1752 void igc_up(struct igc_adapter *adapter) 1753 { 1754 struct igc_hw *hw = &adapter->hw; 1755 int i = 0; 1756 1757 /* hardware has been reset, we need to reload some things */ 1758 igc_configure(adapter); 1759 1760 clear_bit(__IGC_DOWN, &adapter->state); 1761 1762 for (i = 0; i < adapter->num_q_vectors; i++) 1763 napi_enable(&adapter->q_vector[i]->napi); 1764 1765 if (adapter->msix_entries) 1766 igc_configure_msix(adapter); 1767 else 1768 igc_assign_vector(adapter->q_vector[0], 0); 1769 1770 /* Clear any pending interrupts. */ 1771 rd32(IGC_ICR); 1772 igc_irq_enable(adapter); 1773 1774 netif_tx_start_all_queues(adapter->netdev); 1775 1776 /* start the watchdog. */ 1777 hw->mac.get_link_status = 1; 1778 schedule_work(&adapter->watchdog_task); 1779 } 1780 1781 /** 1782 * igc_update_stats - Update the board statistics counters 1783 * @adapter: board private structure 1784 */ 1785 void igc_update_stats(struct igc_adapter *adapter) 1786 { 1787 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 1788 struct pci_dev *pdev = adapter->pdev; 1789 struct igc_hw *hw = &adapter->hw; 1790 u64 _bytes, _packets; 1791 u64 bytes, packets; 1792 unsigned int start; 1793 u32 mpc; 1794 int i; 1795 1796 /* Prevent stats update while adapter is being reset, or if the pci 1797 * connection is down. 1798 */ 1799 if (adapter->link_speed == 0) 1800 return; 1801 if (pci_channel_offline(pdev)) 1802 return; 1803 1804 packets = 0; 1805 bytes = 0; 1806 1807 rcu_read_lock(); 1808 for (i = 0; i < adapter->num_rx_queues; i++) { 1809 struct igc_ring *ring = adapter->rx_ring[i]; 1810 u32 rqdpc = rd32(IGC_RQDPC(i)); 1811 1812 if (hw->mac.type >= igc_i225) 1813 wr32(IGC_RQDPC(i), 0); 1814 1815 if (rqdpc) { 1816 ring->rx_stats.drops += rqdpc; 1817 net_stats->rx_fifo_errors += rqdpc; 1818 } 1819 1820 do { 1821 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 1822 _bytes = ring->rx_stats.bytes; 1823 _packets = ring->rx_stats.packets; 1824 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 1825 bytes += _bytes; 1826 packets += _packets; 1827 } 1828 1829 net_stats->rx_bytes = bytes; 1830 net_stats->rx_packets = packets; 1831 1832 packets = 0; 1833 bytes = 0; 1834 for (i = 0; i < adapter->num_tx_queues; i++) { 1835 struct igc_ring *ring = adapter->tx_ring[i]; 1836 1837 do { 1838 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 1839 _bytes = ring->tx_stats.bytes; 1840 _packets = ring->tx_stats.packets; 1841 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 1842 bytes += _bytes; 1843 packets += _packets; 1844 } 1845 net_stats->tx_bytes = bytes; 1846 net_stats->tx_packets = packets; 1847 rcu_read_unlock(); 1848 1849 /* read stats registers */ 1850 adapter->stats.crcerrs += rd32(IGC_CRCERRS); 1851 adapter->stats.gprc += rd32(IGC_GPRC); 1852 adapter->stats.gorc += rd32(IGC_GORCL); 1853 rd32(IGC_GORCH); /* clear GORCL */ 1854 adapter->stats.bprc += rd32(IGC_BPRC); 1855 adapter->stats.mprc += rd32(IGC_MPRC); 1856 adapter->stats.roc += rd32(IGC_ROC); 1857 1858 adapter->stats.prc64 += rd32(IGC_PRC64); 1859 adapter->stats.prc127 += rd32(IGC_PRC127); 1860 adapter->stats.prc255 += rd32(IGC_PRC255); 1861 adapter->stats.prc511 += rd32(IGC_PRC511); 1862 adapter->stats.prc1023 += rd32(IGC_PRC1023); 1863 adapter->stats.prc1522 += rd32(IGC_PRC1522); 1864 adapter->stats.symerrs += rd32(IGC_SYMERRS); 1865 adapter->stats.sec += rd32(IGC_SEC); 1866 1867 mpc = rd32(IGC_MPC); 1868 adapter->stats.mpc += mpc; 1869 net_stats->rx_fifo_errors += mpc; 1870 adapter->stats.scc += rd32(IGC_SCC); 1871 adapter->stats.ecol += rd32(IGC_ECOL); 1872 adapter->stats.mcc += rd32(IGC_MCC); 1873 adapter->stats.latecol += rd32(IGC_LATECOL); 1874 adapter->stats.dc += rd32(IGC_DC); 1875 adapter->stats.rlec += rd32(IGC_RLEC); 1876 adapter->stats.xonrxc += rd32(IGC_XONRXC); 1877 adapter->stats.xontxc += rd32(IGC_XONTXC); 1878 adapter->stats.xoffrxc += rd32(IGC_XOFFRXC); 1879 adapter->stats.xofftxc += rd32(IGC_XOFFTXC); 1880 adapter->stats.fcruc += rd32(IGC_FCRUC); 1881 adapter->stats.gptc += rd32(IGC_GPTC); 1882 adapter->stats.gotc += rd32(IGC_GOTCL); 1883 rd32(IGC_GOTCH); /* clear GOTCL */ 1884 adapter->stats.rnbc += rd32(IGC_RNBC); 1885 adapter->stats.ruc += rd32(IGC_RUC); 1886 adapter->stats.rfc += rd32(IGC_RFC); 1887 adapter->stats.rjc += rd32(IGC_RJC); 1888 adapter->stats.tor += rd32(IGC_TORH); 1889 adapter->stats.tot += rd32(IGC_TOTH); 1890 adapter->stats.tpr += rd32(IGC_TPR); 1891 1892 adapter->stats.ptc64 += rd32(IGC_PTC64); 1893 adapter->stats.ptc127 += rd32(IGC_PTC127); 1894 adapter->stats.ptc255 += rd32(IGC_PTC255); 1895 adapter->stats.ptc511 += rd32(IGC_PTC511); 1896 adapter->stats.ptc1023 += rd32(IGC_PTC1023); 1897 adapter->stats.ptc1522 += rd32(IGC_PTC1522); 1898 1899 adapter->stats.mptc += rd32(IGC_MPTC); 1900 adapter->stats.bptc += rd32(IGC_BPTC); 1901 1902 adapter->stats.tpt += rd32(IGC_TPT); 1903 adapter->stats.colc += rd32(IGC_COLC); 1904 1905 adapter->stats.algnerrc += rd32(IGC_ALGNERRC); 1906 1907 adapter->stats.tsctc += rd32(IGC_TSCTC); 1908 adapter->stats.tsctfc += rd32(IGC_TSCTFC); 1909 1910 adapter->stats.iac += rd32(IGC_IAC); 1911 adapter->stats.icrxoc += rd32(IGC_ICRXOC); 1912 adapter->stats.icrxptc += rd32(IGC_ICRXPTC); 1913 adapter->stats.icrxatc += rd32(IGC_ICRXATC); 1914 adapter->stats.ictxptc += rd32(IGC_ICTXPTC); 1915 adapter->stats.ictxatc += rd32(IGC_ICTXATC); 1916 adapter->stats.ictxqec += rd32(IGC_ICTXQEC); 1917 adapter->stats.ictxqmtc += rd32(IGC_ICTXQMTC); 1918 adapter->stats.icrxdmtc += rd32(IGC_ICRXDMTC); 1919 1920 /* Fill out the OS statistics structure */ 1921 net_stats->multicast = adapter->stats.mprc; 1922 net_stats->collisions = adapter->stats.colc; 1923 1924 /* Rx Errors */ 1925 1926 /* RLEC on some newer hardware can be incorrect so build 1927 * our own version based on RUC and ROC 1928 */ 1929 net_stats->rx_errors = adapter->stats.rxerrc + 1930 adapter->stats.crcerrs + adapter->stats.algnerrc + 1931 adapter->stats.ruc + adapter->stats.roc + 1932 adapter->stats.cexterr; 1933 net_stats->rx_length_errors = adapter->stats.ruc + 1934 adapter->stats.roc; 1935 net_stats->rx_crc_errors = adapter->stats.crcerrs; 1936 net_stats->rx_frame_errors = adapter->stats.algnerrc; 1937 net_stats->rx_missed_errors = adapter->stats.mpc; 1938 1939 /* Tx Errors */ 1940 net_stats->tx_errors = adapter->stats.ecol + 1941 adapter->stats.latecol; 1942 net_stats->tx_aborted_errors = adapter->stats.ecol; 1943 net_stats->tx_window_errors = adapter->stats.latecol; 1944 net_stats->tx_carrier_errors = adapter->stats.tncrs; 1945 1946 /* Tx Dropped needs to be maintained elsewhere */ 1947 1948 /* Management Stats */ 1949 adapter->stats.mgptc += rd32(IGC_MGTPTC); 1950 adapter->stats.mgprc += rd32(IGC_MGTPRC); 1951 adapter->stats.mgpdc += rd32(IGC_MGTPDC); 1952 } 1953 1954 static void igc_nfc_filter_exit(struct igc_adapter *adapter) 1955 { 1956 struct igc_nfc_filter *rule; 1957 1958 spin_lock(&adapter->nfc_lock); 1959 1960 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 1961 igc_erase_filter(adapter, rule); 1962 1963 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node) 1964 igc_erase_filter(adapter, rule); 1965 1966 spin_unlock(&adapter->nfc_lock); 1967 } 1968 1969 static void igc_nfc_filter_restore(struct igc_adapter *adapter) 1970 { 1971 struct igc_nfc_filter *rule; 1972 1973 spin_lock(&adapter->nfc_lock); 1974 1975 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) 1976 igc_add_filter(adapter, rule); 1977 1978 spin_unlock(&adapter->nfc_lock); 1979 } 1980 1981 /** 1982 * igc_down - Close the interface 1983 * @adapter: board private structure 1984 */ 1985 void igc_down(struct igc_adapter *adapter) 1986 { 1987 struct net_device *netdev = adapter->netdev; 1988 struct igc_hw *hw = &adapter->hw; 1989 u32 tctl, rctl; 1990 int i = 0; 1991 1992 set_bit(__IGC_DOWN, &adapter->state); 1993 1994 /* disable receives in the hardware */ 1995 rctl = rd32(IGC_RCTL); 1996 wr32(IGC_RCTL, rctl & ~IGC_RCTL_EN); 1997 /* flush and sleep below */ 1998 1999 igc_nfc_filter_exit(adapter); 2000 2001 /* set trans_start so we don't get spurious watchdogs during reset */ 2002 netif_trans_update(netdev); 2003 2004 netif_carrier_off(netdev); 2005 netif_tx_stop_all_queues(netdev); 2006 2007 /* disable transmits in the hardware */ 2008 tctl = rd32(IGC_TCTL); 2009 tctl &= ~IGC_TCTL_EN; 2010 wr32(IGC_TCTL, tctl); 2011 /* flush both disables and wait for them to finish */ 2012 wrfl(); 2013 usleep_range(10000, 20000); 2014 2015 igc_irq_disable(adapter); 2016 2017 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE; 2018 2019 for (i = 0; i < adapter->num_q_vectors; i++) { 2020 if (adapter->q_vector[i]) { 2021 napi_synchronize(&adapter->q_vector[i]->napi); 2022 napi_disable(&adapter->q_vector[i]->napi); 2023 } 2024 } 2025 2026 del_timer_sync(&adapter->watchdog_timer); 2027 del_timer_sync(&adapter->phy_info_timer); 2028 2029 /* record the stats before reset*/ 2030 spin_lock(&adapter->stats64_lock); 2031 igc_update_stats(adapter); 2032 spin_unlock(&adapter->stats64_lock); 2033 2034 adapter->link_speed = 0; 2035 adapter->link_duplex = 0; 2036 2037 if (!pci_channel_offline(adapter->pdev)) 2038 igc_reset(adapter); 2039 2040 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 2041 adapter->flags &= ~IGC_FLAG_VLAN_PROMISC; 2042 2043 igc_clean_all_tx_rings(adapter); 2044 igc_clean_all_rx_rings(adapter); 2045 } 2046 2047 void igc_reinit_locked(struct igc_adapter *adapter) 2048 { 2049 WARN_ON(in_interrupt()); 2050 while (test_and_set_bit(__IGC_RESETTING, &adapter->state)) 2051 usleep_range(1000, 2000); 2052 igc_down(adapter); 2053 igc_up(adapter); 2054 clear_bit(__IGC_RESETTING, &adapter->state); 2055 } 2056 2057 static void igc_reset_task(struct work_struct *work) 2058 { 2059 struct igc_adapter *adapter; 2060 2061 adapter = container_of(work, struct igc_adapter, reset_task); 2062 2063 netdev_err(adapter->netdev, "Reset adapter\n"); 2064 igc_reinit_locked(adapter); 2065 } 2066 2067 /** 2068 * igc_change_mtu - Change the Maximum Transfer Unit 2069 * @netdev: network interface device structure 2070 * @new_mtu: new value for maximum frame size 2071 * 2072 * Returns 0 on success, negative on failure 2073 */ 2074 static int igc_change_mtu(struct net_device *netdev, int new_mtu) 2075 { 2076 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 2077 struct igc_adapter *adapter = netdev_priv(netdev); 2078 struct pci_dev *pdev = adapter->pdev; 2079 2080 /* adjust max frame to be at least the size of a standard frame */ 2081 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 2082 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 2083 2084 while (test_and_set_bit(__IGC_RESETTING, &adapter->state)) 2085 usleep_range(1000, 2000); 2086 2087 /* igc_down has a dependency on max_frame_size */ 2088 adapter->max_frame_size = max_frame; 2089 2090 if (netif_running(netdev)) 2091 igc_down(adapter); 2092 2093 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 2094 netdev->mtu, new_mtu); 2095 netdev->mtu = new_mtu; 2096 2097 if (netif_running(netdev)) 2098 igc_up(adapter); 2099 else 2100 igc_reset(adapter); 2101 2102 clear_bit(__IGC_RESETTING, &adapter->state); 2103 2104 return 0; 2105 } 2106 2107 /** 2108 * igc_get_stats - Get System Network Statistics 2109 * @netdev: network interface device structure 2110 * 2111 * Returns the address of the device statistics structure. 2112 * The statistics are updated here and also from the timer callback. 2113 */ 2114 static struct net_device_stats *igc_get_stats(struct net_device *netdev) 2115 { 2116 struct igc_adapter *adapter = netdev_priv(netdev); 2117 2118 if (!test_bit(__IGC_RESETTING, &adapter->state)) 2119 igc_update_stats(adapter); 2120 2121 /* only return the current stats */ 2122 return &netdev->stats; 2123 } 2124 2125 static netdev_features_t igc_fix_features(struct net_device *netdev, 2126 netdev_features_t features) 2127 { 2128 /* Since there is no support for separate Rx/Tx vlan accel 2129 * enable/disable make sure Tx flag is always in same state as Rx. 2130 */ 2131 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2132 features |= NETIF_F_HW_VLAN_CTAG_TX; 2133 else 2134 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2135 2136 return features; 2137 } 2138 2139 static int igc_set_features(struct net_device *netdev, 2140 netdev_features_t features) 2141 { 2142 netdev_features_t changed = netdev->features ^ features; 2143 struct igc_adapter *adapter = netdev_priv(netdev); 2144 2145 /* Add VLAN support */ 2146 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE))) 2147 return 0; 2148 2149 if (!(features & NETIF_F_NTUPLE)) { 2150 struct hlist_node *node2; 2151 struct igc_nfc_filter *rule; 2152 2153 spin_lock(&adapter->nfc_lock); 2154 hlist_for_each_entry_safe(rule, node2, 2155 &adapter->nfc_filter_list, nfc_node) { 2156 igc_erase_filter(adapter, rule); 2157 hlist_del(&rule->nfc_node); 2158 kfree(rule); 2159 } 2160 spin_unlock(&adapter->nfc_lock); 2161 adapter->nfc_filter_count = 0; 2162 } 2163 2164 netdev->features = features; 2165 2166 if (netif_running(netdev)) 2167 igc_reinit_locked(adapter); 2168 else 2169 igc_reset(adapter); 2170 2171 return 1; 2172 } 2173 2174 static netdev_features_t 2175 igc_features_check(struct sk_buff *skb, struct net_device *dev, 2176 netdev_features_t features) 2177 { 2178 unsigned int network_hdr_len, mac_hdr_len; 2179 2180 /* Make certain the headers can be described by a context descriptor */ 2181 mac_hdr_len = skb_network_header(skb) - skb->data; 2182 if (unlikely(mac_hdr_len > IGC_MAX_MAC_HDR_LEN)) 2183 return features & ~(NETIF_F_HW_CSUM | 2184 NETIF_F_SCTP_CRC | 2185 NETIF_F_HW_VLAN_CTAG_TX | 2186 NETIF_F_TSO | 2187 NETIF_F_TSO6); 2188 2189 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 2190 if (unlikely(network_hdr_len > IGC_MAX_NETWORK_HDR_LEN)) 2191 return features & ~(NETIF_F_HW_CSUM | 2192 NETIF_F_SCTP_CRC | 2193 NETIF_F_TSO | 2194 NETIF_F_TSO6); 2195 2196 /* We can only support IPv4 TSO in tunnels if we can mangle the 2197 * inner IP ID field, so strip TSO if MANGLEID is not supported. 2198 */ 2199 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 2200 features &= ~NETIF_F_TSO; 2201 2202 return features; 2203 } 2204 2205 /** 2206 * igc_configure - configure the hardware for RX and TX 2207 * @adapter: private board structure 2208 */ 2209 static void igc_configure(struct igc_adapter *adapter) 2210 { 2211 struct net_device *netdev = adapter->netdev; 2212 int i = 0; 2213 2214 igc_get_hw_control(adapter); 2215 igc_set_rx_mode(netdev); 2216 2217 igc_setup_tctl(adapter); 2218 igc_setup_mrqc(adapter); 2219 igc_setup_rctl(adapter); 2220 2221 igc_nfc_filter_restore(adapter); 2222 igc_configure_tx(adapter); 2223 igc_configure_rx(adapter); 2224 2225 igc_rx_fifo_flush_base(&adapter->hw); 2226 2227 /* call igc_desc_unused which always leaves 2228 * at least 1 descriptor unused to make sure 2229 * next_to_use != next_to_clean 2230 */ 2231 for (i = 0; i < adapter->num_rx_queues; i++) { 2232 struct igc_ring *ring = adapter->rx_ring[i]; 2233 2234 igc_alloc_rx_buffers(ring, igc_desc_unused(ring)); 2235 } 2236 } 2237 2238 /** 2239 * igc_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table 2240 * @adapter: address of board private structure 2241 * @index: Index of the RAR entry which need to be synced with MAC table 2242 */ 2243 static void igc_rar_set_index(struct igc_adapter *adapter, u32 index) 2244 { 2245 u8 *addr = adapter->mac_table[index].addr; 2246 struct igc_hw *hw = &adapter->hw; 2247 u32 rar_low, rar_high; 2248 2249 /* HW expects these to be in network order when they are plugged 2250 * into the registers which are little endian. In order to guarantee 2251 * that ordering we need to do an leXX_to_cpup here in order to be 2252 * ready for the byteswap that occurs with writel 2253 */ 2254 rar_low = le32_to_cpup((__le32 *)(addr)); 2255 rar_high = le16_to_cpup((__le16 *)(addr + 4)); 2256 2257 /* Indicate to hardware the Address is Valid. */ 2258 if (adapter->mac_table[index].state & IGC_MAC_STATE_IN_USE) { 2259 if (is_valid_ether_addr(addr)) 2260 rar_high |= IGC_RAH_AV; 2261 2262 rar_high |= IGC_RAH_POOL_1 << 2263 adapter->mac_table[index].queue; 2264 } 2265 2266 wr32(IGC_RAL(index), rar_low); 2267 wrfl(); 2268 wr32(IGC_RAH(index), rar_high); 2269 wrfl(); 2270 } 2271 2272 /* Set default MAC address for the PF in the first RAR entry */ 2273 static void igc_set_default_mac_filter(struct igc_adapter *adapter) 2274 { 2275 struct igc_mac_addr *mac_table = &adapter->mac_table[0]; 2276 2277 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr); 2278 mac_table->state = IGC_MAC_STATE_DEFAULT | IGC_MAC_STATE_IN_USE; 2279 2280 igc_rar_set_index(adapter, 0); 2281 } 2282 2283 /* If the filter to be added and an already existing filter express 2284 * the same address and address type, it should be possible to only 2285 * override the other configurations, for example the queue to steer 2286 * traffic. 2287 */ 2288 static bool igc_mac_entry_can_be_used(const struct igc_mac_addr *entry, 2289 const u8 *addr, const u8 flags) 2290 { 2291 if (!(entry->state & IGC_MAC_STATE_IN_USE)) 2292 return true; 2293 2294 if ((entry->state & IGC_MAC_STATE_SRC_ADDR) != 2295 (flags & IGC_MAC_STATE_SRC_ADDR)) 2296 return false; 2297 2298 if (!ether_addr_equal(addr, entry->addr)) 2299 return false; 2300 2301 return true; 2302 } 2303 2304 /* Add a MAC filter for 'addr' directing matching traffic to 'queue', 2305 * 'flags' is used to indicate what kind of match is made, match is by 2306 * default for the destination address, if matching by source address 2307 * is desired the flag IGC_MAC_STATE_SRC_ADDR can be used. 2308 */ 2309 static int igc_add_mac_filter_flags(struct igc_adapter *adapter, 2310 const u8 *addr, const u8 queue, 2311 const u8 flags) 2312 { 2313 struct igc_hw *hw = &adapter->hw; 2314 int rar_entries = hw->mac.rar_entry_count; 2315 int i; 2316 2317 if (is_zero_ether_addr(addr)) 2318 return -EINVAL; 2319 2320 /* Search for the first empty entry in the MAC table. 2321 * Do not touch entries at the end of the table reserved for the VF MAC 2322 * addresses. 2323 */ 2324 for (i = 0; i < rar_entries; i++) { 2325 if (!igc_mac_entry_can_be_used(&adapter->mac_table[i], 2326 addr, flags)) 2327 continue; 2328 2329 ether_addr_copy(adapter->mac_table[i].addr, addr); 2330 adapter->mac_table[i].queue = queue; 2331 adapter->mac_table[i].state |= IGC_MAC_STATE_IN_USE | flags; 2332 2333 igc_rar_set_index(adapter, i); 2334 return i; 2335 } 2336 2337 return -ENOSPC; 2338 } 2339 2340 int igc_add_mac_steering_filter(struct igc_adapter *adapter, 2341 const u8 *addr, u8 queue, u8 flags) 2342 { 2343 return igc_add_mac_filter_flags(adapter, addr, queue, 2344 IGC_MAC_STATE_QUEUE_STEERING | flags); 2345 } 2346 2347 /* Remove a MAC filter for 'addr' directing matching traffic to 2348 * 'queue', 'flags' is used to indicate what kind of match need to be 2349 * removed, match is by default for the destination address, if 2350 * matching by source address is to be removed the flag 2351 * IGC_MAC_STATE_SRC_ADDR can be used. 2352 */ 2353 static int igc_del_mac_filter_flags(struct igc_adapter *adapter, 2354 const u8 *addr, const u8 queue, 2355 const u8 flags) 2356 { 2357 struct igc_hw *hw = &adapter->hw; 2358 int rar_entries = hw->mac.rar_entry_count; 2359 int i; 2360 2361 if (is_zero_ether_addr(addr)) 2362 return -EINVAL; 2363 2364 /* Search for matching entry in the MAC table based on given address 2365 * and queue. Do not touch entries at the end of the table reserved 2366 * for the VF MAC addresses. 2367 */ 2368 for (i = 0; i < rar_entries; i++) { 2369 if (!(adapter->mac_table[i].state & IGC_MAC_STATE_IN_USE)) 2370 continue; 2371 if ((adapter->mac_table[i].state & flags) != flags) 2372 continue; 2373 if (adapter->mac_table[i].queue != queue) 2374 continue; 2375 if (!ether_addr_equal(adapter->mac_table[i].addr, addr)) 2376 continue; 2377 2378 /* When a filter for the default address is "deleted", 2379 * we return it to its initial configuration 2380 */ 2381 if (adapter->mac_table[i].state & IGC_MAC_STATE_DEFAULT) { 2382 adapter->mac_table[i].state = 2383 IGC_MAC_STATE_DEFAULT | IGC_MAC_STATE_IN_USE; 2384 } else { 2385 adapter->mac_table[i].state = 0; 2386 adapter->mac_table[i].queue = 0; 2387 memset(adapter->mac_table[i].addr, 0, ETH_ALEN); 2388 } 2389 2390 igc_rar_set_index(adapter, i); 2391 return 0; 2392 } 2393 2394 return -ENOENT; 2395 } 2396 2397 int igc_del_mac_steering_filter(struct igc_adapter *adapter, 2398 const u8 *addr, u8 queue, u8 flags) 2399 { 2400 return igc_del_mac_filter_flags(adapter, addr, queue, 2401 IGC_MAC_STATE_QUEUE_STEERING | flags); 2402 } 2403 2404 /** 2405 * igc_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 2406 * @netdev: network interface device structure 2407 * 2408 * The set_rx_mode entry point is called whenever the unicast or multicast 2409 * address lists or the network interface flags are updated. This routine is 2410 * responsible for configuring the hardware for proper unicast, multicast, 2411 * promiscuous mode, and all-multi behavior. 2412 */ 2413 static void igc_set_rx_mode(struct net_device *netdev) 2414 { 2415 } 2416 2417 /** 2418 * igc_msix_other - msix other interrupt handler 2419 * @irq: interrupt number 2420 * @data: pointer to a q_vector 2421 */ 2422 static irqreturn_t igc_msix_other(int irq, void *data) 2423 { 2424 struct igc_adapter *adapter = data; 2425 struct igc_hw *hw = &adapter->hw; 2426 u32 icr = rd32(IGC_ICR); 2427 2428 /* reading ICR causes bit 31 of EICR to be cleared */ 2429 if (icr & IGC_ICR_DRSTA) 2430 schedule_work(&adapter->reset_task); 2431 2432 if (icr & IGC_ICR_DOUTSYNC) { 2433 /* HW is reporting DMA is out of sync */ 2434 adapter->stats.doosync++; 2435 } 2436 2437 if (icr & IGC_ICR_LSC) { 2438 hw->mac.get_link_status = 1; 2439 /* guard against interrupt when we're going down */ 2440 if (!test_bit(__IGC_DOWN, &adapter->state)) 2441 mod_timer(&adapter->watchdog_timer, jiffies + 1); 2442 } 2443 2444 wr32(IGC_EIMS, adapter->eims_other); 2445 2446 return IRQ_HANDLED; 2447 } 2448 2449 /** 2450 * igc_write_ivar - configure ivar for given MSI-X vector 2451 * @hw: pointer to the HW structure 2452 * @msix_vector: vector number we are allocating to a given ring 2453 * @index: row index of IVAR register to write within IVAR table 2454 * @offset: column offset of in IVAR, should be multiple of 8 2455 * 2456 * The IVAR table consists of 2 columns, 2457 * each containing an cause allocation for an Rx and Tx ring, and a 2458 * variable number of rows depending on the number of queues supported. 2459 */ 2460 static void igc_write_ivar(struct igc_hw *hw, int msix_vector, 2461 int index, int offset) 2462 { 2463 u32 ivar = array_rd32(IGC_IVAR0, index); 2464 2465 /* clear any bits that are currently set */ 2466 ivar &= ~((u32)0xFF << offset); 2467 2468 /* write vector and valid bit */ 2469 ivar |= (msix_vector | IGC_IVAR_VALID) << offset; 2470 2471 array_wr32(IGC_IVAR0, index, ivar); 2472 } 2473 2474 static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector) 2475 { 2476 struct igc_adapter *adapter = q_vector->adapter; 2477 struct igc_hw *hw = &adapter->hw; 2478 int rx_queue = IGC_N0_QUEUE; 2479 int tx_queue = IGC_N0_QUEUE; 2480 2481 if (q_vector->rx.ring) 2482 rx_queue = q_vector->rx.ring->reg_idx; 2483 if (q_vector->tx.ring) 2484 tx_queue = q_vector->tx.ring->reg_idx; 2485 2486 switch (hw->mac.type) { 2487 case igc_i225: 2488 if (rx_queue > IGC_N0_QUEUE) 2489 igc_write_ivar(hw, msix_vector, 2490 rx_queue >> 1, 2491 (rx_queue & 0x1) << 4); 2492 if (tx_queue > IGC_N0_QUEUE) 2493 igc_write_ivar(hw, msix_vector, 2494 tx_queue >> 1, 2495 ((tx_queue & 0x1) << 4) + 8); 2496 q_vector->eims_value = BIT(msix_vector); 2497 break; 2498 default: 2499 WARN_ONCE(hw->mac.type != igc_i225, "Wrong MAC type\n"); 2500 break; 2501 } 2502 2503 /* add q_vector eims value to global eims_enable_mask */ 2504 adapter->eims_enable_mask |= q_vector->eims_value; 2505 2506 /* configure q_vector to set itr on first interrupt */ 2507 q_vector->set_itr = 1; 2508 } 2509 2510 /** 2511 * igc_configure_msix - Configure MSI-X hardware 2512 * @adapter: Pointer to adapter structure 2513 * 2514 * igc_configure_msix sets up the hardware to properly 2515 * generate MSI-X interrupts. 2516 */ 2517 static void igc_configure_msix(struct igc_adapter *adapter) 2518 { 2519 struct igc_hw *hw = &adapter->hw; 2520 int i, vector = 0; 2521 u32 tmp; 2522 2523 adapter->eims_enable_mask = 0; 2524 2525 /* set vector for other causes, i.e. link changes */ 2526 switch (hw->mac.type) { 2527 case igc_i225: 2528 /* Turn on MSI-X capability first, or our settings 2529 * won't stick. And it will take days to debug. 2530 */ 2531 wr32(IGC_GPIE, IGC_GPIE_MSIX_MODE | 2532 IGC_GPIE_PBA | IGC_GPIE_EIAME | 2533 IGC_GPIE_NSICR); 2534 2535 /* enable msix_other interrupt */ 2536 adapter->eims_other = BIT(vector); 2537 tmp = (vector++ | IGC_IVAR_VALID) << 8; 2538 2539 wr32(IGC_IVAR_MISC, tmp); 2540 break; 2541 default: 2542 /* do nothing, since nothing else supports MSI-X */ 2543 break; 2544 } /* switch (hw->mac.type) */ 2545 2546 adapter->eims_enable_mask |= adapter->eims_other; 2547 2548 for (i = 0; i < adapter->num_q_vectors; i++) 2549 igc_assign_vector(adapter->q_vector[i], vector++); 2550 2551 wrfl(); 2552 } 2553 2554 static irqreturn_t igc_msix_ring(int irq, void *data) 2555 { 2556 struct igc_q_vector *q_vector = data; 2557 2558 /* Write the ITR value calculated from the previous interrupt. */ 2559 igc_write_itr(q_vector); 2560 2561 napi_schedule(&q_vector->napi); 2562 2563 return IRQ_HANDLED; 2564 } 2565 2566 /** 2567 * igc_request_msix - Initialize MSI-X interrupts 2568 * @adapter: Pointer to adapter structure 2569 * 2570 * igc_request_msix allocates MSI-X vectors and requests interrupts from the 2571 * kernel. 2572 */ 2573 static int igc_request_msix(struct igc_adapter *adapter) 2574 { 2575 int i = 0, err = 0, vector = 0, free_vector = 0; 2576 struct net_device *netdev = adapter->netdev; 2577 2578 err = request_irq(adapter->msix_entries[vector].vector, 2579 &igc_msix_other, 0, netdev->name, adapter); 2580 if (err) 2581 goto err_out; 2582 2583 for (i = 0; i < adapter->num_q_vectors; i++) { 2584 struct igc_q_vector *q_vector = adapter->q_vector[i]; 2585 2586 vector++; 2587 2588 q_vector->itr_register = adapter->io_addr + IGC_EITR(vector); 2589 2590 if (q_vector->rx.ring && q_vector->tx.ring) 2591 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 2592 q_vector->rx.ring->queue_index); 2593 else if (q_vector->tx.ring) 2594 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 2595 q_vector->tx.ring->queue_index); 2596 else if (q_vector->rx.ring) 2597 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 2598 q_vector->rx.ring->queue_index); 2599 else 2600 sprintf(q_vector->name, "%s-unused", netdev->name); 2601 2602 err = request_irq(adapter->msix_entries[vector].vector, 2603 igc_msix_ring, 0, q_vector->name, 2604 q_vector); 2605 if (err) 2606 goto err_free; 2607 } 2608 2609 igc_configure_msix(adapter); 2610 return 0; 2611 2612 err_free: 2613 /* free already assigned IRQs */ 2614 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 2615 2616 vector--; 2617 for (i = 0; i < vector; i++) { 2618 free_irq(adapter->msix_entries[free_vector++].vector, 2619 adapter->q_vector[i]); 2620 } 2621 err_out: 2622 return err; 2623 } 2624 2625 /** 2626 * igc_reset_q_vector - Reset config for interrupt vector 2627 * @adapter: board private structure to initialize 2628 * @v_idx: Index of vector to be reset 2629 * 2630 * If NAPI is enabled it will delete any references to the 2631 * NAPI struct. This is preparation for igc_free_q_vector. 2632 */ 2633 static void igc_reset_q_vector(struct igc_adapter *adapter, int v_idx) 2634 { 2635 struct igc_q_vector *q_vector = adapter->q_vector[v_idx]; 2636 2637 /* if we're coming from igc_set_interrupt_capability, the vectors are 2638 * not yet allocated 2639 */ 2640 if (!q_vector) 2641 return; 2642 2643 if (q_vector->tx.ring) 2644 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 2645 2646 if (q_vector->rx.ring) 2647 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL; 2648 2649 netif_napi_del(&q_vector->napi); 2650 } 2651 2652 static void igc_reset_interrupt_capability(struct igc_adapter *adapter) 2653 { 2654 int v_idx = adapter->num_q_vectors; 2655 2656 if (adapter->msix_entries) { 2657 pci_disable_msix(adapter->pdev); 2658 kfree(adapter->msix_entries); 2659 adapter->msix_entries = NULL; 2660 } else if (adapter->flags & IGC_FLAG_HAS_MSI) { 2661 pci_disable_msi(adapter->pdev); 2662 } 2663 2664 while (v_idx--) 2665 igc_reset_q_vector(adapter, v_idx); 2666 } 2667 2668 /** 2669 * igc_clear_interrupt_scheme - reset the device to a state of no interrupts 2670 * @adapter: Pointer to adapter structure 2671 * 2672 * This function resets the device so that it has 0 rx queues, tx queues, and 2673 * MSI-X interrupts allocated. 2674 */ 2675 static void igc_clear_interrupt_scheme(struct igc_adapter *adapter) 2676 { 2677 igc_free_q_vectors(adapter); 2678 igc_reset_interrupt_capability(adapter); 2679 } 2680 2681 /** 2682 * igc_free_q_vectors - Free memory allocated for interrupt vectors 2683 * @adapter: board private structure to initialize 2684 * 2685 * This function frees the memory allocated to the q_vectors. In addition if 2686 * NAPI is enabled it will delete any references to the NAPI struct prior 2687 * to freeing the q_vector. 2688 */ 2689 static void igc_free_q_vectors(struct igc_adapter *adapter) 2690 { 2691 int v_idx = adapter->num_q_vectors; 2692 2693 adapter->num_tx_queues = 0; 2694 adapter->num_rx_queues = 0; 2695 adapter->num_q_vectors = 0; 2696 2697 while (v_idx--) { 2698 igc_reset_q_vector(adapter, v_idx); 2699 igc_free_q_vector(adapter, v_idx); 2700 } 2701 } 2702 2703 /** 2704 * igc_free_q_vector - Free memory allocated for specific interrupt vector 2705 * @adapter: board private structure to initialize 2706 * @v_idx: Index of vector to be freed 2707 * 2708 * This function frees the memory allocated to the q_vector. 2709 */ 2710 static void igc_free_q_vector(struct igc_adapter *adapter, int v_idx) 2711 { 2712 struct igc_q_vector *q_vector = adapter->q_vector[v_idx]; 2713 2714 adapter->q_vector[v_idx] = NULL; 2715 2716 /* igc_get_stats64() might access the rings on this vector, 2717 * we must wait a grace period before freeing it. 2718 */ 2719 if (q_vector) 2720 kfree_rcu(q_vector, rcu); 2721 } 2722 2723 /* Need to wait a few seconds after link up to get diagnostic information from 2724 * the phy 2725 */ 2726 static void igc_update_phy_info(struct timer_list *t) 2727 { 2728 struct igc_adapter *adapter = from_timer(adapter, t, phy_info_timer); 2729 2730 igc_get_phy_info(&adapter->hw); 2731 } 2732 2733 /** 2734 * igc_has_link - check shared code for link and determine up/down 2735 * @adapter: pointer to driver private info 2736 */ 2737 bool igc_has_link(struct igc_adapter *adapter) 2738 { 2739 struct igc_hw *hw = &adapter->hw; 2740 bool link_active = false; 2741 2742 /* get_link_status is set on LSC (link status) interrupt or 2743 * rx sequence error interrupt. get_link_status will stay 2744 * false until the igc_check_for_link establishes link 2745 * for copper adapters ONLY 2746 */ 2747 switch (hw->phy.media_type) { 2748 case igc_media_type_copper: 2749 if (!hw->mac.get_link_status) 2750 return true; 2751 hw->mac.ops.check_for_link(hw); 2752 link_active = !hw->mac.get_link_status; 2753 break; 2754 default: 2755 case igc_media_type_unknown: 2756 break; 2757 } 2758 2759 if (hw->mac.type == igc_i225 && 2760 hw->phy.id == I225_I_PHY_ID) { 2761 if (!netif_carrier_ok(adapter->netdev)) { 2762 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE; 2763 } else if (!(adapter->flags & IGC_FLAG_NEED_LINK_UPDATE)) { 2764 adapter->flags |= IGC_FLAG_NEED_LINK_UPDATE; 2765 adapter->link_check_timeout = jiffies; 2766 } 2767 } 2768 2769 return link_active; 2770 } 2771 2772 /** 2773 * igc_watchdog - Timer Call-back 2774 * @data: pointer to adapter cast into an unsigned long 2775 */ 2776 static void igc_watchdog(struct timer_list *t) 2777 { 2778 struct igc_adapter *adapter = from_timer(adapter, t, watchdog_timer); 2779 /* Do the rest outside of interrupt context */ 2780 schedule_work(&adapter->watchdog_task); 2781 } 2782 2783 static void igc_watchdog_task(struct work_struct *work) 2784 { 2785 struct igc_adapter *adapter = container_of(work, 2786 struct igc_adapter, 2787 watchdog_task); 2788 struct net_device *netdev = adapter->netdev; 2789 struct igc_hw *hw = &adapter->hw; 2790 struct igc_phy_info *phy = &hw->phy; 2791 u16 phy_data, retry_count = 20; 2792 u32 connsw; 2793 u32 link; 2794 int i; 2795 2796 link = igc_has_link(adapter); 2797 2798 if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE) { 2799 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 2800 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE; 2801 else 2802 link = false; 2803 } 2804 2805 /* Force link down if we have fiber to swap to */ 2806 if (adapter->flags & IGC_FLAG_MAS_ENABLE) { 2807 if (hw->phy.media_type == igc_media_type_copper) { 2808 connsw = rd32(IGC_CONNSW); 2809 if (!(connsw & IGC_CONNSW_AUTOSENSE_EN)) 2810 link = 0; 2811 } 2812 } 2813 if (link) { 2814 if (!netif_carrier_ok(netdev)) { 2815 u32 ctrl; 2816 2817 hw->mac.ops.get_speed_and_duplex(hw, 2818 &adapter->link_speed, 2819 &adapter->link_duplex); 2820 2821 ctrl = rd32(IGC_CTRL); 2822 /* Link status message must follow this format */ 2823 netdev_info(netdev, 2824 "igc: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 2825 netdev->name, 2826 adapter->link_speed, 2827 adapter->link_duplex == FULL_DUPLEX ? 2828 "Full" : "Half", 2829 (ctrl & IGC_CTRL_TFCE) && 2830 (ctrl & IGC_CTRL_RFCE) ? "RX/TX" : 2831 (ctrl & IGC_CTRL_RFCE) ? "RX" : 2832 (ctrl & IGC_CTRL_TFCE) ? "TX" : "None"); 2833 2834 /* check if SmartSpeed worked */ 2835 igc_check_downshift(hw); 2836 if (phy->speed_downgraded) 2837 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 2838 2839 /* adjust timeout factor according to speed/duplex */ 2840 adapter->tx_timeout_factor = 1; 2841 switch (adapter->link_speed) { 2842 case SPEED_10: 2843 adapter->tx_timeout_factor = 14; 2844 break; 2845 case SPEED_100: 2846 /* maybe add some timeout factor ? */ 2847 break; 2848 } 2849 2850 if (adapter->link_speed != SPEED_1000) 2851 goto no_wait; 2852 2853 /* wait for Remote receiver status OK */ 2854 retry_read_status: 2855 if (!igc_read_phy_reg(hw, PHY_1000T_STATUS, 2856 &phy_data)) { 2857 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) && 2858 retry_count) { 2859 msleep(100); 2860 retry_count--; 2861 goto retry_read_status; 2862 } else if (!retry_count) { 2863 dev_err(&adapter->pdev->dev, "exceed max 2 second\n"); 2864 } 2865 } else { 2866 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n"); 2867 } 2868 no_wait: 2869 netif_carrier_on(netdev); 2870 2871 /* link state has changed, schedule phy info update */ 2872 if (!test_bit(__IGC_DOWN, &adapter->state)) 2873 mod_timer(&adapter->phy_info_timer, 2874 round_jiffies(jiffies + 2 * HZ)); 2875 } 2876 } else { 2877 if (netif_carrier_ok(netdev)) { 2878 adapter->link_speed = 0; 2879 adapter->link_duplex = 0; 2880 2881 /* Links status message must follow this format */ 2882 netdev_info(netdev, "igc: %s NIC Link is Down\n", 2883 netdev->name); 2884 netif_carrier_off(netdev); 2885 2886 /* link state has changed, schedule phy info update */ 2887 if (!test_bit(__IGC_DOWN, &adapter->state)) 2888 mod_timer(&adapter->phy_info_timer, 2889 round_jiffies(jiffies + 2 * HZ)); 2890 2891 /* link is down, time to check for alternate media */ 2892 if (adapter->flags & IGC_FLAG_MAS_ENABLE) { 2893 if (adapter->flags & IGC_FLAG_MEDIA_RESET) { 2894 schedule_work(&adapter->reset_task); 2895 /* return immediately */ 2896 return; 2897 } 2898 } 2899 2900 /* also check for alternate media here */ 2901 } else if (!netif_carrier_ok(netdev) && 2902 (adapter->flags & IGC_FLAG_MAS_ENABLE)) { 2903 if (adapter->flags & IGC_FLAG_MEDIA_RESET) { 2904 schedule_work(&adapter->reset_task); 2905 /* return immediately */ 2906 return; 2907 } 2908 } 2909 } 2910 2911 spin_lock(&adapter->stats64_lock); 2912 igc_update_stats(adapter); 2913 spin_unlock(&adapter->stats64_lock); 2914 2915 for (i = 0; i < adapter->num_tx_queues; i++) { 2916 struct igc_ring *tx_ring = adapter->tx_ring[i]; 2917 2918 if (!netif_carrier_ok(netdev)) { 2919 /* We've lost link, so the controller stops DMA, 2920 * but we've got queued Tx work that's never going 2921 * to get done, so reset controller to flush Tx. 2922 * (Do the reset outside of interrupt context). 2923 */ 2924 if (igc_desc_unused(tx_ring) + 1 < tx_ring->count) { 2925 adapter->tx_timeout_count++; 2926 schedule_work(&adapter->reset_task); 2927 /* return immediately since reset is imminent */ 2928 return; 2929 } 2930 } 2931 2932 /* Force detection of hung controller every watchdog period */ 2933 set_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 2934 } 2935 2936 /* Cause software interrupt to ensure Rx ring is cleaned */ 2937 if (adapter->flags & IGC_FLAG_HAS_MSIX) { 2938 u32 eics = 0; 2939 2940 for (i = 0; i < adapter->num_q_vectors; i++) 2941 eics |= adapter->q_vector[i]->eims_value; 2942 wr32(IGC_EICS, eics); 2943 } else { 2944 wr32(IGC_ICS, IGC_ICS_RXDMT0); 2945 } 2946 2947 /* Reset the timer */ 2948 if (!test_bit(__IGC_DOWN, &adapter->state)) { 2949 if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE) 2950 mod_timer(&adapter->watchdog_timer, 2951 round_jiffies(jiffies + HZ)); 2952 else 2953 mod_timer(&adapter->watchdog_timer, 2954 round_jiffies(jiffies + 2 * HZ)); 2955 } 2956 } 2957 2958 /** 2959 * igc_update_ring_itr - update the dynamic ITR value based on packet size 2960 * @q_vector: pointer to q_vector 2961 * 2962 * Stores a new ITR value based on strictly on packet size. This 2963 * algorithm is less sophisticated than that used in igc_update_itr, 2964 * due to the difficulty of synchronizing statistics across multiple 2965 * receive rings. The divisors and thresholds used by this function 2966 * were determined based on theoretical maximum wire speed and testing 2967 * data, in order to minimize response time while increasing bulk 2968 * throughput. 2969 * NOTE: This function is called only when operating in a multiqueue 2970 * receive environment. 2971 */ 2972 static void igc_update_ring_itr(struct igc_q_vector *q_vector) 2973 { 2974 struct igc_adapter *adapter = q_vector->adapter; 2975 int new_val = q_vector->itr_val; 2976 int avg_wire_size = 0; 2977 unsigned int packets; 2978 2979 /* For non-gigabit speeds, just fix the interrupt rate at 4000 2980 * ints/sec - ITR timer value of 120 ticks. 2981 */ 2982 switch (adapter->link_speed) { 2983 case SPEED_10: 2984 case SPEED_100: 2985 new_val = IGC_4K_ITR; 2986 goto set_itr_val; 2987 default: 2988 break; 2989 } 2990 2991 packets = q_vector->rx.total_packets; 2992 if (packets) 2993 avg_wire_size = q_vector->rx.total_bytes / packets; 2994 2995 packets = q_vector->tx.total_packets; 2996 if (packets) 2997 avg_wire_size = max_t(u32, avg_wire_size, 2998 q_vector->tx.total_bytes / packets); 2999 3000 /* if avg_wire_size isn't set no work was done */ 3001 if (!avg_wire_size) 3002 goto clear_counts; 3003 3004 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 3005 avg_wire_size += 24; 3006 3007 /* Don't starve jumbo frames */ 3008 avg_wire_size = min(avg_wire_size, 3000); 3009 3010 /* Give a little boost to mid-size frames */ 3011 if (avg_wire_size > 300 && avg_wire_size < 1200) 3012 new_val = avg_wire_size / 3; 3013 else 3014 new_val = avg_wire_size / 2; 3015 3016 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 3017 if (new_val < IGC_20K_ITR && 3018 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 3019 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 3020 new_val = IGC_20K_ITR; 3021 3022 set_itr_val: 3023 if (new_val != q_vector->itr_val) { 3024 q_vector->itr_val = new_val; 3025 q_vector->set_itr = 1; 3026 } 3027 clear_counts: 3028 q_vector->rx.total_bytes = 0; 3029 q_vector->rx.total_packets = 0; 3030 q_vector->tx.total_bytes = 0; 3031 q_vector->tx.total_packets = 0; 3032 } 3033 3034 /** 3035 * igc_update_itr - update the dynamic ITR value based on statistics 3036 * @q_vector: pointer to q_vector 3037 * @ring_container: ring info to update the itr for 3038 * 3039 * Stores a new ITR value based on packets and byte 3040 * counts during the last interrupt. The advantage of per interrupt 3041 * computation is faster updates and more accurate ITR for the current 3042 * traffic pattern. Constants in this function were computed 3043 * based on theoretical maximum wire speed and thresholds were set based 3044 * on testing data as well as attempting to minimize response time 3045 * while increasing bulk throughput. 3046 * NOTE: These calculations are only valid when operating in a single- 3047 * queue environment. 3048 */ 3049 static void igc_update_itr(struct igc_q_vector *q_vector, 3050 struct igc_ring_container *ring_container) 3051 { 3052 unsigned int packets = ring_container->total_packets; 3053 unsigned int bytes = ring_container->total_bytes; 3054 u8 itrval = ring_container->itr; 3055 3056 /* no packets, exit with status unchanged */ 3057 if (packets == 0) 3058 return; 3059 3060 switch (itrval) { 3061 case lowest_latency: 3062 /* handle TSO and jumbo frames */ 3063 if (bytes / packets > 8000) 3064 itrval = bulk_latency; 3065 else if ((packets < 5) && (bytes > 512)) 3066 itrval = low_latency; 3067 break; 3068 case low_latency: /* 50 usec aka 20000 ints/s */ 3069 if (bytes > 10000) { 3070 /* this if handles the TSO accounting */ 3071 if (bytes / packets > 8000) 3072 itrval = bulk_latency; 3073 else if ((packets < 10) || ((bytes / packets) > 1200)) 3074 itrval = bulk_latency; 3075 else if ((packets > 35)) 3076 itrval = lowest_latency; 3077 } else if (bytes / packets > 2000) { 3078 itrval = bulk_latency; 3079 } else if (packets <= 2 && bytes < 512) { 3080 itrval = lowest_latency; 3081 } 3082 break; 3083 case bulk_latency: /* 250 usec aka 4000 ints/s */ 3084 if (bytes > 25000) { 3085 if (packets > 35) 3086 itrval = low_latency; 3087 } else if (bytes < 1500) { 3088 itrval = low_latency; 3089 } 3090 break; 3091 } 3092 3093 /* clear work counters since we have the values we need */ 3094 ring_container->total_bytes = 0; 3095 ring_container->total_packets = 0; 3096 3097 /* write updated itr to ring container */ 3098 ring_container->itr = itrval; 3099 } 3100 3101 /** 3102 * igc_intr_msi - Interrupt Handler 3103 * @irq: interrupt number 3104 * @data: pointer to a network interface device structure 3105 */ 3106 static irqreturn_t igc_intr_msi(int irq, void *data) 3107 { 3108 struct igc_adapter *adapter = data; 3109 struct igc_q_vector *q_vector = adapter->q_vector[0]; 3110 struct igc_hw *hw = &adapter->hw; 3111 /* read ICR disables interrupts using IAM */ 3112 u32 icr = rd32(IGC_ICR); 3113 3114 igc_write_itr(q_vector); 3115 3116 if (icr & IGC_ICR_DRSTA) 3117 schedule_work(&adapter->reset_task); 3118 3119 if (icr & IGC_ICR_DOUTSYNC) { 3120 /* HW is reporting DMA is out of sync */ 3121 adapter->stats.doosync++; 3122 } 3123 3124 if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) { 3125 hw->mac.get_link_status = 1; 3126 if (!test_bit(__IGC_DOWN, &adapter->state)) 3127 mod_timer(&adapter->watchdog_timer, jiffies + 1); 3128 } 3129 3130 napi_schedule(&q_vector->napi); 3131 3132 return IRQ_HANDLED; 3133 } 3134 3135 /** 3136 * igc_intr - Legacy Interrupt Handler 3137 * @irq: interrupt number 3138 * @data: pointer to a network interface device structure 3139 */ 3140 static irqreturn_t igc_intr(int irq, void *data) 3141 { 3142 struct igc_adapter *adapter = data; 3143 struct igc_q_vector *q_vector = adapter->q_vector[0]; 3144 struct igc_hw *hw = &adapter->hw; 3145 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 3146 * need for the IMC write 3147 */ 3148 u32 icr = rd32(IGC_ICR); 3149 3150 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 3151 * not set, then the adapter didn't send an interrupt 3152 */ 3153 if (!(icr & IGC_ICR_INT_ASSERTED)) 3154 return IRQ_NONE; 3155 3156 igc_write_itr(q_vector); 3157 3158 if (icr & IGC_ICR_DRSTA) 3159 schedule_work(&adapter->reset_task); 3160 3161 if (icr & IGC_ICR_DOUTSYNC) { 3162 /* HW is reporting DMA is out of sync */ 3163 adapter->stats.doosync++; 3164 } 3165 3166 if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) { 3167 hw->mac.get_link_status = 1; 3168 /* guard against interrupt when we're going down */ 3169 if (!test_bit(__IGC_DOWN, &adapter->state)) 3170 mod_timer(&adapter->watchdog_timer, jiffies + 1); 3171 } 3172 3173 napi_schedule(&q_vector->napi); 3174 3175 return IRQ_HANDLED; 3176 } 3177 3178 static void igc_set_itr(struct igc_q_vector *q_vector) 3179 { 3180 struct igc_adapter *adapter = q_vector->adapter; 3181 u32 new_itr = q_vector->itr_val; 3182 u8 current_itr = 0; 3183 3184 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 3185 switch (adapter->link_speed) { 3186 case SPEED_10: 3187 case SPEED_100: 3188 current_itr = 0; 3189 new_itr = IGC_4K_ITR; 3190 goto set_itr_now; 3191 default: 3192 break; 3193 } 3194 3195 igc_update_itr(q_vector, &q_vector->tx); 3196 igc_update_itr(q_vector, &q_vector->rx); 3197 3198 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 3199 3200 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 3201 if (current_itr == lowest_latency && 3202 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 3203 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 3204 current_itr = low_latency; 3205 3206 switch (current_itr) { 3207 /* counts and packets in update_itr are dependent on these numbers */ 3208 case lowest_latency: 3209 new_itr = IGC_70K_ITR; /* 70,000 ints/sec */ 3210 break; 3211 case low_latency: 3212 new_itr = IGC_20K_ITR; /* 20,000 ints/sec */ 3213 break; 3214 case bulk_latency: 3215 new_itr = IGC_4K_ITR; /* 4,000 ints/sec */ 3216 break; 3217 default: 3218 break; 3219 } 3220 3221 set_itr_now: 3222 if (new_itr != q_vector->itr_val) { 3223 /* this attempts to bias the interrupt rate towards Bulk 3224 * by adding intermediate steps when interrupt rate is 3225 * increasing 3226 */ 3227 new_itr = new_itr > q_vector->itr_val ? 3228 max((new_itr * q_vector->itr_val) / 3229 (new_itr + (q_vector->itr_val >> 2)), 3230 new_itr) : new_itr; 3231 /* Don't write the value here; it resets the adapter's 3232 * internal timer, and causes us to delay far longer than 3233 * we should between interrupts. Instead, we write the ITR 3234 * value at the beginning of the next interrupt so the timing 3235 * ends up being correct. 3236 */ 3237 q_vector->itr_val = new_itr; 3238 q_vector->set_itr = 1; 3239 } 3240 } 3241 3242 static void igc_ring_irq_enable(struct igc_q_vector *q_vector) 3243 { 3244 struct igc_adapter *adapter = q_vector->adapter; 3245 struct igc_hw *hw = &adapter->hw; 3246 3247 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 3248 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 3249 if (adapter->num_q_vectors == 1) 3250 igc_set_itr(q_vector); 3251 else 3252 igc_update_ring_itr(q_vector); 3253 } 3254 3255 if (!test_bit(__IGC_DOWN, &adapter->state)) { 3256 if (adapter->msix_entries) 3257 wr32(IGC_EIMS, q_vector->eims_value); 3258 else 3259 igc_irq_enable(adapter); 3260 } 3261 } 3262 3263 /** 3264 * igc_poll - NAPI Rx polling callback 3265 * @napi: napi polling structure 3266 * @budget: count of how many packets we should handle 3267 */ 3268 static int igc_poll(struct napi_struct *napi, int budget) 3269 { 3270 struct igc_q_vector *q_vector = container_of(napi, 3271 struct igc_q_vector, 3272 napi); 3273 bool clean_complete = true; 3274 int work_done = 0; 3275 3276 if (q_vector->tx.ring) 3277 clean_complete = igc_clean_tx_irq(q_vector, budget); 3278 3279 if (q_vector->rx.ring) { 3280 int cleaned = igc_clean_rx_irq(q_vector, budget); 3281 3282 work_done += cleaned; 3283 if (cleaned >= budget) 3284 clean_complete = false; 3285 } 3286 3287 /* If all work not completed, return budget and keep polling */ 3288 if (!clean_complete) 3289 return budget; 3290 3291 /* Exit the polling mode, but don't re-enable interrupts if stack might 3292 * poll us due to busy-polling 3293 */ 3294 if (likely(napi_complete_done(napi, work_done))) 3295 igc_ring_irq_enable(q_vector); 3296 3297 return min(work_done, budget - 1); 3298 } 3299 3300 /** 3301 * igc_set_interrupt_capability - set MSI or MSI-X if supported 3302 * @adapter: Pointer to adapter structure 3303 * 3304 * Attempt to configure interrupts using the best available 3305 * capabilities of the hardware and kernel. 3306 */ 3307 static void igc_set_interrupt_capability(struct igc_adapter *adapter, 3308 bool msix) 3309 { 3310 int numvecs, i; 3311 int err; 3312 3313 if (!msix) 3314 goto msi_only; 3315 adapter->flags |= IGC_FLAG_HAS_MSIX; 3316 3317 /* Number of supported queues. */ 3318 adapter->num_rx_queues = adapter->rss_queues; 3319 3320 adapter->num_tx_queues = adapter->rss_queues; 3321 3322 /* start with one vector for every Rx queue */ 3323 numvecs = adapter->num_rx_queues; 3324 3325 /* if Tx handler is separate add 1 for every Tx queue */ 3326 if (!(adapter->flags & IGC_FLAG_QUEUE_PAIRS)) 3327 numvecs += adapter->num_tx_queues; 3328 3329 /* store the number of vectors reserved for queues */ 3330 adapter->num_q_vectors = numvecs; 3331 3332 /* add 1 vector for link status interrupts */ 3333 numvecs++; 3334 3335 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), 3336 GFP_KERNEL); 3337 3338 if (!adapter->msix_entries) 3339 return; 3340 3341 /* populate entry values */ 3342 for (i = 0; i < numvecs; i++) 3343 adapter->msix_entries[i].entry = i; 3344 3345 err = pci_enable_msix_range(adapter->pdev, 3346 adapter->msix_entries, 3347 numvecs, 3348 numvecs); 3349 if (err > 0) 3350 return; 3351 3352 kfree(adapter->msix_entries); 3353 adapter->msix_entries = NULL; 3354 3355 igc_reset_interrupt_capability(adapter); 3356 3357 msi_only: 3358 adapter->flags &= ~IGC_FLAG_HAS_MSIX; 3359 3360 adapter->rss_queues = 1; 3361 adapter->flags |= IGC_FLAG_QUEUE_PAIRS; 3362 adapter->num_rx_queues = 1; 3363 adapter->num_tx_queues = 1; 3364 adapter->num_q_vectors = 1; 3365 if (!pci_enable_msi(adapter->pdev)) 3366 adapter->flags |= IGC_FLAG_HAS_MSI; 3367 } 3368 3369 static void igc_add_ring(struct igc_ring *ring, 3370 struct igc_ring_container *head) 3371 { 3372 head->ring = ring; 3373 head->count++; 3374 } 3375 3376 /** 3377 * igc_alloc_q_vector - Allocate memory for a single interrupt vector 3378 * @adapter: board private structure to initialize 3379 * @v_count: q_vectors allocated on adapter, used for ring interleaving 3380 * @v_idx: index of vector in adapter struct 3381 * @txr_count: total number of Tx rings to allocate 3382 * @txr_idx: index of first Tx ring to allocate 3383 * @rxr_count: total number of Rx rings to allocate 3384 * @rxr_idx: index of first Rx ring to allocate 3385 * 3386 * We allocate one q_vector. If allocation fails we return -ENOMEM. 3387 */ 3388 static int igc_alloc_q_vector(struct igc_adapter *adapter, 3389 unsigned int v_count, unsigned int v_idx, 3390 unsigned int txr_count, unsigned int txr_idx, 3391 unsigned int rxr_count, unsigned int rxr_idx) 3392 { 3393 struct igc_q_vector *q_vector; 3394 struct igc_ring *ring; 3395 int ring_count; 3396 3397 /* igc only supports 1 Tx and/or 1 Rx queue per vector */ 3398 if (txr_count > 1 || rxr_count > 1) 3399 return -ENOMEM; 3400 3401 ring_count = txr_count + rxr_count; 3402 3403 /* allocate q_vector and rings */ 3404 q_vector = adapter->q_vector[v_idx]; 3405 if (!q_vector) 3406 q_vector = kzalloc(struct_size(q_vector, ring, ring_count), 3407 GFP_KERNEL); 3408 else 3409 memset(q_vector, 0, struct_size(q_vector, ring, ring_count)); 3410 if (!q_vector) 3411 return -ENOMEM; 3412 3413 /* initialize NAPI */ 3414 netif_napi_add(adapter->netdev, &q_vector->napi, 3415 igc_poll, 64); 3416 3417 /* tie q_vector and adapter together */ 3418 adapter->q_vector[v_idx] = q_vector; 3419 q_vector->adapter = adapter; 3420 3421 /* initialize work limits */ 3422 q_vector->tx.work_limit = adapter->tx_work_limit; 3423 3424 /* initialize ITR configuration */ 3425 q_vector->itr_register = adapter->io_addr + IGC_EITR(0); 3426 q_vector->itr_val = IGC_START_ITR; 3427 3428 /* initialize pointer to rings */ 3429 ring = q_vector->ring; 3430 3431 /* initialize ITR */ 3432 if (rxr_count) { 3433 /* rx or rx/tx vector */ 3434 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 3435 q_vector->itr_val = adapter->rx_itr_setting; 3436 } else { 3437 /* tx only vector */ 3438 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 3439 q_vector->itr_val = adapter->tx_itr_setting; 3440 } 3441 3442 if (txr_count) { 3443 /* assign generic ring traits */ 3444 ring->dev = &adapter->pdev->dev; 3445 ring->netdev = adapter->netdev; 3446 3447 /* configure backlink on ring */ 3448 ring->q_vector = q_vector; 3449 3450 /* update q_vector Tx values */ 3451 igc_add_ring(ring, &q_vector->tx); 3452 3453 /* apply Tx specific ring traits */ 3454 ring->count = adapter->tx_ring_count; 3455 ring->queue_index = txr_idx; 3456 3457 /* assign ring to adapter */ 3458 adapter->tx_ring[txr_idx] = ring; 3459 3460 /* push pointer to next ring */ 3461 ring++; 3462 } 3463 3464 if (rxr_count) { 3465 /* assign generic ring traits */ 3466 ring->dev = &adapter->pdev->dev; 3467 ring->netdev = adapter->netdev; 3468 3469 /* configure backlink on ring */ 3470 ring->q_vector = q_vector; 3471 3472 /* update q_vector Rx values */ 3473 igc_add_ring(ring, &q_vector->rx); 3474 3475 /* apply Rx specific ring traits */ 3476 ring->count = adapter->rx_ring_count; 3477 ring->queue_index = rxr_idx; 3478 3479 /* assign ring to adapter */ 3480 adapter->rx_ring[rxr_idx] = ring; 3481 } 3482 3483 return 0; 3484 } 3485 3486 /** 3487 * igc_alloc_q_vectors - Allocate memory for interrupt vectors 3488 * @adapter: board private structure to initialize 3489 * 3490 * We allocate one q_vector per queue interrupt. If allocation fails we 3491 * return -ENOMEM. 3492 */ 3493 static int igc_alloc_q_vectors(struct igc_adapter *adapter) 3494 { 3495 int rxr_remaining = adapter->num_rx_queues; 3496 int txr_remaining = adapter->num_tx_queues; 3497 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 3498 int q_vectors = adapter->num_q_vectors; 3499 int err; 3500 3501 if (q_vectors >= (rxr_remaining + txr_remaining)) { 3502 for (; rxr_remaining; v_idx++) { 3503 err = igc_alloc_q_vector(adapter, q_vectors, v_idx, 3504 0, 0, 1, rxr_idx); 3505 3506 if (err) 3507 goto err_out; 3508 3509 /* update counts and index */ 3510 rxr_remaining--; 3511 rxr_idx++; 3512 } 3513 } 3514 3515 for (; v_idx < q_vectors; v_idx++) { 3516 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 3517 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 3518 3519 err = igc_alloc_q_vector(adapter, q_vectors, v_idx, 3520 tqpv, txr_idx, rqpv, rxr_idx); 3521 3522 if (err) 3523 goto err_out; 3524 3525 /* update counts and index */ 3526 rxr_remaining -= rqpv; 3527 txr_remaining -= tqpv; 3528 rxr_idx++; 3529 txr_idx++; 3530 } 3531 3532 return 0; 3533 3534 err_out: 3535 adapter->num_tx_queues = 0; 3536 adapter->num_rx_queues = 0; 3537 adapter->num_q_vectors = 0; 3538 3539 while (v_idx--) 3540 igc_free_q_vector(adapter, v_idx); 3541 3542 return -ENOMEM; 3543 } 3544 3545 /** 3546 * igc_cache_ring_register - Descriptor ring to register mapping 3547 * @adapter: board private structure to initialize 3548 * 3549 * Once we know the feature-set enabled for the device, we'll cache 3550 * the register offset the descriptor ring is assigned to. 3551 */ 3552 static void igc_cache_ring_register(struct igc_adapter *adapter) 3553 { 3554 int i = 0, j = 0; 3555 3556 switch (adapter->hw.mac.type) { 3557 case igc_i225: 3558 /* Fall through */ 3559 default: 3560 for (; i < adapter->num_rx_queues; i++) 3561 adapter->rx_ring[i]->reg_idx = i; 3562 for (; j < adapter->num_tx_queues; j++) 3563 adapter->tx_ring[j]->reg_idx = j; 3564 break; 3565 } 3566 } 3567 3568 /** 3569 * igc_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 3570 * @adapter: Pointer to adapter structure 3571 * 3572 * This function initializes the interrupts and allocates all of the queues. 3573 */ 3574 static int igc_init_interrupt_scheme(struct igc_adapter *adapter, bool msix) 3575 { 3576 struct pci_dev *pdev = adapter->pdev; 3577 int err = 0; 3578 3579 igc_set_interrupt_capability(adapter, msix); 3580 3581 err = igc_alloc_q_vectors(adapter); 3582 if (err) { 3583 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 3584 goto err_alloc_q_vectors; 3585 } 3586 3587 igc_cache_ring_register(adapter); 3588 3589 return 0; 3590 3591 err_alloc_q_vectors: 3592 igc_reset_interrupt_capability(adapter); 3593 return err; 3594 } 3595 3596 static void igc_free_irq(struct igc_adapter *adapter) 3597 { 3598 if (adapter->msix_entries) { 3599 int vector = 0, i; 3600 3601 free_irq(adapter->msix_entries[vector++].vector, adapter); 3602 3603 for (i = 0; i < adapter->num_q_vectors; i++) 3604 free_irq(adapter->msix_entries[vector++].vector, 3605 adapter->q_vector[i]); 3606 } else { 3607 free_irq(adapter->pdev->irq, adapter); 3608 } 3609 } 3610 3611 /** 3612 * igc_irq_disable - Mask off interrupt generation on the NIC 3613 * @adapter: board private structure 3614 */ 3615 static void igc_irq_disable(struct igc_adapter *adapter) 3616 { 3617 struct igc_hw *hw = &adapter->hw; 3618 3619 if (adapter->msix_entries) { 3620 u32 regval = rd32(IGC_EIAM); 3621 3622 wr32(IGC_EIAM, regval & ~adapter->eims_enable_mask); 3623 wr32(IGC_EIMC, adapter->eims_enable_mask); 3624 regval = rd32(IGC_EIAC); 3625 wr32(IGC_EIAC, regval & ~adapter->eims_enable_mask); 3626 } 3627 3628 wr32(IGC_IAM, 0); 3629 wr32(IGC_IMC, ~0); 3630 wrfl(); 3631 3632 if (adapter->msix_entries) { 3633 int vector = 0, i; 3634 3635 synchronize_irq(adapter->msix_entries[vector++].vector); 3636 3637 for (i = 0; i < adapter->num_q_vectors; i++) 3638 synchronize_irq(adapter->msix_entries[vector++].vector); 3639 } else { 3640 synchronize_irq(adapter->pdev->irq); 3641 } 3642 } 3643 3644 /** 3645 * igc_irq_enable - Enable default interrupt generation settings 3646 * @adapter: board private structure 3647 */ 3648 static void igc_irq_enable(struct igc_adapter *adapter) 3649 { 3650 struct igc_hw *hw = &adapter->hw; 3651 3652 if (adapter->msix_entries) { 3653 u32 ims = IGC_IMS_LSC | IGC_IMS_DOUTSYNC | IGC_IMS_DRSTA; 3654 u32 regval = rd32(IGC_EIAC); 3655 3656 wr32(IGC_EIAC, regval | adapter->eims_enable_mask); 3657 regval = rd32(IGC_EIAM); 3658 wr32(IGC_EIAM, regval | adapter->eims_enable_mask); 3659 wr32(IGC_EIMS, adapter->eims_enable_mask); 3660 wr32(IGC_IMS, ims); 3661 } else { 3662 wr32(IGC_IMS, IMS_ENABLE_MASK | IGC_IMS_DRSTA); 3663 wr32(IGC_IAM, IMS_ENABLE_MASK | IGC_IMS_DRSTA); 3664 } 3665 } 3666 3667 /** 3668 * igc_request_irq - initialize interrupts 3669 * @adapter: Pointer to adapter structure 3670 * 3671 * Attempts to configure interrupts using the best available 3672 * capabilities of the hardware and kernel. 3673 */ 3674 static int igc_request_irq(struct igc_adapter *adapter) 3675 { 3676 struct net_device *netdev = adapter->netdev; 3677 struct pci_dev *pdev = adapter->pdev; 3678 int err = 0; 3679 3680 if (adapter->flags & IGC_FLAG_HAS_MSIX) { 3681 err = igc_request_msix(adapter); 3682 if (!err) 3683 goto request_done; 3684 /* fall back to MSI */ 3685 igc_free_all_tx_resources(adapter); 3686 igc_free_all_rx_resources(adapter); 3687 3688 igc_clear_interrupt_scheme(adapter); 3689 err = igc_init_interrupt_scheme(adapter, false); 3690 if (err) 3691 goto request_done; 3692 igc_setup_all_tx_resources(adapter); 3693 igc_setup_all_rx_resources(adapter); 3694 igc_configure(adapter); 3695 } 3696 3697 igc_assign_vector(adapter->q_vector[0], 0); 3698 3699 if (adapter->flags & IGC_FLAG_HAS_MSI) { 3700 err = request_irq(pdev->irq, &igc_intr_msi, 0, 3701 netdev->name, adapter); 3702 if (!err) 3703 goto request_done; 3704 3705 /* fall back to legacy interrupts */ 3706 igc_reset_interrupt_capability(adapter); 3707 adapter->flags &= ~IGC_FLAG_HAS_MSI; 3708 } 3709 3710 err = request_irq(pdev->irq, &igc_intr, IRQF_SHARED, 3711 netdev->name, adapter); 3712 3713 if (err) 3714 dev_err(&pdev->dev, "Error %d getting interrupt\n", 3715 err); 3716 3717 request_done: 3718 return err; 3719 } 3720 3721 static void igc_write_itr(struct igc_q_vector *q_vector) 3722 { 3723 u32 itr_val = q_vector->itr_val & IGC_QVECTOR_MASK; 3724 3725 if (!q_vector->set_itr) 3726 return; 3727 3728 if (!itr_val) 3729 itr_val = IGC_ITR_VAL_MASK; 3730 3731 itr_val |= IGC_EITR_CNT_IGNR; 3732 3733 writel(itr_val, q_vector->itr_register); 3734 q_vector->set_itr = 0; 3735 } 3736 3737 /** 3738 * igc_open - Called when a network interface is made active 3739 * @netdev: network interface device structure 3740 * 3741 * Returns 0 on success, negative value on failure 3742 * 3743 * The open entry point is called when a network interface is made 3744 * active by the system (IFF_UP). At this point all resources needed 3745 * for transmit and receive operations are allocated, the interrupt 3746 * handler is registered with the OS, the watchdog timer is started, 3747 * and the stack is notified that the interface is ready. 3748 */ 3749 static int __igc_open(struct net_device *netdev, bool resuming) 3750 { 3751 struct igc_adapter *adapter = netdev_priv(netdev); 3752 struct igc_hw *hw = &adapter->hw; 3753 int err = 0; 3754 int i = 0; 3755 3756 /* disallow open during test */ 3757 3758 if (test_bit(__IGC_TESTING, &adapter->state)) { 3759 WARN_ON(resuming); 3760 return -EBUSY; 3761 } 3762 3763 netif_carrier_off(netdev); 3764 3765 /* allocate transmit descriptors */ 3766 err = igc_setup_all_tx_resources(adapter); 3767 if (err) 3768 goto err_setup_tx; 3769 3770 /* allocate receive descriptors */ 3771 err = igc_setup_all_rx_resources(adapter); 3772 if (err) 3773 goto err_setup_rx; 3774 3775 igc_power_up_link(adapter); 3776 3777 igc_configure(adapter); 3778 3779 err = igc_request_irq(adapter); 3780 if (err) 3781 goto err_req_irq; 3782 3783 /* Notify the stack of the actual queue counts. */ 3784 err = netif_set_real_num_tx_queues(netdev, adapter->num_tx_queues); 3785 if (err) 3786 goto err_set_queues; 3787 3788 err = netif_set_real_num_rx_queues(netdev, adapter->num_rx_queues); 3789 if (err) 3790 goto err_set_queues; 3791 3792 clear_bit(__IGC_DOWN, &adapter->state); 3793 3794 for (i = 0; i < adapter->num_q_vectors; i++) 3795 napi_enable(&adapter->q_vector[i]->napi); 3796 3797 /* Clear any pending interrupts. */ 3798 rd32(IGC_ICR); 3799 igc_irq_enable(adapter); 3800 3801 netif_tx_start_all_queues(netdev); 3802 3803 /* start the watchdog. */ 3804 hw->mac.get_link_status = 1; 3805 schedule_work(&adapter->watchdog_task); 3806 3807 return IGC_SUCCESS; 3808 3809 err_set_queues: 3810 igc_free_irq(adapter); 3811 err_req_irq: 3812 igc_release_hw_control(adapter); 3813 igc_power_down_link(adapter); 3814 igc_free_all_rx_resources(adapter); 3815 err_setup_rx: 3816 igc_free_all_tx_resources(adapter); 3817 err_setup_tx: 3818 igc_reset(adapter); 3819 3820 return err; 3821 } 3822 3823 static int igc_open(struct net_device *netdev) 3824 { 3825 return __igc_open(netdev, false); 3826 } 3827 3828 /** 3829 * igc_close - Disables a network interface 3830 * @netdev: network interface device structure 3831 * 3832 * Returns 0, this is not allowed to fail 3833 * 3834 * The close entry point is called when an interface is de-activated 3835 * by the OS. The hardware is still under the driver's control, but 3836 * needs to be disabled. A global MAC reset is issued to stop the 3837 * hardware, and all transmit and receive resources are freed. 3838 */ 3839 static int __igc_close(struct net_device *netdev, bool suspending) 3840 { 3841 struct igc_adapter *adapter = netdev_priv(netdev); 3842 3843 WARN_ON(test_bit(__IGC_RESETTING, &adapter->state)); 3844 3845 igc_down(adapter); 3846 3847 igc_release_hw_control(adapter); 3848 3849 igc_free_irq(adapter); 3850 3851 igc_free_all_tx_resources(adapter); 3852 igc_free_all_rx_resources(adapter); 3853 3854 return 0; 3855 } 3856 3857 static int igc_close(struct net_device *netdev) 3858 { 3859 if (netif_device_present(netdev) || netdev->dismantle) 3860 return __igc_close(netdev, false); 3861 return 0; 3862 } 3863 3864 static const struct net_device_ops igc_netdev_ops = { 3865 .ndo_open = igc_open, 3866 .ndo_stop = igc_close, 3867 .ndo_start_xmit = igc_xmit_frame, 3868 .ndo_set_mac_address = igc_set_mac, 3869 .ndo_change_mtu = igc_change_mtu, 3870 .ndo_get_stats = igc_get_stats, 3871 .ndo_fix_features = igc_fix_features, 3872 .ndo_set_features = igc_set_features, 3873 .ndo_features_check = igc_features_check, 3874 }; 3875 3876 /* PCIe configuration access */ 3877 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value) 3878 { 3879 struct igc_adapter *adapter = hw->back; 3880 3881 pci_read_config_word(adapter->pdev, reg, value); 3882 } 3883 3884 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value) 3885 { 3886 struct igc_adapter *adapter = hw->back; 3887 3888 pci_write_config_word(adapter->pdev, reg, *value); 3889 } 3890 3891 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value) 3892 { 3893 struct igc_adapter *adapter = hw->back; 3894 u16 cap_offset; 3895 3896 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); 3897 if (!cap_offset) 3898 return -IGC_ERR_CONFIG; 3899 3900 pci_read_config_word(adapter->pdev, cap_offset + reg, value); 3901 3902 return IGC_SUCCESS; 3903 } 3904 3905 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value) 3906 { 3907 struct igc_adapter *adapter = hw->back; 3908 u16 cap_offset; 3909 3910 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); 3911 if (!cap_offset) 3912 return -IGC_ERR_CONFIG; 3913 3914 pci_write_config_word(adapter->pdev, cap_offset + reg, *value); 3915 3916 return IGC_SUCCESS; 3917 } 3918 3919 u32 igc_rd32(struct igc_hw *hw, u32 reg) 3920 { 3921 struct igc_adapter *igc = container_of(hw, struct igc_adapter, hw); 3922 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr); 3923 u32 value = 0; 3924 3925 if (IGC_REMOVED(hw_addr)) 3926 return ~value; 3927 3928 value = readl(&hw_addr[reg]); 3929 3930 /* reads should not return all F's */ 3931 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 3932 struct net_device *netdev = igc->netdev; 3933 3934 hw->hw_addr = NULL; 3935 netif_device_detach(netdev); 3936 netdev_err(netdev, "PCIe link lost, device now detached\n"); 3937 } 3938 3939 return value; 3940 } 3941 3942 int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx) 3943 { 3944 struct pci_dev *pdev = adapter->pdev; 3945 struct igc_mac_info *mac = &adapter->hw.mac; 3946 3947 mac->autoneg = 0; 3948 3949 /* Make sure dplx is at most 1 bit and lsb of speed is not set 3950 * for the switch() below to work 3951 */ 3952 if ((spd & 1) || (dplx & ~1)) 3953 goto err_inval; 3954 3955 switch (spd + dplx) { 3956 case SPEED_10 + DUPLEX_HALF: 3957 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3958 break; 3959 case SPEED_10 + DUPLEX_FULL: 3960 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3961 break; 3962 case SPEED_100 + DUPLEX_HALF: 3963 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3964 break; 3965 case SPEED_100 + DUPLEX_FULL: 3966 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3967 break; 3968 case SPEED_1000 + DUPLEX_FULL: 3969 mac->autoneg = 1; 3970 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 3971 break; 3972 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 3973 goto err_inval; 3974 case SPEED_2500 + DUPLEX_FULL: 3975 mac->autoneg = 1; 3976 adapter->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL; 3977 break; 3978 case SPEED_2500 + DUPLEX_HALF: /* not supported */ 3979 default: 3980 goto err_inval; 3981 } 3982 3983 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 3984 adapter->hw.phy.mdix = AUTO_ALL_MODES; 3985 3986 return 0; 3987 3988 err_inval: 3989 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 3990 return -EINVAL; 3991 } 3992 3993 /** 3994 * igc_probe - Device Initialization Routine 3995 * @pdev: PCI device information struct 3996 * @ent: entry in igc_pci_tbl 3997 * 3998 * Returns 0 on success, negative on failure 3999 * 4000 * igc_probe initializes an adapter identified by a pci_dev structure. 4001 * The OS initialization, configuring the adapter private structure, 4002 * and a hardware reset occur. 4003 */ 4004 static int igc_probe(struct pci_dev *pdev, 4005 const struct pci_device_id *ent) 4006 { 4007 struct igc_adapter *adapter; 4008 struct net_device *netdev; 4009 struct igc_hw *hw; 4010 const struct igc_info *ei = igc_info_tbl[ent->driver_data]; 4011 int err; 4012 4013 err = pci_enable_device_mem(pdev); 4014 if (err) 4015 return err; 4016 4017 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 4018 if (!err) { 4019 err = dma_set_coherent_mask(&pdev->dev, 4020 DMA_BIT_MASK(64)); 4021 } else { 4022 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 4023 if (err) { 4024 err = dma_set_coherent_mask(&pdev->dev, 4025 DMA_BIT_MASK(32)); 4026 if (err) { 4027 dev_err(&pdev->dev, "igc: Wrong DMA config\n"); 4028 goto err_dma; 4029 } 4030 } 4031 } 4032 4033 err = pci_request_selected_regions(pdev, 4034 pci_select_bars(pdev, 4035 IORESOURCE_MEM), 4036 igc_driver_name); 4037 if (err) 4038 goto err_pci_reg; 4039 4040 pci_enable_pcie_error_reporting(pdev); 4041 4042 pci_set_master(pdev); 4043 4044 err = -ENOMEM; 4045 netdev = alloc_etherdev_mq(sizeof(struct igc_adapter), 4046 IGC_MAX_TX_QUEUES); 4047 4048 if (!netdev) 4049 goto err_alloc_etherdev; 4050 4051 SET_NETDEV_DEV(netdev, &pdev->dev); 4052 4053 pci_set_drvdata(pdev, netdev); 4054 adapter = netdev_priv(netdev); 4055 adapter->netdev = netdev; 4056 adapter->pdev = pdev; 4057 hw = &adapter->hw; 4058 hw->back = adapter; 4059 adapter->port_num = hw->bus.func; 4060 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 4061 4062 err = pci_save_state(pdev); 4063 if (err) 4064 goto err_ioremap; 4065 4066 err = -EIO; 4067 adapter->io_addr = ioremap(pci_resource_start(pdev, 0), 4068 pci_resource_len(pdev, 0)); 4069 if (!adapter->io_addr) 4070 goto err_ioremap; 4071 4072 /* hw->hw_addr can be zeroed, so use adapter->io_addr for unmap */ 4073 hw->hw_addr = adapter->io_addr; 4074 4075 netdev->netdev_ops = &igc_netdev_ops; 4076 igc_set_ethtool_ops(netdev); 4077 netdev->watchdog_timeo = 5 * HZ; 4078 4079 netdev->mem_start = pci_resource_start(pdev, 0); 4080 netdev->mem_end = pci_resource_end(pdev, 0); 4081 4082 /* PCI config space info */ 4083 hw->vendor_id = pdev->vendor; 4084 hw->device_id = pdev->device; 4085 hw->revision_id = pdev->revision; 4086 hw->subsystem_vendor_id = pdev->subsystem_vendor; 4087 hw->subsystem_device_id = pdev->subsystem_device; 4088 4089 /* Copy the default MAC and PHY function pointers */ 4090 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 4091 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 4092 4093 /* Initialize skew-specific constants */ 4094 err = ei->get_invariants(hw); 4095 if (err) 4096 goto err_sw_init; 4097 4098 /* setup the private structure */ 4099 err = igc_sw_init(adapter); 4100 if (err) 4101 goto err_sw_init; 4102 4103 /* copy netdev features into list of user selectable features */ 4104 netdev->hw_features |= NETIF_F_NTUPLE; 4105 4106 /* MTU range: 68 - 9216 */ 4107 netdev->min_mtu = ETH_MIN_MTU; 4108 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE; 4109 4110 /* before reading the NVM, reset the controller to put the device in a 4111 * known good starting state 4112 */ 4113 hw->mac.ops.reset_hw(hw); 4114 4115 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) { 4116 /* copy the MAC address out of the NVM */ 4117 if (hw->mac.ops.read_mac_addr(hw)) 4118 dev_err(&pdev->dev, "NVM Read Error\n"); 4119 } 4120 4121 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 4122 4123 if (!is_valid_ether_addr(netdev->dev_addr)) { 4124 dev_err(&pdev->dev, "Invalid MAC Address\n"); 4125 err = -EIO; 4126 goto err_eeprom; 4127 } 4128 4129 /* configure RXPBSIZE and TXPBSIZE */ 4130 wr32(IGC_RXPBS, I225_RXPBSIZE_DEFAULT); 4131 wr32(IGC_TXPBS, I225_TXPBSIZE_DEFAULT); 4132 4133 timer_setup(&adapter->watchdog_timer, igc_watchdog, 0); 4134 timer_setup(&adapter->phy_info_timer, igc_update_phy_info, 0); 4135 4136 INIT_WORK(&adapter->reset_task, igc_reset_task); 4137 INIT_WORK(&adapter->watchdog_task, igc_watchdog_task); 4138 4139 /* Initialize link properties that are user-changeable */ 4140 adapter->fc_autoneg = true; 4141 hw->mac.autoneg = true; 4142 hw->phy.autoneg_advertised = 0xaf; 4143 4144 hw->fc.requested_mode = igc_fc_default; 4145 hw->fc.current_mode = igc_fc_default; 4146 4147 /* reset the hardware with the new settings */ 4148 igc_reset(adapter); 4149 4150 /* let the f/w know that the h/w is now under the control of the 4151 * driver. 4152 */ 4153 igc_get_hw_control(adapter); 4154 4155 strncpy(netdev->name, "eth%d", IFNAMSIZ); 4156 err = register_netdev(netdev); 4157 if (err) 4158 goto err_register; 4159 4160 /* carrier off reporting is important to ethtool even BEFORE open */ 4161 netif_carrier_off(netdev); 4162 4163 /* Check if Media Autosense is enabled */ 4164 adapter->ei = *ei; 4165 4166 /* print pcie link status and MAC address */ 4167 pcie_print_link_status(pdev); 4168 netdev_info(netdev, "MAC: %pM\n", netdev->dev_addr); 4169 4170 return 0; 4171 4172 err_register: 4173 igc_release_hw_control(adapter); 4174 err_eeprom: 4175 if (!igc_check_reset_block(hw)) 4176 igc_reset_phy(hw); 4177 err_sw_init: 4178 igc_clear_interrupt_scheme(adapter); 4179 iounmap(adapter->io_addr); 4180 err_ioremap: 4181 free_netdev(netdev); 4182 err_alloc_etherdev: 4183 pci_release_selected_regions(pdev, 4184 pci_select_bars(pdev, IORESOURCE_MEM)); 4185 err_pci_reg: 4186 err_dma: 4187 pci_disable_device(pdev); 4188 return err; 4189 } 4190 4191 /** 4192 * igc_remove - Device Removal Routine 4193 * @pdev: PCI device information struct 4194 * 4195 * igc_remove is called by the PCI subsystem to alert the driver 4196 * that it should release a PCI device. This could be caused by a 4197 * Hot-Plug event, or because the driver is going to be removed from 4198 * memory. 4199 */ 4200 static void igc_remove(struct pci_dev *pdev) 4201 { 4202 struct net_device *netdev = pci_get_drvdata(pdev); 4203 struct igc_adapter *adapter = netdev_priv(netdev); 4204 4205 set_bit(__IGC_DOWN, &adapter->state); 4206 4207 del_timer_sync(&adapter->watchdog_timer); 4208 del_timer_sync(&adapter->phy_info_timer); 4209 4210 cancel_work_sync(&adapter->reset_task); 4211 cancel_work_sync(&adapter->watchdog_task); 4212 4213 /* Release control of h/w to f/w. If f/w is AMT enabled, this 4214 * would have already happened in close and is redundant. 4215 */ 4216 igc_release_hw_control(adapter); 4217 unregister_netdev(netdev); 4218 4219 igc_clear_interrupt_scheme(adapter); 4220 pci_iounmap(pdev, adapter->io_addr); 4221 pci_release_mem_regions(pdev); 4222 4223 kfree(adapter->mac_table); 4224 kfree(adapter->shadow_vfta); 4225 free_netdev(netdev); 4226 4227 pci_disable_pcie_error_reporting(pdev); 4228 4229 pci_disable_device(pdev); 4230 } 4231 4232 static struct pci_driver igc_driver = { 4233 .name = igc_driver_name, 4234 .id_table = igc_pci_tbl, 4235 .probe = igc_probe, 4236 .remove = igc_remove, 4237 }; 4238 4239 void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 4240 const u32 max_rss_queues) 4241 { 4242 /* Determine if we need to pair queues. */ 4243 /* If rss_queues > half of max_rss_queues, pair the queues in 4244 * order to conserve interrupts due to limited supply. 4245 */ 4246 if (adapter->rss_queues > (max_rss_queues / 2)) 4247 adapter->flags |= IGC_FLAG_QUEUE_PAIRS; 4248 else 4249 adapter->flags &= ~IGC_FLAG_QUEUE_PAIRS; 4250 } 4251 4252 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter) 4253 { 4254 unsigned int max_rss_queues; 4255 4256 /* Determine the maximum number of RSS queues supported. */ 4257 max_rss_queues = IGC_MAX_RX_QUEUES; 4258 4259 return max_rss_queues; 4260 } 4261 4262 static void igc_init_queue_configuration(struct igc_adapter *adapter) 4263 { 4264 u32 max_rss_queues; 4265 4266 max_rss_queues = igc_get_max_rss_queues(adapter); 4267 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 4268 4269 igc_set_flag_queue_pairs(adapter, max_rss_queues); 4270 } 4271 4272 /** 4273 * igc_sw_init - Initialize general software structures (struct igc_adapter) 4274 * @adapter: board private structure to initialize 4275 * 4276 * igc_sw_init initializes the Adapter private data structure. 4277 * Fields are initialized based on PCI device information and 4278 * OS network device settings (MTU size). 4279 */ 4280 static int igc_sw_init(struct igc_adapter *adapter) 4281 { 4282 struct net_device *netdev = adapter->netdev; 4283 struct pci_dev *pdev = adapter->pdev; 4284 struct igc_hw *hw = &adapter->hw; 4285 4286 int size = sizeof(struct igc_mac_addr) * hw->mac.rar_entry_count; 4287 4288 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 4289 4290 /* set default ring sizes */ 4291 adapter->tx_ring_count = IGC_DEFAULT_TXD; 4292 adapter->rx_ring_count = IGC_DEFAULT_RXD; 4293 4294 /* set default ITR values */ 4295 adapter->rx_itr_setting = IGC_DEFAULT_ITR; 4296 adapter->tx_itr_setting = IGC_DEFAULT_ITR; 4297 4298 /* set default work limits */ 4299 adapter->tx_work_limit = IGC_DEFAULT_TX_WORK; 4300 4301 /* adjust max frame to be at least the size of a standard frame */ 4302 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 4303 VLAN_HLEN; 4304 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 4305 4306 spin_lock_init(&adapter->nfc_lock); 4307 spin_lock_init(&adapter->stats64_lock); 4308 /* Assume MSI-X interrupts, will be checked during IRQ allocation */ 4309 adapter->flags |= IGC_FLAG_HAS_MSIX; 4310 4311 adapter->mac_table = kzalloc(size, GFP_ATOMIC); 4312 if (!adapter->mac_table) 4313 return -ENOMEM; 4314 4315 igc_init_queue_configuration(adapter); 4316 4317 /* This call may decrease the number of queues */ 4318 if (igc_init_interrupt_scheme(adapter, true)) { 4319 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4320 return -ENOMEM; 4321 } 4322 4323 /* Explicitly disable IRQ since the NIC can be in any state. */ 4324 igc_irq_disable(adapter); 4325 4326 set_bit(__IGC_DOWN, &adapter->state); 4327 4328 return 0; 4329 } 4330 4331 /** 4332 * igc_reinit_queues - return error 4333 * @adapter: pointer to adapter structure 4334 */ 4335 int igc_reinit_queues(struct igc_adapter *adapter) 4336 { 4337 struct net_device *netdev = adapter->netdev; 4338 struct pci_dev *pdev = adapter->pdev; 4339 int err = 0; 4340 4341 if (netif_running(netdev)) 4342 igc_close(netdev); 4343 4344 igc_reset_interrupt_capability(adapter); 4345 4346 if (igc_init_interrupt_scheme(adapter, true)) { 4347 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 4348 return -ENOMEM; 4349 } 4350 4351 if (netif_running(netdev)) 4352 err = igc_open(netdev); 4353 4354 return err; 4355 } 4356 4357 /** 4358 * igc_get_hw_dev - return device 4359 * @hw: pointer to hardware structure 4360 * 4361 * used by hardware layer to print debugging information 4362 */ 4363 struct net_device *igc_get_hw_dev(struct igc_hw *hw) 4364 { 4365 struct igc_adapter *adapter = hw->back; 4366 4367 return adapter->netdev; 4368 } 4369 4370 /** 4371 * igc_init_module - Driver Registration Routine 4372 * 4373 * igc_init_module is the first routine called when the driver is 4374 * loaded. All it does is register with the PCI subsystem. 4375 */ 4376 static int __init igc_init_module(void) 4377 { 4378 int ret; 4379 4380 pr_info("%s - version %s\n", 4381 igc_driver_string, igc_driver_version); 4382 4383 pr_info("%s\n", igc_copyright); 4384 4385 ret = pci_register_driver(&igc_driver); 4386 return ret; 4387 } 4388 4389 module_init(igc_init_module); 4390 4391 /** 4392 * igc_exit_module - Driver Exit Cleanup Routine 4393 * 4394 * igc_exit_module is called just before the driver is removed 4395 * from memory. 4396 */ 4397 static void __exit igc_exit_module(void) 4398 { 4399 pci_unregister_driver(&igc_driver); 4400 } 4401 4402 module_exit(igc_exit_module); 4403 /* igc_main.c */ 4404