1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #include <linux/pci.h> 5 #include <linux/delay.h> 6 7 #include "igc_mac.h" 8 #include "igc_hw.h" 9 10 /** 11 * igc_disable_pcie_master - Disables PCI-express master access 12 * @hw: pointer to the HW structure 13 * 14 * Returns 0 (0) if successful, else returns -10 15 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 16 * the master requests to be disabled. 17 * 18 * Disables PCI-Express master access and verifies there are no pending 19 * requests. 20 */ 21 s32 igc_disable_pcie_master(struct igc_hw *hw) 22 { 23 s32 timeout = MASTER_DISABLE_TIMEOUT; 24 s32 ret_val = 0; 25 u32 ctrl; 26 27 ctrl = rd32(IGC_CTRL); 28 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE; 29 wr32(IGC_CTRL, ctrl); 30 31 while (timeout) { 32 if (!(rd32(IGC_STATUS) & 33 IGC_STATUS_GIO_MASTER_ENABLE)) 34 break; 35 usleep_range(2000, 3000); 36 timeout--; 37 } 38 39 if (!timeout) { 40 hw_dbg("Master requests are pending.\n"); 41 ret_val = -IGC_ERR_MASTER_REQUESTS_PENDING; 42 goto out; 43 } 44 45 out: 46 return ret_val; 47 } 48 49 /** 50 * igc_init_rx_addrs - Initialize receive addresses 51 * @hw: pointer to the HW structure 52 * @rar_count: receive address registers 53 * 54 * Setup the receive address registers by setting the base receive address 55 * register to the devices MAC address and clearing all the other receive 56 * address registers to 0. 57 */ 58 void igc_init_rx_addrs(struct igc_hw *hw, u16 rar_count) 59 { 60 u8 mac_addr[ETH_ALEN] = {0}; 61 u32 i; 62 63 /* Setup the receive address */ 64 hw_dbg("Programming MAC Address into RAR[0]\n"); 65 66 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 67 68 /* Zero out the other (rar_entry_count - 1) receive addresses */ 69 hw_dbg("Clearing RAR[1-%u]\n", rar_count - 1); 70 for (i = 1; i < rar_count; i++) 71 hw->mac.ops.rar_set(hw, mac_addr, i); 72 } 73 74 /** 75 * igc_set_fc_watermarks - Set flow control high/low watermarks 76 * @hw: pointer to the HW structure 77 * 78 * Sets the flow control high/low threshold (watermark) registers. If 79 * flow control XON frame transmission is enabled, then set XON frame 80 * transmission as well. 81 */ 82 static s32 igc_set_fc_watermarks(struct igc_hw *hw) 83 { 84 u32 fcrtl = 0, fcrth = 0; 85 86 /* Set the flow control receive threshold registers. Normally, 87 * these registers will be set to a default threshold that may be 88 * adjusted later by the driver's runtime code. However, if the 89 * ability to transmit pause frames is not enabled, then these 90 * registers will be set to 0. 91 */ 92 if (hw->fc.current_mode & igc_fc_tx_pause) { 93 /* We need to set up the Receive Threshold high and low water 94 * marks as well as (optionally) enabling the transmission of 95 * XON frames. 96 */ 97 fcrtl = hw->fc.low_water; 98 if (hw->fc.send_xon) 99 fcrtl |= IGC_FCRTL_XONE; 100 101 fcrth = hw->fc.high_water; 102 } 103 wr32(IGC_FCRTL, fcrtl); 104 wr32(IGC_FCRTH, fcrth); 105 106 return 0; 107 } 108 109 /** 110 * igc_setup_link - Setup flow control and link settings 111 * @hw: pointer to the HW structure 112 * 113 * Determines which flow control settings to use, then configures flow 114 * control. Calls the appropriate media-specific link configuration 115 * function. Assuming the adapter has a valid link partner, a valid link 116 * should be established. Assumes the hardware has previously been reset 117 * and the transmitter and receiver are not enabled. 118 */ 119 s32 igc_setup_link(struct igc_hw *hw) 120 { 121 s32 ret_val = 0; 122 123 /* In the case of the phy reset being blocked, we already have a link. 124 * We do not need to set it up again. 125 */ 126 if (igc_check_reset_block(hw)) 127 goto out; 128 129 /* If requested flow control is set to default, set flow control 130 * to the both 'rx' and 'tx' pause frames. 131 */ 132 if (hw->fc.requested_mode == igc_fc_default) 133 hw->fc.requested_mode = igc_fc_full; 134 135 /* We want to save off the original Flow Control configuration just 136 * in case we get disconnected and then reconnected into a different 137 * hub or switch with different Flow Control capabilities. 138 */ 139 hw->fc.current_mode = hw->fc.requested_mode; 140 141 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 142 143 /* Call the necessary media_type subroutine to configure the link. */ 144 ret_val = hw->mac.ops.setup_physical_interface(hw); 145 if (ret_val) 146 goto out; 147 148 /* Initialize the flow control address, type, and PAUSE timer 149 * registers to their default values. This is done even if flow 150 * control is disabled, because it does not hurt anything to 151 * initialize these registers. 152 */ 153 hw_dbg("Initializing the Flow Control address, type and timer regs\n"); 154 wr32(IGC_FCT, FLOW_CONTROL_TYPE); 155 wr32(IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 156 wr32(IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW); 157 158 wr32(IGC_FCTTV, hw->fc.pause_time); 159 160 ret_val = igc_set_fc_watermarks(hw); 161 162 out: 163 return ret_val; 164 } 165 166 /** 167 * igc_force_mac_fc - Force the MAC's flow control settings 168 * @hw: pointer to the HW structure 169 * 170 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 171 * device control register to reflect the adapter settings. TFCE and RFCE 172 * need to be explicitly set by software when a copper PHY is used because 173 * autonegotiation is managed by the PHY rather than the MAC. Software must 174 * also configure these bits when link is forced on a fiber connection. 175 */ 176 s32 igc_force_mac_fc(struct igc_hw *hw) 177 { 178 s32 ret_val = 0; 179 u32 ctrl; 180 181 ctrl = rd32(IGC_CTRL); 182 183 /* Because we didn't get link via the internal auto-negotiation 184 * mechanism (we either forced link or we got link via PHY 185 * auto-neg), we have to manually enable/disable transmit an 186 * receive flow control. 187 * 188 * The "Case" statement below enables/disable flow control 189 * according to the "hw->fc.current_mode" parameter. 190 * 191 * The possible values of the "fc" parameter are: 192 * 0: Flow control is completely disabled 193 * 1: Rx flow control is enabled (we can receive pause 194 * frames but not send pause frames). 195 * 2: Tx flow control is enabled (we can send pause frames 196 * frames but we do not receive pause frames). 197 * 3: Both Rx and TX flow control (symmetric) is enabled. 198 * other: No other values should be possible at this point. 199 */ 200 hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); 201 202 switch (hw->fc.current_mode) { 203 case igc_fc_none: 204 ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE)); 205 break; 206 case igc_fc_rx_pause: 207 ctrl &= (~IGC_CTRL_TFCE); 208 ctrl |= IGC_CTRL_RFCE; 209 break; 210 case igc_fc_tx_pause: 211 ctrl &= (~IGC_CTRL_RFCE); 212 ctrl |= IGC_CTRL_TFCE; 213 break; 214 case igc_fc_full: 215 ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE); 216 break; 217 default: 218 hw_dbg("Flow control param set incorrectly\n"); 219 ret_val = -IGC_ERR_CONFIG; 220 goto out; 221 } 222 223 wr32(IGC_CTRL, ctrl); 224 225 out: 226 return ret_val; 227 } 228 229 /** 230 * igc_clear_hw_cntrs_base - Clear base hardware counters 231 * @hw: pointer to the HW structure 232 * 233 * Clears the base hardware counters by reading the counter registers. 234 */ 235 void igc_clear_hw_cntrs_base(struct igc_hw *hw) 236 { 237 rd32(IGC_CRCERRS); 238 rd32(IGC_MPC); 239 rd32(IGC_SCC); 240 rd32(IGC_ECOL); 241 rd32(IGC_MCC); 242 rd32(IGC_LATECOL); 243 rd32(IGC_COLC); 244 rd32(IGC_RERC); 245 rd32(IGC_DC); 246 rd32(IGC_RLEC); 247 rd32(IGC_XONRXC); 248 rd32(IGC_XONTXC); 249 rd32(IGC_XOFFRXC); 250 rd32(IGC_XOFFTXC); 251 rd32(IGC_FCRUC); 252 rd32(IGC_GPRC); 253 rd32(IGC_BPRC); 254 rd32(IGC_MPRC); 255 rd32(IGC_GPTC); 256 rd32(IGC_GORCL); 257 rd32(IGC_GORCH); 258 rd32(IGC_GOTCL); 259 rd32(IGC_GOTCH); 260 rd32(IGC_RNBC); 261 rd32(IGC_RUC); 262 rd32(IGC_RFC); 263 rd32(IGC_ROC); 264 rd32(IGC_RJC); 265 rd32(IGC_TORL); 266 rd32(IGC_TORH); 267 rd32(IGC_TOTL); 268 rd32(IGC_TOTH); 269 rd32(IGC_TPR); 270 rd32(IGC_TPT); 271 rd32(IGC_MPTC); 272 rd32(IGC_BPTC); 273 274 rd32(IGC_PRC64); 275 rd32(IGC_PRC127); 276 rd32(IGC_PRC255); 277 rd32(IGC_PRC511); 278 rd32(IGC_PRC1023); 279 rd32(IGC_PRC1522); 280 rd32(IGC_PTC64); 281 rd32(IGC_PTC127); 282 rd32(IGC_PTC255); 283 rd32(IGC_PTC511); 284 rd32(IGC_PTC1023); 285 rd32(IGC_PTC1522); 286 287 rd32(IGC_ALGNERRC); 288 rd32(IGC_RXERRC); 289 rd32(IGC_TNCRS); 290 rd32(IGC_HTDPMC); 291 rd32(IGC_TSCTC); 292 293 rd32(IGC_MGTPRC); 294 rd32(IGC_MGTPDC); 295 rd32(IGC_MGTPTC); 296 297 rd32(IGC_IAC); 298 rd32(IGC_ICRXOC); 299 300 rd32(IGC_ICRXPTC); 301 rd32(IGC_ICRXATC); 302 rd32(IGC_ICTXPTC); 303 rd32(IGC_ICTXATC); 304 rd32(IGC_ICTXQEC); 305 rd32(IGC_ICTXQMTC); 306 rd32(IGC_ICRXDMTC); 307 308 rd32(IGC_RPTHC); 309 rd32(IGC_TLPIC); 310 rd32(IGC_RLPIC); 311 rd32(IGC_HGPTC); 312 rd32(IGC_HGORCL); 313 rd32(IGC_HGORCH); 314 rd32(IGC_HGOTCL); 315 rd32(IGC_HGOTCH); 316 rd32(IGC_LENERRS); 317 } 318 319 /** 320 * igc_rar_set - Set receive address register 321 * @hw: pointer to the HW structure 322 * @addr: pointer to the receive address 323 * @index: receive address array register 324 * 325 * Sets the receive address array register at index to the address passed 326 * in by addr. 327 */ 328 void igc_rar_set(struct igc_hw *hw, u8 *addr, u32 index) 329 { 330 u32 rar_low, rar_high; 331 332 /* HW expects these in little endian so we reverse the byte order 333 * from network order (big endian) to little endian 334 */ 335 rar_low = ((u32)addr[0] | 336 ((u32)addr[1] << 8) | 337 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 338 339 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 340 341 /* If MAC address zero, no need to set the AV bit */ 342 if (rar_low || rar_high) 343 rar_high |= IGC_RAH_AV; 344 345 /* Some bridges will combine consecutive 32-bit writes into 346 * a single burst write, which will malfunction on some parts. 347 * The flushes avoid this. 348 */ 349 wr32(IGC_RAL(index), rar_low); 350 wrfl(); 351 wr32(IGC_RAH(index), rar_high); 352 wrfl(); 353 } 354 355 /** 356 * igc_check_for_copper_link - Check for link (Copper) 357 * @hw: pointer to the HW structure 358 * 359 * Checks to see of the link status of the hardware has changed. If a 360 * change in link status has been detected, then we read the PHY registers 361 * to get the current speed/duplex if link exists. 362 */ 363 s32 igc_check_for_copper_link(struct igc_hw *hw) 364 { 365 struct igc_mac_info *mac = &hw->mac; 366 s32 ret_val; 367 bool link; 368 369 /* We only want to go out to the PHY registers to see if Auto-Neg 370 * has completed and/or if our link status has changed. The 371 * get_link_status flag is set upon receiving a Link Status 372 * Change or Rx Sequence Error interrupt. 373 */ 374 if (!mac->get_link_status) { 375 ret_val = 0; 376 goto out; 377 } 378 379 /* First we want to see if the MII Status Register reports 380 * link. If so, then we want to get the current speed/duplex 381 * of the PHY. 382 */ 383 ret_val = igc_phy_has_link(hw, 1, 0, &link); 384 if (ret_val) 385 goto out; 386 387 if (!link) 388 goto out; /* No link detected */ 389 390 mac->get_link_status = false; 391 392 /* Check if there was DownShift, must be checked 393 * immediately after link-up 394 */ 395 igc_check_downshift(hw); 396 397 /* If we are forcing speed/duplex, then we simply return since 398 * we have already determined whether we have link or not. 399 */ 400 if (!mac->autoneg) { 401 ret_val = -IGC_ERR_CONFIG; 402 goto out; 403 } 404 405 /* Auto-Neg is enabled. Auto Speed Detection takes care 406 * of MAC speed/duplex configuration. So we only need to 407 * configure Collision Distance in the MAC. 408 */ 409 igc_config_collision_dist(hw); 410 411 /* Configure Flow Control now that Auto-Neg has completed. 412 * First, we need to restore the desired flow control 413 * settings because we may have had to re-autoneg with a 414 * different link partner. 415 */ 416 ret_val = igc_config_fc_after_link_up(hw); 417 if (ret_val) 418 hw_dbg("Error configuring flow control\n"); 419 420 out: 421 /* Now that we are aware of our link settings, we can set the LTR 422 * thresholds. 423 */ 424 ret_val = igc_set_ltr_i225(hw, link); 425 426 return ret_val; 427 } 428 429 /** 430 * igc_config_collision_dist - Configure collision distance 431 * @hw: pointer to the HW structure 432 * 433 * Configures the collision distance to the default value and is used 434 * during link setup. Currently no func pointer exists and all 435 * implementations are handled in the generic version of this function. 436 */ 437 void igc_config_collision_dist(struct igc_hw *hw) 438 { 439 u32 tctl; 440 441 tctl = rd32(IGC_TCTL); 442 443 tctl &= ~IGC_TCTL_COLD; 444 tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT; 445 446 wr32(IGC_TCTL, tctl); 447 wrfl(); 448 } 449 450 /** 451 * igc_config_fc_after_link_up - Configures flow control after link 452 * @hw: pointer to the HW structure 453 * 454 * Checks the status of auto-negotiation after link up to ensure that the 455 * speed and duplex were not forced. If the link needed to be forced, then 456 * flow control needs to be forced also. If auto-negotiation is enabled 457 * and did not fail, then we configure flow control based on our link 458 * partner. 459 */ 460 s32 igc_config_fc_after_link_up(struct igc_hw *hw) 461 { 462 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 463 struct igc_mac_info *mac = &hw->mac; 464 u16 speed, duplex; 465 s32 ret_val = 0; 466 467 /* Check for the case where we have fiber media and auto-neg failed 468 * so we had to force link. In this case, we need to force the 469 * configuration of the MAC to match the "fc" parameter. 470 */ 471 if (mac->autoneg_failed) 472 ret_val = igc_force_mac_fc(hw); 473 474 if (ret_val) { 475 hw_dbg("Error forcing flow control settings\n"); 476 goto out; 477 } 478 479 /* Check for the case where we have copper media and auto-neg is 480 * enabled. In this case, we need to check and see if Auto-Neg 481 * has completed, and if so, how the PHY and link partner has 482 * flow control configured. 483 */ 484 if (mac->autoneg) { 485 /* Read the MII Status Register and check to see if AutoNeg 486 * has completed. We read this twice because this reg has 487 * some "sticky" (latched) bits. 488 */ 489 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, 490 &mii_status_reg); 491 if (ret_val) 492 goto out; 493 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, 494 &mii_status_reg); 495 if (ret_val) 496 goto out; 497 498 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 499 hw_dbg("Copper PHY and Auto Neg has not completed.\n"); 500 goto out; 501 } 502 503 /* The AutoNeg process has completed, so we now need to 504 * read both the Auto Negotiation Advertisement 505 * Register (Address 4) and the Auto_Negotiation Base 506 * Page Ability Register (Address 5) to determine how 507 * flow control was negotiated. 508 */ 509 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 510 &mii_nway_adv_reg); 511 if (ret_val) 512 goto out; 513 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 514 &mii_nway_lp_ability_reg); 515 if (ret_val) 516 goto out; 517 /* Two bits in the Auto Negotiation Advertisement Register 518 * (Address 4) and two bits in the Auto Negotiation Base 519 * Page Ability Register (Address 5) determine flow control 520 * for both the PHY and the link partner. The following 521 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 522 * 1999, describes these PAUSE resolution bits and how flow 523 * control is determined based upon these settings. 524 * NOTE: DC = Don't Care 525 * 526 * LOCAL DEVICE | LINK PARTNER 527 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 528 *-------|---------|-------|---------|-------------------- 529 * 0 | 0 | DC | DC | igc_fc_none 530 * 0 | 1 | 0 | DC | igc_fc_none 531 * 0 | 1 | 1 | 0 | igc_fc_none 532 * 0 | 1 | 1 | 1 | igc_fc_tx_pause 533 * 1 | 0 | 0 | DC | igc_fc_none 534 * 1 | DC | 1 | DC | igc_fc_full 535 * 1 | 1 | 0 | 0 | igc_fc_none 536 * 1 | 1 | 0 | 1 | igc_fc_rx_pause 537 * 538 * Are both PAUSE bits set to 1? If so, this implies 539 * Symmetric Flow Control is enabled at both ends. The 540 * ASM_DIR bits are irrelevant per the spec. 541 * 542 * For Symmetric Flow Control: 543 * 544 * LOCAL DEVICE | LINK PARTNER 545 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 546 *-------|---------|-------|---------|-------------------- 547 * 1 | DC | 1 | DC | IGC_fc_full 548 * 549 */ 550 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 551 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 552 /* Now we need to check if the user selected RX ONLY 553 * of pause frames. In this case, we had to advertise 554 * FULL flow control because we could not advertise RX 555 * ONLY. Hence, we must now check to see if we need to 556 * turn OFF the TRANSMISSION of PAUSE frames. 557 */ 558 if (hw->fc.requested_mode == igc_fc_full) { 559 hw->fc.current_mode = igc_fc_full; 560 hw_dbg("Flow Control = FULL.\n"); 561 } else { 562 hw->fc.current_mode = igc_fc_rx_pause; 563 hw_dbg("Flow Control = RX PAUSE frames only.\n"); 564 } 565 } 566 567 /* For receiving PAUSE frames ONLY. 568 * 569 * LOCAL DEVICE | LINK PARTNER 570 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 571 *-------|---------|-------|---------|-------------------- 572 * 0 | 1 | 1 | 1 | igc_fc_tx_pause 573 */ 574 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 575 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 576 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 577 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 578 hw->fc.current_mode = igc_fc_tx_pause; 579 hw_dbg("Flow Control = TX PAUSE frames only.\n"); 580 } 581 /* For transmitting PAUSE frames ONLY. 582 * 583 * LOCAL DEVICE | LINK PARTNER 584 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 585 *-------|---------|-------|---------|-------------------- 586 * 1 | 1 | 0 | 1 | igc_fc_rx_pause 587 */ 588 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 589 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 590 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 591 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 592 hw->fc.current_mode = igc_fc_rx_pause; 593 hw_dbg("Flow Control = RX PAUSE frames only.\n"); 594 } 595 /* Per the IEEE spec, at this point flow control should be 596 * disabled. However, we want to consider that we could 597 * be connected to a legacy switch that doesn't advertise 598 * desired flow control, but can be forced on the link 599 * partner. So if we advertised no flow control, that is 600 * what we will resolve to. If we advertised some kind of 601 * receive capability (Rx Pause Only or Full Flow Control) 602 * and the link partner advertised none, we will configure 603 * ourselves to enable Rx Flow Control only. We can do 604 * this safely for two reasons: If the link partner really 605 * didn't want flow control enabled, and we enable Rx, no 606 * harm done since we won't be receiving any PAUSE frames 607 * anyway. If the intent on the link partner was to have 608 * flow control enabled, then by us enabling RX only, we 609 * can at least receive pause frames and process them. 610 * This is a good idea because in most cases, since we are 611 * predominantly a server NIC, more times than not we will 612 * be asked to delay transmission of packets than asking 613 * our link partner to pause transmission of frames. 614 */ 615 else if ((hw->fc.requested_mode == igc_fc_none) || 616 (hw->fc.requested_mode == igc_fc_tx_pause) || 617 (hw->fc.strict_ieee)) { 618 hw->fc.current_mode = igc_fc_none; 619 hw_dbg("Flow Control = NONE.\n"); 620 } else { 621 hw->fc.current_mode = igc_fc_rx_pause; 622 hw_dbg("Flow Control = RX PAUSE frames only.\n"); 623 } 624 625 /* Now we need to do one last check... If we auto- 626 * negotiated to HALF DUPLEX, flow control should not be 627 * enabled per IEEE 802.3 spec. 628 */ 629 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex); 630 if (ret_val) { 631 hw_dbg("Error getting link speed and duplex\n"); 632 goto out; 633 } 634 635 if (duplex == HALF_DUPLEX) 636 hw->fc.current_mode = igc_fc_none; 637 638 /* Now we call a subroutine to actually force the MAC 639 * controller to use the correct flow control settings. 640 */ 641 ret_val = igc_force_mac_fc(hw); 642 if (ret_val) { 643 hw_dbg("Error forcing flow control settings\n"); 644 goto out; 645 } 646 } 647 648 out: 649 return 0; 650 } 651 652 /** 653 * igc_get_auto_rd_done - Check for auto read completion 654 * @hw: pointer to the HW structure 655 * 656 * Check EEPROM for Auto Read done bit. 657 */ 658 s32 igc_get_auto_rd_done(struct igc_hw *hw) 659 { 660 s32 ret_val = 0; 661 s32 i = 0; 662 663 while (i < AUTO_READ_DONE_TIMEOUT) { 664 if (rd32(IGC_EECD) & IGC_EECD_AUTO_RD) 665 break; 666 usleep_range(1000, 2000); 667 i++; 668 } 669 670 if (i == AUTO_READ_DONE_TIMEOUT) { 671 hw_dbg("Auto read by HW from NVM has not completed.\n"); 672 ret_val = -IGC_ERR_RESET; 673 goto out; 674 } 675 676 out: 677 return ret_val; 678 } 679 680 /** 681 * igc_get_speed_and_duplex_copper - Retrieve current speed/duplex 682 * @hw: pointer to the HW structure 683 * @speed: stores the current speed 684 * @duplex: stores the current duplex 685 * 686 * Read the status register for the current speed/duplex and store the current 687 * speed and duplex for copper connections. 688 */ 689 s32 igc_get_speed_and_duplex_copper(struct igc_hw *hw, u16 *speed, 690 u16 *duplex) 691 { 692 u32 status; 693 694 status = rd32(IGC_STATUS); 695 if (status & IGC_STATUS_SPEED_1000) { 696 /* For I225, STATUS will indicate 1G speed in both 1 Gbps 697 * and 2.5 Gbps link modes. An additional bit is used 698 * to differentiate between 1 Gbps and 2.5 Gbps. 699 */ 700 if (hw->mac.type == igc_i225 && 701 (status & IGC_STATUS_SPEED_2500)) { 702 *speed = SPEED_2500; 703 hw_dbg("2500 Mbs, "); 704 } else { 705 *speed = SPEED_1000; 706 hw_dbg("1000 Mbs, "); 707 } 708 } else if (status & IGC_STATUS_SPEED_100) { 709 *speed = SPEED_100; 710 hw_dbg("100 Mbs, "); 711 } else { 712 *speed = SPEED_10; 713 hw_dbg("10 Mbs, "); 714 } 715 716 if (status & IGC_STATUS_FD) { 717 *duplex = FULL_DUPLEX; 718 hw_dbg("Full Duplex\n"); 719 } else { 720 *duplex = HALF_DUPLEX; 721 hw_dbg("Half Duplex\n"); 722 } 723 724 return 0; 725 } 726 727 /** 728 * igc_put_hw_semaphore - Release hardware semaphore 729 * @hw: pointer to the HW structure 730 * 731 * Release hardware semaphore used to access the PHY or NVM 732 */ 733 void igc_put_hw_semaphore(struct igc_hw *hw) 734 { 735 u32 swsm; 736 737 swsm = rd32(IGC_SWSM); 738 739 swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI); 740 741 wr32(IGC_SWSM, swsm); 742 } 743 744 /** 745 * igc_enable_mng_pass_thru - Enable processing of ARP's 746 * @hw: pointer to the HW structure 747 * 748 * Verifies the hardware needs to leave interface enabled so that frames can 749 * be directed to and from the management interface. 750 */ 751 bool igc_enable_mng_pass_thru(struct igc_hw *hw) 752 { 753 bool ret_val = false; 754 u32 fwsm, factps; 755 u32 manc; 756 757 if (!hw->mac.asf_firmware_present) 758 goto out; 759 760 manc = rd32(IGC_MANC); 761 762 if (!(manc & IGC_MANC_RCV_TCO_EN)) 763 goto out; 764 765 if (hw->mac.arc_subsystem_valid) { 766 fwsm = rd32(IGC_FWSM); 767 factps = rd32(IGC_FACTPS); 768 769 if (!(factps & IGC_FACTPS_MNGCG) && 770 ((fwsm & IGC_FWSM_MODE_MASK) == 771 (igc_mng_mode_pt << IGC_FWSM_MODE_SHIFT))) { 772 ret_val = true; 773 goto out; 774 } 775 } else { 776 if ((manc & IGC_MANC_SMBUS_EN) && 777 !(manc & IGC_MANC_ASF_EN)) { 778 ret_val = true; 779 goto out; 780 } 781 } 782 783 out: 784 return ret_val; 785 } 786 787 /** 788 * igc_hash_mc_addr - Generate a multicast hash value 789 * @hw: pointer to the HW structure 790 * @mc_addr: pointer to a multicast address 791 * 792 * Generates a multicast address hash value which is used to determine 793 * the multicast filter table array address and new table value. See 794 * igc_mta_set() 795 **/ 796 static u32 igc_hash_mc_addr(struct igc_hw *hw, u8 *mc_addr) 797 { 798 u32 hash_value, hash_mask; 799 u8 bit_shift = 0; 800 801 /* Register count multiplied by bits per register */ 802 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 803 804 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 805 * where 0xFF would still fall within the hash mask. 806 */ 807 while (hash_mask >> bit_shift != 0xFF) 808 bit_shift++; 809 810 /* The portion of the address that is used for the hash table 811 * is determined by the mc_filter_type setting. 812 * The algorithm is such that there is a total of 8 bits of shifting. 813 * The bit_shift for a mc_filter_type of 0 represents the number of 814 * left-shifts where the MSB of mc_addr[5] would still fall within 815 * the hash_mask. Case 0 does this exactly. Since there are a total 816 * of 8 bits of shifting, then mc_addr[4] will shift right the 817 * remaining number of bits. Thus 8 - bit_shift. The rest of the 818 * cases are a variation of this algorithm...essentially raising the 819 * number of bits to shift mc_addr[5] left, while still keeping the 820 * 8-bit shifting total. 821 * 822 * For example, given the following Destination MAC Address and an 823 * MTA register count of 128 (thus a 4096-bit vector and 0xFFF mask), 824 * we can see that the bit_shift for case 0 is 4. These are the hash 825 * values resulting from each mc_filter_type... 826 * [0] [1] [2] [3] [4] [5] 827 * 01 AA 00 12 34 56 828 * LSB MSB 829 * 830 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 831 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 832 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 833 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 834 */ 835 switch (hw->mac.mc_filter_type) { 836 default: 837 case 0: 838 break; 839 case 1: 840 bit_shift += 1; 841 break; 842 case 2: 843 bit_shift += 2; 844 break; 845 case 3: 846 bit_shift += 4; 847 break; 848 } 849 850 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 851 (((u16)mc_addr[5]) << bit_shift))); 852 853 return hash_value; 854 } 855 856 /** 857 * igc_update_mc_addr_list - Update Multicast addresses 858 * @hw: pointer to the HW structure 859 * @mc_addr_list: array of multicast addresses to program 860 * @mc_addr_count: number of multicast addresses to program 861 * 862 * Updates entire Multicast Table Array. 863 * The caller must have a packed mc_addr_list of multicast addresses. 864 **/ 865 void igc_update_mc_addr_list(struct igc_hw *hw, 866 u8 *mc_addr_list, u32 mc_addr_count) 867 { 868 u32 hash_value, hash_bit, hash_reg; 869 int i; 870 871 /* clear mta_shadow */ 872 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 873 874 /* update mta_shadow from mc_addr_list */ 875 for (i = 0; (u32)i < mc_addr_count; i++) { 876 hash_value = igc_hash_mc_addr(hw, mc_addr_list); 877 878 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 879 hash_bit = hash_value & 0x1F; 880 881 hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit); 882 mc_addr_list += ETH_ALEN; 883 } 884 885 /* replace the entire MTA table */ 886 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 887 array_wr32(IGC_MTA, i, hw->mac.mta_shadow[i]); 888 wrfl(); 889 } 890