1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #include <linux/pci.h> 5 #include <linux/delay.h> 6 7 #include "igc_mac.h" 8 #include "igc_hw.h" 9 10 /* forward declaration */ 11 static s32 igc_set_default_fc(struct igc_hw *hw); 12 static s32 igc_set_fc_watermarks(struct igc_hw *hw); 13 14 /** 15 * igc_disable_pcie_master - Disables PCI-express master access 16 * @hw: pointer to the HW structure 17 * 18 * Returns 0 (0) if successful, else returns -10 19 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 20 * the master requests to be disabled. 21 * 22 * Disables PCI-Express master access and verifies there are no pending 23 * requests. 24 */ 25 s32 igc_disable_pcie_master(struct igc_hw *hw) 26 { 27 s32 timeout = MASTER_DISABLE_TIMEOUT; 28 s32 ret_val = 0; 29 u32 ctrl; 30 31 ctrl = rd32(IGC_CTRL); 32 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE; 33 wr32(IGC_CTRL, ctrl); 34 35 while (timeout) { 36 if (!(rd32(IGC_STATUS) & 37 IGC_STATUS_GIO_MASTER_ENABLE)) 38 break; 39 usleep_range(2000, 3000); 40 timeout--; 41 } 42 43 if (!timeout) { 44 hw_dbg("Master requests are pending.\n"); 45 ret_val = -IGC_ERR_MASTER_REQUESTS_PENDING; 46 goto out; 47 } 48 49 out: 50 return ret_val; 51 } 52 53 /** 54 * igc_init_rx_addrs - Initialize receive addresses 55 * @hw: pointer to the HW structure 56 * @rar_count: receive address registers 57 * 58 * Setup the receive address registers by setting the base receive address 59 * register to the devices MAC address and clearing all the other receive 60 * address registers to 0. 61 */ 62 void igc_init_rx_addrs(struct igc_hw *hw, u16 rar_count) 63 { 64 u8 mac_addr[ETH_ALEN] = {0}; 65 u32 i; 66 67 /* Setup the receive address */ 68 hw_dbg("Programming MAC Address into RAR[0]\n"); 69 70 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 71 72 /* Zero out the other (rar_entry_count - 1) receive addresses */ 73 hw_dbg("Clearing RAR[1-%u]\n", rar_count - 1); 74 for (i = 1; i < rar_count; i++) 75 hw->mac.ops.rar_set(hw, mac_addr, i); 76 } 77 78 /** 79 * igc_setup_link - Setup flow control and link settings 80 * @hw: pointer to the HW structure 81 * 82 * Determines which flow control settings to use, then configures flow 83 * control. Calls the appropriate media-specific link configuration 84 * function. Assuming the adapter has a valid link partner, a valid link 85 * should be established. Assumes the hardware has previously been reset 86 * and the transmitter and receiver are not enabled. 87 */ 88 s32 igc_setup_link(struct igc_hw *hw) 89 { 90 s32 ret_val = 0; 91 92 /* In the case of the phy reset being blocked, we already have a link. 93 * We do not need to set it up again. 94 */ 95 if (igc_check_reset_block(hw)) 96 goto out; 97 98 /* If requested flow control is set to default, set flow control 99 * based on the EEPROM flow control settings. 100 */ 101 if (hw->fc.requested_mode == igc_fc_default) { 102 ret_val = igc_set_default_fc(hw); 103 if (ret_val) 104 goto out; 105 } 106 107 /* We want to save off the original Flow Control configuration just 108 * in case we get disconnected and then reconnected into a different 109 * hub or switch with different Flow Control capabilities. 110 */ 111 hw->fc.current_mode = hw->fc.requested_mode; 112 113 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 114 115 /* Call the necessary media_type subroutine to configure the link. */ 116 ret_val = hw->mac.ops.setup_physical_interface(hw); 117 if (ret_val) 118 goto out; 119 120 /* Initialize the flow control address, type, and PAUSE timer 121 * registers to their default values. This is done even if flow 122 * control is disabled, because it does not hurt anything to 123 * initialize these registers. 124 */ 125 hw_dbg("Initializing the Flow Control address, type and timer regs\n"); 126 wr32(IGC_FCT, FLOW_CONTROL_TYPE); 127 wr32(IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 128 wr32(IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW); 129 130 wr32(IGC_FCTTV, hw->fc.pause_time); 131 132 ret_val = igc_set_fc_watermarks(hw); 133 134 out: 135 return ret_val; 136 } 137 138 /** 139 * igc_set_default_fc - Set flow control default values 140 * @hw: pointer to the HW structure 141 * 142 * Read the EEPROM for the default values for flow control and store the 143 * values. 144 */ 145 static s32 igc_set_default_fc(struct igc_hw *hw) 146 { 147 hw->fc.requested_mode = igc_fc_full; 148 return 0; 149 } 150 151 /** 152 * igc_force_mac_fc - Force the MAC's flow control settings 153 * @hw: pointer to the HW structure 154 * 155 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 156 * device control register to reflect the adapter settings. TFCE and RFCE 157 * need to be explicitly set by software when a copper PHY is used because 158 * autonegotiation is managed by the PHY rather than the MAC. Software must 159 * also configure these bits when link is forced on a fiber connection. 160 */ 161 s32 igc_force_mac_fc(struct igc_hw *hw) 162 { 163 s32 ret_val = 0; 164 u32 ctrl; 165 166 ctrl = rd32(IGC_CTRL); 167 168 /* Because we didn't get link via the internal auto-negotiation 169 * mechanism (we either forced link or we got link via PHY 170 * auto-neg), we have to manually enable/disable transmit an 171 * receive flow control. 172 * 173 * The "Case" statement below enables/disable flow control 174 * according to the "hw->fc.current_mode" parameter. 175 * 176 * The possible values of the "fc" parameter are: 177 * 0: Flow control is completely disabled 178 * 1: Rx flow control is enabled (we can receive pause 179 * frames but not send pause frames). 180 * 2: Tx flow control is enabled (we can send pause frames 181 * frames but we do not receive pause frames). 182 * 3: Both Rx and TX flow control (symmetric) is enabled. 183 * other: No other values should be possible at this point. 184 */ 185 hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); 186 187 switch (hw->fc.current_mode) { 188 case igc_fc_none: 189 ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE)); 190 break; 191 case igc_fc_rx_pause: 192 ctrl &= (~IGC_CTRL_TFCE); 193 ctrl |= IGC_CTRL_RFCE; 194 break; 195 case igc_fc_tx_pause: 196 ctrl &= (~IGC_CTRL_RFCE); 197 ctrl |= IGC_CTRL_TFCE; 198 break; 199 case igc_fc_full: 200 ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE); 201 break; 202 default: 203 hw_dbg("Flow control param set incorrectly\n"); 204 ret_val = -IGC_ERR_CONFIG; 205 goto out; 206 } 207 208 wr32(IGC_CTRL, ctrl); 209 210 out: 211 return ret_val; 212 } 213 214 /** 215 * igc_set_fc_watermarks - Set flow control high/low watermarks 216 * @hw: pointer to the HW structure 217 * 218 * Sets the flow control high/low threshold (watermark) registers. If 219 * flow control XON frame transmission is enabled, then set XON frame 220 * transmission as well. 221 */ 222 static s32 igc_set_fc_watermarks(struct igc_hw *hw) 223 { 224 u32 fcrtl = 0, fcrth = 0; 225 226 /* Set the flow control receive threshold registers. Normally, 227 * these registers will be set to a default threshold that may be 228 * adjusted later by the driver's runtime code. However, if the 229 * ability to transmit pause frames is not enabled, then these 230 * registers will be set to 0. 231 */ 232 if (hw->fc.current_mode & igc_fc_tx_pause) { 233 /* We need to set up the Receive Threshold high and low water 234 * marks as well as (optionally) enabling the transmission of 235 * XON frames. 236 */ 237 fcrtl = hw->fc.low_water; 238 if (hw->fc.send_xon) 239 fcrtl |= IGC_FCRTL_XONE; 240 241 fcrth = hw->fc.high_water; 242 } 243 wr32(IGC_FCRTL, fcrtl); 244 wr32(IGC_FCRTH, fcrth); 245 246 return 0; 247 } 248 249 /** 250 * igc_clear_hw_cntrs_base - Clear base hardware counters 251 * @hw: pointer to the HW structure 252 * 253 * Clears the base hardware counters by reading the counter registers. 254 */ 255 void igc_clear_hw_cntrs_base(struct igc_hw *hw) 256 { 257 rd32(IGC_CRCERRS); 258 rd32(IGC_SYMERRS); 259 rd32(IGC_MPC); 260 rd32(IGC_SCC); 261 rd32(IGC_ECOL); 262 rd32(IGC_MCC); 263 rd32(IGC_LATECOL); 264 rd32(IGC_COLC); 265 rd32(IGC_DC); 266 rd32(IGC_SEC); 267 rd32(IGC_RLEC); 268 rd32(IGC_XONRXC); 269 rd32(IGC_XONTXC); 270 rd32(IGC_XOFFRXC); 271 rd32(IGC_XOFFTXC); 272 rd32(IGC_FCRUC); 273 rd32(IGC_GPRC); 274 rd32(IGC_BPRC); 275 rd32(IGC_MPRC); 276 rd32(IGC_GPTC); 277 rd32(IGC_GORCL); 278 rd32(IGC_GORCH); 279 rd32(IGC_GOTCL); 280 rd32(IGC_GOTCH); 281 rd32(IGC_RNBC); 282 rd32(IGC_RUC); 283 rd32(IGC_RFC); 284 rd32(IGC_ROC); 285 rd32(IGC_RJC); 286 rd32(IGC_TORL); 287 rd32(IGC_TORH); 288 rd32(IGC_TOTL); 289 rd32(IGC_TOTH); 290 rd32(IGC_TPR); 291 rd32(IGC_TPT); 292 rd32(IGC_MPTC); 293 rd32(IGC_BPTC); 294 295 rd32(IGC_PRC64); 296 rd32(IGC_PRC127); 297 rd32(IGC_PRC255); 298 rd32(IGC_PRC511); 299 rd32(IGC_PRC1023); 300 rd32(IGC_PRC1522); 301 rd32(IGC_PTC64); 302 rd32(IGC_PTC127); 303 rd32(IGC_PTC255); 304 rd32(IGC_PTC511); 305 rd32(IGC_PTC1023); 306 rd32(IGC_PTC1522); 307 308 rd32(IGC_ALGNERRC); 309 rd32(IGC_RXERRC); 310 rd32(IGC_TNCRS); 311 rd32(IGC_CEXTERR); 312 rd32(IGC_TSCTC); 313 rd32(IGC_TSCTFC); 314 315 rd32(IGC_MGTPRC); 316 rd32(IGC_MGTPDC); 317 rd32(IGC_MGTPTC); 318 319 rd32(IGC_IAC); 320 rd32(IGC_ICRXOC); 321 322 rd32(IGC_ICRXPTC); 323 rd32(IGC_ICRXATC); 324 rd32(IGC_ICTXPTC); 325 rd32(IGC_ICTXATC); 326 rd32(IGC_ICTXQEC); 327 rd32(IGC_ICTXQMTC); 328 rd32(IGC_ICRXDMTC); 329 330 rd32(IGC_CBTMPC); 331 rd32(IGC_HTDPMC); 332 rd32(IGC_CBRMPC); 333 rd32(IGC_RPTHC); 334 rd32(IGC_HGPTC); 335 rd32(IGC_HTCBDPC); 336 rd32(IGC_HGORCL); 337 rd32(IGC_HGORCH); 338 rd32(IGC_HGOTCL); 339 rd32(IGC_HGOTCH); 340 rd32(IGC_LENERRS); 341 } 342 343 /** 344 * igc_rar_set - Set receive address register 345 * @hw: pointer to the HW structure 346 * @addr: pointer to the receive address 347 * @index: receive address array register 348 * 349 * Sets the receive address array register at index to the address passed 350 * in by addr. 351 */ 352 void igc_rar_set(struct igc_hw *hw, u8 *addr, u32 index) 353 { 354 u32 rar_low, rar_high; 355 356 /* HW expects these in little endian so we reverse the byte order 357 * from network order (big endian) to little endian 358 */ 359 rar_low = ((u32)addr[0] | 360 ((u32)addr[1] << 8) | 361 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 362 363 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 364 365 /* If MAC address zero, no need to set the AV bit */ 366 if (rar_low || rar_high) 367 rar_high |= IGC_RAH_AV; 368 369 /* Some bridges will combine consecutive 32-bit writes into 370 * a single burst write, which will malfunction on some parts. 371 * The flushes avoid this. 372 */ 373 wr32(IGC_RAL(index), rar_low); 374 wrfl(); 375 wr32(IGC_RAH(index), rar_high); 376 wrfl(); 377 } 378 379 /** 380 * igc_check_for_copper_link - Check for link (Copper) 381 * @hw: pointer to the HW structure 382 * 383 * Checks to see of the link status of the hardware has changed. If a 384 * change in link status has been detected, then we read the PHY registers 385 * to get the current speed/duplex if link exists. 386 */ 387 s32 igc_check_for_copper_link(struct igc_hw *hw) 388 { 389 struct igc_mac_info *mac = &hw->mac; 390 s32 ret_val; 391 bool link; 392 393 /* We only want to go out to the PHY registers to see if Auto-Neg 394 * has completed and/or if our link status has changed. The 395 * get_link_status flag is set upon receiving a Link Status 396 * Change or Rx Sequence Error interrupt. 397 */ 398 if (!mac->get_link_status) { 399 ret_val = 0; 400 goto out; 401 } 402 403 /* First we want to see if the MII Status Register reports 404 * link. If so, then we want to get the current speed/duplex 405 * of the PHY. 406 */ 407 ret_val = igc_phy_has_link(hw, 1, 0, &link); 408 if (ret_val) 409 goto out; 410 411 if (!link) 412 goto out; /* No link detected */ 413 414 mac->get_link_status = false; 415 416 /* Check if there was DownShift, must be checked 417 * immediately after link-up 418 */ 419 igc_check_downshift(hw); 420 421 /* If we are forcing speed/duplex, then we simply return since 422 * we have already determined whether we have link or not. 423 */ 424 if (!mac->autoneg) { 425 ret_val = -IGC_ERR_CONFIG; 426 goto out; 427 } 428 429 /* Auto-Neg is enabled. Auto Speed Detection takes care 430 * of MAC speed/duplex configuration. So we only need to 431 * configure Collision Distance in the MAC. 432 */ 433 igc_config_collision_dist(hw); 434 435 /* Configure Flow Control now that Auto-Neg has completed. 436 * First, we need to restore the desired flow control 437 * settings because we may have had to re-autoneg with a 438 * different link partner. 439 */ 440 ret_val = igc_config_fc_after_link_up(hw); 441 if (ret_val) 442 hw_dbg("Error configuring flow control\n"); 443 444 out: 445 return ret_val; 446 } 447 448 /** 449 * igc_config_collision_dist - Configure collision distance 450 * @hw: pointer to the HW structure 451 * 452 * Configures the collision distance to the default value and is used 453 * during link setup. Currently no func pointer exists and all 454 * implementations are handled in the generic version of this function. 455 */ 456 void igc_config_collision_dist(struct igc_hw *hw) 457 { 458 u32 tctl; 459 460 tctl = rd32(IGC_TCTL); 461 462 tctl &= ~IGC_TCTL_COLD; 463 tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT; 464 465 wr32(IGC_TCTL, tctl); 466 wrfl(); 467 } 468 469 /** 470 * igc_config_fc_after_link_up - Configures flow control after link 471 * @hw: pointer to the HW structure 472 * 473 * Checks the status of auto-negotiation after link up to ensure that the 474 * speed and duplex were not forced. If the link needed to be forced, then 475 * flow control needs to be forced also. If auto-negotiation is enabled 476 * and did not fail, then we configure flow control based on our link 477 * partner. 478 */ 479 s32 igc_config_fc_after_link_up(struct igc_hw *hw) 480 { 481 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 482 struct igc_mac_info *mac = &hw->mac; 483 u16 speed, duplex; 484 s32 ret_val = 0; 485 486 /* Check for the case where we have fiber media and auto-neg failed 487 * so we had to force link. In this case, we need to force the 488 * configuration of the MAC to match the "fc" parameter. 489 */ 490 if (mac->autoneg_failed) { 491 if (hw->phy.media_type == igc_media_type_copper) 492 ret_val = igc_force_mac_fc(hw); 493 } 494 495 if (ret_val) { 496 hw_dbg("Error forcing flow control settings\n"); 497 goto out; 498 } 499 500 /* Check for the case where we have copper media and auto-neg is 501 * enabled. In this case, we need to check and see if Auto-Neg 502 * has completed, and if so, how the PHY and link partner has 503 * flow control configured. 504 */ 505 if (hw->phy.media_type == igc_media_type_copper && mac->autoneg) { 506 /* Read the MII Status Register and check to see if AutoNeg 507 * has completed. We read this twice because this reg has 508 * some "sticky" (latched) bits. 509 */ 510 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, 511 &mii_status_reg); 512 if (ret_val) 513 goto out; 514 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, 515 &mii_status_reg); 516 if (ret_val) 517 goto out; 518 519 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 520 hw_dbg("Copper PHY and Auto Neg has not completed.\n"); 521 goto out; 522 } 523 524 /* The AutoNeg process has completed, so we now need to 525 * read both the Auto Negotiation Advertisement 526 * Register (Address 4) and the Auto_Negotiation Base 527 * Page Ability Register (Address 5) to determine how 528 * flow control was negotiated. 529 */ 530 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 531 &mii_nway_adv_reg); 532 if (ret_val) 533 goto out; 534 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 535 &mii_nway_lp_ability_reg); 536 if (ret_val) 537 goto out; 538 /* Two bits in the Auto Negotiation Advertisement Register 539 * (Address 4) and two bits in the Auto Negotiation Base 540 * Page Ability Register (Address 5) determine flow control 541 * for both the PHY and the link partner. The following 542 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 543 * 1999, describes these PAUSE resolution bits and how flow 544 * control is determined based upon these settings. 545 * NOTE: DC = Don't Care 546 * 547 * LOCAL DEVICE | LINK PARTNER 548 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 549 *-------|---------|-------|---------|-------------------- 550 * 0 | 0 | DC | DC | igc_fc_none 551 * 0 | 1 | 0 | DC | igc_fc_none 552 * 0 | 1 | 1 | 0 | igc_fc_none 553 * 0 | 1 | 1 | 1 | igc_fc_tx_pause 554 * 1 | 0 | 0 | DC | igc_fc_none 555 * 1 | DC | 1 | DC | igc_fc_full 556 * 1 | 1 | 0 | 0 | igc_fc_none 557 * 1 | 1 | 0 | 1 | igc_fc_rx_pause 558 * 559 * Are both PAUSE bits set to 1? If so, this implies 560 * Symmetric Flow Control is enabled at both ends. The 561 * ASM_DIR bits are irrelevant per the spec. 562 * 563 * For Symmetric Flow Control: 564 * 565 * LOCAL DEVICE | LINK PARTNER 566 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 567 *-------|---------|-------|---------|-------------------- 568 * 1 | DC | 1 | DC | IGC_fc_full 569 * 570 */ 571 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 572 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 573 /* Now we need to check if the user selected RX ONLY 574 * of pause frames. In this case, we had to advertise 575 * FULL flow control because we could not advertise RX 576 * ONLY. Hence, we must now check to see if we need to 577 * turn OFF the TRANSMISSION of PAUSE frames. 578 */ 579 if (hw->fc.requested_mode == igc_fc_full) { 580 hw->fc.current_mode = igc_fc_full; 581 hw_dbg("Flow Control = FULL.\n"); 582 } else { 583 hw->fc.current_mode = igc_fc_rx_pause; 584 hw_dbg("Flow Control = RX PAUSE frames only.\n"); 585 } 586 } 587 588 /* For receiving PAUSE frames ONLY. 589 * 590 * LOCAL DEVICE | LINK PARTNER 591 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 592 *-------|---------|-------|---------|-------------------- 593 * 0 | 1 | 1 | 1 | igc_fc_tx_pause 594 */ 595 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 596 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 597 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 598 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 599 hw->fc.current_mode = igc_fc_tx_pause; 600 hw_dbg("Flow Control = TX PAUSE frames only.\n"); 601 } 602 /* For transmitting PAUSE frames ONLY. 603 * 604 * LOCAL DEVICE | LINK PARTNER 605 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 606 *-------|---------|-------|---------|-------------------- 607 * 1 | 1 | 0 | 1 | igc_fc_rx_pause 608 */ 609 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 610 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 611 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 612 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 613 hw->fc.current_mode = igc_fc_rx_pause; 614 hw_dbg("Flow Control = RX PAUSE frames only.\n"); 615 } 616 /* Per the IEEE spec, at this point flow control should be 617 * disabled. However, we want to consider that we could 618 * be connected to a legacy switch that doesn't advertise 619 * desired flow control, but can be forced on the link 620 * partner. So if we advertised no flow control, that is 621 * what we will resolve to. If we advertised some kind of 622 * receive capability (Rx Pause Only or Full Flow Control) 623 * and the link partner advertised none, we will configure 624 * ourselves to enable Rx Flow Control only. We can do 625 * this safely for two reasons: If the link partner really 626 * didn't want flow control enabled, and we enable Rx, no 627 * harm done since we won't be receiving any PAUSE frames 628 * anyway. If the intent on the link partner was to have 629 * flow control enabled, then by us enabling RX only, we 630 * can at least receive pause frames and process them. 631 * This is a good idea because in most cases, since we are 632 * predominantly a server NIC, more times than not we will 633 * be asked to delay transmission of packets than asking 634 * our link partner to pause transmission of frames. 635 */ 636 else if ((hw->fc.requested_mode == igc_fc_none) || 637 (hw->fc.requested_mode == igc_fc_tx_pause) || 638 (hw->fc.strict_ieee)) { 639 hw->fc.current_mode = igc_fc_none; 640 hw_dbg("Flow Control = NONE.\n"); 641 } else { 642 hw->fc.current_mode = igc_fc_rx_pause; 643 hw_dbg("Flow Control = RX PAUSE frames only.\n"); 644 } 645 646 /* Now we need to do one last check... If we auto- 647 * negotiated to HALF DUPLEX, flow control should not be 648 * enabled per IEEE 802.3 spec. 649 */ 650 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex); 651 if (ret_val) { 652 hw_dbg("Error getting link speed and duplex\n"); 653 goto out; 654 } 655 656 if (duplex == HALF_DUPLEX) 657 hw->fc.current_mode = igc_fc_none; 658 659 /* Now we call a subroutine to actually force the MAC 660 * controller to use the correct flow control settings. 661 */ 662 ret_val = igc_force_mac_fc(hw); 663 if (ret_val) { 664 hw_dbg("Error forcing flow control settings\n"); 665 goto out; 666 } 667 } 668 669 out: 670 return 0; 671 } 672 673 /** 674 * igc_get_auto_rd_done - Check for auto read completion 675 * @hw: pointer to the HW structure 676 * 677 * Check EEPROM for Auto Read done bit. 678 */ 679 s32 igc_get_auto_rd_done(struct igc_hw *hw) 680 { 681 s32 ret_val = 0; 682 s32 i = 0; 683 684 while (i < AUTO_READ_DONE_TIMEOUT) { 685 if (rd32(IGC_EECD) & IGC_EECD_AUTO_RD) 686 break; 687 usleep_range(1000, 2000); 688 i++; 689 } 690 691 if (i == AUTO_READ_DONE_TIMEOUT) { 692 hw_dbg("Auto read by HW from NVM has not completed.\n"); 693 ret_val = -IGC_ERR_RESET; 694 goto out; 695 } 696 697 out: 698 return ret_val; 699 } 700 701 /** 702 * igc_get_speed_and_duplex_copper - Retrieve current speed/duplex 703 * @hw: pointer to the HW structure 704 * @speed: stores the current speed 705 * @duplex: stores the current duplex 706 * 707 * Read the status register for the current speed/duplex and store the current 708 * speed and duplex for copper connections. 709 */ 710 s32 igc_get_speed_and_duplex_copper(struct igc_hw *hw, u16 *speed, 711 u16 *duplex) 712 { 713 u32 status; 714 715 status = rd32(IGC_STATUS); 716 if (status & IGC_STATUS_SPEED_1000) { 717 /* For I225, STATUS will indicate 1G speed in both 1 Gbps 718 * and 2.5 Gbps link modes. An additional bit is used 719 * to differentiate between 1 Gbps and 2.5 Gbps. 720 */ 721 if (hw->mac.type == igc_i225 && 722 (status & IGC_STATUS_SPEED_2500)) { 723 *speed = SPEED_2500; 724 hw_dbg("2500 Mbs, "); 725 } else { 726 *speed = SPEED_1000; 727 hw_dbg("1000 Mbs, "); 728 } 729 } else if (status & IGC_STATUS_SPEED_100) { 730 *speed = SPEED_100; 731 hw_dbg("100 Mbs, "); 732 } else { 733 *speed = SPEED_10; 734 hw_dbg("10 Mbs, "); 735 } 736 737 if (status & IGC_STATUS_FD) { 738 *duplex = FULL_DUPLEX; 739 hw_dbg("Full Duplex\n"); 740 } else { 741 *duplex = HALF_DUPLEX; 742 hw_dbg("Half Duplex\n"); 743 } 744 745 return 0; 746 } 747 748 /** 749 * igc_put_hw_semaphore - Release hardware semaphore 750 * @hw: pointer to the HW structure 751 * 752 * Release hardware semaphore used to access the PHY or NVM 753 */ 754 void igc_put_hw_semaphore(struct igc_hw *hw) 755 { 756 u32 swsm; 757 758 swsm = rd32(IGC_SWSM); 759 760 swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI); 761 762 wr32(IGC_SWSM, swsm); 763 } 764 765 /** 766 * igc_enable_mng_pass_thru - Enable processing of ARP's 767 * @hw: pointer to the HW structure 768 * 769 * Verifies the hardware needs to leave interface enabled so that frames can 770 * be directed to and from the management interface. 771 */ 772 bool igc_enable_mng_pass_thru(struct igc_hw *hw) 773 { 774 bool ret_val = false; 775 u32 fwsm, factps; 776 u32 manc; 777 778 if (!hw->mac.asf_firmware_present) 779 goto out; 780 781 manc = rd32(IGC_MANC); 782 783 if (!(manc & IGC_MANC_RCV_TCO_EN)) 784 goto out; 785 786 if (hw->mac.arc_subsystem_valid) { 787 fwsm = rd32(IGC_FWSM); 788 factps = rd32(IGC_FACTPS); 789 790 if (!(factps & IGC_FACTPS_MNGCG) && 791 ((fwsm & IGC_FWSM_MODE_MASK) == 792 (igc_mng_mode_pt << IGC_FWSM_MODE_SHIFT))) { 793 ret_val = true; 794 goto out; 795 } 796 } else { 797 if ((manc & IGC_MANC_SMBUS_EN) && 798 !(manc & IGC_MANC_ASF_EN)) { 799 ret_val = true; 800 goto out; 801 } 802 } 803 804 out: 805 return ret_val; 806 } 807