1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #include <linux/pci.h> 5 #include <linux/delay.h> 6 7 #include "igc_mac.h" 8 #include "igc_hw.h" 9 10 /** 11 * igc_disable_pcie_master - Disables PCI-express master access 12 * @hw: pointer to the HW structure 13 * 14 * Returns 0 (0) if successful, else returns -10 15 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 16 * the master requests to be disabled. 17 * 18 * Disables PCI-Express master access and verifies there are no pending 19 * requests. 20 */ 21 s32 igc_disable_pcie_master(struct igc_hw *hw) 22 { 23 s32 timeout = MASTER_DISABLE_TIMEOUT; 24 s32 ret_val = 0; 25 u32 ctrl; 26 27 ctrl = rd32(IGC_CTRL); 28 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE; 29 wr32(IGC_CTRL, ctrl); 30 31 while (timeout) { 32 if (!(rd32(IGC_STATUS) & 33 IGC_STATUS_GIO_MASTER_ENABLE)) 34 break; 35 usleep_range(2000, 3000); 36 timeout--; 37 } 38 39 if (!timeout) { 40 hw_dbg("Master requests are pending.\n"); 41 ret_val = -IGC_ERR_MASTER_REQUESTS_PENDING; 42 goto out; 43 } 44 45 out: 46 return ret_val; 47 } 48 49 /** 50 * igc_init_rx_addrs - Initialize receive addresses 51 * @hw: pointer to the HW structure 52 * @rar_count: receive address registers 53 * 54 * Setup the receive address registers by setting the base receive address 55 * register to the devices MAC address and clearing all the other receive 56 * address registers to 0. 57 */ 58 void igc_init_rx_addrs(struct igc_hw *hw, u16 rar_count) 59 { 60 u8 mac_addr[ETH_ALEN] = {0}; 61 u32 i; 62 63 /* Setup the receive address */ 64 hw_dbg("Programming MAC Address into RAR[0]\n"); 65 66 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 67 68 /* Zero out the other (rar_entry_count - 1) receive addresses */ 69 hw_dbg("Clearing RAR[1-%u]\n", rar_count - 1); 70 for (i = 1; i < rar_count; i++) 71 hw->mac.ops.rar_set(hw, mac_addr, i); 72 } 73 74 /** 75 * igc_set_fc_watermarks - Set flow control high/low watermarks 76 * @hw: pointer to the HW structure 77 * 78 * Sets the flow control high/low threshold (watermark) registers. If 79 * flow control XON frame transmission is enabled, then set XON frame 80 * transmission as well. 81 */ 82 static s32 igc_set_fc_watermarks(struct igc_hw *hw) 83 { 84 u32 fcrtl = 0, fcrth = 0; 85 86 /* Set the flow control receive threshold registers. Normally, 87 * these registers will be set to a default threshold that may be 88 * adjusted later by the driver's runtime code. However, if the 89 * ability to transmit pause frames is not enabled, then these 90 * registers will be set to 0. 91 */ 92 if (hw->fc.current_mode & igc_fc_tx_pause) { 93 /* We need to set up the Receive Threshold high and low water 94 * marks as well as (optionally) enabling the transmission of 95 * XON frames. 96 */ 97 fcrtl = hw->fc.low_water; 98 if (hw->fc.send_xon) 99 fcrtl |= IGC_FCRTL_XONE; 100 101 fcrth = hw->fc.high_water; 102 } 103 wr32(IGC_FCRTL, fcrtl); 104 wr32(IGC_FCRTH, fcrth); 105 106 return 0; 107 } 108 109 /** 110 * igc_setup_link - Setup flow control and link settings 111 * @hw: pointer to the HW structure 112 * 113 * Determines which flow control settings to use, then configures flow 114 * control. Calls the appropriate media-specific link configuration 115 * function. Assuming the adapter has a valid link partner, a valid link 116 * should be established. Assumes the hardware has previously been reset 117 * and the transmitter and receiver are not enabled. 118 */ 119 s32 igc_setup_link(struct igc_hw *hw) 120 { 121 s32 ret_val = 0; 122 123 /* In the case of the phy reset being blocked, we already have a link. 124 * We do not need to set it up again. 125 */ 126 if (igc_check_reset_block(hw)) 127 goto out; 128 129 /* If requested flow control is set to default, set flow control 130 * to the both 'rx' and 'tx' pause frames. 131 */ 132 if (hw->fc.requested_mode == igc_fc_default) 133 hw->fc.requested_mode = igc_fc_full; 134 135 /* We want to save off the original Flow Control configuration just 136 * in case we get disconnected and then reconnected into a different 137 * hub or switch with different Flow Control capabilities. 138 */ 139 hw->fc.current_mode = hw->fc.requested_mode; 140 141 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 142 143 /* Call the necessary media_type subroutine to configure the link. */ 144 ret_val = hw->mac.ops.setup_physical_interface(hw); 145 if (ret_val) 146 goto out; 147 148 /* Initialize the flow control address, type, and PAUSE timer 149 * registers to their default values. This is done even if flow 150 * control is disabled, because it does not hurt anything to 151 * initialize these registers. 152 */ 153 hw_dbg("Initializing the Flow Control address, type and timer regs\n"); 154 wr32(IGC_FCT, FLOW_CONTROL_TYPE); 155 wr32(IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 156 wr32(IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW); 157 158 wr32(IGC_FCTTV, hw->fc.pause_time); 159 160 ret_val = igc_set_fc_watermarks(hw); 161 162 out: 163 return ret_val; 164 } 165 166 /** 167 * igc_force_mac_fc - Force the MAC's flow control settings 168 * @hw: pointer to the HW structure 169 * 170 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 171 * device control register to reflect the adapter settings. TFCE and RFCE 172 * need to be explicitly set by software when a copper PHY is used because 173 * autonegotiation is managed by the PHY rather than the MAC. Software must 174 * also configure these bits when link is forced on a fiber connection. 175 */ 176 s32 igc_force_mac_fc(struct igc_hw *hw) 177 { 178 s32 ret_val = 0; 179 u32 ctrl; 180 181 ctrl = rd32(IGC_CTRL); 182 183 /* Because we didn't get link via the internal auto-negotiation 184 * mechanism (we either forced link or we got link via PHY 185 * auto-neg), we have to manually enable/disable transmit an 186 * receive flow control. 187 * 188 * The "Case" statement below enables/disable flow control 189 * according to the "hw->fc.current_mode" parameter. 190 * 191 * The possible values of the "fc" parameter are: 192 * 0: Flow control is completely disabled 193 * 1: Rx flow control is enabled (we can receive pause 194 * frames but not send pause frames). 195 * 2: Tx flow control is enabled (we can send pause frames 196 * frames but we do not receive pause frames). 197 * 3: Both Rx and TX flow control (symmetric) is enabled. 198 * other: No other values should be possible at this point. 199 */ 200 hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); 201 202 switch (hw->fc.current_mode) { 203 case igc_fc_none: 204 ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE)); 205 break; 206 case igc_fc_rx_pause: 207 ctrl &= (~IGC_CTRL_TFCE); 208 ctrl |= IGC_CTRL_RFCE; 209 break; 210 case igc_fc_tx_pause: 211 ctrl &= (~IGC_CTRL_RFCE); 212 ctrl |= IGC_CTRL_TFCE; 213 break; 214 case igc_fc_full: 215 ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE); 216 break; 217 default: 218 hw_dbg("Flow control param set incorrectly\n"); 219 ret_val = -IGC_ERR_CONFIG; 220 goto out; 221 } 222 223 wr32(IGC_CTRL, ctrl); 224 225 out: 226 return ret_val; 227 } 228 229 /** 230 * igc_clear_hw_cntrs_base - Clear base hardware counters 231 * @hw: pointer to the HW structure 232 * 233 * Clears the base hardware counters by reading the counter registers. 234 */ 235 void igc_clear_hw_cntrs_base(struct igc_hw *hw) 236 { 237 rd32(IGC_CRCERRS); 238 rd32(IGC_MPC); 239 rd32(IGC_SCC); 240 rd32(IGC_ECOL); 241 rd32(IGC_MCC); 242 rd32(IGC_LATECOL); 243 rd32(IGC_COLC); 244 rd32(IGC_RERC); 245 rd32(IGC_DC); 246 rd32(IGC_RLEC); 247 rd32(IGC_XONRXC); 248 rd32(IGC_XONTXC); 249 rd32(IGC_XOFFRXC); 250 rd32(IGC_XOFFTXC); 251 rd32(IGC_FCRUC); 252 rd32(IGC_GPRC); 253 rd32(IGC_BPRC); 254 rd32(IGC_MPRC); 255 rd32(IGC_GPTC); 256 rd32(IGC_GORCL); 257 rd32(IGC_GORCH); 258 rd32(IGC_GOTCL); 259 rd32(IGC_GOTCH); 260 rd32(IGC_RNBC); 261 rd32(IGC_RUC); 262 rd32(IGC_RFC); 263 rd32(IGC_ROC); 264 rd32(IGC_RJC); 265 rd32(IGC_TORL); 266 rd32(IGC_TORH); 267 rd32(IGC_TOTL); 268 rd32(IGC_TOTH); 269 rd32(IGC_TPR); 270 rd32(IGC_TPT); 271 rd32(IGC_MPTC); 272 rd32(IGC_BPTC); 273 274 rd32(IGC_PRC64); 275 rd32(IGC_PRC127); 276 rd32(IGC_PRC255); 277 rd32(IGC_PRC511); 278 rd32(IGC_PRC1023); 279 rd32(IGC_PRC1522); 280 rd32(IGC_PTC64); 281 rd32(IGC_PTC127); 282 rd32(IGC_PTC255); 283 rd32(IGC_PTC511); 284 rd32(IGC_PTC1023); 285 rd32(IGC_PTC1522); 286 287 rd32(IGC_ALGNERRC); 288 rd32(IGC_RXERRC); 289 rd32(IGC_TNCRS); 290 rd32(IGC_HTDPMC); 291 rd32(IGC_TSCTC); 292 rd32(IGC_TSCTFC); 293 294 rd32(IGC_MGTPRC); 295 rd32(IGC_MGTPDC); 296 rd32(IGC_MGTPTC); 297 298 rd32(IGC_IAC); 299 rd32(IGC_ICRXOC); 300 301 rd32(IGC_ICRXPTC); 302 rd32(IGC_ICRXATC); 303 rd32(IGC_ICTXPTC); 304 rd32(IGC_ICTXATC); 305 rd32(IGC_ICTXQEC); 306 rd32(IGC_ICTXQMTC); 307 rd32(IGC_ICRXDMTC); 308 309 rd32(IGC_RPTHC); 310 rd32(IGC_HGPTC); 311 rd32(IGC_HGORCL); 312 rd32(IGC_HGORCH); 313 rd32(IGC_HGOTCL); 314 rd32(IGC_HGOTCH); 315 rd32(IGC_LENERRS); 316 } 317 318 /** 319 * igc_rar_set - Set receive address register 320 * @hw: pointer to the HW structure 321 * @addr: pointer to the receive address 322 * @index: receive address array register 323 * 324 * Sets the receive address array register at index to the address passed 325 * in by addr. 326 */ 327 void igc_rar_set(struct igc_hw *hw, u8 *addr, u32 index) 328 { 329 u32 rar_low, rar_high; 330 331 /* HW expects these in little endian so we reverse the byte order 332 * from network order (big endian) to little endian 333 */ 334 rar_low = ((u32)addr[0] | 335 ((u32)addr[1] << 8) | 336 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 337 338 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 339 340 /* If MAC address zero, no need to set the AV bit */ 341 if (rar_low || rar_high) 342 rar_high |= IGC_RAH_AV; 343 344 /* Some bridges will combine consecutive 32-bit writes into 345 * a single burst write, which will malfunction on some parts. 346 * The flushes avoid this. 347 */ 348 wr32(IGC_RAL(index), rar_low); 349 wrfl(); 350 wr32(IGC_RAH(index), rar_high); 351 wrfl(); 352 } 353 354 /** 355 * igc_check_for_copper_link - Check for link (Copper) 356 * @hw: pointer to the HW structure 357 * 358 * Checks to see of the link status of the hardware has changed. If a 359 * change in link status has been detected, then we read the PHY registers 360 * to get the current speed/duplex if link exists. 361 */ 362 s32 igc_check_for_copper_link(struct igc_hw *hw) 363 { 364 struct igc_mac_info *mac = &hw->mac; 365 s32 ret_val; 366 bool link; 367 368 /* We only want to go out to the PHY registers to see if Auto-Neg 369 * has completed and/or if our link status has changed. The 370 * get_link_status flag is set upon receiving a Link Status 371 * Change or Rx Sequence Error interrupt. 372 */ 373 if (!mac->get_link_status) { 374 ret_val = 0; 375 goto out; 376 } 377 378 /* First we want to see if the MII Status Register reports 379 * link. If so, then we want to get the current speed/duplex 380 * of the PHY. 381 */ 382 ret_val = igc_phy_has_link(hw, 1, 0, &link); 383 if (ret_val) 384 goto out; 385 386 if (!link) 387 goto out; /* No link detected */ 388 389 mac->get_link_status = false; 390 391 /* Check if there was DownShift, must be checked 392 * immediately after link-up 393 */ 394 igc_check_downshift(hw); 395 396 /* If we are forcing speed/duplex, then we simply return since 397 * we have already determined whether we have link or not. 398 */ 399 if (!mac->autoneg) { 400 ret_val = -IGC_ERR_CONFIG; 401 goto out; 402 } 403 404 /* Auto-Neg is enabled. Auto Speed Detection takes care 405 * of MAC speed/duplex configuration. So we only need to 406 * configure Collision Distance in the MAC. 407 */ 408 igc_config_collision_dist(hw); 409 410 /* Configure Flow Control now that Auto-Neg has completed. 411 * First, we need to restore the desired flow control 412 * settings because we may have had to re-autoneg with a 413 * different link partner. 414 */ 415 ret_val = igc_config_fc_after_link_up(hw); 416 if (ret_val) 417 hw_dbg("Error configuring flow control\n"); 418 419 out: 420 return ret_val; 421 } 422 423 /** 424 * igc_config_collision_dist - Configure collision distance 425 * @hw: pointer to the HW structure 426 * 427 * Configures the collision distance to the default value and is used 428 * during link setup. Currently no func pointer exists and all 429 * implementations are handled in the generic version of this function. 430 */ 431 void igc_config_collision_dist(struct igc_hw *hw) 432 { 433 u32 tctl; 434 435 tctl = rd32(IGC_TCTL); 436 437 tctl &= ~IGC_TCTL_COLD; 438 tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT; 439 440 wr32(IGC_TCTL, tctl); 441 wrfl(); 442 } 443 444 /** 445 * igc_config_fc_after_link_up - Configures flow control after link 446 * @hw: pointer to the HW structure 447 * 448 * Checks the status of auto-negotiation after link up to ensure that the 449 * speed and duplex were not forced. If the link needed to be forced, then 450 * flow control needs to be forced also. If auto-negotiation is enabled 451 * and did not fail, then we configure flow control based on our link 452 * partner. 453 */ 454 s32 igc_config_fc_after_link_up(struct igc_hw *hw) 455 { 456 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 457 struct igc_mac_info *mac = &hw->mac; 458 u16 speed, duplex; 459 s32 ret_val = 0; 460 461 /* Check for the case where we have fiber media and auto-neg failed 462 * so we had to force link. In this case, we need to force the 463 * configuration of the MAC to match the "fc" parameter. 464 */ 465 if (mac->autoneg_failed) { 466 if (hw->phy.media_type == igc_media_type_copper) 467 ret_val = igc_force_mac_fc(hw); 468 } 469 470 if (ret_val) { 471 hw_dbg("Error forcing flow control settings\n"); 472 goto out; 473 } 474 475 /* Check for the case where we have copper media and auto-neg is 476 * enabled. In this case, we need to check and see if Auto-Neg 477 * has completed, and if so, how the PHY and link partner has 478 * flow control configured. 479 */ 480 if (hw->phy.media_type == igc_media_type_copper && mac->autoneg) { 481 /* Read the MII Status Register and check to see if AutoNeg 482 * has completed. We read this twice because this reg has 483 * some "sticky" (latched) bits. 484 */ 485 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, 486 &mii_status_reg); 487 if (ret_val) 488 goto out; 489 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, 490 &mii_status_reg); 491 if (ret_val) 492 goto out; 493 494 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 495 hw_dbg("Copper PHY and Auto Neg has not completed.\n"); 496 goto out; 497 } 498 499 /* The AutoNeg process has completed, so we now need to 500 * read both the Auto Negotiation Advertisement 501 * Register (Address 4) and the Auto_Negotiation Base 502 * Page Ability Register (Address 5) to determine how 503 * flow control was negotiated. 504 */ 505 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 506 &mii_nway_adv_reg); 507 if (ret_val) 508 goto out; 509 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 510 &mii_nway_lp_ability_reg); 511 if (ret_val) 512 goto out; 513 /* Two bits in the Auto Negotiation Advertisement Register 514 * (Address 4) and two bits in the Auto Negotiation Base 515 * Page Ability Register (Address 5) determine flow control 516 * for both the PHY and the link partner. The following 517 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 518 * 1999, describes these PAUSE resolution bits and how flow 519 * control is determined based upon these settings. 520 * NOTE: DC = Don't Care 521 * 522 * LOCAL DEVICE | LINK PARTNER 523 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 524 *-------|---------|-------|---------|-------------------- 525 * 0 | 0 | DC | DC | igc_fc_none 526 * 0 | 1 | 0 | DC | igc_fc_none 527 * 0 | 1 | 1 | 0 | igc_fc_none 528 * 0 | 1 | 1 | 1 | igc_fc_tx_pause 529 * 1 | 0 | 0 | DC | igc_fc_none 530 * 1 | DC | 1 | DC | igc_fc_full 531 * 1 | 1 | 0 | 0 | igc_fc_none 532 * 1 | 1 | 0 | 1 | igc_fc_rx_pause 533 * 534 * Are both PAUSE bits set to 1? If so, this implies 535 * Symmetric Flow Control is enabled at both ends. The 536 * ASM_DIR bits are irrelevant per the spec. 537 * 538 * For Symmetric Flow Control: 539 * 540 * LOCAL DEVICE | LINK PARTNER 541 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 542 *-------|---------|-------|---------|-------------------- 543 * 1 | DC | 1 | DC | IGC_fc_full 544 * 545 */ 546 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 547 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 548 /* Now we need to check if the user selected RX ONLY 549 * of pause frames. In this case, we had to advertise 550 * FULL flow control because we could not advertise RX 551 * ONLY. Hence, we must now check to see if we need to 552 * turn OFF the TRANSMISSION of PAUSE frames. 553 */ 554 if (hw->fc.requested_mode == igc_fc_full) { 555 hw->fc.current_mode = igc_fc_full; 556 hw_dbg("Flow Control = FULL.\n"); 557 } else { 558 hw->fc.current_mode = igc_fc_rx_pause; 559 hw_dbg("Flow Control = RX PAUSE frames only.\n"); 560 } 561 } 562 563 /* For receiving PAUSE frames ONLY. 564 * 565 * LOCAL DEVICE | LINK PARTNER 566 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 567 *-------|---------|-------|---------|-------------------- 568 * 0 | 1 | 1 | 1 | igc_fc_tx_pause 569 */ 570 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 571 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 572 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 573 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 574 hw->fc.current_mode = igc_fc_tx_pause; 575 hw_dbg("Flow Control = TX PAUSE frames only.\n"); 576 } 577 /* For transmitting PAUSE frames ONLY. 578 * 579 * LOCAL DEVICE | LINK PARTNER 580 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 581 *-------|---------|-------|---------|-------------------- 582 * 1 | 1 | 0 | 1 | igc_fc_rx_pause 583 */ 584 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 585 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 586 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 587 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 588 hw->fc.current_mode = igc_fc_rx_pause; 589 hw_dbg("Flow Control = RX PAUSE frames only.\n"); 590 } 591 /* Per the IEEE spec, at this point flow control should be 592 * disabled. However, we want to consider that we could 593 * be connected to a legacy switch that doesn't advertise 594 * desired flow control, but can be forced on the link 595 * partner. So if we advertised no flow control, that is 596 * what we will resolve to. If we advertised some kind of 597 * receive capability (Rx Pause Only or Full Flow Control) 598 * and the link partner advertised none, we will configure 599 * ourselves to enable Rx Flow Control only. We can do 600 * this safely for two reasons: If the link partner really 601 * didn't want flow control enabled, and we enable Rx, no 602 * harm done since we won't be receiving any PAUSE frames 603 * anyway. If the intent on the link partner was to have 604 * flow control enabled, then by us enabling RX only, we 605 * can at least receive pause frames and process them. 606 * This is a good idea because in most cases, since we are 607 * predominantly a server NIC, more times than not we will 608 * be asked to delay transmission of packets than asking 609 * our link partner to pause transmission of frames. 610 */ 611 else if ((hw->fc.requested_mode == igc_fc_none) || 612 (hw->fc.requested_mode == igc_fc_tx_pause) || 613 (hw->fc.strict_ieee)) { 614 hw->fc.current_mode = igc_fc_none; 615 hw_dbg("Flow Control = NONE.\n"); 616 } else { 617 hw->fc.current_mode = igc_fc_rx_pause; 618 hw_dbg("Flow Control = RX PAUSE frames only.\n"); 619 } 620 621 /* Now we need to do one last check... If we auto- 622 * negotiated to HALF DUPLEX, flow control should not be 623 * enabled per IEEE 802.3 spec. 624 */ 625 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex); 626 if (ret_val) { 627 hw_dbg("Error getting link speed and duplex\n"); 628 goto out; 629 } 630 631 if (duplex == HALF_DUPLEX) 632 hw->fc.current_mode = igc_fc_none; 633 634 /* Now we call a subroutine to actually force the MAC 635 * controller to use the correct flow control settings. 636 */ 637 ret_val = igc_force_mac_fc(hw); 638 if (ret_val) { 639 hw_dbg("Error forcing flow control settings\n"); 640 goto out; 641 } 642 } 643 644 out: 645 return 0; 646 } 647 648 /** 649 * igc_get_auto_rd_done - Check for auto read completion 650 * @hw: pointer to the HW structure 651 * 652 * Check EEPROM for Auto Read done bit. 653 */ 654 s32 igc_get_auto_rd_done(struct igc_hw *hw) 655 { 656 s32 ret_val = 0; 657 s32 i = 0; 658 659 while (i < AUTO_READ_DONE_TIMEOUT) { 660 if (rd32(IGC_EECD) & IGC_EECD_AUTO_RD) 661 break; 662 usleep_range(1000, 2000); 663 i++; 664 } 665 666 if (i == AUTO_READ_DONE_TIMEOUT) { 667 hw_dbg("Auto read by HW from NVM has not completed.\n"); 668 ret_val = -IGC_ERR_RESET; 669 goto out; 670 } 671 672 out: 673 return ret_val; 674 } 675 676 /** 677 * igc_get_speed_and_duplex_copper - Retrieve current speed/duplex 678 * @hw: pointer to the HW structure 679 * @speed: stores the current speed 680 * @duplex: stores the current duplex 681 * 682 * Read the status register for the current speed/duplex and store the current 683 * speed and duplex for copper connections. 684 */ 685 s32 igc_get_speed_and_duplex_copper(struct igc_hw *hw, u16 *speed, 686 u16 *duplex) 687 { 688 u32 status; 689 690 status = rd32(IGC_STATUS); 691 if (status & IGC_STATUS_SPEED_1000) { 692 /* For I225, STATUS will indicate 1G speed in both 1 Gbps 693 * and 2.5 Gbps link modes. An additional bit is used 694 * to differentiate between 1 Gbps and 2.5 Gbps. 695 */ 696 if (hw->mac.type == igc_i225 && 697 (status & IGC_STATUS_SPEED_2500)) { 698 *speed = SPEED_2500; 699 hw_dbg("2500 Mbs, "); 700 } else { 701 *speed = SPEED_1000; 702 hw_dbg("1000 Mbs, "); 703 } 704 } else if (status & IGC_STATUS_SPEED_100) { 705 *speed = SPEED_100; 706 hw_dbg("100 Mbs, "); 707 } else { 708 *speed = SPEED_10; 709 hw_dbg("10 Mbs, "); 710 } 711 712 if (status & IGC_STATUS_FD) { 713 *duplex = FULL_DUPLEX; 714 hw_dbg("Full Duplex\n"); 715 } else { 716 *duplex = HALF_DUPLEX; 717 hw_dbg("Half Duplex\n"); 718 } 719 720 return 0; 721 } 722 723 /** 724 * igc_put_hw_semaphore - Release hardware semaphore 725 * @hw: pointer to the HW structure 726 * 727 * Release hardware semaphore used to access the PHY or NVM 728 */ 729 void igc_put_hw_semaphore(struct igc_hw *hw) 730 { 731 u32 swsm; 732 733 swsm = rd32(IGC_SWSM); 734 735 swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI); 736 737 wr32(IGC_SWSM, swsm); 738 } 739 740 /** 741 * igc_enable_mng_pass_thru - Enable processing of ARP's 742 * @hw: pointer to the HW structure 743 * 744 * Verifies the hardware needs to leave interface enabled so that frames can 745 * be directed to and from the management interface. 746 */ 747 bool igc_enable_mng_pass_thru(struct igc_hw *hw) 748 { 749 bool ret_val = false; 750 u32 fwsm, factps; 751 u32 manc; 752 753 if (!hw->mac.asf_firmware_present) 754 goto out; 755 756 manc = rd32(IGC_MANC); 757 758 if (!(manc & IGC_MANC_RCV_TCO_EN)) 759 goto out; 760 761 if (hw->mac.arc_subsystem_valid) { 762 fwsm = rd32(IGC_FWSM); 763 factps = rd32(IGC_FACTPS); 764 765 if (!(factps & IGC_FACTPS_MNGCG) && 766 ((fwsm & IGC_FWSM_MODE_MASK) == 767 (igc_mng_mode_pt << IGC_FWSM_MODE_SHIFT))) { 768 ret_val = true; 769 goto out; 770 } 771 } else { 772 if ((manc & IGC_MANC_SMBUS_EN) && 773 !(manc & IGC_MANC_ASF_EN)) { 774 ret_val = true; 775 goto out; 776 } 777 } 778 779 out: 780 return ret_val; 781 } 782 783 /** 784 * igc_hash_mc_addr - Generate a multicast hash value 785 * @hw: pointer to the HW structure 786 * @mc_addr: pointer to a multicast address 787 * 788 * Generates a multicast address hash value which is used to determine 789 * the multicast filter table array address and new table value. See 790 * igc_mta_set() 791 **/ 792 static u32 igc_hash_mc_addr(struct igc_hw *hw, u8 *mc_addr) 793 { 794 u32 hash_value, hash_mask; 795 u8 bit_shift = 0; 796 797 /* Register count multiplied by bits per register */ 798 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 799 800 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 801 * where 0xFF would still fall within the hash mask. 802 */ 803 while (hash_mask >> bit_shift != 0xFF) 804 bit_shift++; 805 806 /* The portion of the address that is used for the hash table 807 * is determined by the mc_filter_type setting. 808 * The algorithm is such that there is a total of 8 bits of shifting. 809 * The bit_shift for a mc_filter_type of 0 represents the number of 810 * left-shifts where the MSB of mc_addr[5] would still fall within 811 * the hash_mask. Case 0 does this exactly. Since there are a total 812 * of 8 bits of shifting, then mc_addr[4] will shift right the 813 * remaining number of bits. Thus 8 - bit_shift. The rest of the 814 * cases are a variation of this algorithm...essentially raising the 815 * number of bits to shift mc_addr[5] left, while still keeping the 816 * 8-bit shifting total. 817 * 818 * For example, given the following Destination MAC Address and an 819 * MTA register count of 128 (thus a 4096-bit vector and 0xFFF mask), 820 * we can see that the bit_shift for case 0 is 4. These are the hash 821 * values resulting from each mc_filter_type... 822 * [0] [1] [2] [3] [4] [5] 823 * 01 AA 00 12 34 56 824 * LSB MSB 825 * 826 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 827 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 828 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 829 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 830 */ 831 switch (hw->mac.mc_filter_type) { 832 default: 833 case 0: 834 break; 835 case 1: 836 bit_shift += 1; 837 break; 838 case 2: 839 bit_shift += 2; 840 break; 841 case 3: 842 bit_shift += 4; 843 break; 844 } 845 846 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 847 (((u16)mc_addr[5]) << bit_shift))); 848 849 return hash_value; 850 } 851 852 /** 853 * igc_update_mc_addr_list - Update Multicast addresses 854 * @hw: pointer to the HW structure 855 * @mc_addr_list: array of multicast addresses to program 856 * @mc_addr_count: number of multicast addresses to program 857 * 858 * Updates entire Multicast Table Array. 859 * The caller must have a packed mc_addr_list of multicast addresses. 860 **/ 861 void igc_update_mc_addr_list(struct igc_hw *hw, 862 u8 *mc_addr_list, u32 mc_addr_count) 863 { 864 u32 hash_value, hash_bit, hash_reg; 865 int i; 866 867 /* clear mta_shadow */ 868 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 869 870 /* update mta_shadow from mc_addr_list */ 871 for (i = 0; (u32)i < mc_addr_count; i++) { 872 hash_value = igc_hash_mc_addr(hw, mc_addr_list); 873 874 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 875 hash_bit = hash_value & 0x1F; 876 877 hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit); 878 mc_addr_list += ETH_ALEN; 879 } 880 881 /* replace the entire MTA table */ 882 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 883 array_wr32(IGC_MTA, i, hw->mac.mta_shadow[i]); 884 wrfl(); 885 } 886