1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_HW_H_ 5 #define _IGC_HW_H_ 6 7 #include <linux/types.h> 8 #include <linux/if_ether.h> 9 #include <linux/netdevice.h> 10 11 #include "igc_regs.h" 12 #include "igc_defines.h" 13 #include "igc_mac.h" 14 #include "igc_phy.h" 15 #include "igc_nvm.h" 16 #include "igc_i225.h" 17 #include "igc_base.h" 18 19 #define IGC_DEV_ID_I225_LM 0x15F2 20 #define IGC_DEV_ID_I225_V 0x15F3 21 22 #define IGC_FUNC_0 0 23 24 /* Function pointers for the MAC. */ 25 struct igc_mac_operations { 26 s32 (*check_for_link)(struct igc_hw *hw); 27 s32 (*reset_hw)(struct igc_hw *hw); 28 s32 (*init_hw)(struct igc_hw *hw); 29 s32 (*setup_physical_interface)(struct igc_hw *hw); 30 void (*rar_set)(struct igc_hw *hw, u8 *address, u32 index); 31 s32 (*read_mac_addr)(struct igc_hw *hw); 32 s32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed, 33 u16 *duplex); 34 s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask); 35 void (*release_swfw_sync)(struct igc_hw *hw, u16 mask); 36 }; 37 38 enum igc_mac_type { 39 igc_undefined = 0, 40 igc_i225, 41 igc_num_macs /* List is 1-based, so subtract 1 for true count. */ 42 }; 43 44 enum igc_phy_type { 45 igc_phy_unknown = 0, 46 igc_phy_none, 47 igc_phy_i225, 48 }; 49 50 enum igc_media_type { 51 igc_media_type_unknown = 0, 52 igc_media_type_copper = 1, 53 igc_num_media_types 54 }; 55 56 enum igc_nvm_type { 57 igc_nvm_unknown = 0, 58 igc_nvm_eeprom_spi, 59 igc_nvm_flash_hw, 60 igc_nvm_invm, 61 }; 62 63 struct igc_info { 64 s32 (*get_invariants)(struct igc_hw *hw); 65 struct igc_mac_operations *mac_ops; 66 const struct igc_phy_operations *phy_ops; 67 struct igc_nvm_operations *nvm_ops; 68 }; 69 70 extern const struct igc_info igc_base_info; 71 72 struct igc_mac_info { 73 struct igc_mac_operations ops; 74 75 u8 addr[ETH_ALEN]; 76 u8 perm_addr[ETH_ALEN]; 77 78 enum igc_mac_type type; 79 80 u32 collision_delta; 81 u32 ledctl_default; 82 u32 ledctl_mode1; 83 u32 ledctl_mode2; 84 u32 mc_filter_type; 85 u32 tx_packet_delta; 86 u32 txcw; 87 88 u16 mta_reg_count; 89 u16 uta_reg_count; 90 91 u16 rar_entry_count; 92 93 u8 forced_speed_duplex; 94 95 bool adaptive_ifs; 96 bool has_fwsm; 97 bool asf_firmware_present; 98 bool arc_subsystem_valid; 99 100 bool autoneg; 101 bool autoneg_failed; 102 bool get_link_status; 103 }; 104 105 struct igc_nvm_operations { 106 s32 (*acquire)(struct igc_hw *hw); 107 s32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 108 void (*release)(struct igc_hw *hw); 109 s32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 110 s32 (*update)(struct igc_hw *hw); 111 s32 (*validate)(struct igc_hw *hw); 112 s32 (*valid_led_default)(struct igc_hw *hw, u16 *data); 113 }; 114 115 struct igc_phy_operations { 116 s32 (*acquire)(struct igc_hw *hw); 117 s32 (*check_reset_block)(struct igc_hw *hw); 118 s32 (*force_speed_duplex)(struct igc_hw *hw); 119 s32 (*get_phy_info)(struct igc_hw *hw); 120 s32 (*read_reg)(struct igc_hw *hw, u32 address, u16 *data); 121 void (*release)(struct igc_hw *hw); 122 s32 (*reset)(struct igc_hw *hw); 123 s32 (*write_reg)(struct igc_hw *hw, u32 address, u16 data); 124 }; 125 126 struct igc_nvm_info { 127 struct igc_nvm_operations ops; 128 enum igc_nvm_type type; 129 130 u32 flash_bank_size; 131 u32 flash_base_addr; 132 133 u16 word_size; 134 u16 delay_usec; 135 u16 address_bits; 136 u16 opcode_bits; 137 u16 page_size; 138 }; 139 140 struct igc_phy_info { 141 struct igc_phy_operations ops; 142 143 enum igc_phy_type type; 144 145 u32 addr; 146 u32 id; 147 u32 reset_delay_us; /* in usec */ 148 u32 revision; 149 150 enum igc_media_type media_type; 151 152 u16 autoneg_advertised; 153 u16 autoneg_mask; 154 u16 cable_length; 155 u16 max_cable_length; 156 u16 min_cable_length; 157 u16 pair_length[4]; 158 159 u8 mdix; 160 161 bool disable_polarity_correction; 162 bool is_mdix; 163 bool polarity_correction; 164 bool reset_disable; 165 bool speed_downgraded; 166 bool autoneg_wait_to_complete; 167 }; 168 169 struct igc_bus_info { 170 u16 func; 171 u16 pci_cmd_word; 172 }; 173 174 enum igc_fc_mode { 175 igc_fc_none = 0, 176 igc_fc_rx_pause, 177 igc_fc_tx_pause, 178 igc_fc_full, 179 igc_fc_default = 0xFF 180 }; 181 182 struct igc_fc_info { 183 u32 high_water; /* Flow control high-water mark */ 184 u32 low_water; /* Flow control low-water mark */ 185 u16 pause_time; /* Flow control pause timer */ 186 bool send_xon; /* Flow control send XON */ 187 bool strict_ieee; /* Strict IEEE mode */ 188 enum igc_fc_mode current_mode; /* Type of flow control */ 189 enum igc_fc_mode requested_mode; 190 }; 191 192 struct igc_dev_spec_base { 193 bool global_device_reset; 194 bool eee_disable; 195 bool clear_semaphore_once; 196 bool module_plugged; 197 u8 media_port; 198 bool mas_capable; 199 }; 200 201 struct igc_hw { 202 void *back; 203 204 u8 __iomem *hw_addr; 205 unsigned long io_base; 206 207 struct igc_mac_info mac; 208 struct igc_fc_info fc; 209 struct igc_nvm_info nvm; 210 struct igc_phy_info phy; 211 212 struct igc_bus_info bus; 213 214 union { 215 struct igc_dev_spec_base _base; 216 } dev_spec; 217 218 u16 device_id; 219 u16 subsystem_vendor_id; 220 u16 subsystem_device_id; 221 u16 vendor_id; 222 223 u8 revision_id; 224 }; 225 226 /* Statistics counters collected by the MAC */ 227 struct igc_hw_stats { 228 u64 crcerrs; 229 u64 algnerrc; 230 u64 symerrs; 231 u64 rxerrc; 232 u64 mpc; 233 u64 scc; 234 u64 ecol; 235 u64 mcc; 236 u64 latecol; 237 u64 colc; 238 u64 dc; 239 u64 tncrs; 240 u64 sec; 241 u64 cexterr; 242 u64 rlec; 243 u64 xonrxc; 244 u64 xontxc; 245 u64 xoffrxc; 246 u64 xofftxc; 247 u64 fcruc; 248 u64 prc64; 249 u64 prc127; 250 u64 prc255; 251 u64 prc511; 252 u64 prc1023; 253 u64 prc1522; 254 u64 gprc; 255 u64 bprc; 256 u64 mprc; 257 u64 gptc; 258 u64 gorc; 259 u64 gotc; 260 u64 rnbc; 261 u64 ruc; 262 u64 rfc; 263 u64 roc; 264 u64 rjc; 265 u64 mgprc; 266 u64 mgpdc; 267 u64 mgptc; 268 u64 tor; 269 u64 tot; 270 u64 tpr; 271 u64 tpt; 272 u64 ptc64; 273 u64 ptc127; 274 u64 ptc255; 275 u64 ptc511; 276 u64 ptc1023; 277 u64 ptc1522; 278 u64 mptc; 279 u64 bptc; 280 u64 tsctc; 281 u64 tsctfc; 282 u64 iac; 283 u64 icrxptc; 284 u64 icrxatc; 285 u64 ictxptc; 286 u64 ictxatc; 287 u64 ictxqec; 288 u64 ictxqmtc; 289 u64 icrxdmtc; 290 u64 icrxoc; 291 u64 cbtmpc; 292 u64 htdpmc; 293 u64 cbrdpc; 294 u64 cbrmpc; 295 u64 rpthc; 296 u64 hgptc; 297 u64 htcbdpc; 298 u64 hgorc; 299 u64 hgotc; 300 u64 lenerrs; 301 u64 scvpc; 302 u64 hrmpc; 303 u64 doosync; 304 u64 o2bgptc; 305 u64 o2bspc; 306 u64 b2ospc; 307 u64 b2ogprc; 308 }; 309 310 struct net_device *igc_get_hw_dev(struct igc_hw *hw); 311 #define hw_dbg(format, arg...) \ 312 netdev_dbg(igc_get_hw_dev(hw), format, ##arg) 313 314 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 315 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 316 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 317 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 318 319 #endif /* _IGC_HW_H_ */ 320