1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c)  2018 Intel Corporation */
3 
4 #ifndef _IGC_HW_H_
5 #define _IGC_HW_H_
6 
7 #include <linux/types.h>
8 #include <linux/if_ether.h>
9 #include <linux/netdevice.h>
10 
11 #include "igc_regs.h"
12 #include "igc_defines.h"
13 #include "igc_mac.h"
14 #include "igc_phy.h"
15 #include "igc_nvm.h"
16 #include "igc_i225.h"
17 #include "igc_base.h"
18 
19 #define IGC_DEV_ID_I225_LM			0x15F2
20 #define IGC_DEV_ID_I225_V			0x15F3
21 
22 #define IGC_FUNC_0				0
23 
24 /* Function pointers for the MAC. */
25 struct igc_mac_operations {
26 	s32 (*check_for_link)(struct igc_hw *hw);
27 	s32 (*reset_hw)(struct igc_hw *hw);
28 	s32 (*init_hw)(struct igc_hw *hw);
29 	s32 (*setup_physical_interface)(struct igc_hw *hw);
30 	void (*rar_set)(struct igc_hw *hw, u8 *address, u32 index);
31 	s32 (*read_mac_addr)(struct igc_hw *hw);
32 	s32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed,
33 				    u16 *duplex);
34 	s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask);
35 	void (*release_swfw_sync)(struct igc_hw *hw, u16 mask);
36 };
37 
38 enum igc_mac_type {
39 	igc_undefined = 0,
40 	igc_i225,
41 	igc_num_macs  /* List is 1-based, so subtract 1 for true count. */
42 };
43 
44 enum igc_phy_type {
45 	igc_phy_unknown = 0,
46 	igc_phy_none,
47 	igc_phy_i225,
48 };
49 
50 enum igc_media_type {
51 	igc_media_type_unknown = 0,
52 	igc_media_type_copper = 1,
53 	igc_num_media_types
54 };
55 
56 enum igc_nvm_type {
57 	igc_nvm_unknown = 0,
58 	igc_nvm_eeprom_spi,
59 	igc_nvm_flash_hw,
60 	igc_nvm_invm,
61 };
62 
63 struct igc_info {
64 	s32 (*get_invariants)(struct igc_hw *hw);
65 	struct igc_mac_operations *mac_ops;
66 	const struct igc_phy_operations *phy_ops;
67 	struct igc_nvm_operations *nvm_ops;
68 };
69 
70 extern const struct igc_info igc_base_info;
71 
72 struct igc_mac_info {
73 	struct igc_mac_operations ops;
74 
75 	u8 addr[ETH_ALEN];
76 	u8 perm_addr[ETH_ALEN];
77 
78 	enum igc_mac_type type;
79 
80 	u32 collision_delta;
81 	u32 ledctl_default;
82 	u32 ledctl_mode1;
83 	u32 ledctl_mode2;
84 	u32 mc_filter_type;
85 	u32 tx_packet_delta;
86 	u32 txcw;
87 
88 	u16 mta_reg_count;
89 	u16 uta_reg_count;
90 
91 	u16 rar_entry_count;
92 
93 	u8 forced_speed_duplex;
94 
95 	bool adaptive_ifs;
96 	bool has_fwsm;
97 	bool asf_firmware_present;
98 	bool arc_subsystem_valid;
99 
100 	bool autoneg;
101 	bool autoneg_failed;
102 	bool get_link_status;
103 };
104 
105 struct igc_nvm_operations {
106 	s32 (*acquire)(struct igc_hw *hw);
107 	s32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data);
108 	void (*release)(struct igc_hw *hw);
109 	s32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data);
110 	s32 (*update)(struct igc_hw *hw);
111 	s32 (*validate)(struct igc_hw *hw);
112 	s32 (*valid_led_default)(struct igc_hw *hw, u16 *data);
113 };
114 
115 struct igc_phy_operations {
116 	s32 (*acquire)(struct igc_hw *hw);
117 	s32 (*check_polarity)(struct igc_hw *hw);
118 	s32 (*check_reset_block)(struct igc_hw *hw);
119 	s32 (*force_speed_duplex)(struct igc_hw *hw);
120 	s32 (*get_cfg_done)(struct igc_hw *hw);
121 	s32 (*get_cable_length)(struct igc_hw *hw);
122 	s32 (*get_phy_info)(struct igc_hw *hw);
123 	s32 (*read_reg)(struct igc_hw *hw, u32 address, u16 *data);
124 	void (*release)(struct igc_hw *hw);
125 	s32 (*reset)(struct igc_hw *hw);
126 	s32 (*write_reg)(struct igc_hw *hw, u32 address, u16 data);
127 };
128 
129 struct igc_nvm_info {
130 	struct igc_nvm_operations ops;
131 	enum igc_nvm_type type;
132 
133 	u32 flash_bank_size;
134 	u32 flash_base_addr;
135 
136 	u16 word_size;
137 	u16 delay_usec;
138 	u16 address_bits;
139 	u16 opcode_bits;
140 	u16 page_size;
141 };
142 
143 struct igc_phy_info {
144 	struct igc_phy_operations ops;
145 
146 	enum igc_phy_type type;
147 
148 	u32 addr;
149 	u32 id;
150 	u32 reset_delay_us; /* in usec */
151 	u32 revision;
152 
153 	enum igc_media_type media_type;
154 
155 	u16 autoneg_advertised;
156 	u16 autoneg_mask;
157 	u16 cable_length;
158 	u16 max_cable_length;
159 	u16 min_cable_length;
160 	u16 pair_length[4];
161 
162 	u8 mdix;
163 
164 	bool disable_polarity_correction;
165 	bool is_mdix;
166 	bool polarity_correction;
167 	bool reset_disable;
168 	bool speed_downgraded;
169 	bool autoneg_wait_to_complete;
170 };
171 
172 struct igc_bus_info {
173 	u16 func;
174 	u16 pci_cmd_word;
175 };
176 
177 enum igc_fc_mode {
178 	igc_fc_none = 0,
179 	igc_fc_rx_pause,
180 	igc_fc_tx_pause,
181 	igc_fc_full,
182 	igc_fc_default = 0xFF
183 };
184 
185 struct igc_fc_info {
186 	u32 high_water;     /* Flow control high-water mark */
187 	u32 low_water;      /* Flow control low-water mark */
188 	u16 pause_time;     /* Flow control pause timer */
189 	bool send_xon;      /* Flow control send XON */
190 	bool strict_ieee;   /* Strict IEEE mode */
191 	enum igc_fc_mode current_mode; /* Type of flow control */
192 	enum igc_fc_mode requested_mode;
193 };
194 
195 struct igc_dev_spec_base {
196 	bool global_device_reset;
197 	bool eee_disable;
198 	bool clear_semaphore_once;
199 	bool module_plugged;
200 	u8 media_port;
201 	bool mas_capable;
202 };
203 
204 struct igc_hw {
205 	void *back;
206 
207 	u8 __iomem *hw_addr;
208 	unsigned long io_base;
209 
210 	struct igc_mac_info  mac;
211 	struct igc_fc_info   fc;
212 	struct igc_nvm_info  nvm;
213 	struct igc_phy_info  phy;
214 
215 	struct igc_bus_info bus;
216 
217 	union {
218 		struct igc_dev_spec_base	_base;
219 	} dev_spec;
220 
221 	u16 device_id;
222 	u16 subsystem_vendor_id;
223 	u16 subsystem_device_id;
224 	u16 vendor_id;
225 
226 	u8 revision_id;
227 };
228 
229 /* Statistics counters collected by the MAC */
230 struct igc_hw_stats {
231 	u64 crcerrs;
232 	u64 algnerrc;
233 	u64 symerrs;
234 	u64 rxerrc;
235 	u64 mpc;
236 	u64 scc;
237 	u64 ecol;
238 	u64 mcc;
239 	u64 latecol;
240 	u64 colc;
241 	u64 dc;
242 	u64 tncrs;
243 	u64 sec;
244 	u64 cexterr;
245 	u64 rlec;
246 	u64 xonrxc;
247 	u64 xontxc;
248 	u64 xoffrxc;
249 	u64 xofftxc;
250 	u64 fcruc;
251 	u64 prc64;
252 	u64 prc127;
253 	u64 prc255;
254 	u64 prc511;
255 	u64 prc1023;
256 	u64 prc1522;
257 	u64 gprc;
258 	u64 bprc;
259 	u64 mprc;
260 	u64 gptc;
261 	u64 gorc;
262 	u64 gotc;
263 	u64 rnbc;
264 	u64 ruc;
265 	u64 rfc;
266 	u64 roc;
267 	u64 rjc;
268 	u64 mgprc;
269 	u64 mgpdc;
270 	u64 mgptc;
271 	u64 tor;
272 	u64 tot;
273 	u64 tpr;
274 	u64 tpt;
275 	u64 ptc64;
276 	u64 ptc127;
277 	u64 ptc255;
278 	u64 ptc511;
279 	u64 ptc1023;
280 	u64 ptc1522;
281 	u64 mptc;
282 	u64 bptc;
283 	u64 tsctc;
284 	u64 tsctfc;
285 	u64 iac;
286 	u64 icrxptc;
287 	u64 icrxatc;
288 	u64 ictxptc;
289 	u64 ictxatc;
290 	u64 ictxqec;
291 	u64 ictxqmtc;
292 	u64 icrxdmtc;
293 	u64 icrxoc;
294 	u64 cbtmpc;
295 	u64 htdpmc;
296 	u64 cbrdpc;
297 	u64 cbrmpc;
298 	u64 rpthc;
299 	u64 hgptc;
300 	u64 htcbdpc;
301 	u64 hgorc;
302 	u64 hgotc;
303 	u64 lenerrs;
304 	u64 scvpc;
305 	u64 hrmpc;
306 	u64 doosync;
307 	u64 o2bgptc;
308 	u64 o2bspc;
309 	u64 b2ospc;
310 	u64 b2ogprc;
311 };
312 
313 struct net_device *igc_get_hw_dev(struct igc_hw *hw);
314 #define hw_dbg(format, arg...) \
315 	netdev_dbg(igc_get_hw_dev(hw), format, ##arg)
316 
317 s32  igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
318 s32  igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
319 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
320 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
321 
322 #endif /* _IGC_HW_H_ */
323