1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_HW_H_ 5 #define _IGC_HW_H_ 6 7 #include <linux/types.h> 8 #include <linux/if_ether.h> 9 #include <linux/netdevice.h> 10 11 #include "igc_regs.h" 12 #include "igc_defines.h" 13 #include "igc_mac.h" 14 #include "igc_phy.h" 15 #include "igc_nvm.h" 16 #include "igc_i225.h" 17 #include "igc_base.h" 18 19 #define IGC_DEV_ID_I225_LM 0x15F2 20 #define IGC_DEV_ID_I225_V 0x15F3 21 22 #define IGC_FUNC_0 0 23 24 /* Function pointers for the MAC. */ 25 struct igc_mac_operations { 26 s32 (*check_for_link)(struct igc_hw *hw); 27 s32 (*reset_hw)(struct igc_hw *hw); 28 s32 (*init_hw)(struct igc_hw *hw); 29 s32 (*setup_physical_interface)(struct igc_hw *hw); 30 void (*rar_set)(struct igc_hw *hw, u8 *address, u32 index); 31 s32 (*read_mac_addr)(struct igc_hw *hw); 32 s32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed, 33 u16 *duplex); 34 s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask); 35 void (*release_swfw_sync)(struct igc_hw *hw, u16 mask); 36 }; 37 38 enum igc_mac_type { 39 igc_undefined = 0, 40 igc_i225, 41 igc_num_macs /* List is 1-based, so subtract 1 for true count. */ 42 }; 43 44 enum igc_phy_type { 45 igc_phy_unknown = 0, 46 igc_phy_none, 47 igc_phy_i225, 48 }; 49 50 enum igc_media_type { 51 igc_media_type_unknown = 0, 52 igc_media_type_copper = 1, 53 igc_num_media_types 54 }; 55 56 enum igc_nvm_type { 57 igc_nvm_unknown = 0, 58 igc_nvm_flash_hw, 59 igc_nvm_invm, 60 }; 61 62 struct igc_info { 63 s32 (*get_invariants)(struct igc_hw *hw); 64 struct igc_mac_operations *mac_ops; 65 const struct igc_phy_operations *phy_ops; 66 struct igc_nvm_operations *nvm_ops; 67 }; 68 69 extern const struct igc_info igc_base_info; 70 71 struct igc_mac_info { 72 struct igc_mac_operations ops; 73 74 u8 addr[ETH_ALEN]; 75 u8 perm_addr[ETH_ALEN]; 76 77 enum igc_mac_type type; 78 79 u32 collision_delta; 80 u32 ledctl_default; 81 u32 ledctl_mode1; 82 u32 ledctl_mode2; 83 u32 mc_filter_type; 84 u32 tx_packet_delta; 85 u32 txcw; 86 87 u16 mta_reg_count; 88 u16 uta_reg_count; 89 90 u16 rar_entry_count; 91 92 u8 forced_speed_duplex; 93 94 bool adaptive_ifs; 95 bool has_fwsm; 96 bool asf_firmware_present; 97 bool arc_subsystem_valid; 98 99 bool autoneg; 100 bool autoneg_failed; 101 bool get_link_status; 102 }; 103 104 struct igc_nvm_operations { 105 s32 (*acquire)(struct igc_hw *hw); 106 s32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 107 void (*release)(struct igc_hw *hw); 108 s32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 109 s32 (*update)(struct igc_hw *hw); 110 s32 (*validate)(struct igc_hw *hw); 111 s32 (*valid_led_default)(struct igc_hw *hw, u16 *data); 112 }; 113 114 struct igc_phy_operations { 115 s32 (*acquire)(struct igc_hw *hw); 116 s32 (*check_polarity)(struct igc_hw *hw); 117 s32 (*check_reset_block)(struct igc_hw *hw); 118 s32 (*force_speed_duplex)(struct igc_hw *hw); 119 s32 (*get_cfg_done)(struct igc_hw *hw); 120 s32 (*get_cable_length)(struct igc_hw *hw); 121 s32 (*get_phy_info)(struct igc_hw *hw); 122 s32 (*read_reg)(struct igc_hw *hw, u32 address, u16 *data); 123 void (*release)(struct igc_hw *hw); 124 s32 (*reset)(struct igc_hw *hw); 125 s32 (*write_reg)(struct igc_hw *hw, u32 address, u16 data); 126 }; 127 128 struct igc_nvm_info { 129 struct igc_nvm_operations ops; 130 enum igc_nvm_type type; 131 132 u32 flash_bank_size; 133 u32 flash_base_addr; 134 135 u16 word_size; 136 u16 delay_usec; 137 u16 address_bits; 138 u16 opcode_bits; 139 u16 page_size; 140 }; 141 142 struct igc_phy_info { 143 struct igc_phy_operations ops; 144 145 enum igc_phy_type type; 146 147 u32 addr; 148 u32 id; 149 u32 reset_delay_us; /* in usec */ 150 u32 revision; 151 152 enum igc_media_type media_type; 153 154 u16 autoneg_advertised; 155 u16 autoneg_mask; 156 u16 cable_length; 157 u16 max_cable_length; 158 u16 min_cable_length; 159 u16 pair_length[4]; 160 161 u8 mdix; 162 163 bool disable_polarity_correction; 164 bool is_mdix; 165 bool polarity_correction; 166 bool reset_disable; 167 bool speed_downgraded; 168 bool autoneg_wait_to_complete; 169 }; 170 171 struct igc_bus_info { 172 u16 func; 173 u16 pci_cmd_word; 174 }; 175 176 enum igc_fc_mode { 177 igc_fc_none = 0, 178 igc_fc_rx_pause, 179 igc_fc_tx_pause, 180 igc_fc_full, 181 igc_fc_default = 0xFF 182 }; 183 184 struct igc_fc_info { 185 u32 high_water; /* Flow control high-water mark */ 186 u32 low_water; /* Flow control low-water mark */ 187 u16 pause_time; /* Flow control pause timer */ 188 bool send_xon; /* Flow control send XON */ 189 bool strict_ieee; /* Strict IEEE mode */ 190 enum igc_fc_mode current_mode; /* Type of flow control */ 191 enum igc_fc_mode requested_mode; 192 }; 193 194 struct igc_dev_spec_base { 195 bool global_device_reset; 196 bool eee_disable; 197 bool clear_semaphore_once; 198 bool module_plugged; 199 u8 media_port; 200 bool mas_capable; 201 }; 202 203 struct igc_hw { 204 void *back; 205 206 u8 __iomem *hw_addr; 207 unsigned long io_base; 208 209 struct igc_mac_info mac; 210 struct igc_fc_info fc; 211 struct igc_nvm_info nvm; 212 struct igc_phy_info phy; 213 214 struct igc_bus_info bus; 215 216 union { 217 struct igc_dev_spec_base _base; 218 } dev_spec; 219 220 u16 device_id; 221 u16 subsystem_vendor_id; 222 u16 subsystem_device_id; 223 u16 vendor_id; 224 225 u8 revision_id; 226 }; 227 228 /* Statistics counters collected by the MAC */ 229 struct igc_hw_stats { 230 u64 crcerrs; 231 u64 algnerrc; 232 u64 symerrs; 233 u64 rxerrc; 234 u64 mpc; 235 u64 scc; 236 u64 ecol; 237 u64 mcc; 238 u64 latecol; 239 u64 colc; 240 u64 dc; 241 u64 tncrs; 242 u64 sec; 243 u64 cexterr; 244 u64 rlec; 245 u64 xonrxc; 246 u64 xontxc; 247 u64 xoffrxc; 248 u64 xofftxc; 249 u64 fcruc; 250 u64 prc64; 251 u64 prc127; 252 u64 prc255; 253 u64 prc511; 254 u64 prc1023; 255 u64 prc1522; 256 u64 gprc; 257 u64 bprc; 258 u64 mprc; 259 u64 gptc; 260 u64 gorc; 261 u64 gotc; 262 u64 rnbc; 263 u64 ruc; 264 u64 rfc; 265 u64 roc; 266 u64 rjc; 267 u64 mgprc; 268 u64 mgpdc; 269 u64 mgptc; 270 u64 tor; 271 u64 tot; 272 u64 tpr; 273 u64 tpt; 274 u64 ptc64; 275 u64 ptc127; 276 u64 ptc255; 277 u64 ptc511; 278 u64 ptc1023; 279 u64 ptc1522; 280 u64 mptc; 281 u64 bptc; 282 u64 tsctc; 283 u64 tsctfc; 284 u64 iac; 285 u64 icrxptc; 286 u64 icrxatc; 287 u64 ictxptc; 288 u64 ictxatc; 289 u64 ictxqec; 290 u64 ictxqmtc; 291 u64 icrxdmtc; 292 u64 icrxoc; 293 u64 cbtmpc; 294 u64 htdpmc; 295 u64 cbrdpc; 296 u64 cbrmpc; 297 u64 rpthc; 298 u64 hgptc; 299 u64 htcbdpc; 300 u64 hgorc; 301 u64 hgotc; 302 u64 lenerrs; 303 u64 scvpc; 304 u64 hrmpc; 305 u64 doosync; 306 u64 o2bgptc; 307 u64 o2bspc; 308 u64 b2ospc; 309 u64 b2ogprc; 310 }; 311 312 struct net_device *igc_get_hw_dev(struct igc_hw *hw); 313 #define hw_dbg(format, arg...) \ 314 netdev_dbg(igc_get_hw_dev(hw), format, ##arg) 315 316 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 317 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 318 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 319 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 320 321 #endif /* _IGC_HW_H_ */ 322