1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_HW_H_ 5 #define _IGC_HW_H_ 6 7 #include <linux/types.h> 8 #include <linux/if_ether.h> 9 #include <linux/netdevice.h> 10 11 #include "igc_regs.h" 12 #include "igc_defines.h" 13 #include "igc_mac.h" 14 #include "igc_phy.h" 15 #include "igc_nvm.h" 16 #include "igc_i225.h" 17 #include "igc_base.h" 18 19 #define IGC_DEV_ID_I225_LM 0x15F2 20 #define IGC_DEV_ID_I225_V 0x15F3 21 #define IGC_DEV_ID_I225_I 0x15F8 22 #define IGC_DEV_ID_I220_V 0x15F7 23 #define IGC_DEV_ID_I225_K 0x3100 24 #define IGC_DEV_ID_I225_K2 0x3101 25 #define IGC_DEV_ID_I225_LMVP 0x5502 26 #define IGC_DEV_ID_I225_IT 0x0D9F 27 #define IGC_DEV_ID_I225_BLANK_NVM 0x15FD 28 29 /* Function pointers for the MAC. */ 30 struct igc_mac_operations { 31 s32 (*check_for_link)(struct igc_hw *hw); 32 s32 (*reset_hw)(struct igc_hw *hw); 33 s32 (*init_hw)(struct igc_hw *hw); 34 s32 (*setup_physical_interface)(struct igc_hw *hw); 35 void (*rar_set)(struct igc_hw *hw, u8 *address, u32 index); 36 s32 (*read_mac_addr)(struct igc_hw *hw); 37 s32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed, 38 u16 *duplex); 39 s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask); 40 void (*release_swfw_sync)(struct igc_hw *hw, u16 mask); 41 }; 42 43 enum igc_mac_type { 44 igc_undefined = 0, 45 igc_i225, 46 igc_num_macs /* List is 1-based, so subtract 1 for true count. */ 47 }; 48 49 enum igc_phy_type { 50 igc_phy_unknown = 0, 51 igc_phy_none, 52 igc_phy_i225, 53 }; 54 55 enum igc_media_type { 56 igc_media_type_unknown = 0, 57 igc_media_type_copper = 1, 58 igc_num_media_types 59 }; 60 61 enum igc_nvm_type { 62 igc_nvm_unknown = 0, 63 igc_nvm_eeprom_spi, 64 igc_nvm_flash_hw, 65 igc_nvm_invm, 66 }; 67 68 struct igc_info { 69 s32 (*get_invariants)(struct igc_hw *hw); 70 struct igc_mac_operations *mac_ops; 71 const struct igc_phy_operations *phy_ops; 72 struct igc_nvm_operations *nvm_ops; 73 }; 74 75 extern const struct igc_info igc_base_info; 76 77 struct igc_mac_info { 78 struct igc_mac_operations ops; 79 80 u8 addr[ETH_ALEN]; 81 u8 perm_addr[ETH_ALEN]; 82 83 enum igc_mac_type type; 84 85 u32 collision_delta; 86 u32 ledctl_default; 87 u32 ledctl_mode1; 88 u32 ledctl_mode2; 89 u32 mc_filter_type; 90 u32 tx_packet_delta; 91 u32 txcw; 92 93 u16 mta_reg_count; 94 u16 uta_reg_count; 95 96 u32 mta_shadow[MAX_MTA_REG]; 97 u16 rar_entry_count; 98 99 u8 forced_speed_duplex; 100 101 bool adaptive_ifs; 102 bool has_fwsm; 103 bool asf_firmware_present; 104 bool arc_subsystem_valid; 105 106 bool autoneg; 107 bool autoneg_failed; 108 bool get_link_status; 109 }; 110 111 struct igc_nvm_operations { 112 s32 (*acquire)(struct igc_hw *hw); 113 s32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 114 void (*release)(struct igc_hw *hw); 115 s32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 116 s32 (*update)(struct igc_hw *hw); 117 s32 (*validate)(struct igc_hw *hw); 118 s32 (*valid_led_default)(struct igc_hw *hw, u16 *data); 119 }; 120 121 struct igc_phy_operations { 122 s32 (*acquire)(struct igc_hw *hw); 123 s32 (*check_reset_block)(struct igc_hw *hw); 124 s32 (*force_speed_duplex)(struct igc_hw *hw); 125 s32 (*get_phy_info)(struct igc_hw *hw); 126 s32 (*read_reg)(struct igc_hw *hw, u32 address, u16 *data); 127 void (*release)(struct igc_hw *hw); 128 s32 (*reset)(struct igc_hw *hw); 129 s32 (*write_reg)(struct igc_hw *hw, u32 address, u16 data); 130 }; 131 132 struct igc_nvm_info { 133 struct igc_nvm_operations ops; 134 enum igc_nvm_type type; 135 136 u32 flash_bank_size; 137 u32 flash_base_addr; 138 139 u16 word_size; 140 u16 delay_usec; 141 u16 address_bits; 142 u16 opcode_bits; 143 u16 page_size; 144 }; 145 146 struct igc_phy_info { 147 struct igc_phy_operations ops; 148 149 enum igc_phy_type type; 150 151 u32 addr; 152 u32 id; 153 u32 reset_delay_us; /* in usec */ 154 u32 revision; 155 156 enum igc_media_type media_type; 157 158 u16 autoneg_advertised; 159 u16 autoneg_mask; 160 161 u8 mdix; 162 163 bool is_mdix; 164 bool reset_disable; 165 bool speed_downgraded; 166 bool autoneg_wait_to_complete; 167 }; 168 169 struct igc_bus_info { 170 u16 func; 171 u16 pci_cmd_word; 172 }; 173 174 enum igc_fc_mode { 175 igc_fc_none = 0, 176 igc_fc_rx_pause, 177 igc_fc_tx_pause, 178 igc_fc_full, 179 igc_fc_default = 0xFF 180 }; 181 182 struct igc_fc_info { 183 u32 high_water; /* Flow control high-water mark */ 184 u32 low_water; /* Flow control low-water mark */ 185 u16 pause_time; /* Flow control pause timer */ 186 bool send_xon; /* Flow control send XON */ 187 bool strict_ieee; /* Strict IEEE mode */ 188 enum igc_fc_mode current_mode; /* Type of flow control */ 189 enum igc_fc_mode requested_mode; 190 }; 191 192 struct igc_dev_spec_base { 193 bool clear_semaphore_once; 194 }; 195 196 struct igc_hw { 197 void *back; 198 199 u8 __iomem *hw_addr; 200 unsigned long io_base; 201 202 struct igc_mac_info mac; 203 struct igc_fc_info fc; 204 struct igc_nvm_info nvm; 205 struct igc_phy_info phy; 206 207 struct igc_bus_info bus; 208 209 union { 210 struct igc_dev_spec_base _base; 211 } dev_spec; 212 213 u16 device_id; 214 u16 subsystem_vendor_id; 215 u16 subsystem_device_id; 216 u16 vendor_id; 217 218 u8 revision_id; 219 }; 220 221 /* Statistics counters collected by the MAC */ 222 struct igc_hw_stats { 223 u64 crcerrs; 224 u64 algnerrc; 225 u64 symerrs; 226 u64 rxerrc; 227 u64 mpc; 228 u64 scc; 229 u64 ecol; 230 u64 mcc; 231 u64 latecol; 232 u64 colc; 233 u64 dc; 234 u64 tncrs; 235 u64 sec; 236 u64 cexterr; 237 u64 rlec; 238 u64 xonrxc; 239 u64 xontxc; 240 u64 xoffrxc; 241 u64 xofftxc; 242 u64 fcruc; 243 u64 prc64; 244 u64 prc127; 245 u64 prc255; 246 u64 prc511; 247 u64 prc1023; 248 u64 prc1522; 249 u64 gprc; 250 u64 bprc; 251 u64 mprc; 252 u64 gptc; 253 u64 gorc; 254 u64 gotc; 255 u64 rnbc; 256 u64 ruc; 257 u64 rfc; 258 u64 roc; 259 u64 rjc; 260 u64 mgprc; 261 u64 mgpdc; 262 u64 mgptc; 263 u64 tor; 264 u64 tot; 265 u64 tpr; 266 u64 tpt; 267 u64 ptc64; 268 u64 ptc127; 269 u64 ptc255; 270 u64 ptc511; 271 u64 ptc1023; 272 u64 ptc1522; 273 u64 mptc; 274 u64 bptc; 275 u64 tsctc; 276 u64 tsctfc; 277 u64 iac; 278 u64 icrxptc; 279 u64 icrxatc; 280 u64 ictxptc; 281 u64 ictxatc; 282 u64 ictxqec; 283 u64 ictxqmtc; 284 u64 icrxdmtc; 285 u64 icrxoc; 286 u64 cbtmpc; 287 u64 htdpmc; 288 u64 cbrdpc; 289 u64 cbrmpc; 290 u64 rpthc; 291 u64 hgptc; 292 u64 htcbdpc; 293 u64 hgorc; 294 u64 hgotc; 295 u64 lenerrs; 296 u64 scvpc; 297 u64 hrmpc; 298 u64 doosync; 299 u64 o2bgptc; 300 u64 o2bspc; 301 u64 b2ospc; 302 u64 b2ogprc; 303 }; 304 305 struct net_device *igc_get_hw_dev(struct igc_hw *hw); 306 #define hw_dbg(format, arg...) \ 307 netdev_dbg(igc_get_hw_dev(hw), format, ##arg) 308 309 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 310 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 311 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 312 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 313 314 #endif /* _IGC_HW_H_ */ 315