1d89f8841SSasha Neftin /* SPDX-License-Identifier: GPL-2.0 */ 2d89f8841SSasha Neftin /* Copyright (c) 2018 Intel Corporation */ 3d89f8841SSasha Neftin 4d89f8841SSasha Neftin #ifndef _IGC_HW_H_ 5d89f8841SSasha Neftin #define _IGC_HW_H_ 6d89f8841SSasha Neftin 7146740f9SSasha Neftin #include <linux/types.h> 8146740f9SSasha Neftin #include <linux/if_ether.h> 9146740f9SSasha Neftin #include "igc_regs.h" 10146740f9SSasha Neftin #include "igc_defines.h" 11146740f9SSasha Neftin #include "igc_mac.h" 12146740f9SSasha Neftin #include "igc_i225.h" 13146740f9SSasha Neftin 14d89f8841SSasha Neftin #define IGC_DEV_ID_I225_LM 0x15F2 15d89f8841SSasha Neftin #define IGC_DEV_ID_I225_V 0x15F3 16d89f8841SSasha Neftin 17146740f9SSasha Neftin /* Function pointers for the MAC. */ 18146740f9SSasha Neftin struct igc_mac_operations { 19146740f9SSasha Neftin }; 20146740f9SSasha Neftin 21146740f9SSasha Neftin enum igc_mac_type { 22146740f9SSasha Neftin igc_undefined = 0, 23146740f9SSasha Neftin igc_i225, 24146740f9SSasha Neftin igc_num_macs /* List is 1-based, so subtract 1 for true count. */ 25146740f9SSasha Neftin }; 26146740f9SSasha Neftin 27146740f9SSasha Neftin enum igc_phy_type { 28146740f9SSasha Neftin igc_phy_unknown = 0, 29146740f9SSasha Neftin igc_phy_none, 30146740f9SSasha Neftin igc_phy_i225, 31146740f9SSasha Neftin }; 32146740f9SSasha Neftin 33146740f9SSasha Neftin struct igc_mac_info { 34146740f9SSasha Neftin struct igc_mac_operations ops; 35146740f9SSasha Neftin 36146740f9SSasha Neftin u8 addr[ETH_ALEN]; 37146740f9SSasha Neftin u8 perm_addr[ETH_ALEN]; 38146740f9SSasha Neftin 39146740f9SSasha Neftin enum igc_mac_type type; 40146740f9SSasha Neftin 41146740f9SSasha Neftin u32 collision_delta; 42146740f9SSasha Neftin u32 ledctl_default; 43146740f9SSasha Neftin u32 ledctl_mode1; 44146740f9SSasha Neftin u32 ledctl_mode2; 45146740f9SSasha Neftin u32 mc_filter_type; 46146740f9SSasha Neftin u32 tx_packet_delta; 47146740f9SSasha Neftin u32 txcw; 48146740f9SSasha Neftin 49146740f9SSasha Neftin u16 mta_reg_count; 50146740f9SSasha Neftin u16 uta_reg_count; 51146740f9SSasha Neftin 52146740f9SSasha Neftin u16 rar_entry_count; 53146740f9SSasha Neftin 54146740f9SSasha Neftin u8 forced_speed_duplex; 55146740f9SSasha Neftin 56146740f9SSasha Neftin bool adaptive_ifs; 57146740f9SSasha Neftin bool has_fwsm; 58146740f9SSasha Neftin bool arc_subsystem_valid; 59146740f9SSasha Neftin 60146740f9SSasha Neftin bool autoneg; 61146740f9SSasha Neftin bool autoneg_failed; 62c9a11c23SSasha Neftin bool get_link_status; 63146740f9SSasha Neftin }; 64146740f9SSasha Neftin 65146740f9SSasha Neftin struct igc_bus_info { 66146740f9SSasha Neftin u16 func; 67146740f9SSasha Neftin u16 pci_cmd_word; 68146740f9SSasha Neftin }; 69146740f9SSasha Neftin 70146740f9SSasha Neftin struct igc_hw { 71146740f9SSasha Neftin void *back; 72146740f9SSasha Neftin 73146740f9SSasha Neftin u8 __iomem *hw_addr; 74146740f9SSasha Neftin unsigned long io_base; 75146740f9SSasha Neftin 76146740f9SSasha Neftin struct igc_mac_info mac; 77146740f9SSasha Neftin 78146740f9SSasha Neftin struct igc_bus_info bus; 79146740f9SSasha Neftin 80146740f9SSasha Neftin u16 device_id; 81146740f9SSasha Neftin u16 subsystem_vendor_id; 82146740f9SSasha Neftin u16 subsystem_device_id; 83146740f9SSasha Neftin u16 vendor_id; 84146740f9SSasha Neftin 85146740f9SSasha Neftin u8 revision_id; 86146740f9SSasha Neftin }; 87146740f9SSasha Neftin 88146740f9SSasha Neftin s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 89146740f9SSasha Neftin s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 90146740f9SSasha Neftin void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 91146740f9SSasha Neftin void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 92146740f9SSasha Neftin 93d89f8841SSasha Neftin #endif /* _IGC_HW_H_ */ 94