1d89f8841SSasha Neftin /* SPDX-License-Identifier: GPL-2.0 */ 2d89f8841SSasha Neftin /* Copyright (c) 2018 Intel Corporation */ 3d89f8841SSasha Neftin 4d89f8841SSasha Neftin #ifndef _IGC_HW_H_ 5d89f8841SSasha Neftin #define _IGC_HW_H_ 6d89f8841SSasha Neftin 7146740f9SSasha Neftin #include <linux/types.h> 8146740f9SSasha Neftin #include <linux/if_ether.h> 9c0071c7aSSasha Neftin #include <linux/netdevice.h> 10c0071c7aSSasha Neftin 11146740f9SSasha Neftin #include "igc_regs.h" 12146740f9SSasha Neftin #include "igc_defines.h" 13146740f9SSasha Neftin #include "igc_mac.h" 14ab405612SSasha Neftin #include "igc_nvm.h" 15146740f9SSasha Neftin #include "igc_i225.h" 1613b5b7fdSSasha Neftin #include "igc_base.h" 17146740f9SSasha Neftin 18d89f8841SSasha Neftin #define IGC_DEV_ID_I225_LM 0x15F2 19d89f8841SSasha Neftin #define IGC_DEV_ID_I225_V 0x15F3 20d89f8841SSasha Neftin 21146740f9SSasha Neftin /* Function pointers for the MAC. */ 22146740f9SSasha Neftin struct igc_mac_operations { 23c0071c7aSSasha Neftin s32 (*check_for_link)(struct igc_hw *hw); 24c0071c7aSSasha Neftin s32 (*reset_hw)(struct igc_hw *hw); 25c0071c7aSSasha Neftin s32 (*init_hw)(struct igc_hw *hw); 26c0071c7aSSasha Neftin s32 (*setup_physical_interface)(struct igc_hw *hw); 27c0071c7aSSasha Neftin void (*rar_set)(struct igc_hw *hw, u8 *address, u32 index); 28c0071c7aSSasha Neftin s32 (*read_mac_addr)(struct igc_hw *hw); 29c0071c7aSSasha Neftin s32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed, 30c0071c7aSSasha Neftin u16 *duplex); 31c0071c7aSSasha Neftin s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask); 32c0071c7aSSasha Neftin void (*release_swfw_sync)(struct igc_hw *hw, u16 mask); 33146740f9SSasha Neftin }; 34146740f9SSasha Neftin 35146740f9SSasha Neftin enum igc_mac_type { 36146740f9SSasha Neftin igc_undefined = 0, 37146740f9SSasha Neftin igc_i225, 38146740f9SSasha Neftin igc_num_macs /* List is 1-based, so subtract 1 for true count. */ 39146740f9SSasha Neftin }; 40146740f9SSasha Neftin 41146740f9SSasha Neftin enum igc_phy_type { 42146740f9SSasha Neftin igc_phy_unknown = 0, 43146740f9SSasha Neftin igc_phy_none, 44146740f9SSasha Neftin igc_phy_i225, 45146740f9SSasha Neftin }; 46146740f9SSasha Neftin 47c0071c7aSSasha Neftin enum igc_nvm_type { 48c0071c7aSSasha Neftin igc_nvm_unknown = 0, 49c0071c7aSSasha Neftin igc_nvm_flash_hw, 50c0071c7aSSasha Neftin igc_nvm_invm, 51c0071c7aSSasha Neftin }; 52c0071c7aSSasha Neftin 53c0071c7aSSasha Neftin struct igc_info { 54c0071c7aSSasha Neftin s32 (*get_invariants)(struct igc_hw *hw); 55c0071c7aSSasha Neftin struct igc_mac_operations *mac_ops; 56c0071c7aSSasha Neftin const struct igc_phy_operations *phy_ops; 57c0071c7aSSasha Neftin struct igc_nvm_operations *nvm_ops; 58c0071c7aSSasha Neftin }; 59c0071c7aSSasha Neftin 60ab405612SSasha Neftin extern const struct igc_info igc_base_info; 61ab405612SSasha Neftin 62146740f9SSasha Neftin struct igc_mac_info { 63146740f9SSasha Neftin struct igc_mac_operations ops; 64146740f9SSasha Neftin 65146740f9SSasha Neftin u8 addr[ETH_ALEN]; 66146740f9SSasha Neftin u8 perm_addr[ETH_ALEN]; 67146740f9SSasha Neftin 68146740f9SSasha Neftin enum igc_mac_type type; 69146740f9SSasha Neftin 70146740f9SSasha Neftin u32 collision_delta; 71146740f9SSasha Neftin u32 ledctl_default; 72146740f9SSasha Neftin u32 ledctl_mode1; 73146740f9SSasha Neftin u32 ledctl_mode2; 74146740f9SSasha Neftin u32 mc_filter_type; 75146740f9SSasha Neftin u32 tx_packet_delta; 76146740f9SSasha Neftin u32 txcw; 77146740f9SSasha Neftin 78146740f9SSasha Neftin u16 mta_reg_count; 79146740f9SSasha Neftin u16 uta_reg_count; 80146740f9SSasha Neftin 81146740f9SSasha Neftin u16 rar_entry_count; 82146740f9SSasha Neftin 83146740f9SSasha Neftin u8 forced_speed_duplex; 84146740f9SSasha Neftin 85146740f9SSasha Neftin bool adaptive_ifs; 86146740f9SSasha Neftin bool has_fwsm; 87146740f9SSasha Neftin bool arc_subsystem_valid; 88146740f9SSasha Neftin 89146740f9SSasha Neftin bool autoneg; 90146740f9SSasha Neftin bool autoneg_failed; 91c9a11c23SSasha Neftin bool get_link_status; 92146740f9SSasha Neftin }; 93146740f9SSasha Neftin 94c0071c7aSSasha Neftin struct igc_nvm_operations { 95c0071c7aSSasha Neftin s32 (*acquire)(struct igc_hw *hw); 96c0071c7aSSasha Neftin s32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 97c0071c7aSSasha Neftin void (*release)(struct igc_hw *hw); 98c0071c7aSSasha Neftin s32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 99c0071c7aSSasha Neftin s32 (*update)(struct igc_hw *hw); 100c0071c7aSSasha Neftin s32 (*validate)(struct igc_hw *hw); 101c0071c7aSSasha Neftin s32 (*valid_led_default)(struct igc_hw *hw, u16 *data); 102c0071c7aSSasha Neftin }; 103c0071c7aSSasha Neftin 104c0071c7aSSasha Neftin struct igc_nvm_info { 105c0071c7aSSasha Neftin struct igc_nvm_operations ops; 106c0071c7aSSasha Neftin enum igc_nvm_type type; 107c0071c7aSSasha Neftin 108c0071c7aSSasha Neftin u32 flash_bank_size; 109c0071c7aSSasha Neftin u32 flash_base_addr; 110c0071c7aSSasha Neftin 111c0071c7aSSasha Neftin u16 word_size; 112c0071c7aSSasha Neftin u16 delay_usec; 113c0071c7aSSasha Neftin u16 address_bits; 114c0071c7aSSasha Neftin u16 opcode_bits; 115c0071c7aSSasha Neftin u16 page_size; 116c0071c7aSSasha Neftin }; 117c0071c7aSSasha Neftin 118146740f9SSasha Neftin struct igc_bus_info { 119146740f9SSasha Neftin u16 func; 120146740f9SSasha Neftin u16 pci_cmd_word; 121146740f9SSasha Neftin }; 122146740f9SSasha Neftin 123c0071c7aSSasha Neftin enum igc_fc_mode { 124c0071c7aSSasha Neftin igc_fc_none = 0, 125c0071c7aSSasha Neftin igc_fc_rx_pause, 126c0071c7aSSasha Neftin igc_fc_tx_pause, 127c0071c7aSSasha Neftin igc_fc_full, 128c0071c7aSSasha Neftin igc_fc_default = 0xFF 129c0071c7aSSasha Neftin }; 130c0071c7aSSasha Neftin 131c0071c7aSSasha Neftin struct igc_fc_info { 132c0071c7aSSasha Neftin u32 high_water; /* Flow control high-water mark */ 133c0071c7aSSasha Neftin u32 low_water; /* Flow control low-water mark */ 134c0071c7aSSasha Neftin u16 pause_time; /* Flow control pause timer */ 135c0071c7aSSasha Neftin bool send_xon; /* Flow control send XON */ 136c0071c7aSSasha Neftin bool strict_ieee; /* Strict IEEE mode */ 137c0071c7aSSasha Neftin enum igc_fc_mode current_mode; /* Type of flow control */ 138c0071c7aSSasha Neftin enum igc_fc_mode requested_mode; 139c0071c7aSSasha Neftin }; 140c0071c7aSSasha Neftin 141c0071c7aSSasha Neftin struct igc_dev_spec_base { 142c0071c7aSSasha Neftin bool global_device_reset; 143c0071c7aSSasha Neftin bool eee_disable; 144c0071c7aSSasha Neftin bool clear_semaphore_once; 145c0071c7aSSasha Neftin bool module_plugged; 146c0071c7aSSasha Neftin u8 media_port; 147c0071c7aSSasha Neftin }; 148c0071c7aSSasha Neftin 149146740f9SSasha Neftin struct igc_hw { 150146740f9SSasha Neftin void *back; 151146740f9SSasha Neftin 152146740f9SSasha Neftin u8 __iomem *hw_addr; 153146740f9SSasha Neftin unsigned long io_base; 154146740f9SSasha Neftin 155146740f9SSasha Neftin struct igc_mac_info mac; 156c0071c7aSSasha Neftin struct igc_fc_info fc; 157c0071c7aSSasha Neftin struct igc_nvm_info nvm; 158146740f9SSasha Neftin 159146740f9SSasha Neftin struct igc_bus_info bus; 160146740f9SSasha Neftin 161c0071c7aSSasha Neftin union { 162c0071c7aSSasha Neftin struct igc_dev_spec_base _base; 163c0071c7aSSasha Neftin } dev_spec; 164c0071c7aSSasha Neftin 165146740f9SSasha Neftin u16 device_id; 166146740f9SSasha Neftin u16 subsystem_vendor_id; 167146740f9SSasha Neftin u16 subsystem_device_id; 168146740f9SSasha Neftin u16 vendor_id; 169146740f9SSasha Neftin 170146740f9SSasha Neftin u8 revision_id; 171146740f9SSasha Neftin }; 172146740f9SSasha Neftin 1733df25e4cSSasha Neftin /* Statistics counters collected by the MAC */ 1743df25e4cSSasha Neftin struct igc_hw_stats { 1753df25e4cSSasha Neftin u64 crcerrs; 1763df25e4cSSasha Neftin u64 algnerrc; 1773df25e4cSSasha Neftin u64 symerrs; 1783df25e4cSSasha Neftin u64 rxerrc; 1793df25e4cSSasha Neftin u64 mpc; 1803df25e4cSSasha Neftin u64 scc; 1813df25e4cSSasha Neftin u64 ecol; 1823df25e4cSSasha Neftin u64 mcc; 1833df25e4cSSasha Neftin u64 latecol; 1843df25e4cSSasha Neftin u64 colc; 1853df25e4cSSasha Neftin u64 dc; 1863df25e4cSSasha Neftin u64 tncrs; 1873df25e4cSSasha Neftin u64 sec; 1883df25e4cSSasha Neftin u64 cexterr; 1893df25e4cSSasha Neftin u64 rlec; 1903df25e4cSSasha Neftin u64 xonrxc; 1913df25e4cSSasha Neftin u64 xontxc; 1923df25e4cSSasha Neftin u64 xoffrxc; 1933df25e4cSSasha Neftin u64 xofftxc; 1943df25e4cSSasha Neftin u64 fcruc; 1953df25e4cSSasha Neftin u64 prc64; 1963df25e4cSSasha Neftin u64 prc127; 1973df25e4cSSasha Neftin u64 prc255; 1983df25e4cSSasha Neftin u64 prc511; 1993df25e4cSSasha Neftin u64 prc1023; 2003df25e4cSSasha Neftin u64 prc1522; 2013df25e4cSSasha Neftin u64 gprc; 2023df25e4cSSasha Neftin u64 bprc; 2033df25e4cSSasha Neftin u64 mprc; 2043df25e4cSSasha Neftin u64 gptc; 2053df25e4cSSasha Neftin u64 gorc; 2063df25e4cSSasha Neftin u64 gotc; 2073df25e4cSSasha Neftin u64 rnbc; 2083df25e4cSSasha Neftin u64 ruc; 2093df25e4cSSasha Neftin u64 rfc; 2103df25e4cSSasha Neftin u64 roc; 2113df25e4cSSasha Neftin u64 rjc; 2123df25e4cSSasha Neftin u64 mgprc; 2133df25e4cSSasha Neftin u64 mgpdc; 2143df25e4cSSasha Neftin u64 mgptc; 2153df25e4cSSasha Neftin u64 tor; 2163df25e4cSSasha Neftin u64 tot; 2173df25e4cSSasha Neftin u64 tpr; 2183df25e4cSSasha Neftin u64 tpt; 2193df25e4cSSasha Neftin u64 ptc64; 2203df25e4cSSasha Neftin u64 ptc127; 2213df25e4cSSasha Neftin u64 ptc255; 2223df25e4cSSasha Neftin u64 ptc511; 2233df25e4cSSasha Neftin u64 ptc1023; 2243df25e4cSSasha Neftin u64 ptc1522; 2253df25e4cSSasha Neftin u64 mptc; 2263df25e4cSSasha Neftin u64 bptc; 2273df25e4cSSasha Neftin u64 tsctc; 2283df25e4cSSasha Neftin u64 tsctfc; 2293df25e4cSSasha Neftin u64 iac; 2303df25e4cSSasha Neftin u64 icrxptc; 2313df25e4cSSasha Neftin u64 icrxatc; 2323df25e4cSSasha Neftin u64 ictxptc; 2333df25e4cSSasha Neftin u64 ictxatc; 2343df25e4cSSasha Neftin u64 ictxqec; 2353df25e4cSSasha Neftin u64 ictxqmtc; 2363df25e4cSSasha Neftin u64 icrxdmtc; 2373df25e4cSSasha Neftin u64 icrxoc; 2383df25e4cSSasha Neftin u64 cbtmpc; 2393df25e4cSSasha Neftin u64 htdpmc; 2403df25e4cSSasha Neftin u64 cbrdpc; 2413df25e4cSSasha Neftin u64 cbrmpc; 2423df25e4cSSasha Neftin u64 rpthc; 2433df25e4cSSasha Neftin u64 hgptc; 2443df25e4cSSasha Neftin u64 htcbdpc; 2453df25e4cSSasha Neftin u64 hgorc; 2463df25e4cSSasha Neftin u64 hgotc; 2473df25e4cSSasha Neftin u64 lenerrs; 2483df25e4cSSasha Neftin u64 scvpc; 2493df25e4cSSasha Neftin u64 hrmpc; 2503df25e4cSSasha Neftin u64 doosync; 2513df25e4cSSasha Neftin u64 o2bgptc; 2523df25e4cSSasha Neftin u64 o2bspc; 2533df25e4cSSasha Neftin u64 b2ospc; 2543df25e4cSSasha Neftin u64 b2ogprc; 2553df25e4cSSasha Neftin }; 2563df25e4cSSasha Neftin 257c0071c7aSSasha Neftin struct net_device *igc_get_hw_dev(struct igc_hw *hw); 258c0071c7aSSasha Neftin #define hw_dbg(format, arg...) \ 259c0071c7aSSasha Neftin netdev_dbg(igc_get_hw_dev(hw), format, ##arg) 260c0071c7aSSasha Neftin 261146740f9SSasha Neftin s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 262146740f9SSasha Neftin s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 263146740f9SSasha Neftin void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 264146740f9SSasha Neftin void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 265146740f9SSasha Neftin 266d89f8841SSasha Neftin #endif /* _IGC_HW_H_ */ 267