1d89f8841SSasha Neftin /* SPDX-License-Identifier: GPL-2.0 */ 2d89f8841SSasha Neftin /* Copyright (c) 2018 Intel Corporation */ 3d89f8841SSasha Neftin 4d89f8841SSasha Neftin #ifndef _IGC_HW_H_ 5d89f8841SSasha Neftin #define _IGC_HW_H_ 6d89f8841SSasha Neftin 7146740f9SSasha Neftin #include <linux/types.h> 8146740f9SSasha Neftin #include <linux/if_ether.h> 9c0071c7aSSasha Neftin #include <linux/netdevice.h> 10c0071c7aSSasha Neftin 11146740f9SSasha Neftin #include "igc_regs.h" 12146740f9SSasha Neftin #include "igc_defines.h" 13146740f9SSasha Neftin #include "igc_mac.h" 145586838fSSasha Neftin #include "igc_phy.h" 15ab405612SSasha Neftin #include "igc_nvm.h" 16146740f9SSasha Neftin #include "igc_i225.h" 1713b5b7fdSSasha Neftin #include "igc_base.h" 18146740f9SSasha Neftin 19d89f8841SSasha Neftin #define IGC_DEV_ID_I225_LM 0x15F2 20d89f8841SSasha Neftin #define IGC_DEV_ID_I225_V 0x15F3 216d37a382SSasha Neftin #define IGC_DEV_ID_I225_I 0x15F8 226d37a382SSasha Neftin #define IGC_DEV_ID_I220_V 0x15F7 236d37a382SSasha Neftin #define IGC_DEV_ID_I225_K 0x3100 24c2a3f8feSSasha Neftin #define IGC_DEV_ID_I225_K2 0x3101 25c2a3f8feSSasha Neftin #define IGC_DEV_ID_I225_LMVP 0x5502 26c2a3f8feSSasha Neftin #define IGC_DEV_ID_I225_IT 0x0D9F 270e7d4b93SSasha Neftin #define IGC_DEV_ID_I225_BLANK_NVM 0x15FD 28d89f8841SSasha Neftin 29146740f9SSasha Neftin /* Function pointers for the MAC. */ 30146740f9SSasha Neftin struct igc_mac_operations { 31c0071c7aSSasha Neftin s32 (*check_for_link)(struct igc_hw *hw); 32c0071c7aSSasha Neftin s32 (*reset_hw)(struct igc_hw *hw); 33c0071c7aSSasha Neftin s32 (*init_hw)(struct igc_hw *hw); 34c0071c7aSSasha Neftin s32 (*setup_physical_interface)(struct igc_hw *hw); 35c0071c7aSSasha Neftin void (*rar_set)(struct igc_hw *hw, u8 *address, u32 index); 36c0071c7aSSasha Neftin s32 (*read_mac_addr)(struct igc_hw *hw); 37c0071c7aSSasha Neftin s32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed, 38c0071c7aSSasha Neftin u16 *duplex); 39c0071c7aSSasha Neftin s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask); 40c0071c7aSSasha Neftin void (*release_swfw_sync)(struct igc_hw *hw, u16 mask); 41146740f9SSasha Neftin }; 42146740f9SSasha Neftin 43146740f9SSasha Neftin enum igc_mac_type { 44146740f9SSasha Neftin igc_undefined = 0, 45146740f9SSasha Neftin igc_i225, 46146740f9SSasha Neftin igc_num_macs /* List is 1-based, so subtract 1 for true count. */ 47146740f9SSasha Neftin }; 48146740f9SSasha Neftin 49146740f9SSasha Neftin enum igc_phy_type { 50146740f9SSasha Neftin igc_phy_unknown = 0, 51146740f9SSasha Neftin igc_phy_none, 52146740f9SSasha Neftin igc_phy_i225, 53146740f9SSasha Neftin }; 54146740f9SSasha Neftin 555586838fSSasha Neftin enum igc_media_type { 565586838fSSasha Neftin igc_media_type_unknown = 0, 575586838fSSasha Neftin igc_media_type_copper = 1, 585586838fSSasha Neftin igc_num_media_types 595586838fSSasha Neftin }; 605586838fSSasha Neftin 61c0071c7aSSasha Neftin enum igc_nvm_type { 62c0071c7aSSasha Neftin igc_nvm_unknown = 0, 638c5ad0daSSasha Neftin igc_nvm_eeprom_spi, 64c0071c7aSSasha Neftin igc_nvm_flash_hw, 65c0071c7aSSasha Neftin igc_nvm_invm, 66c0071c7aSSasha Neftin }; 67c0071c7aSSasha Neftin 68c0071c7aSSasha Neftin struct igc_info { 69c0071c7aSSasha Neftin s32 (*get_invariants)(struct igc_hw *hw); 70c0071c7aSSasha Neftin struct igc_mac_operations *mac_ops; 71c0071c7aSSasha Neftin const struct igc_phy_operations *phy_ops; 72c0071c7aSSasha Neftin struct igc_nvm_operations *nvm_ops; 73c0071c7aSSasha Neftin }; 74c0071c7aSSasha Neftin 75ab405612SSasha Neftin extern const struct igc_info igc_base_info; 76ab405612SSasha Neftin 77146740f9SSasha Neftin struct igc_mac_info { 78146740f9SSasha Neftin struct igc_mac_operations ops; 79146740f9SSasha Neftin 80146740f9SSasha Neftin u8 addr[ETH_ALEN]; 81146740f9SSasha Neftin u8 perm_addr[ETH_ALEN]; 82146740f9SSasha Neftin 83146740f9SSasha Neftin enum igc_mac_type type; 84146740f9SSasha Neftin 85146740f9SSasha Neftin u32 collision_delta; 86146740f9SSasha Neftin u32 ledctl_default; 87146740f9SSasha Neftin u32 ledctl_mode1; 88146740f9SSasha Neftin u32 ledctl_mode2; 89146740f9SSasha Neftin u32 mc_filter_type; 90146740f9SSasha Neftin u32 tx_packet_delta; 91146740f9SSasha Neftin u32 txcw; 92146740f9SSasha Neftin 93146740f9SSasha Neftin u16 mta_reg_count; 94146740f9SSasha Neftin u16 uta_reg_count; 95146740f9SSasha Neftin 967f839684SSasha Neftin u32 mta_shadow[MAX_MTA_REG]; 97146740f9SSasha Neftin u16 rar_entry_count; 98146740f9SSasha Neftin 99146740f9SSasha Neftin u8 forced_speed_duplex; 100146740f9SSasha Neftin 101146740f9SSasha Neftin bool adaptive_ifs; 102146740f9SSasha Neftin bool has_fwsm; 1035586838fSSasha Neftin bool asf_firmware_present; 104146740f9SSasha Neftin bool arc_subsystem_valid; 105146740f9SSasha Neftin 106146740f9SSasha Neftin bool autoneg; 107146740f9SSasha Neftin bool autoneg_failed; 108c9a11c23SSasha Neftin bool get_link_status; 109146740f9SSasha Neftin }; 110146740f9SSasha Neftin 111c0071c7aSSasha Neftin struct igc_nvm_operations { 112c0071c7aSSasha Neftin s32 (*acquire)(struct igc_hw *hw); 113c0071c7aSSasha Neftin s32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 114c0071c7aSSasha Neftin void (*release)(struct igc_hw *hw); 115c0071c7aSSasha Neftin s32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 116c0071c7aSSasha Neftin s32 (*update)(struct igc_hw *hw); 117c0071c7aSSasha Neftin s32 (*validate)(struct igc_hw *hw); 118c0071c7aSSasha Neftin s32 (*valid_led_default)(struct igc_hw *hw, u16 *data); 119c0071c7aSSasha Neftin }; 120c0071c7aSSasha Neftin 1215586838fSSasha Neftin struct igc_phy_operations { 1225586838fSSasha Neftin s32 (*acquire)(struct igc_hw *hw); 1235586838fSSasha Neftin s32 (*check_reset_block)(struct igc_hw *hw); 1245586838fSSasha Neftin s32 (*force_speed_duplex)(struct igc_hw *hw); 1255586838fSSasha Neftin s32 (*get_phy_info)(struct igc_hw *hw); 1265586838fSSasha Neftin s32 (*read_reg)(struct igc_hw *hw, u32 address, u16 *data); 1275586838fSSasha Neftin void (*release)(struct igc_hw *hw); 1285586838fSSasha Neftin s32 (*reset)(struct igc_hw *hw); 1295586838fSSasha Neftin s32 (*write_reg)(struct igc_hw *hw, u32 address, u16 data); 1305586838fSSasha Neftin }; 1315586838fSSasha Neftin 132c0071c7aSSasha Neftin struct igc_nvm_info { 133c0071c7aSSasha Neftin struct igc_nvm_operations ops; 134c0071c7aSSasha Neftin enum igc_nvm_type type; 135c0071c7aSSasha Neftin 136c0071c7aSSasha Neftin u32 flash_bank_size; 137c0071c7aSSasha Neftin u32 flash_base_addr; 138c0071c7aSSasha Neftin 139c0071c7aSSasha Neftin u16 word_size; 140c0071c7aSSasha Neftin u16 delay_usec; 141c0071c7aSSasha Neftin u16 address_bits; 142c0071c7aSSasha Neftin u16 opcode_bits; 143c0071c7aSSasha Neftin u16 page_size; 144c0071c7aSSasha Neftin }; 145c0071c7aSSasha Neftin 1465586838fSSasha Neftin struct igc_phy_info { 1475586838fSSasha Neftin struct igc_phy_operations ops; 1485586838fSSasha Neftin 1495586838fSSasha Neftin enum igc_phy_type type; 1505586838fSSasha Neftin 1515586838fSSasha Neftin u32 addr; 1525586838fSSasha Neftin u32 id; 1535586838fSSasha Neftin u32 reset_delay_us; /* in usec */ 1545586838fSSasha Neftin u32 revision; 1555586838fSSasha Neftin 1565586838fSSasha Neftin enum igc_media_type media_type; 1575586838fSSasha Neftin 1585586838fSSasha Neftin u16 autoneg_advertised; 1595586838fSSasha Neftin u16 autoneg_mask; 1605586838fSSasha Neftin 1615586838fSSasha Neftin u8 mdix; 1625586838fSSasha Neftin 1635586838fSSasha Neftin bool is_mdix; 1645586838fSSasha Neftin bool reset_disable; 1655586838fSSasha Neftin bool speed_downgraded; 1665586838fSSasha Neftin bool autoneg_wait_to_complete; 1675586838fSSasha Neftin }; 1685586838fSSasha Neftin 169146740f9SSasha Neftin struct igc_bus_info { 170146740f9SSasha Neftin u16 func; 171146740f9SSasha Neftin u16 pci_cmd_word; 172146740f9SSasha Neftin }; 173146740f9SSasha Neftin 174c0071c7aSSasha Neftin enum igc_fc_mode { 175c0071c7aSSasha Neftin igc_fc_none = 0, 176c0071c7aSSasha Neftin igc_fc_rx_pause, 177c0071c7aSSasha Neftin igc_fc_tx_pause, 178c0071c7aSSasha Neftin igc_fc_full, 179c0071c7aSSasha Neftin igc_fc_default = 0xFF 180c0071c7aSSasha Neftin }; 181c0071c7aSSasha Neftin 182c0071c7aSSasha Neftin struct igc_fc_info { 183c0071c7aSSasha Neftin u32 high_water; /* Flow control high-water mark */ 184c0071c7aSSasha Neftin u32 low_water; /* Flow control low-water mark */ 185c0071c7aSSasha Neftin u16 pause_time; /* Flow control pause timer */ 186c0071c7aSSasha Neftin bool send_xon; /* Flow control send XON */ 187c0071c7aSSasha Neftin bool strict_ieee; /* Strict IEEE mode */ 188c0071c7aSSasha Neftin enum igc_fc_mode current_mode; /* Type of flow control */ 189c0071c7aSSasha Neftin enum igc_fc_mode requested_mode; 190c0071c7aSSasha Neftin }; 191c0071c7aSSasha Neftin 192c0071c7aSSasha Neftin struct igc_dev_spec_base { 193c0071c7aSSasha Neftin bool clear_semaphore_once; 19493ec439aSSasha Neftin bool eee_enable; 195c0071c7aSSasha Neftin }; 196c0071c7aSSasha Neftin 197146740f9SSasha Neftin struct igc_hw { 198146740f9SSasha Neftin void *back; 199146740f9SSasha Neftin 200146740f9SSasha Neftin u8 __iomem *hw_addr; 201146740f9SSasha Neftin unsigned long io_base; 202146740f9SSasha Neftin 203146740f9SSasha Neftin struct igc_mac_info mac; 204c0071c7aSSasha Neftin struct igc_fc_info fc; 205c0071c7aSSasha Neftin struct igc_nvm_info nvm; 2065586838fSSasha Neftin struct igc_phy_info phy; 207146740f9SSasha Neftin 208146740f9SSasha Neftin struct igc_bus_info bus; 209146740f9SSasha Neftin 210c0071c7aSSasha Neftin union { 211c0071c7aSSasha Neftin struct igc_dev_spec_base _base; 212c0071c7aSSasha Neftin } dev_spec; 213c0071c7aSSasha Neftin 214146740f9SSasha Neftin u16 device_id; 215146740f9SSasha Neftin u16 subsystem_vendor_id; 216146740f9SSasha Neftin u16 subsystem_device_id; 217146740f9SSasha Neftin u16 vendor_id; 218146740f9SSasha Neftin 219146740f9SSasha Neftin u8 revision_id; 220146740f9SSasha Neftin }; 221146740f9SSasha Neftin 2223df25e4cSSasha Neftin /* Statistics counters collected by the MAC */ 2233df25e4cSSasha Neftin struct igc_hw_stats { 2243df25e4cSSasha Neftin u64 crcerrs; 2253df25e4cSSasha Neftin u64 algnerrc; 2263df25e4cSSasha Neftin u64 symerrs; 2273df25e4cSSasha Neftin u64 rxerrc; 2283df25e4cSSasha Neftin u64 mpc; 2293df25e4cSSasha Neftin u64 scc; 2303df25e4cSSasha Neftin u64 ecol; 2313df25e4cSSasha Neftin u64 mcc; 2323df25e4cSSasha Neftin u64 latecol; 2333df25e4cSSasha Neftin u64 colc; 2343df25e4cSSasha Neftin u64 dc; 2353df25e4cSSasha Neftin u64 tncrs; 2363df25e4cSSasha Neftin u64 sec; 2373df25e4cSSasha Neftin u64 cexterr; 2383df25e4cSSasha Neftin u64 rlec; 2393df25e4cSSasha Neftin u64 xonrxc; 2403df25e4cSSasha Neftin u64 xontxc; 2413df25e4cSSasha Neftin u64 xoffrxc; 2423df25e4cSSasha Neftin u64 xofftxc; 2433df25e4cSSasha Neftin u64 fcruc; 2443df25e4cSSasha Neftin u64 prc64; 2453df25e4cSSasha Neftin u64 prc127; 2463df25e4cSSasha Neftin u64 prc255; 2473df25e4cSSasha Neftin u64 prc511; 2483df25e4cSSasha Neftin u64 prc1023; 2493df25e4cSSasha Neftin u64 prc1522; 2503df25e4cSSasha Neftin u64 gprc; 2513df25e4cSSasha Neftin u64 bprc; 2523df25e4cSSasha Neftin u64 mprc; 2533df25e4cSSasha Neftin u64 gptc; 2543df25e4cSSasha Neftin u64 gorc; 2553df25e4cSSasha Neftin u64 gotc; 2563df25e4cSSasha Neftin u64 rnbc; 2573df25e4cSSasha Neftin u64 ruc; 2583df25e4cSSasha Neftin u64 rfc; 2593df25e4cSSasha Neftin u64 roc; 2603df25e4cSSasha Neftin u64 rjc; 2613df25e4cSSasha Neftin u64 mgprc; 2623df25e4cSSasha Neftin u64 mgpdc; 2633df25e4cSSasha Neftin u64 mgptc; 2643df25e4cSSasha Neftin u64 tor; 2653df25e4cSSasha Neftin u64 tot; 2663df25e4cSSasha Neftin u64 tpr; 2673df25e4cSSasha Neftin u64 tpt; 2683df25e4cSSasha Neftin u64 ptc64; 2693df25e4cSSasha Neftin u64 ptc127; 2703df25e4cSSasha Neftin u64 ptc255; 2713df25e4cSSasha Neftin u64 ptc511; 2723df25e4cSSasha Neftin u64 ptc1023; 2733df25e4cSSasha Neftin u64 ptc1522; 2743df25e4cSSasha Neftin u64 mptc; 2753df25e4cSSasha Neftin u64 bptc; 2763df25e4cSSasha Neftin u64 tsctc; 2773df25e4cSSasha Neftin u64 tsctfc; 2783df25e4cSSasha Neftin u64 iac; 2793df25e4cSSasha Neftin u64 icrxptc; 2803df25e4cSSasha Neftin u64 icrxatc; 2813df25e4cSSasha Neftin u64 ictxptc; 2823df25e4cSSasha Neftin u64 ictxatc; 2833df25e4cSSasha Neftin u64 ictxqec; 2843df25e4cSSasha Neftin u64 ictxqmtc; 2853df25e4cSSasha Neftin u64 icrxdmtc; 2863df25e4cSSasha Neftin u64 icrxoc; 2873df25e4cSSasha Neftin u64 cbtmpc; 2883df25e4cSSasha Neftin u64 htdpmc; 2893df25e4cSSasha Neftin u64 cbrdpc; 2903df25e4cSSasha Neftin u64 cbrmpc; 2913df25e4cSSasha Neftin u64 rpthc; 2923df25e4cSSasha Neftin u64 hgptc; 2933df25e4cSSasha Neftin u64 htcbdpc; 2943df25e4cSSasha Neftin u64 hgorc; 2953df25e4cSSasha Neftin u64 hgotc; 2963df25e4cSSasha Neftin u64 lenerrs; 2973df25e4cSSasha Neftin u64 scvpc; 2983df25e4cSSasha Neftin u64 hrmpc; 2993df25e4cSSasha Neftin u64 doosync; 3003df25e4cSSasha Neftin u64 o2bgptc; 3013df25e4cSSasha Neftin u64 o2bspc; 3023df25e4cSSasha Neftin u64 b2ospc; 3033df25e4cSSasha Neftin u64 b2ogprc; 3043df25e4cSSasha Neftin }; 3053df25e4cSSasha Neftin 306c0071c7aSSasha Neftin struct net_device *igc_get_hw_dev(struct igc_hw *hw); 307c0071c7aSSasha Neftin #define hw_dbg(format, arg...) \ 308c0071c7aSSasha Neftin netdev_dbg(igc_get_hw_dev(hw), format, ##arg) 309c0071c7aSSasha Neftin 310146740f9SSasha Neftin s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 311146740f9SSasha Neftin s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 312146740f9SSasha Neftin void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 313146740f9SSasha Neftin void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 314146740f9SSasha Neftin 315d89f8841SSasha Neftin #endif /* _IGC_HW_H_ */ 316