1d89f8841SSasha Neftin /* SPDX-License-Identifier: GPL-2.0 */ 2d89f8841SSasha Neftin /* Copyright (c) 2018 Intel Corporation */ 3d89f8841SSasha Neftin 4d89f8841SSasha Neftin #ifndef _IGC_HW_H_ 5d89f8841SSasha Neftin #define _IGC_HW_H_ 6d89f8841SSasha Neftin 7146740f9SSasha Neftin #include <linux/types.h> 8146740f9SSasha Neftin #include <linux/if_ether.h> 9c0071c7aSSasha Neftin #include <linux/netdevice.h> 10c0071c7aSSasha Neftin 11146740f9SSasha Neftin #include "igc_regs.h" 12146740f9SSasha Neftin #include "igc_defines.h" 13146740f9SSasha Neftin #include "igc_mac.h" 145586838fSSasha Neftin #include "igc_phy.h" 15ab405612SSasha Neftin #include "igc_nvm.h" 16146740f9SSasha Neftin #include "igc_i225.h" 1713b5b7fdSSasha Neftin #include "igc_base.h" 18146740f9SSasha Neftin 19d89f8841SSasha Neftin #define IGC_DEV_ID_I225_LM 0x15F2 20d89f8841SSasha Neftin #define IGC_DEV_ID_I225_V 0x15F3 216d37a382SSasha Neftin #define IGC_DEV_ID_I225_I 0x15F8 226d37a382SSasha Neftin #define IGC_DEV_ID_I220_V 0x15F7 236d37a382SSasha Neftin #define IGC_DEV_ID_I225_K 0x3100 24c2a3f8feSSasha Neftin #define IGC_DEV_ID_I225_K2 0x3101 2579cc8322SSasha Neftin #define IGC_DEV_ID_I226_K 0x3102 26c2a3f8feSSasha Neftin #define IGC_DEV_ID_I225_LMVP 0x5502 278f20571dSSasha Neftin #define IGC_DEV_ID_I226_LMVP 0x5503 28c2a3f8feSSasha Neftin #define IGC_DEV_ID_I225_IT 0x0D9F 2943546211SSasha Neftin #define IGC_DEV_ID_I226_LM 0x125B 3043546211SSasha Neftin #define IGC_DEV_ID_I226_V 0x125C 3143546211SSasha Neftin #define IGC_DEV_ID_I226_IT 0x125D 3243546211SSasha Neftin #define IGC_DEV_ID_I221_V 0x125E 3343546211SSasha Neftin #define IGC_DEV_ID_I226_BLANK_NVM 0x125F 340e7d4b93SSasha Neftin #define IGC_DEV_ID_I225_BLANK_NVM 0x15FD 35d89f8841SSasha Neftin 36146740f9SSasha Neftin /* Function pointers for the MAC. */ 37146740f9SSasha Neftin struct igc_mac_operations { 38c0071c7aSSasha Neftin s32 (*check_for_link)(struct igc_hw *hw); 39c0071c7aSSasha Neftin s32 (*reset_hw)(struct igc_hw *hw); 40c0071c7aSSasha Neftin s32 (*init_hw)(struct igc_hw *hw); 41c0071c7aSSasha Neftin s32 (*setup_physical_interface)(struct igc_hw *hw); 42c0071c7aSSasha Neftin void (*rar_set)(struct igc_hw *hw, u8 *address, u32 index); 43c0071c7aSSasha Neftin s32 (*read_mac_addr)(struct igc_hw *hw); 44c0071c7aSSasha Neftin s32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed, 45c0071c7aSSasha Neftin u16 *duplex); 46c0071c7aSSasha Neftin s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask); 47c0071c7aSSasha Neftin void (*release_swfw_sync)(struct igc_hw *hw, u16 mask); 48146740f9SSasha Neftin }; 49146740f9SSasha Neftin 50146740f9SSasha Neftin enum igc_mac_type { 51146740f9SSasha Neftin igc_undefined = 0, 52146740f9SSasha Neftin igc_i225, 53146740f9SSasha Neftin igc_num_macs /* List is 1-based, so subtract 1 for true count. */ 54146740f9SSasha Neftin }; 55146740f9SSasha Neftin 565586838fSSasha Neftin enum igc_media_type { 575586838fSSasha Neftin igc_media_type_unknown = 0, 585586838fSSasha Neftin igc_media_type_copper = 1, 595586838fSSasha Neftin igc_num_media_types 605586838fSSasha Neftin }; 615586838fSSasha Neftin 62c0071c7aSSasha Neftin enum igc_nvm_type { 63c0071c7aSSasha Neftin igc_nvm_unknown = 0, 648c5ad0daSSasha Neftin igc_nvm_eeprom_spi, 65c0071c7aSSasha Neftin }; 66c0071c7aSSasha Neftin 67c0071c7aSSasha Neftin struct igc_info { 68c0071c7aSSasha Neftin s32 (*get_invariants)(struct igc_hw *hw); 69c0071c7aSSasha Neftin struct igc_mac_operations *mac_ops; 70c0071c7aSSasha Neftin const struct igc_phy_operations *phy_ops; 71c0071c7aSSasha Neftin struct igc_nvm_operations *nvm_ops; 72c0071c7aSSasha Neftin }; 73c0071c7aSSasha Neftin 74ab405612SSasha Neftin extern const struct igc_info igc_base_info; 75ab405612SSasha Neftin 76146740f9SSasha Neftin struct igc_mac_info { 77146740f9SSasha Neftin struct igc_mac_operations ops; 78146740f9SSasha Neftin 79146740f9SSasha Neftin u8 addr[ETH_ALEN]; 80146740f9SSasha Neftin u8 perm_addr[ETH_ALEN]; 81146740f9SSasha Neftin 82146740f9SSasha Neftin enum igc_mac_type type; 83146740f9SSasha Neftin 84146740f9SSasha Neftin u32 mc_filter_type; 85146740f9SSasha Neftin 86146740f9SSasha Neftin u16 mta_reg_count; 87146740f9SSasha Neftin u16 uta_reg_count; 88146740f9SSasha Neftin 897f839684SSasha Neftin u32 mta_shadow[MAX_MTA_REG]; 90146740f9SSasha Neftin u16 rar_entry_count; 91146740f9SSasha Neftin 925586838fSSasha Neftin bool asf_firmware_present; 93146740f9SSasha Neftin bool arc_subsystem_valid; 94146740f9SSasha Neftin 95146740f9SSasha Neftin bool autoneg; 96146740f9SSasha Neftin bool autoneg_failed; 97c9a11c23SSasha Neftin bool get_link_status; 98146740f9SSasha Neftin }; 99146740f9SSasha Neftin 100c0071c7aSSasha Neftin struct igc_nvm_operations { 101c0071c7aSSasha Neftin s32 (*acquire)(struct igc_hw *hw); 102c0071c7aSSasha Neftin s32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 103c0071c7aSSasha Neftin void (*release)(struct igc_hw *hw); 104c0071c7aSSasha Neftin s32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 105c0071c7aSSasha Neftin s32 (*update)(struct igc_hw *hw); 106c0071c7aSSasha Neftin s32 (*validate)(struct igc_hw *hw); 107c0071c7aSSasha Neftin }; 108c0071c7aSSasha Neftin 1095586838fSSasha Neftin struct igc_phy_operations { 1105586838fSSasha Neftin s32 (*acquire)(struct igc_hw *hw); 1115586838fSSasha Neftin s32 (*check_reset_block)(struct igc_hw *hw); 1125586838fSSasha Neftin s32 (*force_speed_duplex)(struct igc_hw *hw); 1135586838fSSasha Neftin s32 (*get_phy_info)(struct igc_hw *hw); 1145586838fSSasha Neftin s32 (*read_reg)(struct igc_hw *hw, u32 address, u16 *data); 1155586838fSSasha Neftin void (*release)(struct igc_hw *hw); 1165586838fSSasha Neftin s32 (*reset)(struct igc_hw *hw); 1175586838fSSasha Neftin s32 (*write_reg)(struct igc_hw *hw, u32 address, u16 data); 1185586838fSSasha Neftin }; 1195586838fSSasha Neftin 120c0071c7aSSasha Neftin struct igc_nvm_info { 121c0071c7aSSasha Neftin struct igc_nvm_operations ops; 122c0071c7aSSasha Neftin enum igc_nvm_type type; 123c0071c7aSSasha Neftin 124c0071c7aSSasha Neftin u16 word_size; 125c0071c7aSSasha Neftin u16 delay_usec; 126c0071c7aSSasha Neftin u16 address_bits; 127c0071c7aSSasha Neftin u16 opcode_bits; 128c0071c7aSSasha Neftin u16 page_size; 129c0071c7aSSasha Neftin }; 130c0071c7aSSasha Neftin 1315586838fSSasha Neftin struct igc_phy_info { 1325586838fSSasha Neftin struct igc_phy_operations ops; 1335586838fSSasha Neftin 1345586838fSSasha Neftin u32 addr; 1355586838fSSasha Neftin u32 id; 1365586838fSSasha Neftin u32 reset_delay_us; /* in usec */ 1375586838fSSasha Neftin u32 revision; 1385586838fSSasha Neftin 1395586838fSSasha Neftin enum igc_media_type media_type; 1405586838fSSasha Neftin 1415586838fSSasha Neftin u16 autoneg_advertised; 1425586838fSSasha Neftin u16 autoneg_mask; 1435586838fSSasha Neftin 1445586838fSSasha Neftin u8 mdix; 1455586838fSSasha Neftin 1465586838fSSasha Neftin bool is_mdix; 1475586838fSSasha Neftin bool speed_downgraded; 1485586838fSSasha Neftin bool autoneg_wait_to_complete; 1495586838fSSasha Neftin }; 1505586838fSSasha Neftin 151146740f9SSasha Neftin struct igc_bus_info { 152146740f9SSasha Neftin u16 func; 153146740f9SSasha Neftin u16 pci_cmd_word; 154146740f9SSasha Neftin }; 155146740f9SSasha Neftin 156c0071c7aSSasha Neftin enum igc_fc_mode { 157c0071c7aSSasha Neftin igc_fc_none = 0, 158c0071c7aSSasha Neftin igc_fc_rx_pause, 159c0071c7aSSasha Neftin igc_fc_tx_pause, 160c0071c7aSSasha Neftin igc_fc_full, 161c0071c7aSSasha Neftin igc_fc_default = 0xFF 162c0071c7aSSasha Neftin }; 163c0071c7aSSasha Neftin 164c0071c7aSSasha Neftin struct igc_fc_info { 165c0071c7aSSasha Neftin u32 high_water; /* Flow control high-water mark */ 166c0071c7aSSasha Neftin u32 low_water; /* Flow control low-water mark */ 167c0071c7aSSasha Neftin u16 pause_time; /* Flow control pause timer */ 168c0071c7aSSasha Neftin bool send_xon; /* Flow control send XON */ 169c0071c7aSSasha Neftin bool strict_ieee; /* Strict IEEE mode */ 170c0071c7aSSasha Neftin enum igc_fc_mode current_mode; /* Type of flow control */ 171c0071c7aSSasha Neftin enum igc_fc_mode requested_mode; 172c0071c7aSSasha Neftin }; 173c0071c7aSSasha Neftin 174c0071c7aSSasha Neftin struct igc_dev_spec_base { 175c0071c7aSSasha Neftin bool clear_semaphore_once; 17693ec439aSSasha Neftin bool eee_enable; 177c0071c7aSSasha Neftin }; 178c0071c7aSSasha Neftin 179146740f9SSasha Neftin struct igc_hw { 180146740f9SSasha Neftin void *back; 181146740f9SSasha Neftin 182146740f9SSasha Neftin u8 __iomem *hw_addr; 183146740f9SSasha Neftin unsigned long io_base; 184146740f9SSasha Neftin 185146740f9SSasha Neftin struct igc_mac_info mac; 186c0071c7aSSasha Neftin struct igc_fc_info fc; 187c0071c7aSSasha Neftin struct igc_nvm_info nvm; 1885586838fSSasha Neftin struct igc_phy_info phy; 189146740f9SSasha Neftin 190146740f9SSasha Neftin struct igc_bus_info bus; 191146740f9SSasha Neftin 192c0071c7aSSasha Neftin union { 193c0071c7aSSasha Neftin struct igc_dev_spec_base _base; 194c0071c7aSSasha Neftin } dev_spec; 195c0071c7aSSasha Neftin 196146740f9SSasha Neftin u16 device_id; 197146740f9SSasha Neftin u16 subsystem_vendor_id; 198146740f9SSasha Neftin u16 subsystem_device_id; 199146740f9SSasha Neftin u16 vendor_id; 200146740f9SSasha Neftin 201146740f9SSasha Neftin u8 revision_id; 202146740f9SSasha Neftin }; 203146740f9SSasha Neftin 2043df25e4cSSasha Neftin /* Statistics counters collected by the MAC */ 2053df25e4cSSasha Neftin struct igc_hw_stats { 2063df25e4cSSasha Neftin u64 crcerrs; 2073df25e4cSSasha Neftin u64 algnerrc; 2083df25e4cSSasha Neftin u64 symerrs; 2093df25e4cSSasha Neftin u64 rxerrc; 2103df25e4cSSasha Neftin u64 mpc; 2113df25e4cSSasha Neftin u64 scc; 2123df25e4cSSasha Neftin u64 ecol; 2133df25e4cSSasha Neftin u64 mcc; 2143df25e4cSSasha Neftin u64 latecol; 2153df25e4cSSasha Neftin u64 colc; 2163df25e4cSSasha Neftin u64 dc; 2173df25e4cSSasha Neftin u64 tncrs; 2183df25e4cSSasha Neftin u64 sec; 2193df25e4cSSasha Neftin u64 cexterr; 2203df25e4cSSasha Neftin u64 rlec; 2213df25e4cSSasha Neftin u64 xonrxc; 2223df25e4cSSasha Neftin u64 xontxc; 2233df25e4cSSasha Neftin u64 xoffrxc; 2243df25e4cSSasha Neftin u64 xofftxc; 2253df25e4cSSasha Neftin u64 fcruc; 2263df25e4cSSasha Neftin u64 prc64; 2273df25e4cSSasha Neftin u64 prc127; 2283df25e4cSSasha Neftin u64 prc255; 2293df25e4cSSasha Neftin u64 prc511; 2303df25e4cSSasha Neftin u64 prc1023; 2313df25e4cSSasha Neftin u64 prc1522; 23240edc734SSasha Neftin u64 tlpic; 23340edc734SSasha Neftin u64 rlpic; 2343df25e4cSSasha Neftin u64 gprc; 2353df25e4cSSasha Neftin u64 bprc; 2363df25e4cSSasha Neftin u64 mprc; 2373df25e4cSSasha Neftin u64 gptc; 2383df25e4cSSasha Neftin u64 gorc; 2393df25e4cSSasha Neftin u64 gotc; 2403df25e4cSSasha Neftin u64 rnbc; 2413df25e4cSSasha Neftin u64 ruc; 2423df25e4cSSasha Neftin u64 rfc; 2433df25e4cSSasha Neftin u64 roc; 2443df25e4cSSasha Neftin u64 rjc; 2453df25e4cSSasha Neftin u64 mgprc; 2463df25e4cSSasha Neftin u64 mgpdc; 2473df25e4cSSasha Neftin u64 mgptc; 2483df25e4cSSasha Neftin u64 tor; 2493df25e4cSSasha Neftin u64 tot; 2503df25e4cSSasha Neftin u64 tpr; 2513df25e4cSSasha Neftin u64 tpt; 2523df25e4cSSasha Neftin u64 ptc64; 2533df25e4cSSasha Neftin u64 ptc127; 2543df25e4cSSasha Neftin u64 ptc255; 2553df25e4cSSasha Neftin u64 ptc511; 2563df25e4cSSasha Neftin u64 ptc1023; 2573df25e4cSSasha Neftin u64 ptc1522; 2583df25e4cSSasha Neftin u64 mptc; 2593df25e4cSSasha Neftin u64 bptc; 2603df25e4cSSasha Neftin u64 tsctc; 2613df25e4cSSasha Neftin u64 tsctfc; 2623df25e4cSSasha Neftin u64 iac; 2633df25e4cSSasha Neftin u64 htdpmc; 2643df25e4cSSasha Neftin u64 rpthc; 2653df25e4cSSasha Neftin u64 hgptc; 2663df25e4cSSasha Neftin u64 hgorc; 2673df25e4cSSasha Neftin u64 hgotc; 2683df25e4cSSasha Neftin u64 lenerrs; 2693df25e4cSSasha Neftin u64 scvpc; 2703df25e4cSSasha Neftin u64 hrmpc; 2713df25e4cSSasha Neftin u64 doosync; 2723df25e4cSSasha Neftin u64 o2bgptc; 2733df25e4cSSasha Neftin u64 o2bspc; 2743df25e4cSSasha Neftin u64 b2ospc; 2753df25e4cSSasha Neftin u64 b2ogprc; 276*92a0dcb8STan Tee Min u64 txdrop; 2773df25e4cSSasha Neftin }; 2783df25e4cSSasha Neftin 279c0071c7aSSasha Neftin struct net_device *igc_get_hw_dev(struct igc_hw *hw); 280c0071c7aSSasha Neftin #define hw_dbg(format, arg...) \ 281c0071c7aSSasha Neftin netdev_dbg(igc_get_hw_dev(hw), format, ##arg) 282c0071c7aSSasha Neftin 283146740f9SSasha Neftin s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 284146740f9SSasha Neftin s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 285146740f9SSasha Neftin void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 286146740f9SSasha Neftin void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 287146740f9SSasha Neftin 288d89f8841SSasha Neftin #endif /* _IGC_HW_H_ */ 289