1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_BASE_H 5 #define _IGC_BASE_H 6 7 /* forward declaration */ 8 void igc_rx_fifo_flush_base(struct igc_hw *hw); 9 void igc_power_down_phy_copper_base(struct igc_hw *hw); 10 11 /* Transmit Descriptor - Advanced */ 12 union igc_adv_tx_desc { 13 struct { 14 __le64 buffer_addr; /* Address of descriptor's data buf */ 15 __le32 cmd_type_len; 16 __le32 olinfo_status; 17 } read; 18 struct { 19 __le64 rsvd; /* Reserved */ 20 __le32 nxtseq_seed; 21 __le32 status; 22 } wb; 23 }; 24 25 /* Adv Transmit Descriptor Config Masks */ 26 #define IGC_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */ 27 #define IGC_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 28 #define IGC_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 29 #define IGC_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ 30 #define IGC_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 31 #define IGC_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ 32 #define IGC_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 33 #define IGC_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 34 #define IGC_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 35 #define IGC_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 36 37 #define IGC_RAR_ENTRIES 16 38 39 /* Receive Descriptor - Advanced */ 40 union igc_adv_rx_desc { 41 struct { 42 __le64 pkt_addr; /* Packet buffer address */ 43 __le64 hdr_addr; /* Header buffer address */ 44 } read; 45 struct { 46 struct { 47 union { 48 __le32 data; 49 struct { 50 __le16 pkt_info; /*RSS type, Pkt type*/ 51 /* Split Header, header buffer len */ 52 __le16 hdr_info; 53 } hs_rss; 54 } lo_dword; 55 union { 56 __le32 rss; /* RSS Hash */ 57 struct { 58 __le16 ip_id; /* IP id */ 59 __le16 csum; /* Packet Checksum */ 60 } csum_ip; 61 } hi_dword; 62 } lower; 63 struct { 64 __le32 status_error; /* ext status/error */ 65 __le16 length; /* Packet length */ 66 __le16 vlan; /* VLAN tag */ 67 } upper; 68 } wb; /* writeback */ 69 }; 70 71 /* Additional Transmit Descriptor Control definitions */ 72 #define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ 73 74 /* Additional Receive Descriptor Control definitions */ 75 #define IGC_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */ 76 77 /* SRRCTL bit definitions */ 78 #define IGC_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 79 #define IGC_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 80 #define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 81 82 #endif /* _IGC_BASE_H */ 83